Package device and method of forming same

Abstract

In a package device in which an integrated circuit device is bonded to a substrate, stresses caused by mechanical strain, CTE mismatch, etc. may be mitigated or eliminated by incorporating stress buffer air gaps into a protective material, such as a gap filling oxide. The air gap may be formed by adjusting and changing deposition parameters during the deposition process and / or by adjusting the size and placement of adjacent integrated circuit devices in the package and / or by forming trenches in the protective material prior to the bonding process. The embodiment of the invention also relates to a packaging device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a packaged device and a method for forming the same. Background Art

[0002] As integration density increases in the field of semiconductor devices, there is a need for increased density in packaging. Differences in material properties, such as the coefficient of thermal expansion (CTE), may cause performance and reliability issues for such packaged devices. As an example, when an integrated circuit die is bonded to a substrate and embedded in a protective material, such as an oxide, a CTE mismatch between the protective material and other components of the packaging structure may cause stress, leading to delamination in some cases and potentially causing peeling or cracks in some cases. Therefore, structures and methods are needed to improve the performance and reliability of packaged semiconductor devices. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a packaged device, the method comprising: bonding a top die to a bottom substrate; depositing a dielectric layer over the bottom substrate and around the top die by implementing a dielectric deposition process; and forming a cavity in the dielectric layer, the cavity being adjacent to at least one side of the top die, wherein the cavity is configured to relieve stress on the top die caused by a coefficient of thermal expansion (CTE) mismatch between the dielectric layer and components of the packaged device.

[0004] Still other embodiments of the present application provide a method for forming a packaged device, the method comprising: mounting an integrated circuit die on a substrate; embedding the integrated circuit die in a protective material; and forming a stress compensation cavity in the protective material, the stress compensation cavity being adjacent to at least one side of the integrated circuit die.

[0005] Still other embodiments of the present application provide a packaging device comprising: a bottom substrate; an integrated circuit die bonded to the bottom substrate; a dielectric layer located above the bottom substrate and at least partially surrounding the integrated circuit die; and an air-filled cavity located within the dielectric layer and adjacent to at least one side of the integrated circuit die. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the disclosed embodiments can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a cross-sectional view of an exemplary packaged device embodiment.

[0008] FIG. 2A to FIG. 2Eis a cross-sectional view of steps in an embodiment of a method manufacturing process.

[0009] Figure 3 is a top view of an exemplary embodiment packaged device.

[0010] FIG. 4A to FIG. 4B and FIG. 5A to FIG. 5F It is a cross-sectional view of relevant steps in another method manufacturing process embodiment.

[0011] FIG. 6A to FIG. 6D is a cross-sectional view of steps in yet another method manufacturing process embodiment.

[0012] 7A to 7E is a top view of an exemplary packaged device.

[0013] Fig. 8A , Figure 8B and Figure 8C is a flow chart illustrating steps of an embodiment of a manufacturing process. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] Figure 1An exemplary packaged device 100 is shown, which includes a bottom device 2 having one or more integrated circuit devices 4 bonded to its upper surface. Each of the integrated circuit devices 4 may be a logic die (e.g., an application processor (AP), a central processing unit, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC), a static random access memory (SRAM) die, a wide input / output (wide IO) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), a biomedical die, etc. Each of the integrated circuit devices 4 may also be a system-on-chip (SoC) die, etc.

[0017] Further details about an exemplary integrated circuit device 4 will now be provided. As shown, the respective integrated circuit device 4 includes a respective substrate 14. Active and / or passive devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and / or on the substrate 14. The devices may be interconnected by respective interconnect structures 16, as is well known in the field of integrated circuit devices. The interconnect structure 16 electrically connects the devices on the substrate 14 to form one or more integrated circuits. The interconnect structure 16 may include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, etc.) and interconnect wiring or metallization patterns embedded in the one or more dielectric layers. The material of the one or more dielectric layers may include silicon oxide (SiO x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0) or other suitable dielectric materials. The interconnect wiring may include metal wiring. For example, the interconnect wiring includes copper wiring, copper pads, aluminum pads, or combinations thereof formed by one or more single damascene processes, dual damascene processes, etc. The side of the integrated circuit device 4 including the exposed backside surface of the substrate 14 may also be referred to as the backside of the integrated circuit device 4.

[0018] The corresponding substrate 14 of the integrated circuit device 4 may include a crystalline silicon wafer. The substrate 14 may include various doped regions depending on the design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the doped region may be doped with a p-type or n-type dopant. The doped region may be doped with a p-type dopant, such as boron or BF2; an n-type dopant, such as phosphorus or arsenic; and / or a combination thereof. The doped region may be configured for an n-type fin field effect transistor (FinFET) and / or a p-type FinFET. In some optional embodiments, the substrate 14 may include an active layer of a semiconductor on insulator (SOI) substrate. The substrate 14 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0019] The bonding layer 10 may include a dielectric layer. The bonding pad 8 is embedded in the bonding layer 10 and allows a connection to be made to the interconnect structure 16 and thus to the device on the substrate 14. The material of the bonding layer 10 may be silicon oxide (SiO x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0), tetraethyl orthosilicate (TEOS) or other suitable dielectric materials, and the bonding pads 8 may include conductive pads (e.g., copper pads), conductive vias (e.g., copper vias), or combinations thereof. The bonding layer 10 may be formed by: depositing a dielectric material over the interconnect structure 16 using, for example, a chemical vapor deposition (CVD) process (e.g., a plasma enhanced CVD process or other suitable process); patterning the dielectric material to form a bonding layer 10 including openings or holes; and filling the openings or holes defined in the bonding layer 10 with a conductive material to form bonding pads 8 embedded in the bonding layer 10. In other embodiments, the bonding pads 8 are formed first, and the bonding layer 10 is deposited around them.

[0020] The bottom device 2 can serve as a mechanical support structure for the integrated circuit devices 4. In some examples, the bottom device 2 also provides electrical connections between the respective integrated circuit devices 4, between the integrated circuit devices 4 and active and / or passive components formed on or within the bottom device 2, and between the integrated circuit devices 4 and other components located outside the package device 100. For example, in Figure 1In the embodiment shown in , the bottom device 2 includes a substrate 3, active devices (such as transistors, photoelectric sensors, MEM devices, etc.) 5, passive devices (such as resistors, capacitors, inductors, etc.) 7 and a multi-layer interconnect structure 9. As an example, the bottom device 2 can be an integrated circuit device manufactured using materials and formation processes similar to those used in forming the integrated circuit device 4. In other embodiments, the bottom device 2 can be a semiconductor wafer, such as a bulk silicon wafer, a silicon on insulator (SOI) wafer, an interposer, a coreless substrate, a printed circuit board (PCB), a ceramic wafer, etc. In the illustrated embodiment, the bottom device 2 includes circuits that contribute to the function of the package device 100, but this is not a necessary component of the currently disclosed embodiment. As will be appreciated by those skilled in the art, the interconnect structure 9 includes a stack of conductive components, some of which are interconnected by conductive interlayer vias, and the corresponding layers of the conductive interlayer vias are embedded in the corresponding layers of the stack of dielectric materials. The bottom device 2 also includes a bonding pad 11 at the topmost surface of the bottom device 2.

[0021] Figure 1 1 and 2. A bonding layer 13 disposed on the interconnect structure 9 is also shown, wherein bonding pads 11 are disposed in the bonding layer 13 and are flush with the bonding layer 13 and exposed through the bonding layer 13. These bonding pads 11 allow electrical connections to be made to the interconnect structure 9 and to the integrated circuit device 4 bonded to the bottom device 2. In the illustrated embodiment, the bottom device 2 also includes a through substrate via (TSV) 15, which can be electrically connected to the metallization pattern and / or the active device 5 and / or the passive device 7 in the interconnect structure 9. The TSV 15 can be formed by: forming an opening in the substrate 3 by, for example, etching, milling, laser technology, a combination thereof, etc. A thin barrier layer (not shown) can be conformally deposited over the front side of the substrate 3 and in the opening, such as by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, etc. The barrier layer can include nitrides, nitride oxides, such as titanium nitride, titanium oxynitride, tantalum nitride, tungsten nitride, a combination thereof, etc. A conductive material is deposited over the thin barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, and the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, and the like. Excess conductive material and barrier layers may be removed from the front side of the substrate 3 by, for example, chemical mechanical polishing. Thus, in some embodiments, the TSV 15 may include a conductive material and a thin barrier layer between the conductive material and the substrate 3. In a subsequent processing step, the substrate 3 may be thinned to expose the TSV 15 so that electrical connections may be made thereto. After thinning the substrate 3 (see Figure 2D ), TSV 15 provides electrical connection from the back side of substrate 3 to interconnect structure 9.

[0022] at last, Figure 1 Also shown is a protective material 6 that seals or surrounds the integrated circuit device 4 and also seals or surrounds the exposed portion of the top surface of the bottom device 2. In some embodiments, the protective material 6 is an oxide and may be referred to herein as a gap fill oxide or GFO. x , but other materials are also within the contemplation of the embodiments of the present disclosure. For example, the protective material 6 may include one or more layers of silicon oxide, silicon nitride, silicon oxynitride, polymers, molding compounds, combinations thereof, etc. - provided that the material meets the requirements of the particular application, such as providing electrical insulation, moisture resistance, thermal management, mechanical protection, etc. A particularly advantageous feature of the embodiments described herein is the presence of air gaps within the protective material 6, such as Figure 1 . As will be described in more detail below, for example, the air gap 12 can be used as a stress buffer to mitigate or otherwise improve the effects of coefficient of thermal expansion (CTE) mismatch between components of the packaged device 100 (such as between the protective layer 6 and the bottom device 2).

[0023] Now refer to FIG. 2A to FIG. 2C Additional details of an exemplary process for forming the packaged device 100 are provided. The integrated circuit device 4 is bonded to the bottom device 2, for example, by metal-to-metal bonding of the contact pads 8 of the respective integrated circuit device 4 to the corresponding bonding pads 11 of the bottom device 2 and dielectric-to-dielectric bonding of the top dielectric layer 10 of the respective integrated circuit device 4 to the bonding dielectric layer 13 of the bottom device 2. FIG. 2A to FIG. 2C In the illustrated embodiment of , although not limiting of the disclosed embodiments, the integrated circuit device 4 is disposed face-down so that the front side of the integrated circuit device 4 faces the bottom device 2, and the back side of the integrated circuit device 4 faces away from the bottom device 2. The integrated circuit device 4 is bonded to the bonding layer 13 on the front side of the bottom device 2 and the bonding pads 11 in the bonding layer 13. For example, the bonding layer 10 of the corresponding integrated circuit device 4 can be directly bonded to the bonding layer 13 of the bottom device 2, and the bonding pads 8 of the corresponding integrated circuit device 4 can be directly bonded to the bonding pads 11 of the bottom device 2. In an embodiment, the bonding between the bonding layer 10 and the bonding layer 13 can be oxide-to-oxide bonding, etc. The bonding process also directly bonds the bonding pads 8 of the integrated circuit device 4 to the bonding pads 11 of the bottom device 2 by direct metal-to-metal bonding. Therefore, the electrical connection between the integrated circuit device 4 and the bottom device 2 is provided by the physical connection of the bonding pads 8 to the bonding pads 11.

[0024] In an embodiment, the bonding process may begin by preparing the integrated circuit device 4 and / or the bottom device 2, for example, by applying a surface treatment 20 to one or more of the bonding layer 10 or the bonding layer 13, such as Figure 2ASchematically shown. The surface treatment may include plasma treatment. The plasma treatment may be implemented in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or more of the bonding layer 10 or the bonding layer 13. Similarly, a preparation process may be implemented for the bonding pad 8 and / or the bonding pad 11.

[0025] The bonding process may then continue by aligning the bonding pad 8 with the bonding pad 11, as shown in FIG. Figure 2B As shown in . In some embodiments, the bonding process includes a pre-bonding step during which the integrated circuit device 4 is placed in contact with the bottom device 2. The pre-bonding can be performed at room temperature (e.g., between about 21° C. and about 25° C.). The bonding process continues with annealing, for example, at a temperature between about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, so that the metal (e.g., copper) in the bonding pad 8 and the metal (e.g., copper) of the bonding pad 11 diffuse into each other and thereby form a direct metal-to-metal bond. Although two integrated circuit devices 4 are shown as being bonded to the bottom device 2, other embodiments may include any number of integrated circuit devices 4 bonded to the bottom device 2.

[0026] After the integrated circuit device 4 is bonded to the bottom device 2, the protective material 6 is formed. In some embodiments, the protective material 6 can be deposited to completely seal the integrated circuit device 4, and then partially removed, for example, by an etch-back process, mechanical grinding and / or abrasion, chemical mechanical polishing, etc., so that the top surface of the protective material 6 is flush with the corresponding top surface of the integrated circuit device 4, such as Figure 2C as shown in . Figure 2C The presence of air gaps 12 within the protective material 6 is also shown.

[0027] exist Figure 2CIn the embodiment shown in , air gaps 12 are formed along the edges of the corresponding integrated circuit device 4 during the deposition of the protective material 6. In the exemplary process, the protective material 6 is silicon oxide deposited using a chemical vapor deposition (CVD) process, wherein TEOS (tetraethyl orthosilicate) and oxygen are introduced as precursor gases into a deposition chamber (not shown) to form a silicon oxide layer. Traditionally, in semiconductor manufacturing processes, it is desirable to deposit the oxide layer in a consistent and uniform manner without gaps or other irregularities. However, contrary to conventional wisdom, it has been determined that by maintaining a low pressure (less than 4 Torr) in the deposition chamber and by increasing the flow rate of the TEOS precursor relative to the oxygen precursor during deposition, air gaps can be intentionally introduced into the material as the material is deposited. In addition, it has been found that the formation of such air gaps, while contrary to conventional thinking about maintaining a uniform and regular layer of material, provides an advantageous component that acts as a stress buffer by allowing the deposited material to deform locally in response to stresses (such as stresses caused by CTE mismatches between the deposited material and other materials and components of the packaged device). It has been further appreciated that under conditions of low pressure and increased TEOS:oxygen flow ratio, air gap formation is substantially localized to regions adjacent and / or around the bottom edge of the integrated circuit device 4. Without being bound by any underlying theory, it is believed that the irregular topography (i.e., the step height between the top surface of the bottom device 2 and the top surface of the integrated circuit device 4) causes localized regions where air gaps 12 will appear. This is particularly advantageous because issues such as stress, delamination, etc. are particularly sensitive near and around the edge of the integrated circuit device 4. As used herein, the term "adjacent" is used to indicate a proximity sufficient to allow an air gap to buffer or otherwise counteract stresses that would otherwise cause deleterious effects (such as delamination, peeling, cracks, etc.) to the affected package components in the absence of the air gap.

[0028] Figure 1 and Figure 2C The corresponding air gap 12 is shown in cross section. Figure 3 FIG. 1 is a top view of the packaged device 100 and shows that the air gap 12 effectively surrounds the corresponding integrated circuit device 4 from this angle. Figure 3 6, because the protective material 6 will block the view of the air gap 12 in an actual product. As shown, due to topographic irregularities, such as a large step height from the upper surface of the bonding layer 13 of the bottom device 2 to the top of the corresponding integrated circuit device 4, the air gap 12 will be formed adjacent to the side of the corresponding integrated circuit device 4 when the deposition process described above is employed. It is believed that the air gap 12 acts as a stress relief buffer and thus reduces or eliminates the possibility of cracks, delamination, peeling, etc. that would otherwise be caused by CTE mismatch and / or other mechanical forces acting on the protective material 6. For simplicity, the air gap 12 is shown in phantom. Figure 3 In some embodiments, and depending on the deposition parameters and the topography of the device being fabricated, the air gap 12 may be formed generally following Figure 3 A series of discontinuous gaps or lines of discontinuous gaps in the pattern shown in .

[0029] Continue About Figure 2D , which shows the result of an optional step of thinning back the substrate 3 of the bottom device 2, which process is used in those embodiments in which TSVs 15 are formed in the bottom device 2. In addition to reducing the overall height of the packaged device 100, this thinning back process exposes the ends of the TSVs 15. Next, a backside interconnect structure 17 ( Figure 2E ), thereby allowing electrical interconnection between components external to the packaged device 100 and circuits on the bottom device 2 and circuits of the integrated circuit device 4.

[0030] In another embodiment, the air gap 12 may be formed to limit high stress areas between adjacent integrated circuit devices 4. Figure 4A and Figure 4B This embodiment is shown, wherein Figure 4A is a top view of an exemplary packaged device 200, and Figure 4B is an exemplary packaged device 200 along with Figure 4A Unless otherwise specified, the cross-sectional view used in the manufacture of Figure 4A and Figure 4B The components and process of the packaged device 200 are similar to those described above for Figure 1 and FIG. 2A to FIG. 2E The embodiments shown in FIG. 1 are identical to those provided by the embodiments shown in FIG. 5 , which is further indicated by the use of common reference numerals for those components and processes that are common to the embodiments.

[0031] like Figure 4A As shown in FIG. 2 , a single air gap 12 is formed between the integrated circuit devices 4. This area may be a relatively high stress area compared to other parts of the packaged device 200, and this embodiment does not require (although does not exclude) modifying or changing the deposition parameters during the step of depositing the protective material 6. In particular, it has been determined that when the aspect ratio of the spacing between the integrated circuit devices 4 is greater than about 1.5, an air gap 12 may be formed between the respective integrated circuit devices 4. In other words, and with reference to FIG. Figure 4B, assuming that the ratio of the height (H1) of the respective integrated circuit devices 4 to the distance (W1) between the nearest edges of the respective integrated circuit devices 4 is greater than about 1.5, an air gap 12 will be formed. Without being bound by any particular underlying theory of operation, it is believed that the protective material 6 will be formed in a conformal manner on the surface of the bonding layer 13 and between the integrated circuit devices 4. Therefore, a seam or gap will be formed between the sidewalls of the respective integrated circuit devices 4, such as Figure 5A As shown, Figure 5A 1 shows an intermediate stage of the deposition of the protective film 6. As more protective material 6 is deposited, the gap shrinks, as shown in FIG. Figure 5B As deposition continues, the material formed over the leftmost integrated circuit device 4 merges with the material formed over the rightmost integrated circuit device 4, thereby completely forming and sealing the air gap 12, as shown in FIG. Figure 5C As shown. Although other deposition processes for other materials may result in the formation of seams within the material, the conventional view in the relevant art is that such seams (if they occur) are unfavorable and should be prevented. Contrary to conventional view, it has been determined that adjusting the height of the respective integrated circuit devices 4 and the spacing therebetween can result in the formation of favorable air gaps in the protective material, which are used to buffer against stresses caused by CTE mismatch and other mechanical stresses. This method of forming the air gap 12 is believed to be particularly advantageous because the air gap 12 will be spaced apart from the side of the integrated circuit device 4 and therefore will not expose the side of the integrated circuit device 4. In addition, the formation process also ensures that the air gap 12 will be spaced apart from the top surface of the bottom device 2 and therefore will not expose the top surface of the bottom device 2, or more specifically, the bonding layer 13. Although not a limitation of the embodiments of the present disclosure, it is believed that air gaps 12 with a size of up to 50μm can be formed by this method.

[0032] Figure 5C It is also shown that in some embodiments, the gaps between the respective integrated circuit devices 4 are overfilled, and in fact the protective material 6 is deposited on top of the topmost surface of the integrated circuit devices 4. This is done to ensure that the integrated circuit devices 4 are completely surrounded by the protective material 6. Then, as shown in FIG. Figure 5D As shown in FIG. 1 , a process such as an etch-back process, mechanical grinding, a CMP process, etc. is performed to planarize the top surface of the protective material 6 and make it flush with the top surface of the corresponding integrated circuit device 4. This overfilling and planarization method is not a necessary feature of any embodiment described herein, but the method is also applicable to FIG. 2A to FIG. 2E The embodiments described are applicable to other embodiments described herein.

[0033] As in the previously described embodiment, if the TSV 15 is formed in the bottom device 2, the wafer 3 of the bottom device 2 may be thinned from the back side to expose the ends of the TSV 15, such as Figure 5E Then, as Fig. 5F As shown, backside interconnect structure 17 is formed to allow electrical interconnection of packaged device 200 with external components.

[0034] refer to FIG. 6A to FIG. 6D Another embodiment for forming a packaged device 300 with a stress buffering air gap is provided. In this embodiment, the protective material 6 is formed before bonding the integrated circuit device 4 to the bottom device 2. For example, Fig. 6A In the example shown in , the integrated circuit device 4 is mounted on a carrier substrate 22. The carrier substrate is a temporary support structure that will be removed later, as described below, and therefore its composition is not special. Various carrier substrates are known in the art, including silicon wafers, ceramic substrates, quartz substrates, etc. In some embodiments, two or more integrated circuit devices 4 are mounted to the carrier substrate 22 using a temporary adhesive. In one embodiment, the carrier substrate is made of a material that is substantially transparent to radiant energy in a specific wavelength range, and a temporary adhesive that loses its adhesive properties when subjected to radiant energy of a specific wavelength can be used.

[0035] Regardless of the carrier substrate and bonding technique employed, the integrated circuit devices 4 are placed on the carrier substrate 22 in an arrangement that matches the desired arrangement when the integrated circuit devices 4 are bonded to the bottom device 2, as will be described in more detail below. In other words, the relative placement and spacing for the integrated circuit devices 4 (as they are temporarily bonded to the carrier substrate 22) should match the desired placement and spacing of the integrated circuit devices 4 (when they are subsequently bonded to the bottom device 2). It should be noted that in this process, the integrated circuit devices 4 are mounted to the carrier substrate in a face-up configuration, which means that the back side (wafer side) of the integrated circuit devices 4 is bonded to the carrier substrate 22 so that the corresponding bonding layer 8 and the corresponding bonding pads 10 are unobstructed.

[0036] Fig. 6A Also shown is a protective material 6 that has been deposited onto the carrier substrate 22 and surrounds the integrated circuit device 4. In this embodiment, the protective material 6 can be deposited using conventional deposition processes and parameters because air gap formation during the deposition process is not required in this embodiment. Fig. 6A , the protective material 6 is shown as being flush and level with the top surface of the integrated circuit device 4. This may be a result of the deposition process. However, in other embodiments, the protective material 6 may be deposited to overfill the gaps between the respective integrated circuit devices 4 and cover the respective integrated circuit devices 4 (such as Figure 5C ), and then thinned back (using etch back, mechanical grinding, CMP, etc.).

[0037] Figure 6B A process for forming a trench 112 in the top surface of the protective material 6 after it has been deposited (and in some embodiments planarized) is shown. The trench 112 can be formed using a photolithography process in which a mask layer 24 is formed atop the protective material 6 and then patterned with an opening corresponding to the trench 112. After patterning the mask layer 24, the protective material 6 is patterned using an appropriate etching process. In the case where the protective material is made of silicon oxide, the trench 112 can be formed, for example, using a wet etching process such as a buffered oxide etch (BOE) process involving an HF etchant. Given the relatively large size of the trench 112 (typically multiples of a few microns or tens of microns) and the relatively loose alignment tolerances for the location of the trench 112, various types of etching processes can be employed to form the trench 112, whether anisotropic or isotropic, wet or dry etching. Those skilled in the art will understand that once informed by the embodiments of the present disclosure, a particular etching process can be determined. In some embodiments, mask layer 24 is a photoresist material that can be deposited, photolithographically patterned, and then used as an etchant mask during an etching process. In other embodiments, mask layer 24 can be a hard mask formed of silicon nitride or other materials that are more resistant to etching processes, in which case a photolithographically patterned photoresist material (not shown) is formed over the hard mask to pattern mask layer 24.

[0038] Once the trench 112 is formed in the top surface of the protective material 6, the integrated circuit device 4 together with the protective material 6 can be mounted on the bottom device 2, such as Figure 6C It should be noted that Figure 6C In the embodiment, the integrated circuit device 4 is relative to Fig. 6A , the orientation shown in is “flipped”. This allows the integrated circuit device 4 to be bonded to the bottom device 2 in a face-to-face orientation, thereby allowing the bonding layer 10 of the corresponding integrated circuit device 4 to dielectrically bond with the bonding layer 13 of the bottom device 2, and allowing the bonding pad 8 of the corresponding integrated circuit device 4 to form a metal-to-metal bond with the corresponding bonding pad 11 of the bottom device 2. It should be noted that when the protective material 6 is mounted to the bottom device 2, the groove 112 becomes “sealed”, thereby forming an air gap 212 (in some embodiments, the protective material 6 will form a dielectric-to-dielectric bond with the bonding layer 13 of the bottom device 2). Similarly, Figure 6C As shown in , once the integrated circuit device is bonded to the bottom device 2, the carrier substrate can be removed because it no longer requires mechanical support. Fig.6D As shown in , processing may continue, such as by thinning back the wafer 3 of the bottom device 2 to expose the TSVs 15 , and forming a backside interconnect structure 17 .

[0039] Fig.6D Only a single air gap 212 is shown between adjacent integrated circuit devices 4. Those skilled in the art will appreciate that any number of grooves of different shapes and locations are within the contemplation of the embodiments of the present disclosure. For example, in some embodiments, it may be desirable to form an air gap in a particular stress-sensitive location, such as an adjacent corner of an integrated circuit device 4. Fig. 7A One such embodiment is shown in a top perspective view. Fig. 7A The embodiment of the present invention is achieved by using a patterned mask 24 ( Figure 6C These openings allow the protective material 6 to be removed during the etching process, thereby producing corresponding trenches 112 at the desired locations, which become air gaps 212, such as Fig. 7A as shown in .

[0040] Figure 7B and Figure 7C It is also a top view of another representative packaged device 300 embodiment and illustrates the FIG. 6A to FIG. 6D The described steps allow for increased flexibility in the size, placement, and arrangement of the air gap 212. This is at least in part because, in these embodiments, the location of the air gap is not limited to areas with irregular topography (such as those with respect to Figure 3 described) or between adjacent integrated circuit dies (such as with respect to Figure 5D For example, Figure 7B As shown in FIG. 1 , the step of patterning the grooves 112 in the protective material 6 using the photomask 24 (as described with reference to FIG. 1 ) is as follows: FIG. 6A to FIG. 6D 112a) allows air gaps to be placed anywhere stress may be generated or may have particularly detrimental effects. In the illustrated embodiment, air gaps 212a are formed at the corners of packaged device 300 because these corners may be subject to high stress. Similarly, protective material 6 can be patterned to form air gaps 212b that can be placed along the sides of integrated circuit devices 4 and between integrated circuit devices 4 to relieve stress in those areas. In addition, protective material 6 can be patterned with trenches 112 ( Figure 7B 4 (not shown) to form one or more air gaps 212c that expose the sides of one or more integrated circuit devices 4, if such exposure is desired.

[0041] Similarly, Figure 7CA process is shown in which patterning the protective material 6 after deposition allows the air gap 212 to be formed into different shapes, such as a circular air gap 212a, an elliptical air gap 212b, a rectangular air gap 212d, and an irregularly shaped air gap 212e. In fact, the size, shape, and placement of the air gap in this embodiment are limited only by the limitations of the process used to pattern the protective material 6, such as photolithography process limitations.

[0042] In the above described embodiment, the air gap 12' is formed after the integrated circuit device 4 is bonded to the bottom device 2. Fig.7D In the exemplary packaged device 400 shown in FIG. 1 , the air gap 12 ′ is formed using a deposition process similar to that described above, such as by controlling the aspect ratio of the spacing between the integrated circuit devices—while the devices are mounted on a temporary carrier substrate 22 (such as Fig. 6A In this way, before the integrated circuit die 4 is bonded to the bottom device 2, the air gap 12' is formed when the protective material 6 is deposited. In addition, after the protective material 6 is deposited, the air gap 12' is formed when the protective material 6 is deposited. FIG. 6A to FIG. 6D Prior to bonding the integrated circuit device 4 and the protective material 6 to the bottom device 2, an additional air gap 212d (or similarly, air gaps 212a, 212b, 212c and / or 212e, such as Figure 7B and Figure 7C By forming the air gaps 12' and 212d (or 212a, 212b, 212c and / or 212d) in the same packaged device, further design flexibility and improved stress resilience can be achieved.

[0043] Fig. 7E 5. In this embodiment, one or more air gaps 12" are formed using a deposition process similar to that described above, such as by adjusting deposition parameters (such as flow rates / ratios of precursor gases) during deposition of protective material 6 - while the device is mounted on a temporary carrier substrate 22 (such as Fig. 6A In this way, before the integrated circuit die 4 is bonded to the bottom device 2, the air gap 12" is formed when the protective material 6 is deposited. In addition, after the protective material 6 is deposited, the air gap 12" is formed when the protective material 6 is deposited. FIG. 6A to FIG. 6D Prior to bonding the integrated circuit device 4 and the protective material 6 to the bottom device 2, an additional air gap 212a (or similarly, air gaps 212b, 212c, 212d and / or 212e, such as Figure 7B and Figure 7CBy forming air gaps 212″ and 212a (or 212b, 212c, 212d and / or 212e) in the same packaged device, further design flexibility and improved stress resilience may be achieved.

[0044] Although the embodiments described above use the term air gap, it should be recognized that the air gap 12, 212 is limited to those spaces filled with ambient air. It is within the contemplation of the embodiments of the present disclosure that the air gap 12, 212 may be filled with some other gas besides air. For example, an inert gas such as nitrogen, argon, etc. may be present in the gap. Figures 1 to 5F In the embodiment of the present invention, the protective film is deposited in the deposition chamber, or the protective film is deposited in the deposition chamber. FIG. 6A to FIG. 6D and 7A to 7E In an embodiment of the present invention, an "air" gap is created which is filled with nitrogen, argon, or the like.

[0045] Fig. 8A is to show such as Figure 2E Flow chart of the main steps in the process embodiment described by the package shown in . The process includes the step of bonding the integrated circuit device (4) to the bottom device 2, as shown in step 80. Then, a protective material 6 is deposited over the integrated circuit device, and an air gap 12 is formed during the deposition process, as shown in step 82. Then, electrical connections for external components can be completed, such as forming a backside interconnect structure 17, as shown in step 84.

[0046] Figure 8B A flow chart for other embodiments is shown, where first a protective material 6 is deposited over the integrated circuit device 4, step 81. Then, an air gap 212 (or more accurately, a trench 112 that becomes an air gap 212) is formed in the protective material 6, step 83. The integrated circuit device 4 is then bonded to the bottom device 2, step 85. Finally, electrical connections for external components may be formed, as shown in step 87.

[0047] Figure 8CA flow chart is shown for an embodiment in which air gaps (e.g., air gaps 12' and / or 12") are formed during a deposition process for a protective material 6, and additional air gaps (e.g., air gaps 212a, 212b, 212c, 212d, and / or 212e) are formed by patterning the protective material 6 after deposition is complete. The process begins by depositing a protective material 6 over an integrated circuit device 4, and forming air gaps 12, 12', 12" in the protective material during the deposition process, step 90. In step 92, the protective material is patterned to form trenches 112 for additional air gaps 212, 212a, 212b, 212c, 212d, 212e, step 92. In step 94, the integrated circuit device 4 is bonded to a bottom device 2, the process sealing the trenches and forming additional air gaps. Then, step 96, electrical connections for external devices are formed, for example by forming an interconnect structure 17.

[0048] One general aspect of the embodiments disclosed herein includes a method of forming a packaged device, the method comprising: bonding a top die to a bottom substrate. The method also comprises: depositing a dielectric layer over the bottom substrate and around the top die by performing a dielectric deposition process. The method also comprises: forming a cavity in the dielectric layer, the cavity being adjacent to at least one side of the top die, wherein the cavity is configured to relieve stress on the top die caused by a mismatch in coefficient of thermal expansion (CTE) between the dielectric layer and components of the packaged device.

[0049] Another general aspect of the embodiments disclosed herein includes a method of forming a packaged device, the method comprising: mounting an integrated circuit die on a substrate. The method also comprises: embedding the integrated circuit die in a protective material. The method also comprises: forming a stress compensation cavity in the protective material, the stress compensation cavity being adjacent to at least one side of the integrated circuit die.

[0050] Another general aspect of the embodiments disclosed herein includes: a packaged device including a bottom substrate and an integrated circuit die bonded to the bottom substrate. The device also includes: a dielectric layer located above the bottom substrate and at least partially surrounding the integrated circuit die. The device also includes: an air-filled cavity located within the dielectric layer and adjacent to at least one side of the integrated circuit die.

[0051] Some embodiments of the present application provide a method for forming a packaged device, the method comprising: bonding a top die to a bottom substrate; depositing a dielectric layer over the bottom substrate and around the top die by implementing a dielectric deposition process; and forming a cavity in the dielectric layer, the cavity being adjacent to at least one side of the top die, wherein the cavity is configured to relieve stress on the top die caused by a coefficient of thermal expansion (CTE) mismatch between the dielectric layer and components of the packaged device.

[0052] In some embodiments, the step of forming the cavity in the dielectric layer comprises: adjusting a parameter of the dielectric deposition process during the step of depositing the dielectric layer. In some embodiments, the dielectric deposition process is implemented in a deposition chamber, and further wherein the parameter is a ratio of precursor gases introduced into the deposition chamber during the dielectric deposition process. In some embodiments, the step of forming the cavity in the dielectric layer comprises: etching a groove in a surface of the dielectric layer; and bonding the surface of the dielectric layer to the surface of the bottom substrate simultaneously with the step of bonding the top die to the bottom substrate. In some embodiments, the method further comprises: filling the groove with a gas before the step of bonding the surface of the dielectric layer to the surface of the bottom substrate, the gas selected from the group consisting of air, nitrogen, an inert gas, and a rare gas, and combinations thereof. In some embodiments, the method further comprises: forming the cavity in the dielectric layer to surround the top die. In some embodiments, the method further comprises: forming the cavity in the dielectric layer adjacent to each side of the top die and laterally displaced from each side of the top die.

[0053] Still other embodiments of the present application provide a method for forming a packaged device, the method comprising: mounting an integrated circuit die on a substrate; embedding the integrated circuit die in a protective material; and forming a stress compensation cavity in the protective material, the stress compensation cavity being adjacent to at least one side of the integrated circuit die.

[0054] In some embodiments, the stress compensation cavity is formed in the protective material during the step of embedding the integrated circuit die in the protective material. In some embodiments, the protective material is formed by a deposition process in a deposition chamber, and further wherein the stress compensation cavity is formed by adjusting the ratio of precursor gases in the deposition chamber during the deposition process. In some embodiments, the method further includes: flattening the top surface of the protective material to be flush with the top surface of the integrated circuit die. In some embodiments, the method further includes: filling the stress compensation cavity with a gas selected from the group consisting of air, an inert gas, a rare gas, nitrogen, and a combination thereof. In some embodiments, the method further includes: directly bonding the integrated circuit die to the substrate. In some embodiments, the stress compensation cavity is formed to expose at least one side of the integrated circuit die. In some embodiments, the step of embedding the integrated circuit die in the protective material includes depositing the protective material around the integrated circuit die. In some embodiments, the stress compensation cavity is configured to deform in shape in response to thermal expansion of the protective material. In some embodiments, the method further includes: mounting the bottom surface of the integrated circuit die to a carrier; forming the stress compensation cavity adjacent to the top surface of the integrated circuit die; bonding the top surface of the integrated circuit die to the substrate; and removing the carrier from the bottom surface of the integrated circuit die.

[0055] Still other embodiments of the present application provide a packaging device comprising: a bottom substrate; an integrated circuit die bonded to the bottom substrate; a dielectric layer located above the bottom substrate and at least partially surrounding the integrated circuit die; and an air-filled cavity located within the dielectric layer and adjacent to at least one side of the integrated circuit die.

[0056] In some embodiments, the air-filled cavity is formed adjacent to a corner of the integrated circuit die. In some embodiments, the air-filled cavity is filled with a fluid selected from the group consisting of air, nitrogen, a rare gas, an inert gas, and combinations thereof.

[0057] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a packaged device, the method comprising: bonding the top die to the bottom substrate; depositing a dielectric layer over the bottom substrate and around the top die by performing a dielectric deposition process; as well as A cavity is formed in the dielectric layer, the cavity being adjacent to at least one side of the top die, wherein the cavity is configured to relieve stress on the top die caused by a coefficient of thermal expansion (CTE) mismatch between the dielectric layer and components of the packaged device.

2. The method according to claim 1, wherein: The step of forming the cavity in the dielectric layer comprises: During the step of depositing the dielectric layer, parameters of the dielectric deposition process are adjusted.

3. The method according to claim 2, wherein: The dielectric deposition process is performed in a deposition chamber, and further wherein the parameter is a ratio of precursor gases introduced into the deposition chamber during the dielectric deposition process.

4. The method according to claim 1, wherein: The step of forming the cavity in the dielectric layer comprises: etching trenches in a surface of the dielectric layer; and The surface of the dielectric layer is bonded to a surface of the bottom substrate simultaneously with the step of bonding the top die to the bottom substrate.

5. The method according to claim 4, further comprising: Prior to the step of bonding the surface of the dielectric layer to the surface of the base substrate, the trench is filled with a gas selected from the group consisting of air, nitrogen, an inert gas and a rare gas, and combinations thereof.

6. The method according to claim 1, further comprising: The cavity is formed in the dielectric layer to surround the top die.

7. The method according to claim 6, further comprising: The cavities are formed in the dielectric layer adjacent to and laterally displaced from each side of the top die.

8. A method for forming a packaged device, the method comprising: mounting an integrated circuit die on a substrate; embedding the integrated circuit die in a protective material; as well as A stress compensating cavity is formed in the protective material, the stress compensating cavity being adjacent to at least one side of the integrated circuit die.

9. The method according to claim 8, wherein: The stress-compensating cavity is formed within the protective material during the step of embedding the integrated circuit die in the protective material.

10. A packaging device, comprising: bottom substrate; an integrated circuit die bonded to the base substrate; a dielectric layer over the base substrate and at least partially surrounding the integrated circuit die; as well as An air-filled cavity is located within the dielectric layer and adjacent to at least one side of the integrated circuit die.

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