Method for assembling EIC to PIC to build optical engine

Abstract

The present disclosure relates to a method for assembling an electronic integrated circuit (EIC) to a photonic integrated circuit (PIC) to build an optical engine. A method for preparing an EIC for the assembly of an optical engine is provided. The method involves stacking a CMOS-based EIC wafer onto a short loop / interposer wafer by front-to-back bonding. This stacked configuration is used as a carrier for thin CMOS wafers. Subsequently, the stacked wafer is thinned down to a desired height and subjected to a final via process. In this process, a thick metal layer from the short loop / interposer wafer acts as an etch stop. The stacked EIC wafer may then be diced and attached to the PIC wafer, thereby forming the optical engine.

Description

Technical Field

[0001] The present technology relates to silicon photonic devices and methods for manufacturing the same. Background Art

[0002] The development of high-speed data communications involved in SERDES devices further requires shorter die-to-die interconnect paths, such as using vertical integration techniques to assemble different integrated circuits. For example, optical engines for high-speed data communications can be built using silicon photonics technology, which requires stacking electronic integrated circuits (EICs) and photonic integrated circuits (PICs). 3D stacking of silicon photonics provides a series of advantages including enhanced device density, improved performance, and shorter interconnect lengths, which can result in lower power consumption and latency. As technology nodes continue to advance to 7nm or less, some existing assembly processes may experience various technical challenges and limitations. Therefore, improved methods for assembling EICs to PICs are desirable and are the subject of the present application. Summary of the invention

[0003] In one aspect, the present disclosure provides an integrated circuit, comprising: a first substrate, comprising a first side and a second side; a circuit, disposed on the first side; a first dielectric layer, located on the circuit, the first dielectric layer comprising a first surface; a second dielectric layer, located on the second side, the second dielectric layer comprising a second surface; a first metal layer, embedded in the first dielectric layer, the first metal layer coupled to the circuit; a second metal layer, located on the first surface, the second metal layer coupled to the first metal layer; a first contact, coupled to the second metal layer; a through hole, comprising a first end and a second end, the first end coupled to the first metal layer a third dielectric layer disposed on the third side, the third dielectric layer comprising a third surface; a third metal layer disposed on the third dielectric layer; a second contact coupled to the third metal layer and disposed on the third surface, the second contact coupled to the second end of the through hole, the second surface being in contact with the third surface; a fourth metal layer disposed on the fourth side and on the sidewall to couple to the third metal layer at the bottom; and a third contact coupled to the fourth metal layer.

[0004] In another aspect, the present disclosure provides a method for processing an integrated circuit, the method comprising: providing a first substrate including a first side and a second side; forming a circuit on the first side; forming a first dielectric layer overlying the circuit and the first side, the first dielectric layer including a first surface; forming a first metal layer embedded in the first dielectric layer, the first metal layer coupled to the circuit; forming a second metal layer on the first surface, the second metal layer coupled to the first metal layer; forming a first contact coupled to the second metal layer on the first surface; forming a through hole including a conductive material, the through hole including a first end and a second end, the first end coupled to the first metal layer, the second end located at a first depth deep into the first substrate; processing the second side so that the second end is at the same level as the second surface of the second dielectric layer on the first back side; providing a second substrate including a third side and a fourth side; forming a second metal layer on the third ... three metal layers; forming a third dielectric layer on the third metal layer and the third side, the third dielectric layer including a third surface; forming a second contact coupled to the third metal layer, the second contact being at the same level as the third surface; coupling the third surface to the second surface to join the second substrate to the first substrate; forming a trench having a bottom at a second depth extending from the fourth side into the second substrate, the bottom being the third metal layer; forming a first polyimide layer overlying the sidewalls of the trench and the fourth side; forming a fourth metal layer overlying the first polyimide layer on the sidewalls and the fourth side of the trench, the fourth metal layer being coupled to the third metal layer at the bottom of the trench; forming a second polyimide layer on the fourth metal layer to fill the trench; and forming a third contact coupled to the fourth metal layer on the second polyimide layer on the fourth side.

[0005] In another aspect, the present disclosure provides a method for stacking an electronic integrated circuit onto a photonic integrated circuit, the method comprising: providing a first substrate comprising a first side and a second side, the first side comprising an electronic circuit coupled to a first metal layer in a first dielectric layer, a first contact coupled to a second metal layer at the same level as a first surface of the first dielectric layer, and a through hole comprising a conductive material coupled to both the first metal layer and the second metal layer, the through hole comprising a first end at the first metal layer and a second end at a first depth deep into the first substrate, the second side comprising a second dielectric layer, the second dielectric layer comprising a second surface at the same level as the second end of the through hole; providing a third substrate comprising a third side and a fourth side. Second substrate, the third side includes a second contact coupled to a third metal layer in a third dielectric layer on the third side, the second contact is located at a third surface of the third dielectric layer; the second substrate is coupled to the first substrate so that the second contact is coupled to the conductive material in the second end of the through hole; a groove is formed from the fourth side into the second substrate, the groove includes a bottom located at a second depth, the bottom is the third metal layer; a fourth metal layer is formed overlying the fourth side and the sidewalls of the groove to couple to the third metal layer at the bottom of the groove; and a third contact is formed coupled to the fourth metal layer, the third contact is configured to couple to an electrical contact of a photonic integrated circuit on the third substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The nature and advantages of certain embodiments may be further understood by reference to the remainder of the specification and to the drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to indicate one of multiple similar components. When a reference numeral is cited without specifying an existing sub-label, the reference numeral refers to all such multiple similar components.

[0007] Figure 1 is a snapshot of front-end-of-line (FEOL) process steps of a method for fabricating electronic integrated circuits to build an optical engine according to an embodiment of the present technology.

[0008] Figure 2 Snapshot diagrams of middle-of-line (MOL) and back-end-of-line (BEOL) process steps of a method for fabricating electronic integrated circuits to build an optical engine according to an embodiment of the present technology.

[0009] Figure 3 is a snapshot of through silicon via (TSV) integration process steps of a method for fabricating an electronic integrated circuit to build an optical engine according to an embodiment of the present technology.

[0010] Figure 4 is a snapshot of BEOL and front side contact formation process steps of a method for fabricating an electronic integrated circuit to build an optical engine according to an embodiment of the present technology.

[0011] Figure 5 is a snapshot of front side carrier bonding and flip chip process steps of a method for preparing electronic integrated circuits to build an optical engine according to an embodiment of the present technology.

[0012] Figure 6 is a snapshot of a backside dry polishing process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology.

[0013] Figure 7 is a snapshot of a backside Si recess etch process step of a method for fabricating an electronic integrated circuit to build an optical engine according to an embodiment of the present technology.

[0014] Figure 8 is a snapshot of a backside passivation process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology.

[0015] Fig. 9 is a snapshot of a backside chemical mechanical polishing (CMP) process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology.

[0016] Fig.10 is a snapshot of a step of providing a short loop / interposer wafer of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology.

[0017] Fig.11 is a snapshot of hybrid bonding of short loop / interposer wafers and peeling of carrier wafers in accordance with a method for fabricating electronic integrated circuits to build an optical engine in accordance with an embodiment of the present technology.

[0018] Fig.12 is a snapshot of a trench formation process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology.

[0019] Fig.13 is a snapshot of a backside redistribution layer process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology.

[0020] Fig.14 is a snapshot of a backside contact formation process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. DETAILED DESCRIPTION

[0021] The present invention relates to semiconductor devices and manufacturing methods. In particular, the present invention presents a method for preparing an electronic integrated circuit for assembling an optical engine. The method involves a hybrid front-to-back bonding of a short loop (SL) wafer to a thin CMOS wafer. This bonding process produces a dual substrate stack with an increased total thickness, which enhances its ability to handle wafers. The bonded SL wafer can then be thinned down to a suitable thickness that allows the formation of backside deep trenches or through silicon vias (TSVs). Etch stops are achieved by utilizing a thick metal layer on the front side of the SL wafer. Other embodiments exist.

[0022] The following description is presented to enable one skilled in the art to make and use the invention and to incorporate the invention into the context of a particular application. Various modifications and various uses in different applications will be apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Therefore, the present technology is not intended to be limited to the embodiments presented, but to be given the widest scope consistent with the principles and novel features disclosed herein.

[0023] In the following description, for purposes of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. However, it will be apparent to one skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although different embodiments have different features, it should be understood that features described for one embodiment may also be incorporated into other embodiments. However, by the same token, any single feature or multiple features of any described embodiment should not be considered essential to every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0024] In one example, the term "circuit board" (including references to "main circuit board" and "sub-sized circuit board") (also known as a printed circuit board (PCB)) refers to a flat rigid board made of insulating material (usually fiberglass or plastic) that contains a complex network of metal paths or "traces" that form the circuits of various electronic devices. Components such as resistors, capacitors, and integrated circuits are then mounted on the circuit board and their leads are soldered to the corresponding traces to create a functioning electronic circuit. "Main" or "sub-sized" primarily refers to the lateral dimensions of the circuit board, which is one of the key features of the present disclosure.

[0025] When an element is referred to herein as being "connected" or "coupled" to another element or "in contact with" another surface, it is understood that the element may be directly connected to the other element or have an intermediate element between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element or "in direct contact with" another surface, it is understood that there are no intermediate elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intermediate elements. When an element is referred to herein as being "electrically coupled" to another element, it is understood that the element may be directly connected to the other element via an electrical conductor.

[0026] When an element is referred to herein as being "disposed" or "positioned" in some geometric manner relative to another element (e.g., disposed on, between, below, adjacent to, or in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element), or have an intermediate element between the elements. Specifically, with respect to geometric relationships, the term "on" a substrate material generally refers to a surface attached to the substrate material, and the term "in" a substrate material generally refers to being within a bulk region of the substrate material (e.g., below the surface). In contrast, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intermediate elements in the "direct" example. However, the presence of a direct placement does not exclude other examples where intermediate elements may be present.

[0027] Similarly, when an element is referred to herein as being "joined" to another element, it is understood that the element may be directly joined to the other element (without any intervening elements) or have intervening elements between the joined elements. In contrast, when an element is referred to as being "directly joined" to another element, it is understood that there are no intervening elements in the "direct" joining between the elements. However, the presence of direct joining does not exclude other forms of joining, in which intervening elements may be present.

[0028] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include multiple different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include multiple dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layers may include intermediate elements present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intermediate elements between the layers. However, the presence of directly coupled or connected layers does not exclude other connections where intermediate elements may exist.

[0029] In addition, when the electrical connection element for chip-to-chip or chip-to-board bonding is referred to as a metal "post" in this article, it should be understood that the post is a vertical cylindrical structure protruding from the surface of a substrate or a package substrate or a dielectric layer on a substrate. The post is usually taller than its width, because the post is a general language meaning, and is sometimes designed to have a high aspect ratio with a significant height compared to its width. This provides high-density interconnection and reduces the occupied area required for electrical connection. The post is mainly used as an interconnect for conducting electricity and heat between different layers or components in a semiconductor device or package. Another option is that "pad" refers to a flat planar area on a substrate or a package substrate. "Pad" is usually wider than its height and has a larger surface area. The pad is mainly used as a contact area or landing pad for wire bonding, welding or other bonding techniques. Copper pads are widely used in various semiconductor packaging processes including traditional wire bonding, tape automated bonding (TAB) and flip chip bonding. In addition, "bumps" (such as Cu / Ni / Au bumps) (also referred to as solder bumps or microbumps) are structures for interconnecting in semiconductor packages. Bumps can be based on pads or posts. "Bumps" are commonly used in various semiconductor packaging technologies including flip chip bonding and chip-to-chip interconnection. In addition, in the specification or claims, each of these electrical connection elements is referred to as an "electrical contact" or "conductive contact" or just a "contact", but the electrical connection element can be any of the different types or shapes of elements mentioned above, depending on various packaging processes or applications.

[0030] A "groove" in a silicon layer refers to a vertical or inclined groove or cavity etched or formed in a layer of silicon material. The groove is a feature that can be produced during the manufacturing process of a semiconductor device or integrated circuit. For example, the purpose of the groove in the silicon layer may vary depending on the specific application or design requirements. Optionally, the groove can be used to provide electrical insulation between different components or regions on the silicon substrate. The groove can be used to create a through-silicon via (TSV), which is a vertical interconnect that passes through the silicon layer to connect different layers or chips in a 3D integrated circuit (IC) structure. For example, a metal contact can partially or completely fill the groove (contacting the sidewalls and bottom surfaces of the groove) to provide an electrical connection. TSV provides a path for electrical signals, power or heat between different levels or components in an IC. Optionally, the groove can be engineered to induce stress on the surrounding silicon material, thereby changing its electrical properties. The size, depth, width and aspect ratio of the groove may vary depending on the specific application, device requirements and semiconductor technology node. The trenches are typically formed by a process such as dry or wet etching, in which silicon material is selectively removed or modified using chemical or plasma-based methods.

[0031] An electronic integrated circuit (often referred to simply as an integrated circuit (IC)) is an electronic device that integrates multiple electronic components and circuit elements onto a single chip or substrate. These components may include transistors, resistors, capacitors, and interconnects, among others. EIC technology enables complex electronic functionality (e.g., logic gates, memory cells, analog circuits, or digital signal processing circuits) to be integrated onto a small semiconductor chip. "Electronic circuit" or simply "circuit" may be used herein, but should be considered to include any component of an EIC. EICs are typically made on silicon wafers or simply referred to as "silicon substrates," which include silicon-on-insulator substrates, although other types of substrates may also be used.

[0032] Photonic integrated circuits (PICs) are a type of integrated circuit that focuses on integrating optical or photonic components and functionality onto a single chip or substrate. Unlike EICs, which primarily handle electronic signals, PICs manipulate and process optical signals, thereby exploiting the properties of light for communications, sensing, or other applications. PICs incorporate optical components such as lasers, waveguides, modulators, photodetectors, and multiplexers onto a chip.

[0033] The general packaging of electronic integrated circuits (EICs) and photonic integrated circuits (PICs) involves the integration and assembly of these two different technologies into a single package, thereby realizing their combined functionality and interconnectivity. The packaging process ensures the protection, electrical connection and mechanical stability of the integrated circuit, while facilitating the interaction of the integrated circuit with the outside world.

[0034] The EIC and PIC chips that have been made separately are ready for packaging. Suitable substrates or carrier materials are selected to mount the EIC and PIC chips. Common substrate materials include semiconductors (such as silicon or other), ceramics, organic laminates, or specialized materials with desired electrical and thermal properties. The EIC and PIC chips are bonded to the substrate using techniques such as flip chip bonding or adhesive bonding. This ensures a firm attachment and establishes an electrical connection between the chip and the substrate. Wire bonding or flip chip interconnection is used to establish an electrical connection between the EIC and PIC chips and the substrate. Wire bonding involves attaching a fine wire between the bonding pads of the chip and the corresponding pads on the substrate. Flip chip interconnection utilizes solder bumps or metal bumps on the chip to directly connect to the corresponding pads on the substrate. For example, as used in flip chips, metal bumps refer to small metal bumps deposited on the surface of the die to provide electrical connections, and the metal bumps should not limit the scope of the claims. The wafers are then cut, and the wafers are flipped and positioned so that the solder balls are aligned with the substrate pads 1. Standard flip chip processing uses pre-mixed solder paste for solder bumps, providing significant control over the alloy composition across the wafer 23 .

[0035] The bonded chips and interconnects are encapsulated with protective materials such as epoxy or resin-based compounds. External interconnects are established to connect the packaged EIC and PIC to the outside world. These interconnects may include wire bonding, solder balls or other suitable connection methods. The interconnects provide electrical paths for power, signal and data transmission to or from the packaged integrated circuit. The packaged EIC and PIC are usually mounted on larger carriers or substrates such as printed circuit boards (PCBs) or modules to facilitate integration into larger systems or electronic devices. Specific packaging techniques, materials and interconnection methods may vary depending on the specific requirements of the EIC and PIC and the target application. Advanced packaging technologies such as system-level packaging (SiP) or multi-chip modules (MCM) or 3D stacking of silicon photonics can be used to further enhance integration and functionality.

[0036] Moreover, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, the terms are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0037] In addition, for ease of description, the methods and processes described herein may be described in a specific order. However, it should be understood that unless the context otherwise requires, intermediate processes may occur before and / or after any portion of the described process, and that various additional procedures may be reordered, added, and / or omitted according to various embodiments.

[0038] Unless otherwise indicated, all numbers used herein to express quantities, sizes, and the like are to be understood as being modified by the term "about" in all instances. In this application, the use of the singular includes the plural unless otherwise specifically stated, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. Moreover, the use of the terms "including" and "having" as well as other forms such as "includes," "included," "has," "have," and "had" are to be considered non-exclusive. At the same time, unless otherwise expressly stated, terms such as "element" or "component" cover both elements and components that include one unit and elements and components that include more than one unit.

[0039] As used herein, the phrase "at least one of" preceding a series of items, where the terms "and" or "or" are utilized to separate any of the items, modifies the list as a whole, rather than modifying each member of the list (i.e., each item). The phrase "at least one of" does not require selection of at least one of each of the listed items; rather, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of the items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where the intended selection is "at least one of each of A, B, and C" or the other selection is "at least one of A, at least one of B, and at least one of C," it is explicitly described as such.

[0040] One general aspect includes an integrated circuit. The integrated circuit includes a first substrate, which may include a first side and a second side. The circuit also includes a circuit disposed on the first side. The circuit also includes a first dielectric layer located on the circuit, which may include a first surface. The circuit also includes a second dielectric layer located on the second side, which may include a second surface. The circuit also includes a first metal layer embedded in the first dielectric layer, the first metal layer coupled to the circuit. The circuit also includes a second metal layer located on the first surface, the second metal layer coupled to the first metal layer. The circuit also includes a first contact coupled to the second metal layer. The circuit also includes a through hole, which may include a first end and a second end, the first end coupled to the first metal layer, and the second end located on the second surface and coupled to the second dielectric layer. The circuit also includes a second substrate, which may include a third side and a fourth side. The circuit also includes a third dielectric layer located on the third side, the third dielectric layer may include a third surface. The circuit also includes a third metal layer located on the third dielectric layer. The circuit also includes a second contact coupled to the third metal layer and located on the third surface, the second contact coupled to the second end of the through hole, the second surface contacting the third surface. The circuit also includes a fourth metal layer, the fourth metal layer is located on the fourth side and the sidewall of the trench passing through the second substrate to couple to the third metal layer at the bottom of the trench. The circuit also includes a third contact coupled to the fourth metal layer.

[0041] The implementation scheme may include one or more of the following features. The first contact may include a metal bump configured to couple to an electrical contact on a printed circuit board. The first substrate may include a silicon wafer having a first thickness in the range of 10um to 12um. The second substrate may include a silicon wafer having a second thickness of 75um or greater. The second contact may include a metal bump. The integrated circuit may include a dual substrate stack formed by a dielectric bond between a second dielectric layer and a third dielectric layer and a metal bond between a metal pad and a second end of a through hole. For example, a "metal pad" refers to a small metal area for making an electrical connection between two different parts of an integrated circuit, and different shapes and metal materials may be used. The third contact may include a metal column with a solder cap, the metal column being configured to couple to an electrical contact of a photonic integrated circuit on a third substrate. The third contact may include a copper column configured to couple to an electrical contact on a photonic integrated circuit.

[0042] Another general aspect includes a method for processing an integrated circuit. The method includes providing a first substrate that may include a first side and a second side. The method also includes forming a circuit on the first side. The method also includes forming a first dielectric layer on the circuit and the first side, the first dielectric layer may include a first surface. The method also includes forming a first metal layer embedded in the first dielectric layer, the first metal layer coupled to the circuit. The method also includes forming a second metal layer on the first surface, the second metal layer coupled to the first metal layer. The method also includes forming a first contact coupled to the second metal layer on the first surface. The method also includes: forming a through hole that may include a conductive material, the through hole may include a first end and a second end, the first end coupled to the first metal layer, the second end located at a first depth deep into the first substrate; processing the second side so that the second end is at the same level as the second surface of the second dielectric layer on the second side. The method also includes providing a second substrate that may include a third side and a fourth side. The method also includes forming a third metal layer on the third side. The method also includes forming a third dielectric layer on the third metal layer and the third side, the third dielectric layer may include a third surface. The method also includes forming a second contact coupled to the third metal layer, the second contact being at the same level as the third surface. The method also includes coupling the third surface to the second surface to join the second substrate to the first substrate. The method also includes forming a trench having a bottom at a second depth extending from the fourth side into the second substrate, the bottom being the third metal layer. The method also includes forming a first polyimide layer on the sidewalls and the fourth side of the trench. The method also includes forming a fourth metal layer on the sidewalls and the first polyimide layer on the fourth side of the trench, the fourth metal layer coupled to the third metal layer at the bottom of the trench. The method also includes forming a second polyimide layer overlying the fourth metal layer to fill the trench. The method also includes forming a third contact coupled to the fourth metal layer on the second polyimide layer on the fourth side.

[0043] Embodiments may include one or more of the following features. A method wherein the first contact may include a Cu / Ni / Au bump may include coupling the Cu / Ni / Au bump to an electrical contact on a printed circuit board. Processing the first back side may include: coupling a carrier substrate to the first side by an adhesive material, the adhesive material being applied to the first contact on the first side and the first surface of the first dielectric layer; and thinning the first substrate so that the second side is located 5um to 10um above the second end of the through hole. The second dielectric layer may include an oxide material layer and a nitride material layer. The method may include thinning the second substrate from the fourth side by dry polishing. The method may include peeling the carrier substrate from the first side of the first silicon substrate by a laser to expose the first contact on the first surface, the first contact being configured to couple to the electrical contact on the printed circuit board. Coupling the third surface to the second surface may include: aligning the second contact with the second end of the through hole; forming a dielectric bond between the second dielectric layer and the third dielectric layer when the third surface contacts the second surface at a first temperature; forming a metal bond between the second contact and the second end of the through hole by annealing the second substrate and the first substrate at a second temperature, the second temperature being higher than the first temperature; and forming a dual substrate stack. Forming a trench extending from the second back side into the second substrate may include: etching from a fourth side to form a trench having an initial depth; depositing a first polyimide layer at least on a sidewall of the trench and on the fourth side; and alternately repeating etching and deposition to increase the depth of the trench from the initial depth to a second depth until etching is stopped by the third metal layer.

[0044] Yet another general aspect includes a method for stacking an electronic integrated circuit to a photonic integrated circuit. The method includes providing a first substrate that may include a first side and a second side, the first side including an electronic circuit coupled to a first metal layer in a first dielectric layer, a first contact coupled to a second metal layer at the same level as a first surface of the first dielectric layer, and a through hole that may include a conductive material coupled to both the first metal layer and the second metal layer, the through hole may include a first end at the first metal layer and a second end at a first depth deep into the first substrate, the second side including a second dielectric layer, the second dielectric layer including a second surface at the same level as the second end of the through hole. The method also includes providing a second substrate that may include a third side and a fourth side, the third side including a second contact coupled to a third metal layer in a third dielectric layer, the second contact being at a third surface of the third dielectric layer. The method also includes coupling the second substrate to the first substrate such that the second contact is coupled to the conductive material in the second end of the through hole. The method also includes forming a trench deep into the second substrate from the fourth side, the trench may include a bottom at the second depth, the bottom being the third metal layer. The method also includes forming a fourth metal layer on the fourth side and the sidewalls of the trench to couple to the third metal layer at the bottom of the trench. The method also includes forming a third contact coupled to the fourth metal layer, the third contact being configured to couple to an electrical contact of the photonic integrated circuit on the third substrate.

[0045] Embodiments may include one or more of the following features. The method may include: coupling the first surface to a carrier substrate; and thinning the first substrate downward from the second side to reduce the first thickness of the first substrate to no less than a first depth of the through hole. Coupling the second substrate to the first substrate may include: forming a dielectric bond between a third dielectric layer and a second dielectric layer by pressing the third surface to contact the second surface at a first temperature; forming a metal bond between the second contact to the conductive material in the second end of the through hole by annealing at a second temperature, the second temperature being higher than the first temperature; and thinning the second substrate from a fourth side to reduce the second thickness of the second substrate to no less than a second depth. The method may include: forming a first polyimide layer on the second back side and the sidewalls of the trench; forming a fourth metal layer overlying the first polyimide layer and coupled to the third metal layer at the bottom of the trench; and forming a second polyimide layer overlying the fourth metal layer.

[0046] For the purpose of building an optical engine, an electronic integrated circuit (EIC) or (or simply referred to as an integrated circuit, or "IC") needs to be prepared first. The EIC wafer from the foundry is usually full thickness and needs to go through several backside wafer processing steps before assembly. The wafer processing steps vary based on the technology node of the wafer and assembly process used to build the optical engine. For example, the use of through-silicon vias (TSVs) by the last via or intermediate via method is the main way to prepare EICs for stacking with photonic integrated circuits (PICs). For example, the last via method may require larger vias, which requires that the etch stop layer in the lower back-end process (BEOL) metal layer is thick enough to withstand the metal consumption during the etching process. In advanced technology nodes (such as the 7nm node), the BEOL layer is thin to a thickness of about 32nm that will be completely etched away in the TSV last process. Etching all the way to the thick metal layer can cause BEOL reliability issues, such as cracks in ultra-low-k dielectrics. Therefore, the existing methods of the last via process have become incompatible with the latest chip technology advances.

[0047] Alternatively, the intermediate via approach can be trimmed for integration into any BEOL layer at the foundry. However, the TSV diameter is proportional to the mechanical stress and usually comes with specific keep-out zone (KOZ) rules. Larger TSVs also have a Cu overload layer that requires a double annealing process and CMP for planarization. Scaling the TSV aspect ratio directly affects the silicon thickness and downstream assembly processes. For TSVs of 7nm and below, the silicon substrate thickness drops to <10um. 3D stacking such an EIC to a PIC and attaching the EIC to a circuit board is a challenge because the thin silicon causes the die to warp and may break when bonding forces are applied.

[0048] Some existing methods use fan-out wafer level packaging to assemble EICs with PICs to build optical engines. The optical engine needs to be reconstructed on a fan-out wafer with a bottom-side redistribution layer (RDL) and through-mold vias (TMVs) after a fully processed EIC. The front-side RDL layer is then processed, raised, and ready for assembly. However, this approach increases the die size of the EIC because all connections to the substrate have passed through the TMVs on the edge of the EIC. This may also cause problems with chip warpage due to the imbalance of the polyimide layer of the double-sided RDL layer.

[0049] In the present disclosure, an improved method for preparing an EIC before stacking with a PIC for building an optical engine is proposed. In a specific embodiment, the EIC is an electronic integrated circuit (IC) based on a complementary metal oxide semiconductor (CMOS) manufacturing process. A CMOS wafer with TSVs is pre-made from a foundry. The CMOS wafer is then hybrid-bonded to an intermediate wafer using front-to-back bonding to form a dual-wafer stack. The intermediate wafer acts as a carrier for the thin CMOS wafer. The dual-wafer stack is then thinned down to the desired height and subjected to a TSV final process, in which an etch stop is accomplished using a thick metal layer pre-formed from the intermediate wafer. The stacked die reinforced based on the dual-wafer stack can then be cut and attached to the PIC die to form an optical engine.

[0050] In some embodiments, a method of preparing an electronic IC for building an optical engine prior to stacking with a photonic IC is illustrated below using a series of snapshot diagrams of key process steps. Figure 1 1 is a block diagram of the front-end-of-line (FEOL) process steps of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This figure is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. The electronic integrated circuit (EIC) is generally based on a silicon substrate 100. In a specific embodiment, the silicon substrate 100 is introduced as an incoming blanket Si wafer having a front side 101 and a back side 102. The silicon substrate 100 is also referred to as a first substrate. The front side 101 is also referred to as a first side, and the back side 102 is also referred to as a second side opposite to the first side. One or more electronic circuits 110 associated with the EIC are fabricated on the front side 101 after the front-end process.

[0051] As an example, the front-end-of-line (FEOL) process in semiconductor manufacturing refers to the initial stages of IC fabrication, where semiconductor wafers are processed to create transistor devices and their associated components. After wafer cleaning, the substrate surface (at the front side 101) is prepared for subsequent processing steps, which include: growing or depositing a thin layer of dielectric material; applying photoresist; performing photolithography; performing etching to selectively remove material at exposed areas; performing doping to modify the electrical properties of the semiconductor material; performing thermal treatment; performing metal deposition to form interconnects; and performing planarization to ensure a flat and smooth surface in which the electronic circuits are embedded, such as Figure 1 As shown in .

[0052] Figure 2is a snapshot diagram of the middle of the line (MOL) and back end of the line (BEOL) process steps of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. FEOL process ( Figure 1 ) lays the foundation for the creation of semiconductor devices, forming transistors, interconnects, and basic components on the wafer. This is followed by middle-of-line (MOL) processes and back-end-of-line (BEOL) processes, in which further interconnections, packaging, and testing are performed to complete the semiconductor device. MOL contacts are key components in semiconductor manufacturing, and the MOL contacts serve as vertical electrical connections between different metal layers in the EIC. These contacts provide a means for signal propagation and interconnection between various components on the EIC. In some embodiments, Figure 2 The snapshot illustrations shown in FIG. 1 also include results from back-end-of-line (BEOL) processes for forming interconnects or wiring to couple electronic circuits to complete the EIC at the front side 101 of the silicon substrate 100. Figure 2 As shown in , on the front side 101, several metal layers are formed to extend to multiple locations in the 2D plane and are connected through vias in the vertical direction on top of the previously formed electronic circuit 110. These metal layers and vias are generally represented by the number 120 and are configured as a metal wiring layer to couple to the electronic circuit 110. Typically, the metal material in the metal layers and vias includes copper, but it should be understood that other materials including metal alloys may also be used depending on the application. After the metal layer, a low-k dielectric material is deposited onto the wafer surface. For example, a dielectric material refers to an electrical insulator that can be polarized by an applied electric field; a low-k dielectric is a material with a small κ (less than 4) that can reduce parasitic capacitance and crosstalk between interconnects. As an example, the dielectric layer may include one or more layers of dielectric material. This dielectric layer serves as an insulating material between metal layers. In Figure 2 , this dielectric layer is represented by a first dielectric layer 125 on the first side 101. For example, the first dielectric layer is silicon dioxide (SiO2). The formation process may involve dielectric deposition, via patterning, etching, linear deposition (for barriers or adhesion promoters between metal layers), seed layer deposition, metal plating, and chemical mechanical polishing (CMP).

[0053] Figure 31 is a snapshot of a through silicon via (TSV) integration process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This figure is merely an example, and the example should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. At the end of the BEOL process, the last metal (Cu) layer of the metal wiring layer 120 may be formed at the surface of the front side 101. A through silicon via 130 with a depth of d1 may be formed from the surface of the front side 101 into the silicon substrate 100 in an intermediate via process, thereby aiming to form an interconnection of the EIC. Based on advanced etching techniques including deep reactive ion etching, inductively coupled plasma etching, cryogenic etching, etc., this through silicon via is characterized by a high aspect ratio, such as 20:1 or higher. The depth d1 may be as large as 10um, corresponding to a diameter of 0.5um or less.

[0054] Figure 4 is a snapshot diagram of the BEOL and front-side contact formation process steps of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. Figure 4A process of filling a conductive material 135 into the through-silicon via 130 is shown. The conductive material 135, typically Cu, is at least partially added to the through-silicon via 130 to form an interconnect in which a first end 135A is located at the surface and a second end 135B extends deep into the through-silicon substrate 100. Furthermore, an additional BEOL process is performed on the surface to form an additional metal wiring layer, the additional metal wiring layer including a first metal layer 136 embedded in the first dielectric layer 125. The first metal layer 136 is configured to couple to the first end 135A of the interconnect, which is also coupled to the metal wiring layer 120 formed in the previous MOL+BEOL process. The additional BEOL process also adds a first dielectric layer 125' to have a first surface above the first metal layer 136, and further forms a second metal layer 137 embedded in the first surface of the first dielectric layer 125'. A first conductive contact 140 may be formed on the second metal layer 137 protruding above the first surface. This is a conductive contact formed at the front side 101, the purpose of which is to couple the electrical contacts on the circuit board when the EIC chip is installed for building an optical engine. In one embodiment, the second metal layer 137 is made of aluminum by electroplating. The first conductive contact 140 can be formed as a Cu / Ni / Au bump. The formation process involves applying a photoresist to mask the surface of the second metal layer 137, patterning to form an exposed area, depositing a Cu layer metal on the exposed area by PVD or electroplating, depositing Ni metal to form a barrier layer on the Cu layer, and depositing an Au layer on the top to provide good conductivity and serve as a protective layer. Although the Cu / Ni / Au bump will eventually be used to mount the EIC on the circuit board, the soldering material (e.g., Sn or Ag) is not applied on top of it. After the Cu / Ni / Au bump is formed, a passivation layer can be added to cover the front side 101. In one embodiment, the passivation layer includes a silicon nitride layer and / or a silicon dioxide layer.

[0055] Figure 5 Snapshot diagram of front-side carrier bonding and flip chip process steps for preparing electronic integrated circuits to build an optical engine according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. Figure 5The process of flipping the first silicon substrate 100 to bond the front side 101 to the surface 201 of the carrier substrate 200 is shown. Before bonding, a thin silicon dioxide (SiO2) layer 145 is grown on the surface of the front side 101, for example, as a passivation layer covering the first dielectric layer 125' and the first surface of the first conductive contact 140 (e.g., Cu / Ni / Au bump). This thin silicon dioxide layer 145 can be applied using a rapid thermal processing (RTP) system. The oxide layer acts as an insulating layer and promotes bonding. Optionally, an adhesive material such as an epoxy-based adhesive or polyimide can be applied on the first surface to enhance the bonding between the carrier substrate and the first substrate. Then, the silicon substrate 100 and the carrier substrate (usually a glass wafer) are pressed together at a first temperature (e.g., room temperature) to perform dielectric bonding (e.g., anodic bonding) in a chamber with a suitable pressure (usually in the range of hundreds of Pascals to thousands of Pascals). For example, dielectric bonding refers to the process of bonding two materials together using a dielectric material, and it should be understood that other types of bonding are also possible mechanisms and methods. The dielectric material is typically an oxide or nitride that is deposited on the surface of a wafer and then bonded to another wafer using heat and pressure. Dielectric bonding is used in many applications including wafer-level packaging, MEMS devices, and 3D integration in semiconductor manufacturing. In addition, an annealing process is performed at a second temperature (e.g., in the range of 300° C. to 450° C.) to promote the migration of ions across the interface and promote the formation of a strong bond between the silicon substrate and the carrier substrate. The back side 102 of the silicon substrate 100 is now located on top to allow any backside processes to be performed. The silicon substrate has a thickness h1 (typically >200um), and the depth d1 of the through-silicon via 135 filled with a conductive material is just about 10um to 12um.

[0056] Figure 6 1 is a snapshot of a backside dry polishing process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This figure is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. In the case of using a carrier substrate 200 as a handling substrate, the silicon substrate 100 can be thinned downward from the back side (i.e., the second side) 102. Figure 6The thickness of the silicon substrate 100' is shown to decrease from h1 to h2. Optionally, the thinning process is performed by dry polishing to reduce the thickness h2 to about 20um, and the back side 102 is located just 5um to 10um above the second end 135B of the conductive material in the through-silicon via 135 while using the carrier substrate 200 as a handling substrate. As an example, the thinning process can be performed in various ways such as mechanical grinding, chemical mechanical polishing (CMP), plasma etching, and / or other ways. Without bonding the carrier substrate, directly thinning the silicon substrate 100' to tens of microns may risk causing the substrate to warp or crack.

[0057] Figure 7 1 is a snapshot of a backside Si recess etching process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This figure is merely an example, and the example should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. In the case of using a carrier substrate as a handling substrate, the backside (second side) 102 of the silicon substrate 100' can be further processed for Si recess etching to expose the second end 135B of the conductive material 135 in the through-silicon via. Figure 7 The second end 135B of the conductive material 135 is shown protruding from the (new) surface at the back side 102 of the silicon substrate 100″ after the recess etching process to selectively lower the silicon surrounding the conductive material (e.g., Cu) to the desired recess depth. The recess etching process can use a dry etching technique such as reactive ion etching or a wet etching technique such as potassium hydroxide etching.

[0058] Figure 8 is a snapshot of a backside passivation process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This figure is merely an example, and the example should not unduly limit the scope of the claims. A person skilled in the art will recognize many variations, substitutions, and modifications. In the case of using a carrier substrate as a handling substrate, the backside (second side) 102 of the silicon (first) substrate 100" is further processed to form a passivation layer overlying the backside with a protruding conductive material at the second end 135B. Optionally, the passivation layer includes one or more dielectric materials. For example, first, the passivation layer includes a silicon nitride (Si3N4) layer 155, or it is followed by a silicon dioxide (SiO2) layer 156 at the topmost surface. This passivation layer (also referred to as the second dielectric layer in this application) helps to ensure the integrity and reliability of the interconnections on the surface of the backside 102. The exposed silicon is shielded from environmental factors by the passivation layer, thereby preventing oxidation and minimizing the risk of surface contamination. The passivation layer also prevents electrical shorts between adjacent interconnects or with other conductive elements.

[0059] Fig. 9 1 is a snapshot of a backside chemical mechanical polishing (CMP) process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This figure is merely an example, and the example should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. A chemical mechanical polishing (CMP) process is further performed on the backside 102 to make the second end 135B of the conductive material of the through silicon via flush with the surface of the passivation layer 156 at the backside 102. Fig. 9 , the silicon (first) substrate (target wafer) having through-silicon vias as 3D interconnects 135 has a thickness h2 of only 10 to 12 um and is very easy to break if there is no support from the carrier substrate 200. The interconnects 135 have their second ends 135B exposed at the back side 102 so that they can be used for coupling with an interposer wafer introduced in the next process step.

[0060] Fig.10 is a snapshot diagram of the steps of providing a short loop / interposer wafer in a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. Fig.10 Process steps for introducing a second silicon substrate 300 as an interposer wafer having a second front side 301 and a second back side 302 are shown. The second silicon substrate 300 is also generally referred to as a second substrate. The second front side 301 of the second substrate is also referred to as a third side 301. The second back side 302 is also referred to as a fourth side 302. This interposer wafer is intended to provide an interposer or interconnect between different wafers or substrates. Compared to the first silicon substrate 100, which is an incoming CMOS wafer (usually from a foundry) with electronic circuits formed therein, the second silicon substrate 300 is a short loop wafer used in a later stage assembly process. In some embodiments, the second silicon substrate 200 is introduced for assisting the back side processing of the first silicon substrate to complete the preparation of the electronic integrated circuit for stacking with the photonic integrated circuit to build an optical engine.

[0061] In a specific embodiment, a second silicon substrate having its front side 301 pre-processed to form at least a third metal layer 340 is provided, wherein a second conductive contact 350 is coupled on top and embedded in a third dielectric layer 345 overlying the front side surface. Optionally, the metal layer 340 can be aluminum formed by electroplating up to a sufficiently large thickness, because the metal layer is intended to be used as an etch stop layer and a conductor for forming an interconnect through the second silicon substrate 300. Optionally, the second conductive contact 350 is provided as a copper material, in particular a hybrid bonding Cu pad embedded in and flush with the surface of the third dielectric layer 345. The third dielectric layer 345 covers the third metal layer 340 and isolates the hybrid bonding Cu pad 350. Optionally, the surface of the dielectric layer 345 and the exposed second end 135B of the conductive via are CMP polished. Both the Cu pad 350 and the third dielectric layer 345 serve as a hybrid bonding element between the second silicon substrate 300 and the first silicon substrate 100. Optionally, the second silicon substrate 300 mentioned above is introduced with its full thickness h0. Another option is that the second silicon substrate 300 is introduced, wherein its thickness h0 is thinned down to about 75um (varies in the range of several um) to facilitate the process of forming a through-silicon deep trench with a high aspect ratio within the scope allowed by technology, thereby limiting the lateral size of the trench to meet the circuit design requirements.

[0062] Fig.11Snapshot diagram of hybrid bonding of short loop / intervening layer wafers and peeling of carrier wafers according to a method for preparing electronic integrated circuits to build an optical engine according to an embodiment of the present technology. This figure is merely an example, and the example should not unduly limit the scope of the claims. A person skilled in the art will recognize many variations, substitutions, and modifications. As shown, the front side (third side) 301 of the second silicon substrate 300 is flipped down to attach to the back side (second side) 102 of the first silicon substrate 100. In one embodiment, the second conductive contact 350 on the front side 301 is aligned with the conductive material at the second end 135B of the through-silicon via interconnect 135 at the back side 102. Since the front side 301 of the second silicon substrate 300 is in physical contact with the back side 102 of the first silicon substrate 100, the third dielectric layer 345 is first in direct physical contact with the second dielectric layer 156. In one embodiment, the two polished surfaces of the third dielectric layer 345 and the second dielectric layer 156 in direct contact at room temperature can result in dielectric bonding. Additional pressure can be applied to strengthen the dielectric bonding. In another embodiment, due to thermal expansion, the second conductive contact 350 may have made physical contact or will make contact after annealing the two substrates at an elevated temperature (e.g., in the range of 400° C. to 500° C.). The elevated temperature helps promote diffusion and mixing of Cu atoms from both the Cu pad 350 and the second end 135B at the contact interface to form a strong metal bond. Annealing also helps activate the dielectric bonding process and promotes the formation of a strong bond between the oxide surfaces. Finally, the hybrid bonding process results in the formation of a dual substrate stack of the first silicon substrate and the second silicon substrate.

[0063] Optionally, the second silicon substrate 300 is processed from the back side (fourth side) 302 to reduce its thickness from full thickness down to about 75um. The thinning process can be performed using a carrier substrate as a handling substrate. In other words, before the carrier substrate 200 is subjected to the stripping process, the thinning process of the second substrate 300 is optionally performed.

[0064] In another embodiment, if Fig.11 , after hybrid bonding of the second silicon substrate 300 and the first silicon substrate 100, the carrier substrate 200 (e.g., a glass wafer) is peeled off from the front side 101 of the first silicon substrate 100. The laser lift-off technique is used to separate the bonded materials at the interface between the carrier substrate 200 and the front side of the first silicon substrate 100 by selectively heating and weakening the bonding interface using laser energy. Specifically, laser pulses are applied to the adhesive material 145 (see FIG. 1 ) in a controlled manner. Fig. 9) or adhesive layer, thereby causing local heating and softening or weakening of bonding. The process is carefully optimized to ensure effective wafer peeling, while minimizing any damage or residual stress on the front side 101 place conductive contact 140 of the first silicon substrate 100. Once the bonding strength is fully weakened, the bonding adhesive material 145 can be separated from the front side 101 by applying gentle mechanical force or applying other separation techniques. After separation, it may be necessary to remove or remove any residue from adhesive or adhesive material on the surface at the front side 101 place. The total thickness h3 of the resulting double substrate stack is optionally in the scope of 80 to 87um, thereby providing a more solid substrate for performing the last through hole process without causing the wafer to warp or break.

[0065] Fig.12 is a snapshot diagram of a groove forming process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This diagram is merely an example, and the example should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. Fig.12 The trench formation process or essentially the last through-hole process from the back side 302 of the second silicon substrate 300 is shown to be performed. In a specific embodiment, a deep reactive ion etching (DRIE) technique is used to etch silicon from a portion 330A of the back side 302 to form a deep trench 330 of a depth d2 from the back side 302 into the second silicon substrate 300 until the etching process is stopped at the bottom 331 by the third metal layer 340 formed on the front side 301. In principle, the trench 330 is similar to a through silicon via, except that the lateral dimension L of the trench (i.e., the lateral dimension of the portion of the back side) can be much larger than the lateral dimension of a typical through silicon via with a high aspect ratio. The aspect ratio of the trench 330 can be relaxed to avoid being too close to other circuits because the second silicon substrate 300 is essentially provided as a blanket wafer. Since the second silicon substrate 300 has been thinned down from its full thickness to about 75um, the deep trench 330 can be formed to have a lateral dimension L of 60um compared to its 75um depth. In addition, the 75um thickness provides the second silicon substrate with sufficient mechanical rigidity and strength to avoid wafer warping or cracking during the DRIE process. The large lateral dimension of the trench facilitates the subsequent passivation process and the formation of the redistribution layer inside the trench. Because the third metal layer 340 is formed with a large thickness at the front side 301 of the second silicon substrate 300 (see Fig.10), so the third metal layer provides enough metal material to withstand the etching metal consumption and stop the etching process to form deep trenches 330 (or through silicon vias) in the second silicon substrate 300. This method solves the big problem of the lower BEOL layer not being thick enough in some existing last via process methods, and also solves another problem of stress-induced wafer warpage and cracking due to the scaling of TSV aspect ratios in thin (about 10um) CMOS wafers from foundries based on advanced (7nm or lower) technology nodes.

[0066] Fig.13 is a snapshot diagram of a backside redistribution layer process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. Fig.13 The structure of the backside redistribution layer based on the deep trench 330 is shown, and the structure is formed by multiple steps, including passivating the first polyimide layer 331, which covers the entire surface except the trench portion 330A (see FIG. Fig.12 ) and all inner sides except a portion 340A of the bottom of the groove. The bottom of the groove is actually a third metal layer 340 formed at the front side 301, which is now attached to the back side 102 of the first silicon substrate 100. The first polyimide layer 331 is an organic substance with excellent dielectric properties, thermal stability and chemical resistance. The organic substance can be applied by uniformly coating on complex or uneven surfaces using various techniques such as spin coating, spray coating or chemical vapor deposition (CVD). In this embodiment, the thickness of the first polyimide layer 331 can be 20um. The bottom portion 340A of the groove can be masked initially, and then the mask can be lifted later.

[0067] Fig.13 It is also shown that the fourth metal layer 332 is then coated over the first polyimide layer 331 along the sidewalls of the trench and the backside surface except for the trench portion. The fourth metal layer 332 is also coated over the bottom portion 340A of the trench to couple with the third metal layer 340. In one embodiment, the fourth metal layer 332 is Cu applied by electroplating and serves as an electrical redistribution layer to connect the electronic circuits in the front side 101 of the first silicon substrate 100 through the third metal layer 340, the second conductive contact 350, the conductive interconnect 135, the first metal layer 136, and the metal wiring layer 120. The fourth metal layer 332 is also laid along the sidewalls of the trench to extend over the backside 302. In addition, as shown in FIG. Fig.13, a second polyimide layer 333 is applied to fill the trenches and overlie the fourth metal layer 332 except for selected portions 332A thereof on the backside 302 or any exposed portions of the first polyimide layer 331 on the backside 302. The second polyimide layer 333 also planarizes the backside 302 at the end of the passivation process. Optionally, after the entire surface of the fourth metal layer 332 is first covered with the second polyimide layer 333, the selected portions 332A of the fourth metal layer 332 can be exposed a second time by etching away the polyimide material to form a cavity 360.

[0068] In another embodiment, the etching is performed to form Fig.12 The trench shown in FIG. 1 is similar to the trench shown in FIG. 1 and the trench shown in FIG. 2 in which the (first) passivation layer is applied to the substrate in a cyclic etch / passivation process. Fig.13 . For the etching step, a reactive gas is introduced and a radio frequency (RF) power source is used to generate a plasma to induce a chemical reaction between the gas and the silicon, thereby producing a volatile residual gas that is pumped out. This step removes a certain amount of silicon from a portion of the second back side 302 by etching to form a groove with an initial depth. For the passivation step, a polyimide gas is introduced and a thin polymer layer is deposited on the trench sidewalls and the mask to protect the trench sidewalls and the mask from further etching. This polyimide layer prevents lateral etching and allows the trench to become deeper. The etching and passivation steps are repeated cyclically until the desired trench depth is reached. Each cycle typically removes silicon to a specific depth, allowing precise control of the trench depth. Once the etching reaches the metal stop layer, i.e., the third metal layer 340, the metal acts as an etching stop. Once the metal stop layer (which can be aluminum (Al), tantalum (Ta) or other suitable metal) reaches such Fig.12 At the (second) depth d2 shown in FIG. 5 , the metal stop layer prevents further etching into the substrate.

[0069] Fig.14 is a snapshot of a backside contact formation process step of a method for preparing an electronic integrated circuit to build an optical engine according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. Fig.14 A third conductive contact 360 is shown formed at the second back side 302 of the second silicon substrate 300. In essence, the third conductive contact 360 serves as a back side contact of the electronic integrated circuit (EIC) in the dual substrate stack, which will be used to bond the photonic integrated circuit (PIC) on top.

[0070] After forming the exposed portion 332A of the fourth metal layer 332 (see Fig.13), a seed layer 361 may be first deposited so as to overlie the exposed portion 332A plus some sidewall regions and upper edge regions of the cavity 360. Then, a metal electroplating process is performed to form a metal pillar 362 on the seed layer 361. In one example, the metal pillar comprises a Cu material and is characterized by a shape in which the height is equal to or greater than the width, which is a design used as an interconnect within a device or package. Copper pillars enable high-density interconnectivity and are very common in advanced packaging technology. In addition, a barrier layer 363 is formed overlying the top surface of the metal pillar 362 to serve as a diffusion barrier for the metal in the metal pillar 362. Optionally, the barrier layer 363 comprises Ni as a good diffusion barrier for Cu in the metal pillar 362. On top of the barrier layer 363, a surface protection layer 364 is formed to provide protection against oxidation and corrosion. Optionally, the protection layer comprises gold. Additionally, solder bumps 365 may be added on top of the surface protection layer 364 to complete the third conductive contact 360 at the back side of the EIC dual substrate stack. Fig.14 The third conductive contact 360 is shown electrically coupled to the electronic circuit 110 of the EIC dual substrate stack. The third conductive contact 360 is ready to engage with a corresponding contact of the PIC chip.

[0071] While the above is a complete description of specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present technology as defined by the appended claims.

Claims

1. An integrated circuit, comprising: A first substrate comprising a first side and a second side; a circuit disposed on the first side; A first dielectric layer located on the circuit, the first dielectric layer comprising a first surface; a second dielectric layer on the second side, the second dielectric layer comprising a second surface; a first metal layer embedded in the first dielectric layer, the first metal layer coupled to the circuit; a second metal layer located on the first surface, the second metal layer coupled to the first metal layer; a first contact coupled to the second metal layer; a via including a first end and a second end, the first end being coupled to the first metal layer, and the second end being located on the second surface and coupled to the second dielectric layer; A second substrate comprising a third side, a fourth side and a trench, wherein the trench comprises a sidewall and a bottom; a third dielectric layer located on the third side, the third dielectric layer comprising a third surface; a third metal layer, located on the third dielectric layer; a second contact coupled to the third metal layer and located on the third surface, the second contact coupled to the second end of the through hole, the second surface in contact with the third surface; a fourth metal layer on the fourth side and on the sidewalls to couple to the third metal layer at the bottom; and A third contact is coupled to the fourth metal layer. 2 . The integrated circuit of claim 1 , wherein the first contact comprises a metal bump configured to couple to an electrical contact on a printed circuit board. 3 . The integrated circuit of claim 1 , wherein the first substrate comprises a silicon wafer having a first thickness in a range of 10 um to 12 um. 4 . The integrated circuit of claim 1 , wherein the second substrate comprises a silicon wafer having a second thickness of 75 um or more. The integrated circuit of claim 1 , wherein the second contact comprises a metal pad. 6 . The integrated circuit of claim 5 , comprising a dual substrate stack formed by a dielectric bond between the second dielectric layer and the third dielectric layer and a metal bond between the metal pad and the second end of the via.

7. The integrated circuit of claim 1, wherein the third contact comprises a metal post having a solder cap, the metal post configured to couple to an electrical contact of a photonic integrated circuit on a third substrate.

8. A method for processing an integrated circuit, the method comprising: providing a first substrate including a first side and a second side; forming a circuit on the first side; forming a first dielectric layer overlying the circuit and the first side, the first dielectric layer comprising a first surface; forming a first metal layer embedded in the first dielectric layer, the first metal layer coupled to the circuit; forming a second metal layer on the first surface, the second metal layer coupled to the first metal layer; forming a first contact coupled to a second metal layer on the first surface; forming a via including a conductive material, the via including a first end and a second end, the first end being coupled to the first metal layer, the second end being located at a first depth into the first substrate; processing the second side so that the second end is at the same level as the second surface of the second dielectric layer on the first back side; providing a second substrate including a third side and a fourth side; forming a third metal layer on the third side; forming a third dielectric layer on the third metal layer and the third side, the third dielectric layer comprising a third surface; forming a second contact coupled to the third metal layer, the second contact being at the same level as the third surface; coupling the third surface to the second surface to bond the second substrate to the first substrate; forming a trench extending from the fourth side into the second substrate and having a bottom at a second depth, the bottom being the third metal layer; forming a first polyimide layer overlying the sidewalls of the trench and the fourth side; forming a fourth metal layer overlying the first polyimide layer on the sidewalls and the fourth side of the trench, the fourth metal layer coupled to the third metal layer at the bottom of the trench; forming a second polyimide layer on the fourth metal layer to fill the trench; and A third contact coupled to the fourth metal layer is formed on the second polyimide layer on the fourth side.

9. The method of claim 8, wherein the first contact comprises a metal bump, the method further comprising coupling the metal bump to an electrical contact on a printed circuit board, the metal bump comprising copper, nickel and / or silver material.

10. The method of claim 8, wherein processing the second side comprises: coupling a carrier substrate to the first side by an adhesive material applied over the first contacts and the first surface of the first dielectric layer on the first side; and The first substrate is thinned so that the second side is located 5 um to 10 um above the second end of the through hole.

11. The method according to claim 10, further comprising: etching the second side to obtain a concave surface below the second end of the through hole; forming a nitride material layer on the recessed surface and the conductive material in the second end; forming an oxide material layer on the nitride material layer; and The oxide material layer on the nitride material layer is planarized so that the second end and the second surface of the second dielectric layer are located at the same level, wherein the second dielectric layer includes the oxide material layer and the nitride material layer. 12 . The method of claim 11 , further comprising thinning the second substrate from the fourth side by dry polishing.

13. The method of claim 8, wherein coupling the third surface to the second surface comprises: aligning the second contact with the second end of the through hole; forming a dielectric bond between the second dielectric layer and the third dielectric layer when the third surface contacts the second surface at a first temperature; forming a metal bond between the second contact and the second end of the through hole by annealing the second substrate and the first substrate at a second temperature, the second temperature being higher than the first temperature; and A dual substrate stack is formed.

14. The method of claim 10, further comprising peeling the carrier substrate from the first side of the first silicon substrate by laser to leave the first contacts on the first surface, the first contacts configured to couple to electrical contacts on a printed circuit board.

15. The method according to claim 8, wherein the forming the trench deep into the second substrate from the fourth side comprises: etching from the fourth side to form a trench having an initial depth; depositing a first polyimide layer at least on the sidewalls of the trench and on the fourth side; and The etching and the depositing are alternately repeated to increase the depth of the trench from the initial depth to the second depth until the etching is stopped by the third metal layer.

16. The method of claim 8, wherein the third contact comprises a copper post configured to couple to an electrical contact on a photonic integrated circuit.

17. A method for stacking an electronic integrated circuit onto a photonic integrated circuit, the method comprising: Providing a first substrate including a first side and a second side, the first side including an electronic circuit coupled to a first metal layer in a first dielectric layer, a first contact coupled to a second metal layer at the same level as a first surface of the first dielectric layer, and a through hole including a conductive material coupled to both the first metal layer and the second metal layer, the through hole including a first end at the first metal layer and a second end at a first depth into the first substrate, the second side including a second dielectric layer including a second surface at the same level as the second end of the through hole; providing a second substrate including a third side and a fourth side, the third side including a second contact coupled to a third metal layer in a third dielectric layer on the third side, the second contact being located at a third surface of the third dielectric layer; coupling the second substrate to the first substrate such that the second contact is coupled to the conductive material in the second end of the via; forming a trench extending from the fourth side into the second substrate, the trench including a bottom located at a second depth, the bottom being the third metal layer; forming a fourth metal layer overlying the fourth side and sidewalls of the trench to couple to the third metal layer at the bottom of the trench; and A third contact coupled to the fourth metal layer is formed, the third contact configured to couple to an electrical contact of a photonic integrated circuit on a third substrate.

18. The method of claim 17, further comprising coupling the first surface to a carrier substrate, and thinning the first substrate downward from the second side to reduce a first thickness of the first substrate to no less than the first depth of the through hole.

19. The method of claim 17, wherein coupling the second substrate to the first substrate comprises: forming a dielectric bond between the third dielectric layer and the second dielectric layer by pressing the third surface into contact with the second surface at a first temperature; forming a metallic bond between the second contact and the conductive material in the second end of the via by annealing at a second temperature, the second temperature being higher than the first temperature; and thinning the second substrate from the fourth side to reduce a second thickness of the second substrate to no less than the second depth.

20. The method of claim 17, comprising: forming a first polyimide layer on the fourth side and the sidewalls of the trench; forming the fourth metal layer overlying the first polyimide layer and coupled to the third metal layer at the bottom of the trench; and forming a second polyimide layer overlying the fourth metal layer.

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