Chip packaging structure and electronic equipment
By setting the first rewiring layer in the chip package structure and realizing chip stacking, the problems of large volume and poor stability of the chip package structure in the prior art are solved, and a smaller package space and higher signal quality are achieved.
Patent Information
- Application Number
- CN202411683863.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-02-21
AI Technical Summary
The existing chip packaging structure is large in size and has poor stability, making it difficult to effectively reduce the packaging space and improve signal quality.
By providing a first rewiring layer on one side of the first chip and a second chip on the side of the first rewiring layer away from the first chip, the two chips are interconnected through the first rewiring layer to realize chip stacking .
Effectively reduce the volume of the chip packaging structure, save packaging space, and reduce the signal transmission path between chips, improving signal quality.
Smart Images
Figure CN119495678A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure and an electronic device. Background Art
[0002] With the continuous development of semiconductor technology, miniaturization and high integration of structure and function have become the development trend of semiconductor components. In some chip packaging structures, two or more chips need to be packaged together. However, some existing packaging methods may result in a large package volume and poor package stability. Summary of the invention
[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a chip packaging structure and an electronic device.
[0004] In a first aspect, an embodiment of the present application provides a chip packaging structure, the chip packaging structure comprising:
[0005] First chip;
[0006] a first redistribution layer located at one side of the first chip, the first chip being electrically connected to the first redistribution layer;
[0007] A first plastic packaging layer covering the first chip;
[0008] A second chip located at a side of the first redistribution layer away from the first chip, the second chip being electrically connected to the first redistribution layer;
[0009] A second plastic packaging layer covering the second chip;
[0010] A plurality of conductive pillars are disposed at intervals on the second plastic packaging layer, and the plurality of conductive pillars are electrically connected to the first redistribution layer respectively.
[0011] In a possible implementation, the chip packaging structure further includes a second redistribution layer located on a side of the second plastic encapsulation layer away from the first plastic encapsulation layer, and the second redistribution layer is electrically connected to the first redistribution layer through a plurality of the conductive pillars.
[0012] In a possible implementation manner, a plurality of solder balls are disposed on a side of the second redistribution layer away from the second plastic packaging layer.
[0013] In a possible implementation, the chip packaging structure also includes a heat dissipation layer, which is located on a side of the second chip away from the first redistribution layer, and the orthographic projection of the heat dissipation layer on the first redistribution layer coincides with the orthographic projection of the second chip on the first redistribution layer.
[0014] In a possible implementation manner, a solder ball is disposed at one end of the conductive column away from the first redistribution layer.
[0015] In a possible implementation manner, a heat dissipation pin is provided at one end of the conductive column away from the first redistribution layer.
[0016] In a possible implementation, the material of the heat dissipation pin includes a metal material;
[0017] Preferably, the material of the heat dissipation pins includes copper.
[0018] In a possible implementation, the first chip includes a first pin surface, the first pin surface is provided with a first pin, and the first chip is electrically connected to the first redistribution layer through the first pin;
[0019] The second chip includes a second pin surface, the second pin surface is provided with second pins, and the second chip is electrically connected to the first redistribution layer through the second pins.
[0020] In a possible implementation manner, the material of the first plastic encapsulation layer and the second plastic encapsulation layer includes epoxy resin molding compound.
[0021] In a second aspect, an embodiment of the present application further provides an electronic device, wherein the electronic device includes the chip packaging structure described in any one of the above aspects.
[0022] Based on any of the above aspects, the chip packaging structure and electronic device provided in the embodiments of the present application, by setting a first redistribution layer on one side of the first chip and setting a second chip on the side of the first redistribution layer away from the first chip, can enable the first chip and the second chip to be interconnected through the first redistribution layer to achieve chip stacking. In this way, the volume of the chip packaging structure can be effectively reduced, the packaging space can be saved, and the signal transmission path between chips can also be reduced, thereby improving signal quality. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0024] Figure 1 One of the structural schematic diagrams of the chip packaging structure provided in this embodiment;
[0025] Figure 2 The second structural schematic diagram of the chip packaging structure provided in this embodiment;
[0026] Figure 3 The third structural diagram of the chip packaging structure provided in this embodiment;
[0027] Figure 4 The fourth structural schematic diagram of the chip packaging structure provided in this embodiment;
[0028] Figure 5 The fifth structural diagram of the chip packaging structure provided in this embodiment;
[0029] Figure 6 The sixth structural diagram of the chip packaging structure provided in this embodiment;
[0030] Figure 7 The seventh structural diagram of the chip packaging structure provided in this embodiment;
[0031] Figure 8 The eighth structural diagram of the chip packaging structure provided in this embodiment;
[0032] Fig. 9 A ninth structural diagram of the chip packaging structure provided in this embodiment;
[0033] Fig.10 The tenth structural diagram of the chip packaging structure provided in this embodiment;
[0034] Fig.11 The eleventh structural diagram of the chip packaging structure provided in this embodiment;
[0035] Fig.12 The twelfth structural diagram of the chip packaging structure provided in this embodiment;
[0036] Fig.13 The thirteenth schematic diagram of the chip packaging structure provided in this embodiment;
[0037] Fig.14 The fourteenth structural diagram of the chip packaging structure provided in this embodiment;
[0038] Fig.15 This is the fifteenth structural schematic diagram of the chip packaging structure provided in this embodiment.
[0039] Icon: 110 - first chip; 111 - first pin; 120 - second chip; 121 - second pin; 200 - first redistribution layer; 300 - first plastic layer; 400 - second plastic layer; 500 - conductive column; 600 - second redistribution layer; 710 - solder ball; 720 - heat dissipation pin; 800 - heat dissipation layer. DETAILED DESCRIPTION
[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0041] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0042] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0043] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0044] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0045] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings.
[0046] Please refer to Figure 1 , Figure 1 A possible schematic diagram of the chip packaging structure provided by this embodiment is illustrated. The chip packaging structure may include a first chip 110, a first redistribution layer 200, a first plastic packaging layer 300, a second chip 120, a second plastic packaging layer 400 and a conductive column 500.
[0047] In this embodiment, the number of the first chip 110 may be one or more. When the number of the first chip 110 is multiple, the multiple first chips 110 are arranged in the same layer, and the multiple first chips 110 may be chips with the same structure or chips with different structures to achieve different functions. Exemplarily, the first chip 110 may be a high bandwidth memory (HBM) chip, an application specific integrated circuit (ASIC) chip, a system on chip (SoC), etc.
[0048] The number of the second chips 120 may also be one or more. When the number of the second chips 120 is multiple, the multiple second chips 120 are arranged in the same layer, and the multiple second chips 120 may be chips with the same structure or chips with different structures to achieve different functions.
[0049] The first redistribution layer 200 may be located at one side of the first chip 110 , and the first chip 110 may be electrically connected to the first redistribution layer 200 .
[0050] In this embodiment, in a direction parallel to the first chip 110, the cross-sectional area of the first redistribution layer 200 may be greater than the cross-sectional area of the first chip 110. When there are multiple first chips 110, the cross-sectional area of the first redistribution layer 200 may be greater than the cross-sectional area of the multiple first chips 110, and the multiple first chips 110 may be electrically connected to the first redistribution layer 200.
[0051] Specifically, the first redistribution layer 200 is generally composed of multiple layers of metal wires, and the first redistribution layer 200 can be formed by photolithography, plating, sputtering, etc. The material of the first redistribution layer 200 can be a metal material, such as copper, aluminum, etc.
[0052] The first plastic encapsulation layer 300 may be disposed around the first chip 110 and completely cover the first chip 110 .
[0053] In this embodiment, in a direction parallel to the first chip 110, the cross-sectional area of the first plastic encapsulation layer 300 may be greater than or equal to the cross-sectional area of the first redistribution layer 200. The first plastic encapsulation layer 300 may also completely cover the surface where the first redistribution layer 200 is connected to the first chip 110, so that external water and oxygen can be effectively prevented from contacting the first chip 110, and the reliability of the chip packaging structure can be improved.
[0054] The second chip 120 may be located on a side of the first redistribution layer 200 away from the first chip 110 , and the second chip 120 may be electrically connected to the first redistribution layer 200 .
[0055] In this embodiment, the second chip 120 and the first chip 110 may be chips with the same structure or chips with different structures. For example, when the first chip 110 and the second chip 120 are different chips, the first chip 110 and the second chip 120 may be a system chip and a high-bandwidth memory chip, respectively, to implement different functions, which is not specifically limited here.
[0056] The second plastic encapsulation layer 400 may be disposed around the second chip 120 and completely cover the second chip 120 .
[0057] In this embodiment, the second plastic encapsulation layer 400 can completely cover the first redistribution layer 200 and the second chip 120 , so that external water and oxygen can be effectively prevented from contacting the first redistribution layer 200 and the second chip 120 , thereby increasing the reliability of the first redistribution layer 200 and the second chip 120 .
[0058] The second plastic encapsulation layer 400 may further include a plurality of conductive pillars 500 disposed at intervals. The plurality of conductive pillars 500 are electrically connected to the first redistribution layer 200 , respectively. The conductive pillars 500 may be used to realize signal fan-out.
[0059] In this embodiment, the second plastic encapsulation layer 400 may expose one end of the conductive pillar 500, and the other end of the conductive pillar 500 may be electrically connected to the first redistribution layer 200. Specifically, a plurality of through holes exposing the first redistribution layer 200 may be provided in the second plastic encapsulation layer 400, and the plurality of through holes are arranged at intervals, and the conductive pillar 500 may be formed by the conductive material filled in the through holes. The surface of the end of the conductive pillar 500 that is not electrically connected to the first redistribution layer 200 may be flush with the surface of the second plastic encapsulation layer 400 away from the first plastic encapsulation layer 300.
[0060] The material of the conductive pillar 500 may include conductive materials such as copper, aluminum, nickel, or an alloy of at least two of the above materials, or a combination of the above materials, which is not specifically limited herein.
[0061] When there are multiple second chips 120 , the conductive pillars 500 may be disposed at gaps between the multiple second chips 120 , or at edges of the multiple second chips 120 , which is not specifically limited herein.
[0062] In addition, the number of the conductive pillars 500 can also be determined according to actual needs.
[0063] For some examples, see Figure 2 The first plastic encapsulation layer 300 may also include a plurality of conductive pillars 500 arranged at intervals, one end of the conductive pillar 500 may be electrically connected to the first redistribution layer 200, and the other end of the conductive pillar 500 may be electrically connected to other film layers located on the side of the first plastic encapsulation layer 300 away from the second plastic encapsulation layer 400.
[0064] In the above structure, by setting the first redistribution layer 200 on one side of the first chip 110 and setting the second chip 120 on the side of the first redistribution layer 200 away from the first chip 110, the first chip 110 and the second chip 120 can be interconnected through the first redistribution layer 200 to achieve chip stacking. In this way, the volume of the chip packaging structure can be effectively reduced, the packaging space can be saved, and the signal transmission path between chips can also be reduced to improve the signal quality.
[0065] In one possible implementation, see Figure 3 The chip packaging structure may further include a second redistribution layer 600 located on a side of the second plastic encapsulation layer 400 away from the first plastic encapsulation layer 300 , and the second redistribution layer 600 may be electrically connected to the first redistribution layer 200 through a plurality of the conductive pillars 500 .
[0066] In this embodiment, the orthographic projection of the second redistribution layer 600 on the second plastic encapsulation layer 400 can completely overlap with the orthographic projection of the first redistribution layer 200 on the second plastic encapsulation layer 400, and the two ends of the conductive column 500 can contact the first redistribution layer 200 and the second redistribution layer 600 respectively, thereby realizing the electrical connection between the first redistribution layer 200 and the second redistribution layer 600.
[0067] Specifically, the second redistribution layer 600 can be formed by photolithography, plating, sputtering, etc. The material of the second redistribution layer 600 can be the same as the material of the first redistribution layer 200, and the material of the second redistribution layer 600 and the material of the first redistribution layer 200 can both be metal materials. For example, the material of the second redistribution layer 600 and the material of the first redistribution layer 200 can both be copper, aluminum, etc.
[0068] For some examples, see Figure 4The second redistribution layer 600 is also provided on the side of the first plastic encapsulation layer 300 away from the second plastic encapsulation layer 400. The first plastic encapsulation layer 300 may also include a plurality of conductive pillars 500 arranged at intervals. The second redistribution layer 600 may be electrically connected to the first redistribution layer 200 through the conductive pillars 500.
[0069] In one possible implementation, see Figure 5 A plurality of solder balls 710 are disposed on a side of the second redistribution layer 600 away from the second plastic encapsulation layer 400 .
[0070] In this embodiment, by planting balls on the side of the second redistribution layer 600 away from the second plastic packaging layer 400, a plurality of solder balls 710 electrically connected to the second redistribution layer 600 can be obtained. The solder balls 710 can play a role of adhesion and diffusion when the chip packaging structure is connected to other electronic devices.
[0071] The material of the solder ball 710 may include one of lead, tin and silver, or an alloy containing any of the above solder metals. The material of the solder ball 710 is preferably tin.
[0072] For some examples, see Figure 6 When the second redistribution layer 600 is also provided on the side of the first plastic encapsulation layer 300 away from the second plastic encapsulation layer 400, and the first plastic encapsulation layer 300 may also include a plurality of conductive pillars 500 arranged at intervals, a plurality of solder balls 710 are also provided on the side of the second redistribution layer 600 away from the first plastic encapsulation layer 300.
[0073] In the above design, compared with only setting the solder ball 710 on the side of the conductive column 500 away from the first redistribution layer 200, this embodiment increases the number of the solder balls 710 by setting the second redistribution layer 600, and makes the arrangement of the solder balls 710 more flexible, which is conducive to signal fan-out.
[0074] In one possible implementation, see Figure 7 The chip packaging structure may further include a heat dissipation layer 800, and the heat dissipation layer 800 may be located on a side of the second chip 120 away from the first redistribution layer 200, and the orthographic projection of the heat dissipation layer 800 on the first redistribution layer 200 may coincide with the orthographic projection of the second chip 120 on the first redistribution layer 200.
[0075] In this embodiment, the heat dissipation layer 800 may include a first surface and a second surface that are relatively arranged. The first surface of the heat dissipation layer 800 may be in contact with the second chip 120, and the second plastic encapsulation layer 400 may expose the second surface of the heat dissipation layer 800. In this way, the heat dissipation layer 800 can be used to solve the heat dissipation problem of the second chip 120.
[0076] Specifically, in a direction perpendicular to the second chip 120 , the sum of the thickness of the heat dissipation layer 800 and the thickness of the second chip 120 may be greater than the height of the conductive pillar 500 .
[0077] For some examples, see Figure 8 The heat dissipation layer 800 may also be located on a side of the first chip 110 away from the first redistribution layer 200 to dissipate heat for the first chip 110 .
[0078] In a possible implementation, a solder ball 710 is disposed at one end of the conductive pillar 500 away from the first redistribution layer 200 .
[0079] In one possible implementation, please refer to Fig. 9 When the chip packaging structure does not include the heat dissipation layer 800, the second plastic encapsulation layer 400 can completely cover the second chip 120, and each of the conductive pillars 500 can be provided with a solder ball 710 on a side away from the first redistribution layer 200. The solder ball 710 can be electrically connected to the first redistribution layer 200 through the conductive pillars 500.
[0080] Please refer to Fig.10 When the chip packaging structure does not include the heat dissipation layer 800 and the first plastic encapsulation layer 300 is also provided with the conductive column 500 , the end of each conductive column 500 that is not connected to the first redistribution layer 200 may be provided with the solder ball 710 .
[0081] In another possible implementation, please refer to Fig.11 When the chip packaging structure includes the heat dissipation layer 800, a solder ball 710 may be disposed on a side of each conductive column 500 away from the first redistribution layer 200. The solder ball 710 may be electrically connected to the first redistribution layer 200 through the conductive column 500.
[0082] Please refer to Fig.12 When the chip packaging structure includes the heat dissipation layer 800 and the first plastic encapsulation layer 300 is also provided with the conductive column 500 , the end of each conductive column 500 that is not connected to the first redistribution layer 200 may be provided with the solder ball 710 .
[0083] The material of the solder ball 710 may include one of lead, tin and silver, or an alloy containing any of the above solder metals. The material of the solder ball 710 is preferably tin.
[0084] In a possible implementation, a heat dissipation pin 720 is provided at one end of the conductive column 500 away from the first redistribution layer 200 .
[0085] In this embodiment, please refer to Fig.13 When the second plastic encapsulation layer 400 includes a plurality of conductive pillars 500, each conductive pillar 500 is provided with a heat dissipation pin 720 on a side away from the first redistribution layer 200. The heat dissipation pin 720 is electrically connected to the first redistribution layer 200 through the conductive pillar 500, and the heat dissipation pin 720 can be used for heat dissipation.
[0086] For some examples, see Fig.14 The first plastic encapsulation layer 300 and the second plastic encapsulation layer 400 may each include a plurality of conductive pillars 500 , and the heat dissipation pins 720 are disposed at the ends of the conductive pillars 500 that are not connected to the first redistribution layer 200 .
[0087] The heat dissipation pins 720 may also be connected to other components, which helps the chip packaging structure to be further electrically connected to other components.
[0088] The heat dissipation pins 720 can be obtained by exposure, development and other methods.
[0089] In a possible implementation, the heat dissipation pin 720 may be made of metal material.
[0090] Copper is preferably used in the embodiment of the present application because copper has good electrical conductivity and low cost.
[0091] In this embodiment, the material of the heat dissipation layer 800 may be the same as the material of the heat dissipation pins 720 , and the material of the heat dissipation layer 800 and the material of the heat dissipation pins 720 may both be copper.
[0092] In one possible implementation, see Fig.15 The first chip 110 may include a first pin surface, on which a first pin 111 is disposed, and the first chip 110 may be electrically connected to the first redistribution layer 200 through the first pin 111 .
[0093] In this embodiment, the first pin surface of the first chip 110 may be located on a side of the first chip 110 close to the first redistribution layer 200. The first pin surface may include a plurality of first pins 111. When the number of the first chip 110 is one, one first chip 110 may be electrically connected to the first redistribution layer 200 through the first pin 111 of the first pin surface. When the number of the first chip 110 is multiple, the multiple first chips 110 are arranged in the same layer, and the multiple first chips 110 may be electrically connected to the first redistribution layer 200 through the first pins 111 of the first pin surface, respectively.
[0094] The second chip 120 may include a second pin surface, on which second pins 121 are disposed. The second chip 120 may be electrically connected to the first redistribution layer 200 through the second pins 121 .
[0095] In this embodiment, the second pin surface of the second chip 120 may be located at a side of the second chip 120 close to the first redistribution layer 200. The second pin surface may include a plurality of second pins 121, and the number of the first pins 111 of the first pin surface may be different from the number of the second pins 121 of the second pin surface. When the number of the second chip 120 is one, one second chip 120 may be electrically connected to the second redistribution layer 600 through the second pins 121 of the second pin surface. When the number of the second chip 120 is multiple, the multiple second chips 120 are arranged in the same layer, and the multiple second chips 120 may be electrically connected to the second redistribution layer 600 through the second pins 121 of the second pin surface, respectively.
[0096] In a possible implementation, the materials of the first molding layer 300 and the second molding layer 400 may include epoxy molding compound.
[0097] In this embodiment, the first molding layer 300 and the second molding layer 400 are made of the same material. The first molding layer 300 and the second molding layer 400 can both be made of insulating materials, for example, epoxy molding compound (EMC).
[0098] An embodiment of the present application also provides an electronic device, which may include the chip packaging structure provided by this embodiment.
[0099] To summarize, this embodiment provides a chip packaging structure and an electronic device. By setting a first redistribution layer on one side of a first chip and setting a second chip on a side of the first redistribution layer away from the first chip, the first chip and the second chip can be interconnected through the first redistribution layer to achieve chip stacking. In this way, the volume of the chip packaging structure can be effectively reduced, the packaging space can be saved, and the signal transmission path between chips can be reduced, thereby improving the signal quality.
[0100] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0101] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A chip packaging structure, characterized in that: include: First chip; a first redistribution layer located at one side of the first chip, the first chip being electrically connected to the first redistribution layer; A first plastic packaging layer covering the first chip; A second chip located at a side of the first redistribution layer away from the first chip, the second chip being electrically connected to the first redistribution layer; A second plastic packaging layer covering the second chip; A plurality of conductive pillars are disposed at intervals on the second plastic packaging layer, and the plurality of conductive pillars are electrically connected to the first redistribution layer respectively.
2. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a second redistribution layer located on a side of the second plastic encapsulation layer away from the first plastic encapsulation layer, and the second redistribution layer is electrically connected to the first redistribution layer through a plurality of the conductive pillars.
3. The chip packaging structure according to claim 2, characterized in that: A plurality of solder balls are arranged on a side of the second redistribution layer away from the second plastic packaging layer.
4. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure also includes a heat dissipation layer, which is located on a side of the second chip away from the first redistribution layer, and an orthographic projection of the heat dissipation layer on the first redistribution layer coincides with an orthographic projection of the second chip on the first redistribution layer.
5. The chip packaging structure according to claim 1 or 4, characterized in that: A solder ball is disposed at one end of the conductive column away from the first redistribution layer.
6. The chip packaging structure according to claim 4, characterized in that: A heat dissipation pin is disposed at one end of the conductive column away from the first redistribution layer.
7. The chip packaging structure according to claim 6, characterized in that: The material of the heat dissipation pins includes metal material; Preferably, the material of the heat dissipation pins includes copper.
8. The chip packaging structure according to claim 1, characterized in that: The first chip comprises a first pin surface, the first pin surface is provided with a first pin, and the first chip is electrically connected to the first redistribution layer through the first pin; The second chip includes a second pin surface, the second pin surface is provided with second pins, and the second chip is electrically connected to the first redistribution layer through the second pins.
9. The chip packaging structure according to claim 1, characterized in that: The materials of the first plastic encapsulation layer and the second plastic encapsulation layer include epoxy resin molding compound.
10. An electronic device, characterized in that: A chip packaging structure comprising any one of claims 1 to 9.