Overcurrent protection circuit and switching power supply
By designing an overcurrent protection circuit that can directly turn off the GaN-based transistor, the problem of slow power loss and response speed during overcurrent protection in the prior art is solved, and high-reliability overcurrent protection is achieved.
Patent Information
- Application Number
- CN202411343051.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2025-02-21
AI Technical Summary
The existing overcurrent protection circuit will generate additional power loss when protecting GaN-based transistors, and the Si-based transistors have a slow response speed and are difficult to shut down quickly, which affects the reliability of overcurrent protection.
An overcurrent protection circuit is designed to monitor the current of the GaN-based transistor in real time through the monitoring sub-circuit. When an overcurrent phenomenon occurs, the GaN-based transistor is directly turned off to avoid shutting down through the Si-based transistor connected in series, thereby not adding additional power loss.
It realizes rapid shutdown of GaN-based transistors without adding additional power loss, improving the reliability of overcurrent protection and reducing the chance of device damage.
Smart Images
Figure CN119496085A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of circuits, and in particular to an overcurrent protection circuit and a switching power supply. Background Art
[0002] Compared with traditional silicon (Si) devices, gallium nitride (GaN) devices have superior characteristics such as higher switching frequency, high efficiency, high power, high voltage resistance, high temperature resistance and strong radiation resistance. They have been widely used in switching power supplies, electric vehicles and fast chargers. An overcurrent protection circuit is usually set to shut down the GaN device when an overcurrent occurs to protect the GaN device and the path in which it is located.
[0003] In the related art, the overcurrent protection circuit includes a switch subcircuit, a monitoring subcircuit and a driving subcircuit. Among them, the switch subcircuit includes a GaN-based transistor and a Si-based transistor connected in series, and the second electrode of the GaN-based transistor is connected to the first electrode of the Si-based transistor. The two ends of the monitoring subcircuit are respectively connected to the first electrode and the second electrode of the Si-based transistor. The monitoring subcircuit is used to monitor whether an overcurrent phenomenon occurs in the switch subcircuit, and to generate a control signal based on the monitoring result. The input end of the driving subcircuit is connected to the output end of the monitoring subcircuit, and the output end of the driving subcircuit is connected to the control electrode of the Si-based transistor. The driving subcircuit is used to control the Si-based transistor to turn on or off according to the control signal output from the output end of the monitoring subcircuit.
[0004] However, turning off the series-connected Si-based transistors to achieve overcurrent protection for GaN-based transistors will generate additional power loss, and the slow response speed of Si-based transistors may make it difficult to quickly shut down when overcurrent occurs, thereby affecting the reliability of the overcurrent protection circuit. Summary of the invention
[0005] The embodiments of the present disclosure provide an overcurrent protection circuit and a switching power supply, which can effectively protect GaN-based transistors and their paths without increasing additional power loss, improve the reliability of overcurrent protection, and reduce the probability of device damage. The technical solution is as follows:
[0006] On the one hand, an overcurrent protection circuit is provided, including a switch subcircuit, a monitoring subcircuit and a driving subcircuit, wherein the switch subcircuit includes a gallium nitride-based transistor M0, and a first electrode of the gallium nitride-based transistor M0 is connected to a first power supply voltage supply terminal; an input terminal of the monitoring subcircuit is connected to a second electrode of the gallium nitride-based transistor M0, and the monitoring subcircuit is used to monitor whether an overcurrent phenomenon occurs in the switch subcircuit, and to generate a control signal based on the monitoring result; a first input terminal of the driving subcircuit is connected to an output terminal of the monitoring subcircuit, a second input terminal of the driving subcircuit is connected to a driving signal supply terminal, and an output terminal of the driving subcircuit is connected to a control electrode of the gallium nitride-based transistor M0, and the driving subcircuit is used to control the gallium nitride-based transistor M0 to be turned on or off according to the control signal output by the output terminal of the monitoring subcircuit and the driving signal provided by the driving signal supply terminal.
[0007] Optionally, the monitoring subcircuit includes a current mirror, a resistor R0 and a comparator, the first end of the current mirror is connected to the second electrode of the gallium nitride-based transistor M0, the second end of the current mirror is connected to the second power supply voltage supply end through the resistor R0, the third end of the current mirror is grounded, and the current mirror is used to monitor the current in the switch subcircuit and generate a mirror current at the second end of the current mirror; the first input end of the comparator is connected to the second end of the current mirror, the second input end of the comparator is connected to the reference voltage supply end, and the output end of the comparator is electrically connected to the first input end of the driving subcircuit.
[0008] Optionally, the monitoring subcircuit further includes a first inverter and a second inverter, the input end of the first inverter is connected to the output end of the comparator, the output end of the first inverter is connected to the input end of the second inverter; the output end of the second inverter is connected to the first input end of the driving subcircuit.
[0009] Optionally, the current mirror includes a first transistor M1 and a second transistor M2, the control electrode of the first transistor M1 is respectively connected to the first electrode of the first transistor M1 and the control electrode of the second transistor M2, the first electrode of the first transistor M1 is the first end of the current mirror, and the second electrode of the first transistor M1 is the third end of the current mirror; the first electrode of the second transistor M2 is the second end of the current mirror, and the second electrode of the second transistor M2 is connected to the second electrode of the first transistor M1.
[0010] Optionally, a ratio of a width-to-length ratio of the first transistor M1 to a width-to-length ratio of the second transistor M2 is 9000 to 11000.
[0011] Optionally, the voltage of the reference voltage supply terminal is 1V to 3V.
[0012] Optionally, the driving subcircuit includes an AND gate and a level converter, wherein a first input terminal of the AND gate is connected to an output terminal of the monitoring subcircuit, and a second input terminal of the AND gate is connected to the driving signal providing terminal; a first input terminal of the level converter is connected to an output terminal of the AND gate, a second input terminal of the level converter is grounded, a third input terminal of the level converter is connected to a negative voltage providing terminal of a power supply, and an output terminal of the level converter is connected to a control electrode of the gallium nitride-based transistor M0, and the level converter is used to control a signal output from an output terminal of the level converter to be a ground signal or a negative voltage shutdown signal according to a signal output from an output terminal of the AND gate.
[0013] Optionally, the driving signal providing end is used to provide a pulse width modulation (PWM) signal.
[0014] Optionally, the gallium nitride-based transistor M0 is a P-channel depletion-type gallium nitride-based transistor.
[0015] On the other hand, a switching power supply is provided, comprising a power chip and any one of the above-mentioned overcurrent protection circuits, wherein the power chip and the overcurrent protection circuit are electrically connected.
[0016] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0017] In the embodiment of the present disclosure, the input end of the monitoring subcircuit is connected to the second pole of the GaN-based transistor M0, and the monitoring subcircuit is used to monitor whether an overcurrent phenomenon occurs in the switch subcircuit, and to generate a control signal based on the monitoring result, so that the current of the path where the GaN-based transistor M0 is located can be monitored in real time. The first input end of the driving subcircuit is connected to the output end of the monitoring subcircuit, the second input end of the driving subcircuit is connected to the driving signal providing end, and the output end of the driving subcircuit is connected to the control pole of the GaN-based transistor M0. The driving subcircuit is used to control the GaN-based transistor M0 to turn on or off according to the control signal output by the output end of the monitoring subcircuit and the driving signal provided by the driving signal providing end. When an overcurrent phenomenon occurs, the output end of the monitoring subcircuit outputs a control signal corresponding to the overcurrent phenomenon to the first input end of the driving subcircuit, and the output end of the driving subcircuit then outputs a corresponding signal to the control pole of the GaN-based transistor M0 according to the control signal and the driving signal to directly control the GaN-based transistor M0 to turn off. Since directly turning off the GaN-based transistor M0 will not generate additional power loss, and the GaN-based transistor M0 can respond quickly, the embodiment of the present disclosure can quickly turn off the GaN-based transistor M0 when an overcurrent phenomenon occurs without increasing additional power loss, thereby effectively protecting the GaN-based transistor M0 and the path in which it is located, improving the reliability of overcurrent protection, and reducing the probability of device damage. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0019] Figure 1 is a structural schematic diagram of an overcurrent protection circuit provided by an embodiment of the present disclosure;
[0020] Figure 2 is a circuit diagram of an overcurrent protection circuit provided by an embodiment of the present disclosure;
[0021] Figure 3 is a waveform diagram provided by an embodiment of the present disclosure;
[0022] Figure 4 It is a schematic diagram of the structure of a GaN-based transistor provided in an embodiment of the present disclosure.
[0023] Reference numerals:
[0024] 1: switch subcircuit; 2: monitoring subcircuit; 20: current mirror; 21: comparator; 22: first inverter; 23: second inverter; 3: driving subcircuit; 30: level converter; 31: AND gate; 101: substrate; 102: nucleation layer; 103: buffer layer; 104 device layer; 105: insulating layer; 106: first electrode; 107: second electrode; 108: control electrode. DETAILED DESCRIPTION
[0025] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0026] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar terms used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Words such as "include" and the like mean that the elements or objects appearing before "include" cover the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
[0027] Figure 1 Schematic diagram of an overcurrent protection circuit provided by an embodiment of the present disclosure. Figure 1 As shown, the overcurrent protection circuit includes a switch subcircuit 1 , a monitoring subcircuit 2 and a driving subcircuit 3 . Figure 2 is a circuit diagram of an overcurrent protection circuit provided by an embodiment of the present disclosure. Figure 1 and Figure 2 The switch subcircuit 1 includes a GaN-based transistor M0, and the first electrode of the GaN-based transistor M0 is connected to the first power supply voltage supply terminal VD. The input terminal of the monitoring subcircuit 2 is connected to the second electrode of the GaN-based transistor M0, and the monitoring subcircuit 2 is used to monitor whether an overcurrent phenomenon occurs in the switch subcircuit 1, and to generate a control signal based on the monitoring result. The first input terminal of the driving subcircuit 3 is connected to the output terminal of the monitoring subcircuit 2, the second input terminal of the driving subcircuit 2 is connected to the driving signal supply terminal, and the output terminal of the driving subcircuit 3 is connected to the control electrode of the GaN-based transistor M0. The driving subcircuit 3 is used to control the GaN-based transistor M0 to be turned on or off according to the control signal output from the output terminal of the monitoring subcircuit 2 and the driving signal provided by the driving signal supply terminal.
[0028] In the embodiment of the present disclosure, the monitoring subcircuit 2 can monitor the current of the path where the GaN-based transistor M0 is located in real time. When an overcurrent phenomenon occurs, the output end of the monitoring subcircuit 2 outputs a control signal corresponding to the overcurrent phenomenon to the first input end of the driving subcircuit 3, and the output end of the driving subcircuit 3 outputs a corresponding signal to the control electrode of the GaN-based transistor M0 according to the control signal and the driving signal provided by the driving signal providing end to directly control the GaN-based transistor M0 to turn off. Since directly turning off the GaN-based transistor M0 will not generate additional power loss, and the GaN-based transistor M0 can respond quickly, the embodiment of the present disclosure can quickly turn off the GaN-based transistor M0 when an overcurrent phenomenon occurs without increasing additional power loss, thereby effectively protecting the GaN-based transistor M0 and the path where it is located, improving the reliability of overcurrent protection, and reducing the probability of device damage.
[0029] When no overcurrent phenomenon occurs, the output end of the monitoring subcircuit 2 outputs a control signal corresponding to no overcurrent phenomenon to the first input end of the driving subcircuit 3, and the output end of the driving subcircuit 3 then outputs a corresponding signal to the control electrode of the GaN-based transistor M0 according to the control signal and the driving signal to control the GaN-based transistor M0 to be turned on or off.
[0030] Optionally, the monitoring subcircuit 2 includes a current mirror 20, a resistor R0 and a comparator 21. The first end of the current mirror 20 is connected to the second electrode of the GaN-based transistor M0, the second end of the current mirror 20 is connected to the second power supply voltage supply terminal VDD through the resistor R0, and the third end of the current mirror 20 is grounded. The current mirror 20 is used to monitor the current in the switch subcircuit 1, that is, to monitor the current Id in the path where the GaN-based transistor M0 is located, and generate a mirror current Id' at the second end of the current mirror 20. The first input end of the comparator 21 is connected to the second end of the current mirror 20, the second input end of the comparator 21 is connected to the reference voltage supply terminal VREF, and the output end of the comparator 21 is electrically connected to the first input end of the driving subcircuit 3. Here, the electrical connection includes the case where the electrical connection is formed by direct connection and the case where the electrical connection is formed by indirect connection.
[0031] The impedance of the current mirror 20 is small, and no additional on-resistance is added, which reduces heat and loss. The current Id in the path where the GaN-based transistor M0 is located is monitored in real time, and the mirror current Id' is converted into a voltage signal VIN through the resistor R0 of the branch where the second end is located and the second power supply voltage supply terminal VDD, and input to the comparator 21. When an overcurrent phenomenon occurs, the comparison result of the voltage signal VIN at the first input terminal of the comparator 21 and the reference voltage at the second input terminal of the comparator 21 will affect the output terminal signal VOUT of the comparator 21, and the output terminal of the comparator 21 outputs a signal corresponding to the overcurrent phenomenon to the first input terminal of the driving sub-circuit 3 to control the GaN-based transistor M0 to turn off.
[0032] Exemplarily, the first electrode is a drain, the second electrode is a source, and the control electrode is a gate.
[0033] In other embodiments, the first electrode may be a source electrode, the second electrode may be a drain electrode, and the control electrode may be a gate electrode, and the present disclosure does not impose any limitation on this.
[0034] Exemplarily, the current Id in the path where the GaN-based transistor M0 is located may also be referred to as the drain current of the GaN-based transistor M0 .
[0035] Optionally, the GaN-based transistor M0 is a P-channel depletion-type GaN-based transistor. The P-channel depletion-type GaN-based transistor has lower gate leakage, parasitic capacitance and on-resistance, and is better suited for low-current, high-sensitivity application scenarios, such as precision circuit control scenarios. The P-channel depletion-type transistor is turned off when the gate voltage VG is negative and less than the threshold voltage Vth, and is turned on when VG is greater than or equal to the threshold voltage Vth.
[0036] Optionally, the monitoring subcircuit 2 further includes a first inverter 22 and a second inverter 23. The input end of the first inverter 22 is connected to the output end of the comparator 21, and the output end of the first inverter 22 is connected to the input end of the second inverter 23. The output end of the second inverter 23 is connected to the first input end of the driving subcircuit 3.
[0037] The signal quality of the output signal VOUT of the comparator 21 can be improved by the first inverter 22 and the second inverter 23, so that the standard level signal can be output from the output of the second inverter 23, and the driving ability and anti-interference ability of the signal can be improved, thereby improving the reliability of the overcurrent protection circuit. The drive signal supply end and the output end of the second inverter 23 are connected to the two input ends of the drive sub-circuit 3 at the same time, and the control signal output by the drive sub-circuit 3 can be accurately controlled by the drive signal and the signal after the output signal VOUT of the comparator 21 is inverted twice, and the on and off state of the GaN-based transistor M0 can be accurately controlled.
[0038] In other embodiments, the inverter may not be provided, and the output end of the comparator 21 is directly connected to the first input end of the driving subcircuit 3 as the output end of the monitoring subcircuit 2 , and the present disclosure does not limit this.
[0039] like Figure 2 As shown, the current mirror 20 includes a first transistor M1 and a second transistor M2. The control electrode of the first transistor M1 is connected to the first electrode of the first transistor M1 and the control electrode of the second transistor M2 respectively, the first electrode of the first transistor M1 is the first end of the current mirror 20, and the second electrode of the first transistor M1 is the third end of the current mirror 20. The first electrode of the second transistor M2 is the second end of the current mirror 20, and the second electrode of the second transistor M2 is connected to the second electrode of the first transistor M1.
[0040] In this way, the impedance of the current mirror 20 can be ensured to be small, so that the current Id of the path where the GaN-based transistor M0 is located can be monitored in real time, and the mirror current Id' can be converted into a voltage signal VIN and input to the first input terminal of the comparator 21 through the resistor R0 of the branch where the second transistor M2 is located and the second power supply voltage supply terminal VDD, and the branch where the second transistor M2 is located will not affect the current Id of the path where the GaN-based transistor M0 is located.
[0041] Exemplarily, the first transistor M1 and the second transistor M2 are both Si-based transistors, for example, low-voltage Si metal oxide semiconductor field effect transistors (MOSFET).
[0042] Optionally, the aspect ratio of the first transistor M1 is much greater than that of the second transistor M2. The aspect ratio of a transistor refers to the ratio of the width to the length of the transistor, which affects the transistor's current gain, input resistance, output resistance, response speed and other characteristics.
[0043] Optionally, a ratio of a width-to-length ratio of the first transistor M1 to a width-to-length ratio of the second transistor M2 is 9000 to 11000.
[0044] In the current mirror 20, the ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the second transistor M2 is the ratio of the current Id in the path where the GaN-based transistor M0 is located to the mirror current Id'. The ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the second transistor M2 is within this range, which is not only conducive to reducing the mirror current Id', so that the overcurrent phenomenon can be reflected by comparing with a smaller reference voltage through the comparator 21, but also can reduce the width-to-length ratio of the second transistor M2, thereby reducing the size of the overcurrent protection circuit.
[0045] For example, the ratio of the width to length ratio of the first transistor M1 to the width to length ratio of the second transistor M2 may be 10000. That is, the ratio of the current Id in the path where the GaN-based transistor M0 is located to the mirror current Id′ may be 10000.
[0046] Exemplarily, the voltage signal VIN and the current Id in the path where the GaN-based transistor M0 is located satisfy the following formula (1):
[0047] VIN=VDD-Id / K×R0 (1);
[0048] Among them, VIN is the voltage of the voltage signal VIN, VDD is the voltage of the second power supply voltage providing terminal VDD, Id is the current of the path where the GaN-based transistor M0 is located, K is the ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the second transistor M2, and R0 is the resistance value of the resistor R0.
[0049] Optionally, the voltage of the reference voltage supply terminal VREF is 1 V to 3 V. In this way, only a small reference voltage needs to be provided to quickly and accurately reflect the overcurrent condition.
[0050] Exemplarily, the voltage of the reference voltage supply terminal VREF may be 1.2V.
[0051] Optionally, the first input terminal of the comparator 21 is a positive input terminal, and the second input terminal of the comparator 21 is a negative input terminal. In this way, when the voltage of the voltage signal VIN at the positive input terminal is less than the voltage of the reference voltage supply terminal VREF at the negative input terminal, the output terminal signal VOUT of the comparator 21 is 0 (low level, 0V), and after passing through the first inverter 22, the output overcurrent protection (OCP) signal is 1 (high level, greater than 0V), indicating that an overcurrent phenomenon has occurred, and then after passing through the second inverter 23, the output control signal is 0 to the first input terminal of the driving sub-circuit 3; when the voltage of the voltage signal VIN at the positive input terminal is greater than or equal to the voltage of the reference voltage supply terminal VREF at the negative input terminal, the output terminal signal VOUT of the comparator 21 is 1, and after passing through the first inverter 22, the output OCP signal is 0, indicating that no overcurrent phenomenon has occurred, and then after passing through the second inverter 23, the output control signal 1 is output to the first input terminal of the driving sub-circuit 3. Then, the output end of the driving sub-circuit 3 outputs a corresponding signal to the control electrode of the GaN-based transistor M0 according to the control signal and the driving signal to control the GaN-based transistor M0 to be turned off or on.
[0052] That is, in this way, when an overcurrent phenomenon occurs, the output signal VOUT of the comparator 21 is a low-level signal, and the control signal output after the first inverter 22 and the second inverter 23 is a low-level signal. The low-level signal has a strong anti-interference ability, which can minimize interference and ensure the reliability of control, thereby improving the reliability of overcurrent protection.
[0053] In other embodiments, the first input terminal of the comparator 21 is a negative input terminal, and the second input terminal of the comparator 21 is a positive input terminal.
[0054] like Figure 2 As shown, the driving subcircuit 3 includes an AND gate 31 and a level converter 30. The first input terminal of the AND gate 31 is connected to the output terminal of the monitoring subcircuit 2, and the second input terminal of the AND gate 31 is connected to the driving signal supply terminal. The first input terminal of the level converter 30 is connected to the output terminal of the AND gate 31, the second input terminal of the level converter 30 is grounded, the third input terminal of the level converter 30 is connected to the negative voltage supply terminal VNEG of the power supply, and the output terminal of the level converter 30 is connected to the control electrode of the GaN-based transistor M0. The level converter 30 is used to control the signal output from the output terminal of the level converter 30 to be a ground signal or a negative voltage shutdown signal according to the signal output from the output terminal of the AND gate 31.
[0055] When the signal at the first input terminal of the input level converter 30 is a low-level signal, indicating that an overcurrent phenomenon has occurred, the level converter 30 controls the signal outputted from its output terminal to be a negative voltage shutdown signal, that is, the voltage of the negative voltage supply terminal VNEG of the power supply, and controls the GaN-based transistor M0 to be turned off. When the signal at the first input terminal of the input level converter 30 is a high-level signal, indicating that an overcurrent phenomenon has not occurred, the level converter 30 controls the signal outputted from its output terminal to be a ground signal, that is, 0V, thereby controlling the GaN-based transistor M0 to be turned on. In this way, the GaN-based transistor M0 and its path can be effectively protected by the AND gate 31 and the level converter 30, thereby improving the reliability of overcurrent protection and reducing the probability of device damage.
[0056] In other embodiments, according to the control signal outputted from the output terminal of the monitoring subcircuit 2, other logic gates may be used in the driving subcircuit 3 to realize the same function. For example, only the first inverter 22 may be provided without the second inverter 23, and the AND gate 31 may be changed into a NAND gate in the driving subcircuit 3, the output terminal of the first inverter 22 is connected to the first input terminal of the NAND gate as the output terminal of the monitoring subcircuit 2, the driving signal supply terminal is connected to the second input terminal of the NAND gate, and the output terminal of the NAND gate is connected to the first input terminal of the level converter 30. In this way, the overcurrent protection circuit can also quickly shut down the GaN-based transistor M0 when an overcurrent phenomenon occurs.
[0057] Optionally, the driving signal providing terminal is used to provide a PWM signal. Due to the high frequency characteristics of the GaN-based transistor M0, the on and off states of the GaN-based transistor M0 can be accurately controlled by the rapid change of the PWM signal, thereby achieving effective management of the power supply and improving energy saving. In addition, the duty cycle of the PWM signal can be adjusted as needed to control the on time of the GaN-based transistor M0, thereby adjusting the output of current and voltage, so that the GaN-based transistor M0 can be better applied to scenarios that require fine power regulation.
[0058] The response process of the overcurrent protection circuit of the embodiment of the present disclosure is exemplarily described below in combination with the specific signal values of each part.
[0059] Exemplarily, the voltage of the first power supply voltage supply terminal VD is 400 V, the voltage of the second power supply voltage supply terminal VDD is 12 V, the voltage of the reference voltage supply terminal VREF is 1.2 V, the voltage of the negative power supply voltage supply terminal VNEG is -20 V, and the voltage of the ground signal GND is 0 V. The ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the second transistor M2 is 10000. The resistance value of the resistor R0 is 1.8 kΩ.
[0060] In the embodiment of the present disclosure, when the current Id of the path where the GaN-based transistor M0 is located is set to be greater than 60A, it indicates that an overcurrent phenomenon occurs, and the threshold voltage Vth for turning off the GaN-based transistor M0 is set to be greater than -20V and less than or equal to -10V.
[0061] Figure 3 is a waveform diagram provided by an embodiment of the present disclosure. Figure 2 and Figure 3 , before time t1, the current Id of the path where the GaN-based transistor M0 is located is less than or equal to 60A, indicating that no overcurrent occurs. When no overcurrent occurs, the mirror current Id' is less than or equal to 6mA, the voltage signal VIN is greater than or equal to 1.2V, that is, VIN is greater than or equal to VREF, the output signal VOUT of the comparator 21 is 1, the OCP signal is 0 after passing through the first inverter 22, and then after passing through the second inverter 23, the control signal 1 and the PWM signal are simultaneously connected to the AND gate 31, and the signal with the same waveform as the PWM signal is output to the level converter 30. The output end of the level converter 30 normally outputs the ground signal GND or the negative voltage shutdown signal VNEG to the control electrode of the GaN-based transistor M0 according to the PWM signal, that is, VG is 0V or -20V, so that the GaN-based transistor M0 is normally turned on or off.
[0062] After time t1, the current Id of the path where the GaN-based transistor M0 is located is greater than 60A, indicating that an overcurrent phenomenon has occurred. When an overcurrent phenomenon occurs, the mirror current Id' is greater than 6mA, and the voltage signal VIN is less than 1.2V, that is, VIN is less than VREF. After a short delay, the output signal VOUT of the comparator 21 is 0. After a short delay of the first inverter 22, the OCP signal is 1 at time t2. After a short delay of the second inverter 23, the control signal 0 and the PWM signal are simultaneously connected to the AND gate 31, and the output signal 0 is output to the level converter 30. The output end of the level converter 30 outputs a negative voltage shutdown signal VNEG to the control electrode of the GaN-based transistor M0, that is, VG is -20V, which is less than the threshold voltage Vth, so that the GaN-based transistor M0 is turned off. After the GaN-based transistor M0 is turned off, the current Id of the path where it is located gradually decreases to 0 and turns off, and then returns to a normal working state without an overcurrent phenomenon at t3.
[0063] Figure 4 Schematic diagram of a GaN-based transistor provided by an embodiment of the present disclosure. The GaN-based transistor is a depletion-type GaN-based transistor. Figure 4 As shown, the GaN-based transistor includes a substrate 101, a nucleation layer 102, a buffer layer 103 and a device layer 104. The nucleation layer 102, the buffer layer 103 and the device layer 104 are sequentially stacked on the surface of the substrate 101.
[0064] Optionally, the substrate 101 is a GaN substrate, a sapphire substrate, a Si substrate or a SiC substrate.
[0065] In the embodiment of the present disclosure, the substrate 101 is a Si substrate.
[0066] Optionally, the nucleation layer 102 is an AlN nucleation layer. The nucleation layer 102 can alleviate the lattice mismatch of the GaN-based transistor and reduce the dislocation density of the GaN-based transistor.
[0067] Exemplarily, the nucleation layer 102 includes a low-temperature AlN nucleation layer and a high-temperature AlN nucleation layer stacked in a direction away from the substrate 101 .
[0068] Optionally, the buffer layer 103 is a GaN buffer layer. The buffer layer 103 can reduce the thermal mismatch stress between the substrate 101 and the semiconductor material, thereby ensuring good quality of the GaN-based transistor.
[0069] In other embodiments, the buffer layer 103 may include an AlGaN buffer layer and a GaN buffer layer stacked in sequence in a direction away from the substrate 101 , which is not limited in the present disclosure.
[0070] In the embodiment of the present disclosure, the device layer 104 may include a channel layer and a barrier layer stacked in sequence in a direction away from the substrate 101 .
[0071] Optionally, the channel layer is a GaN channel layer.
[0072] Optionally, the barrier layer is an AlGaN barrier layer.
[0073] Optionally, the insulating layer 105 is located on a surface of the barrier layer away from the channel layer.
[0074] Optionally, the insulating layer 105 includes a SiN layer and a SiO 2 at least one of the layers.
[0075] like Figure 4 As shown, the GaN-based transistor further includes a first electrode 106, a second electrode 107 and a control electrode 108, which are located on the surface of the insulating layer 105 away from the device layer 104. The first electrode 106 and the second electrode 107 respectively penetrate the insulating layer 105 and are connected to the barrier layer.
[0076] Exemplarily, the first electrode 106 is a drain, the second electrode 107 is a source, and the control electrode 108 is a gate.
[0077] It should be noted that Figure 4The film layer structure of the GaN-based transistor and the material of the above-mentioned film layer are shown as an example only. In other embodiments, the GaN-based transistor may also include more or fewer film layer structures, and the material of each film layer may be selected according to actual needs, etc., and there is no limitation on this in the disclosure.
[0078] The embodiment of the present disclosure also provides a switching power supply, which includes a power chip and the aforementioned overcurrent protection circuit, and the power chip and the overcurrent protection circuit are electrically connected.
[0079] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.
Claims
1. An overcurrent protection circuit, characterized in that: It comprises a switch subcircuit (1), a monitoring subcircuit (2) and a driving subcircuit (3), The switch subcircuit (1) comprises a gallium nitride-based transistor M0, a first electrode of the gallium nitride-based transistor M0 being connected to a first power supply voltage supply terminal; The input end of the monitoring subcircuit (2) is connected to the second electrode of the gallium nitride-based transistor M0, and the monitoring subcircuit (2) is used to monitor whether an overcurrent phenomenon occurs in the switch subcircuit (1), and to generate a control signal based on the monitoring result; The first input end of the driving subcircuit (3) is connected to the output end of the monitoring subcircuit (2), the second input end of the driving subcircuit (3) is connected to the driving signal supply end, the output end of the driving subcircuit (3) is connected to the control electrode of the gallium nitride based transistor M0, and the driving subcircuit (3) is used to control the gallium nitride based transistor M0 to be turned on or off according to the control signal output by the output end of the monitoring subcircuit (2) and the driving signal provided by the driving signal supply end.
2. The overcurrent protection circuit according to claim 1, characterized in that: The monitoring subcircuit (2) comprises a current mirror (20), a resistor R0 and a comparator (21). The first end of the current mirror (20) is connected to the second electrode of the gallium nitride-based transistor M0, the second end of the current mirror (20) is connected to the second power supply voltage supply end through the resistor R0, the third end of the current mirror (20) is grounded, and the current mirror (20) is used to monitor the current in the switch subcircuit (1) and generate a mirror current at the second end of the current mirror (20); The first input end of the comparator (21) is connected to the second end of the current mirror (20), the second input end of the comparator (21) is connected to the reference voltage supply end, and the output end of the comparator (21) is electrically connected to the first input end of the drive subcircuit (3).
3. The overcurrent protection circuit according to claim 2, characterized in that: The monitoring subcircuit (2) further includes a first inverter (22) and a second inverter (23). The input end of the first inverter (22) is connected to the output end of the comparator (21), and the output end of the first inverter (22) is connected to the input end of the second inverter (23); The output end of the second inverter (23) is connected to the first input end of the driving sub-circuit (3).
4. The overcurrent protection circuit according to claim 2, characterized in that: The current mirror (20) comprises a first transistor M1 and a second transistor M2, The control electrode of the first transistor M1 is respectively connected to the first electrode of the first transistor M1 and the control electrode of the second transistor M2, the first electrode of the first transistor M1 is the first end of the current mirror (20), and the second electrode of the first transistor M1 is the third end of the current mirror (20); The first electrode of the second transistor M2 is the second end of the current mirror (20), and the second electrode of the second transistor M2 is connected to the second electrode of the first transistor M1.
5. The overcurrent protection circuit according to claim 4, characterized in that: The ratio of the width to length ratio of the first transistor M1 to the width to length ratio of the second transistor M2 is 9000 to 11000.
6. The overcurrent protection circuit according to any one of claims 2 to 5, characterized in that: The voltage of the reference voltage supply terminal is 1V to 3V.
7. The overcurrent protection circuit according to any one of claims 1 to 5, characterized in that: The driving subcircuit (3) comprises an AND gate (31) and a level converter (30). The first input end of the AND gate (31) is connected to the output end of the monitoring subcircuit (2), and the second input end of the AND gate (31) is connected to the driving signal providing end; The first input end of the level converter (30) is connected to the output end of the AND gate (31), the second input end of the level converter (30) is grounded, the third input end of the level converter (30) is connected to the negative voltage supply end of the power supply, the output end of the level converter (30) is connected to the control electrode of the gallium nitride-based transistor M0, and the level converter (30) is used to control the signal output from the output end of the level converter (30) to be a ground signal or a negative voltage shutdown signal according to the signal output from the output end of the AND gate (31).
8. The overcurrent protection circuit according to any one of claims 1 to 5, characterized in that: The driving signal providing end is used for providing a pulse width modulation signal.
9. The overcurrent protection circuit according to any one of claims 1 to 5, characterized in that: The gallium nitride based transistor M0 is a P-channel depletion type gallium nitride based transistor.
10. A switching power supply, characterized in that: It comprises a power chip and the overcurrent protection circuit according to any one of claims 1 to 9, wherein the power chip and the overcurrent protection circuit are electrically connected.