Self-biased MIPI high-speed receiver with positive feedback
By adopting mutually coupled positive feedback structure and self-biasing design in MIPI high-speed receivers, the problem of sacrificing gain, power consumption and common mode voltage input range when improving bandwidth and data transmission rates in the prior art is solved, and the problem of sacrificing gain, power consumption and common mode voltage input range is realized. Higher gain and faster data transfer rates, while reducing power consumption and integrated area.
Patent Information
- Application Number
- CN202411530302.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-02-21
AI Technical Summary
Existing high-speed receivers often need to sacrifice gain, power consumption, and common-mode voltage input range when increasing bandwidth and data transmission rates, resulting in increased system stability and R&D costs.
Using a self-biased MIPI high-speed receiver based on a mutually coupled positive feedback structure, the goal of increasing the receiver gain and improving the data transmission rate is achieved through the combined design of NMOS and PMOS transistors.
Without additional bias, the receiver gain is effectively increased, power consumption is reduced, and the data transmission rate of 2.5Gbps is achieved, and the integrated area is reduced, and the common-mode voltage input range is increased, avoiding additional voltage sources and Current source requirement.
Smart Images
Figure CN119496473A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of high-speed receiving devices, and in particular to a self-biased MIPI high-speed receiver with positive feedback. Background Art
[0002] The Mobile Industry Processor Interface (MIPI) Alliance is an organization created to unify and standardize interface standards. It standardizes the camera, display, baseband, and radio frequency interfaces in mobile devices, which can effectively solve the defects of slow speed and high power consumption of traditional interface technologies. The high-speed receiver (HS_RX) is the core module in the MIPI D-PHY physical layer, which is used to receive high-speed data.
[0003] The single-channel transmission rate of existing high-speed receivers is generally concentrated in 800Mbps-1.5Gbps. The core of the design of high-speed receiving circuit modules is bandwidth expansion. Bandwidth determines the high-speed data transmission rate, and for ordinary op amps, A V (Magnification) = G m (transconductance)*Rout, and bandwidth = 1 / (Rout*C L )(load capacitance), GBW (gain bandwidth product) = G m / C L From the above formula, it can be seen that the amplification factor is inversely proportional to the bandwidth. V If the bandwidth is large enough to obtain a higher bandwidth, then we should focus on improving GBW, that is, improving transconductance or reducing load capacitance. Improving transconductance generally requires increasing device size and raising the static operating point; then correspondingly, power consumption will also increase, and the integration area will also increase. This will bring huge challenges to system stability and R&D costs.
[0004] The existing technologies mainly include CTLE (Continuous Time Linear Equalization), CGLS (Common Gate Level Shifter) and Cherry-Hooper structure. The above three structures can improve the bandwidth. Among them, CTLE realizes the amplification of high-frequency gain through the parallel coupling of capacitors and resistors, but at the expense of low-frequency gain; while CGLS achieves the increase of high-frequency gain without sacrificing low-frequency gain by letting the current go through different capacitor channels at low and high frequencies. The common defect of both is that the use of capacitors makes the area too large. Cherry-Hooper uses a negative feedback structure. In addition, the common defects of the three are that the common-mode voltage input range is small and the power consumption is large. For this reason, VCDA-ultra-wide common-mode range differential amplifier is designed to input signals through rail-to-rail NMOS and PMOS to improve the common-mode voltage input range, but this structure still requires a lot of additional voltage sources for biasing, and the power consumption is still large.
[0005] In summary, the existing high-speed receiver structure has defects in gain, power consumption, common-mode voltage range, etc., and often in order to obtain one indicator, it is necessary to sacrifice other indicators. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a self-biased MIPI high-speed receiver with positive feedback, which effectively increases the receiver gain and improves the data transmission rate based on the mutually coupled positive feedback structure.
[0007] The present invention provides a self-biased MIPI high-speed receiver with positive feedback, comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; the source of the first transistor and the source of the second transistor are respectively connected to a negative input signal and a positive input signal; the gate of the first transistor and the gate of the second transistor are both connected to a power supply signal; the drain of the third transistor and the drain of the sixth transistor are respectively connected to the drain of the first transistor and the drain of the second transistor; the gate of the third transistor and the gate of the sixth transistor are respectively connected to the positive input signal and the negative input signal; the source of the third transistor and the source of the sixth transistor are both connected to the power supply signal; the gate of the fourth transistor and the gate of the fifth transistor are respectively connected to the drain of the first transistor and the drain of the second transistor; The drain of the second transistor is connected; the drain of the fourth transistor and the drain of the fifth transistor are respectively connected to the drain of the second transistor and the drain of the first transistor; the source of the fourth transistor and the source of the fifth transistor are both connected to the power supply signal; the gate of the seventh transistor and the gate of the eighth transistor are respectively connected to the drain of the second transistor and the drain of the first transistor; the source of the seventh transistor and the source of the eighth transistor are both grounded; the drain of the ninth transistor and the drain of the tenth transistor are respectively connected to the drain of the seventh transistor and the drain of the eighth transistor; the source of the ninth transistor and the source of the tenth transistor are both connected to the power supply signal; the gate of the ninth transistor is connected to the gate of the tenth transistor; the gate of the ninth transistor is connected to the drain of the ninth transistor; the signal of the drain of the tenth transistor is used as the output signal.
[0008] In an embodiment of the present invention, the first transistor, the second transistor, the seventh transistor and the eighth transistor are NMOS transistors.
[0009] In an embodiment of the present invention, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor and the tenth transistor are PMOS transistors.
[0010] In an embodiment of the present invention, the width-to-length ratios of the first transistor and the second transistor are equal.
[0011] In an embodiment of the present invention, the width-to-length ratios of the third transistor and the sixth transistor are equal.
[0012] In an embodiment of the present invention, the fourth transistor and the fifth transistor have the same width-to-length ratio.
[0013] In one embodiment of the present invention, a width-to-length ratio of the fourth transistor and the fifth transistor is greater than a width-to-length ratio of the third transistor and the sixth transistor.
[0014] In one embodiment of the present invention, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor constitute a first-stage gain; the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor constitute a second-stage gain; and the total gain is the product of the first-stage gain and the second-stage gain.
[0015] In one embodiment of the present invention, the first stage gain where g m1 represents the transconductance of the first transistor, g m3 represents the transconductance of the third transistor, g m4,5 represents the transconductance of the fourth transistor and the fifth transistor, r o1 represents the internal resistance of the first transistor, r o2 represents the internal resistance of the second transistor.
[0016] In one embodiment of the present invention, the second stage gain A V2 =-g m8 (r o8 / / r o10 ), where g m8 represents the transconductance of the eighth transistor, r o8 represents the internal resistance of the eighth transistor, r 10 represents the internal resistance of the tenth transistor, and / / represents parallel connection.
[0017] As described above, the self-biased MIPI high-speed receiver with positive feedback of the present invention has the following beneficial effects:
[0018] (1) Based on the mutually coupled positive feedback structure, the receiver gain is effectively increased without sacrificing the common-mode input voltage range and the first-stage output voltage swing, and without adding additional bias;
[0019] (2) Reduces power consumption to a certain extent and can achieve a data transmission rate of 2.5 Gbps;
[0020] (3) Compared with traditional structures such as CTLE and CGLS, the integration area is reduced, the common-mode voltage input range is increased, and no additional voltage source and current source are required. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 It is a schematic diagram showing the structure of a self-biased MIPI high-speed receiver in one embodiment of the present invention;
[0022] Figure 2It is a schematic structural diagram of a self-biased MIPI high-speed receiver with positive feedback in one embodiment of the present invention;
[0023] Figure 3 Shown is a receiving eye diagram of a self-biased MIPI high-speed receiver with positive feedback according to an embodiment of the present invention at a data transmission efficiency of 2.5 Gbps. DETAILED DESCRIPTION
[0024] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0025] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0026] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.
[0027] like Figure 1 As shown, in the self-biased MIPI high-speed receiver of the present invention, there is no need for a static bias such as a current source or an additional reference voltage generator, and since the signal is input from the source of the NMOS tube, it can support V CMRX ≥50mV common-mode input range (ICMR) without reducing the transmission speed. The upper limit of ICMR is (V DD -V th,p ) or slightly lower than this value, and the lower boundary is close to ground. DD is the power supply voltage, V th,pis the threshold voltage of the PMOS tube. The advantage of this structure is self-biasing, but the disadvantage is that the gain improvement is limited and the data transmission rate is still limited to 2Gbps.
[0028] like Figure 2 As shown, the self-biased MIPI high-speed receiver with positive feedback of the present invention includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10.
[0029] The source of the first transistor M1 and the source of the second transistor M2 are respectively connected to the negative input signal V INN and the positive input signal V INP The gate of the first transistor M1 and the gate of the second transistor M2 are both connected to the power supply signal V DD connected.
[0030] The drain of the third transistor M3 and the drain of the sixth transistor M6 are connected to the drain of the first transistor M1 and the drain of the second transistor M2 respectively. The gate of the third transistor M3 and the gate of the sixth transistor M6 are connected to the positive input signal V INP and the negative input signal V INN The source of the third transistor M3 and the source of the sixth transistor M6 are both connected to the power signal V DD connected.
[0031] The gate of the fourth transistor M4 and the gate of the fifth transistor M5 are connected to the drain of the first transistor M1 and the drain of the second transistor M2, respectively. The drain of the fourth transistor M4 and the drain of the fifth transistor M5 are connected to the drain of the second transistor M2 and the drain of the first transistor M1, respectively. The source of the fourth transistor M4 and the source of the fifth transistor M5 are connected to the power signal V DD connected.
[0032] The gate of the seventh transistor M7 and the gate of the eighth transistor M8 are connected to the drain of the second transistor M2 and the drain of the first transistor M1 respectively. The source of the seventh transistor M7 and the source of the eighth transistor M8 are both grounded.
[0033] The drain of the ninth transistor M9 and the drain of the tenth transistor M10 are connected to the drain of the seventh transistor M7 and the drain of the eighth transistor M8 respectively. The source of the ninth transistor M9 and the source of the tenth transistor M10 are connected to the power signal V DDThe gate of the ninth transistor M9 is connected to the gate of the tenth transistor M10. The gate of the ninth transistor M9 is connected to the drain of the ninth transistor M9. The signal of the drain of the tenth transistor M10 is used as the output signal V OUT .
[0034] In one embodiment, the first transistor M1, the second transistor M2, the seventh transistor M7 and the eighth transistor M8 are NMOS transistors, and the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9 and the tenth transistor M10 are PMOS transistors.
[0035] exist Figure 2 In the self-biased MIPI high-speed receiver with positive feedback shown in FIG. INP and the negative input signal V INN Enter the source of the first transistor M1 and the second transistor M2. The first transistor M1 and the second transistor M2 are used as a common gate amplifier. The third transistor M3 and the fourth transistor M4 are used as a common source amplifier.
[0036] The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 constitute a first-stage amplifier to form a first-stage gain. The seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 constitute a second-stage amplifier to form a second-stage gain.
[0037] In the first stage amplifier, the positive input signal V INP and the negative input signal V INN The input is from the source of the first transistor M1 and the second transistor M2, thereby ensuring a sufficiently large input common mode voltage range. The fourth transistor M4 and the fifth transistor M5 are cross-coupled to form positive feedback to improve the overall gain and avoid additional bias sources.
[0038] It should be noted that the first transistor M1 and the second transistor M2 have the same width-to-length ratio; the third transistor M3 and the sixth transistor M6 have the same width-to-length ratio; the fourth transistor M4 and the fifth transistor M5 have the same width-to-length ratio; the fourth transistor M4 and the fifth transistor M5 have a greater width-to-length ratio than the third transistor M3 and the sixth transistor M6, that is:
[0039]
[0040] Since the positive input signal VINP and the negative input signal V INN The source of the first transistor M1 and the second transistor M2 is input, and bias is provided for the third transistor M3 and the sixth transistor M6, so that the total transconductance G m =g m1 +g m3 The fourth transistor M4 and the fifth transistor M5 are coupled to each other to form positive feedback, wherein the gate voltages of the two are provided by the drains of the first transistor M1 and the second transistor M2, respectively, which is equivalent to introducing negative resistance into the circuit, thereby achieving the effect of increasing the first-stage gain, wherein the first-stage gain where g m1 represents the transconductance of the first transistor, g m3 represents the transconductance of the third transistor, g m4,5 represents the transconductance of the fourth transistor and the fifth transistor, r o1 represents the internal resistance of the first transistor, r o2 = represents the internal resistance of the second transistor. Therefore, the width-to-length ratio of the fourth transistor M4, the fifth transistor M5, the third transistor M3, the sixth transistor M6, the first transistor M1, and the second transistor M2 can be adjusted. and m4,5 The relationship between the two is used to increase the gain, thereby achieving 2.5Gbps high-speed data transmission.
[0041] The second stage gain A V2 =-g m8 (r o8 / / r o10 ), where g m8 represents the transconductance of the eighth transistor, r o8 represents the internal resistance of the eighth transistor, r 10 = represents the internal resistance of the tenth transistor, and / / represents parallel connection. Compared with the self-biased MIPI high-speed receiver of the present invention, the self-biased MIPI high-speed receiver with positive feedback of the present invention reduces a power supply signal V DD Biasing the transistor reduces the area without sacrificing gain.
[0042] Therefore, the total gain of the self-biased MIPI high-speed receiver with positive feedback of the present invention is the product of the first-stage gain and the second-stage gain, that is, A V =A V1 A V2 .
[0043] The eye diagram of the self-biased MIPI high-speed receiver with positive feedback of the present invention is simulated. The eye diagram simulation at 2.5 Gbps rate when the common mode voltage is 70 mV and the input voltage peak-to-peak value is 200 mV is as follows Figure 3 As shown in the figure, under the condition of meeting the MIPI PHY Version 2 protocol requirements, the high-speed signal received by the self-biased MIPI high-speed receiver with positive feedback of the present invention is of good quality, without distortion and being affected by a lot of noise, and the rate is increased to 2.5 Gbps without sacrificing power consumption and output voltage swing.
[0044] In summary, the self-biased MIPI high-speed receiver with positive feedback of the present invention is based on a mutually coupled positive feedback structure, which effectively increases the receiver gain without sacrificing the common-mode input voltage range and the first-stage output voltage swing and without adding additional bias; it reduces a certain amount of power consumption and can reach a data transmission rate of 2.5Gbps; compared with traditional structures such as CTLE and CGLS, it reduces the integration area, increases the common-mode voltage input range, and does not require additional voltage source and current source. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0045] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A self-biased MIPI high-speed receiver with positive feedback, characterized in that: including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The source of the first transistor and the source of the second transistor are connected to a negative input signal and a positive input signal respectively; the gate of the first transistor and the gate of the second transistor are both connected to a power supply signal; The drain of the third transistor and the drain of the sixth transistor are connected to the drain of the first transistor and the drain of the second transistor respectively; the gate of the third transistor and the gate of the sixth transistor are connected to the positive input signal and the negative input signal respectively; the source of the third transistor and the source of the sixth transistor are both connected to the power supply signal; The gate of the fourth transistor and the gate of the fifth transistor are connected to the drain of the first transistor and the drain of the second transistor respectively; the drain of the fourth transistor and the drain of the fifth transistor are connected to the drain of the second transistor and the drain of the first transistor respectively; the source of the fourth transistor and the source of the fifth transistor are both connected to the power supply signal; The gate of the seventh transistor and the gate of the eighth transistor are connected to the drain of the second transistor and the drain of the first transistor respectively; the source of the seventh transistor and the source of the eighth transistor are both grounded; The drain of the ninth transistor and the drain of the tenth transistor are respectively connected to the drain of the seventh transistor and the drain of the eighth transistor; the source of the ninth transistor and the source of the tenth transistor are both connected to the power supply signal; the gate of the ninth transistor is connected to the gate of the tenth transistor; the gate of the ninth transistor is connected to the drain of the ninth transistor; the signal of the drain of the tenth transistor is used as the output signal.
2. The self-biased MIPI high-speed receiver with positive feedback according to claim 1, characterized in that: The first transistor, the second transistor, the seventh transistor and the eighth transistor are NMOS transistors.
3. The self-biased MIPI high-speed receiver with positive feedback according to claim 1, characterized in that: The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the ninth transistor and the tenth transistor are PMOS transistors.
4. The self-biased MIPI high-speed receiver with positive feedback according to claim 1, characterized in that: The first transistor and the second transistor have the same width-to-length ratio.
5. The self-biased MIPI high-speed receiver with positive feedback according to claim 1, characterized in that: The third transistor and the sixth transistor have the same width-to-length ratio.
6. The self-biased MIPI high-speed receiver with positive feedback according to claim 1, characterized in that: The fourth transistor and the fifth transistor have the same width-to-length ratio.
7. The self-biased MIPI high-speed receiver with positive feedback according to claim 1, characterized in that: A width-to-length ratio of the fourth transistor and the fifth transistor is greater than a width-to-length ratio of the third transistor and the sixth transistor.
8. The self-biased MIPI high-speed receiver with positive feedback according to claim 1, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor constitute a first-stage gain; the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor constitute a second-stage gain; The total gain is the product of the first stage gain and the second stage gain.
9. The self-biased MIPI high-speed receiver with positive feedback according to claim 8, characterized in that: The first stage gain where g m1 represents the transconductance of the first transistor, g m3 represents the transconductance of the third transistor, g m4,5 represents the transconductance of the fourth transistor and the fifth transistor, r o1 represents the internal resistance of the first transistor, r o2 represents the internal resistance of the second transistor.
10. The self-biased MIPI high-speed receiver with positive feedback according to claim 8, characterized in that: The second stage gain A V2 =-g m8 (r o8 / / r o10 ), where g m8 represents the transconductance of the eighth transistor, r o8 represents the internal resistance of the eighth transistor, r 10 represents the internal resistance of the tenth transistor, and / / represents parallel connection.