Frequency comparator circuit and frequency comparator
By designing frequency comparator circuits, including filters, subtractors and hysteresis circuits, the problem of digital logic circuits dealing with delays and analog circuit ringing is solved, and more stable and accurate frequency comparison is achieved, and the system response speed and performance is improved. .
Patent Information
- Application Number
- CN202411502764.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-02-21
AI Technical Summary
The digital logic circuit responds slowly due to processing delays when comparing frequency. The analog circuit causes ringing due to noise and parasitic effects when processing adjacent frequency signals, and the comparison results are unstable.
A frequency comparator circuit is designed, including a filter circuit, a subtractor circuit and a hysteresis circuit. The filter circuit converts the frequency signal into a voltage signal and attenuates high-frequency noise. The subtractor circuit calculates the voltage difference of the voltage signal to accurately compare the signal amplitude difference. The hysteresis circuit has hysteresis characteristics when comparing the results to prevent error triggering and ringing. .
A more stable and accurate frequency comparison is achieved, which reduces the occurrence of ringing phenomena and improves the system's response speed and performance in high-frequency environments.
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Figure CN119496489A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit design, for example, to a frequency comparator circuit and a frequency comparator. Background Art
[0002] In integrated circuit technology, digital logic circuits are widely used in frequency comparison and signal processing due to their high programmability and flexibility. Digital circuits can perform complex logic operations and are easy to integrate and automate. However, when performing frequency comparison, digital circuits usually require a full clock cycle to complete data acquisition and processing. This processing method causes a delay in the comparison cycle, limiting the response speed and performance of the system in high-frequency environments.
[0003] In the related art, in order to improve the response speed, a pure analog circuit is used for frequency comparison. Based on the phase or amplitude difference of the two signals, when two frequency signals are input to the comparator, the comparator determines which signal has a higher frequency according to the specific characteristics of the signals.
[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:
[0005] When analog circuits process adjacent frequency signals, ringing occurs due to parasitic effects and noise in the circuits, resulting in unstable comparison results.
[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.
[0008] Embodiments of the present disclosure provide a frequency comparator circuit and a frequency comparator to achieve more stable and accurate frequency comparison.
[0009] In some embodiments, the frequency comparator circuit includes: a filter circuit, configured to convert a first frequency signal and a second frequency signal into a first voltage signal and a second voltage signal; a subtractor circuit, connected to the filter circuit, configured to perform a subtraction calculation on the first voltage signal and the second voltage signal, and output a calculation result; a hysteresis circuit, connected to the subtractor circuit, configured to output a comparison result based on the calculation result; wherein, when the calculation result is less than a first threshold voltage, the first comparison result is output; when the calculation result is greater than a second threshold voltage, the second comparison result is output; when the calculation result is greater than or equal to the first threshold voltage, and less than or equal to the second threshold voltage, the comparison result of the previous state is output.
[0010] Optionally, the filter circuit includes: a first filter branch configured to convert a first frequency signal into a first voltage signal; and a second filter branch configured to convert a second frequency signal into a second voltage signal.
[0011] Optionally, the first filter branch includes: a first resistor and a first capacitor; the first end of the first resistor is configured to receive a first frequency signal; the second end of the first resistor is connected to the first end of the first capacitor and is configured to output a first voltage signal; the second end of the first capacitor is grounded; the second filter branch includes: a second resistor and a second capacitor; the first end of the second resistor is configured to receive a second frequency signal; the second end of the second resistor is connected to the first end of the second capacitor and is configured to output a second voltage signal; the second end of the second capacitor is grounded.
[0012] Optionally, the resistance value of the first resistor is the same as the resistance value of the second resistor; the capacitance value of the first capacitor is the same as the capacitance value of the second capacitor.
[0013] Optionally, the frequency of the first frequency signal and the frequency of the second frequency signal are both not 0 and are less than the cutoff frequency of the first filter branch; the cutoff frequency of the first filter branch is the same as the cutoff frequency of the second filter branch.
[0014] Optionally, the subtractor circuit includes: a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and an operational amplifier; the first end of the third resistor is configured to receive a first voltage signal; the second end of the third resistor and the first end of the fifth resistor are both connected to the positive input terminal of the operational amplifier; the first end of the fourth resistor is configured to receive a second voltage signal; the second end of the fourth resistor and the first end of the sixth resistor are both connected to the negative input terminal of the operational amplifier; the second end of the sixth resistor is grounded; the output end of the operational amplifier is connected to the second end of the fifth resistor, and is configured to output a calculation result.
[0015] Optionally, the hysteresis circuit includes: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first NPN transistor, and a second NPN transistor; the base of the first NPN transistor is connected to the first end of the eleventh resistor and is configured to receive a calculation result; the collector of the first NPN transistor is connected to the first end of the seventh resistor and the first end of the eighth resistor; the emitter of the first NPN transistor is connected to the first end of the twelfth resistor and the emitter of the second NPN transistor; the second end of the seventh resistor is connected to a power supply; the second end of the eighth resistor and the first end of the tenth resistor are connected to the base of the second NPN transistor; the first end of the ninth resistor is connected to a power supply; the second end of the ninth resistor is connected to the collector of the second NPN transistor and is configured to output a comparison result; the second end of the tenth resistor, the second end of the eleventh resistor, and the second end of the twelfth resistor are all grounded.
[0016] Optionally, the current flowing through the first NPN transistor is smaller than the current flowing through the second NPN transistor.
[0017] Optionally, the first threshold voltage LTP=I VT1 ×R 12 , the second threshold voltage UTP=I VT2 ×R 12 ; Among them, I VT1 is the conduction current of the first NPN transistor, I VT2 is the conduction current of the second NPN transistor, R 12 is the resistance value of the twelfth resistor.
[0018] In some embodiments, the frequency comparator includes: a frequency comparator circuit as described above.
[0019] The frequency comparator circuit and the frequency comparator provided by the embodiments of the present disclosure can achieve the following technical effects:
[0020] In the disclosed embodiment, the frequency comparator circuit includes a filter circuit, a subtractor circuit and a hysteresis circuit. Through the filter circuit, the frequency signal to be compared can be converted into a voltage signal, and high-frequency noise and interference can also be attenuated, thereby reducing the high-frequency component in the frequency signal and reducing the occurrence of ringing. Then, the voltage difference of the voltage signal is calculated by the subtractor circuit, and the amplitude difference of the two signals can be compared more accurately without being affected by the noise in a single signal. Finally, through the hysteresis circuit, the comparison result has a hysteresis characteristic when it changes. When the calculation result changes between the first threshold voltage and the second threshold voltage, the comparison result will maintain the previous state, thereby eliminating the false triggering caused by the similar frequency of the frequency signal to be compared and reducing the ringing phenomenon. Therefore, through the mutual cooperation between the filter circuit, the subtractor circuit and the hysteresis circuit, a more stable and accurate frequency comparison is achieved.
[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:
[0023] Figure 1 is a circuit framework schematic diagram of a frequency comparator circuit provided by an embodiment of the present disclosure;
[0024] Figure 2 is a circuit diagram of a filter circuit of a frequency comparator circuit provided by an embodiment of the present disclosure;
[0025] Figure 3 is a circuit diagram of a subtractor circuit of a frequency comparator circuit provided by an embodiment of the present disclosure;
[0026] Figure 4 is a circuit diagram of a hysteresis circuit of a frequency comparator circuit provided by an embodiment of the present disclosure;
[0027] Figure 5 is a circuit diagram of a frequency comparator circuit provided by an embodiment of the present disclosure;
[0028] Figure 6 This is a timing diagram of input and output of a hysteresis circuit of a frequency comparator circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0029] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.
[0030] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.
[0031] Unless otherwise stated, the term "plurality" means two or more.
[0032] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.
[0033] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.
[0034] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.
[0035] Combination Figure 1 As shown, the embodiment of the present disclosure provides a frequency comparator circuit, including a filter circuit 10, a subtractor circuit 20 and a hysteresis circuit 30. The filter circuit 10 is configured to convert a first frequency signal f1 and a second frequency signal f2 into a first voltage signal V OUT1 and the second voltage signal V OUT2 The subtractor circuit 20 is connected to the filter circuit 10 and is configured to OUT1 and the second voltage signal V OUT2 Perform subtraction calculation and output the calculation result V i The hysteresis circuit 30 is connected to the subtractor circuit 20 and is configured to i Output comparison result V O Among them, in the calculation result V i When the calculated result V i When the calculated result V i When the voltage is greater than or equal to the first threshold voltage and less than or equal to the second threshold voltage, the comparison result of the previous state is output.
[0036] In the embodiment of the present disclosure, the frequency signal to be compared can be converted into a voltage signal through the filter circuit 10, and high-frequency noise and interference can be attenuated at the same time, thereby reducing the high-frequency component in the frequency signal and reducing the occurrence of ringing. Then, the voltage difference of the voltage signal is calculated by the subtractor circuit 20, so that the amplitude difference of the two signals can be compared more accurately without being affected by the noise in a single signal. Finally, the comparison result V O It has hysteresis characteristics when changing. When the calculated result V i When the comparison result V changes between the first threshold voltage and the second threshold voltage, OThe previous state will be maintained, thereby eliminating false triggering caused by the similar frequencies of the frequency signals to be compared and reducing ringing. Therefore, through the mutual cooperation between the filter circuit 10, the subtractor circuit 20 and the hysteresis circuit 30, a more stable and accurate frequency comparison is achieved.
[0037] Optionally, combined Figure 2 As shown, the filter circuit 10 includes a first filter branch 11 and a second filter branch 12. The first filter branch 11 is configured to convert the first frequency signal f1 into a first voltage signal V OUT1 The second filter branch 12 is configured to convert the second frequency signal f2 into a second voltage signal V OUT2 .
[0038] In this embodiment, in order to realize the conversion of the first frequency signal f1 and the second frequency signal f2, two filter branches are provided to process the first frequency signal f1 and the second frequency signal f2 respectively. In order to improve the relative accuracy of the converted voltage signal, the first filter branch 11 and the second filter branch 12 are the same circuit.
[0039] Optionally, combined Figure 2 and Figure 5 As shown, the first filter branch 11 includes a first resistor R1 and a first capacitor C1. The first end of the first resistor R1 is configured to receive a first frequency signal f1; the second end of the first resistor R1 is connected to the first end of the first capacitor C1 and is configured to output a first voltage signal V OUT1 The second end of the first capacitor C1 is grounded. The second filter branch 12 includes a second resistor R2 and a second capacitor C2. The first end of the second resistor R2 is configured to receive the second frequency signal f2; the second end of the second resistor R2 is connected to the first end of the second capacitor C2, and is configured to output a second voltage signal V OUT2 ; The second end of the second capacitor C2 is grounded.
[0040] In this embodiment, the first filter branch 11 and the second filter branch 12 are both configured as RC low-pass filters, thereby achieving attenuation of high-frequency signals, so that only low-frequency signals to be compared pass through, while high-frequency noise is effectively filtered out.
[0041] Optionally, the resistance value of the first resistor R1 is the same as the resistance value of the second resistor R2; the capacitance value of the first capacitor C1 is the same as the capacitance value of the second capacitor C2.
[0042] In this embodiment, the same resistor and capacitor are arranged in the first filter branch 11 and the second filter branch 12, so that the two branches process the frequency signal in the same way, thereby obtaining an accurate voltage signal.
[0043] Optionally, the frequency of the first frequency signal f1 and the frequency of the second frequency signal f2 are both not 0 and are less than the cutoff frequency of the first filter branch 11 ; the cutoff frequency of the first filter branch 11 is the same as the cutoff frequency of the second filter branch 12 .
[0044] Since the filter branch is an RC low-pass filter, the frequencies of the first frequency signal f1 and the second frequency signal f2 to be compared need to be less than the cut-off frequency of the RC low-pass filter, thereby ensuring that the voltage signal can be obtained.
[0045] The function of the filter circuit 10 will be described below with reference to a specific embodiment.
[0046] Assume that the values of the first frequency signal f1 and the second frequency signal f2 are both A. In the filter circuit 10, the resistance value R1 of the first resistor R1 and the resistance value R2 of the second resistor R2 are the same, R1=R2; the capacitance value C1 of the first capacitor C1 and the capacitance value C2 of the second capacitor C2 are the same, C1=C2. At this time, the cutoff frequency f0 of the first filter branch 11 and the second filter branch 12 is:
[0047]
[0048] When the input frequency is f, the impedance Z seen from the input port is:
[0049]
[0050] The voltage V after the RC filter OUT for:
[0051]
[0052] In the above formula, we can find that the frequency f of the frequency signal and the voltage V of the voltage signal OUT The frequency comparison result V of the frequency signal can be obtained by comparing the voltage of the voltage signal. O .
[0053] In addition, when the input frequency is the cutoff frequency f0, we can get:
[0054] VOUT 0.707A
[0055] Therefore, for the frequency comparator circuit provided in the embodiment of the present disclosure, the frequencies of the first frequency signal f1 and the second frequency signal f2 need to be non-zero and less than the cutoff frequency f0, while the amplitude A is non-zero, and R1, R2, C1, and C2 are also non-zero.
[0056] Optionally, combined Figure 3 and Figure 5As shown, the subtractor circuit 20 includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and an operational amplifier A. The first end of the third resistor R3 is configured to receive the first voltage signal V OUT1 The second end of the third resistor R3 and the first end of the fifth resistor R5 are both connected to the positive input terminal of the operational amplifier A; the first end of the fourth resistor R4 is configured to receive the second voltage signal V OUT2 The second end of the fourth resistor R4 and the first end of the sixth resistor R6 are both connected to the negative input end of the operational amplifier A; the second end of the sixth resistor R6 is grounded; the output end of the operational amplifier A is connected to the second end of the fifth resistor R5, and is configured to output the calculation result V i .
[0057] In this embodiment, it is assumed that the first frequency signal f1 outputs a first voltage signal V after passing through the first filter branch 11. OUT1 The second frequency signal f2 passes through the second filter branch 12 and outputs a second voltage signal V OUT2 The first voltage signal V OUT1 and the second voltage signal V OUT2 Input to the subtractor circuit 20. If the resistance values of the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 in the subtractor circuit 20 are all equal, the calculation result V i =V OUT1 -V OUT2 .
[0058] Optionally, combined Figure 4 and Figure 5 As shown, the hysteresis circuit 30 includes: a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first NPN transistor VT1, and a second NPN transistor VT2. The base of the first NPN transistor VT1 is connected to the first end of the eleventh resistor R11 and is configured to receive the calculation result V i ; The collector of the first NPN transistor VT1 is connected to the first end of the seventh resistor R7 and the first end of the eighth resistor R8; the emitter of the first NPN transistor VT1 is connected to the first end of the twelfth resistor R12 and the emitter of the second NPN transistor VT2; the second end of the seventh resistor R7 is connected to the power supply; the second end of the eighth resistor R8 and the first end of the tenth resistor R10 are connected to the base of the second NPN transistor VT2; the first end of the ninth resistor R9 is connected to the power supply; the second end of the ninth resistor R9 is connected to the collector of the second NPN transistor VT2, and is configured to output the comparison result V O The second end of the tenth resistor R10, the second end of the eleventh resistor R11, and the second end of the twelfth resistor R12 are all grounded.
[0059] In this embodiment, the hysteresis circuit 30 is configured as a Schmitt trigger. The hysteresis characteristic of the Schmitt trigger makes the comparison result V O There is a hysteresis interval in the output process. Taking the power supply voltage VCC = 5V as an example, in the hysteresis circuit 30, after the power supply is powered on, if V i There is no input, at this time V i =0, VCC = 5V, the first NPN transistor VT1 is in the cut-off state, and the second NPN transistor VT2 is in the saturation state. i When the input signal is generated, V i Gradually increases, at this time, the collector voltage of the first NPN transistor VT1 gradually decreases, the base voltage of the second NPN transistor VT2 gradually decreases, the emitter voltage of the second NPN transistor VT2 decreases, and the emitter voltage of the first NPN transistor VT1 decreases, forming a positive feedback trend to promote the conduction saturation of the first NPN transistor VT1. Therefore, only when V i When it increases to a certain extent, the base voltage of the second NPN transistor VT2 will be less than the emitter voltage of the second NPN transistor VT2, and finally the second NPN transistor VT2 will be cut off, and the first NPN transistor VT1 will be saturated and turned on. O Output high level, that is, V O =5V. When V i When V gradually decreases, the base voltage of the first NPN transistor VT1 gradually decreases, the collector voltage of the first NPN transistor VT1 gradually increases, the emitter voltage of the first NPN transistor VT1 gradually decreases, and the emitter voltage of the second NPN transistor VT2 gradually decreases, forming a positive feedback trend to promote the saturation conduction of the second NPN transistor VT2. Therefore, only when V i When it decreases to a certain extent, the base voltage of the second NPN transistor VT2 will be greater than the emitter voltage of the second NPN transistor VT2, and finally the second NPN transistor VT2 will be turned on and the first NPN transistor VT1 will be turned off. O Output low level, that is, V O =0V.
[0060] Therefore, combined with Figure 6 As shown, in the hysteresis circuit 30, if the first comparison result is to be output, that is, V O is low level, the calculated result V i must be less than the first voltage threshold LTP; if the second comparison result is to be output, that is, V O is high level, the calculated result V i must be greater than the second voltage threshold UTP. If the calculated result V iis greater than or equal to the first threshold voltage LTP, and less than or equal to the second threshold voltage UTP, at this time the output will maintain the comparison result of the previous state, that is, the comparison result V O The difference between the first threshold voltage LTP and the second voltage threshold UTP is the hysteresis width. Within the hysteresis width, if the calculated result V i The output of the hysteresis circuit 30 will still maintain the comparison result V of the previous state. O , thus achieving a more accurate frequency comparison. According to the comparison result V O , if V O is low level, indicating that the first voltage signal V OUT1 The voltage value is less than the second voltage signal V OUT2 The voltage value of the first frequency signal f1 is greater than the frequency of the second frequency signal f2 due to the inverse relationship between the voltage signal and the frequency signal. O is a high level, indicating that the frequency of the first frequency signal f1 is lower than the frequency of the second frequency signal f2.
[0061] Optionally, the current flowing through the first NPN transistor VT1 is smaller than the current flowing through the second NPN transistor VT2 .
[0062] In this embodiment, in order to reduce the oscillation phenomenon, it is also necessary to reasonably set the resistance value so that the current flowing through the first NPN transistor VT1 is smaller than the current flowing through the second NPN transistor VT2. If the current flowing through the first NPN transistor VT1 is larger than the current flowing through the second NPN transistor VT2, when V i When the on-state voltage of the first NPN transistor VT1 is increased, the voltage of the emitter of the first NPN transistor VT1 will increase instantly, causing the first NPN transistor VT1 to be turned off again, V i Continue to increase, thus repeating the above phenomenon, and then oscillation occurs.
[0063] Optionally, the first threshold voltage LTP=I VT1 ×R 12 , the second threshold voltage UTP=I VT2 ×R 12 Among them, I VT1 is the conduction current of the first NPN transistor VT1, I VT2 is the conduction current of the second NPN transistor VT2, R 12 is the resistance value of the twelfth resistor R12.
[0064] In this embodiment, it is necessary to select reasonable devices to ensure that the hysteresis width of the hysteresis circuit is an appropriate value. If the hysteresis width is too small, the hysteresis circuit will only have a weak hysteresis characteristic, so that the comparison result V O If the hysteresis width is too large, the frequency comparison result will not appear, thus affecting the accuracy of the frequency comparison.
[0065] An embodiment of the present disclosure provides a frequency comparator, comprising the frequency comparator circuit as described above.
[0066] The frequency comparator provided in the embodiment of the present disclosure overcomes the periodic delay problem of pure digital logic circuits in frequency comparison and the ringing phenomenon that may occur when pure analog circuits process adjacent frequency signals by introducing a low-pass filter and a hysteresis comparison circuit. The embodiment of the present disclosure combines the fast response characteristics of analog circuits and the precise control capabilities of digital circuits, providing a more efficient and stable frequency comparison solution for applications such as high-speed communication, precision measurement, and real-time control systems.
[0067] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.
[0068] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.
[0069] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.
Claims
1. A frequency comparator circuit, characterized in that: include: a filter circuit configured to convert the first frequency signal and the second frequency signal into a first voltage signal and a second voltage signal; A subtractor circuit, connected to the filter circuit, configured to perform a subtraction calculation on the first voltage signal and the second voltage signal, and output a calculation result; a hysteresis circuit connected to the subtractor circuit and configured to output a comparison result according to the calculation result; Wherein, when the calculation result is less than the first threshold voltage, a first comparison result is output; When the calculation result is greater than the second threshold voltage, the second comparison result is output; when the calculation result is greater than or equal to the first threshold voltage and less than or equal to the second threshold voltage, the comparison result of the previous state is output.
2. The frequency comparator circuit according to claim 1, characterized in that: The filter circuit includes: A first filter branch is configured to convert a first frequency signal into a first voltage signal; The second filter branch is configured to convert the second frequency signal into a second voltage signal.
3. The frequency comparator circuit according to claim 2, characterized in that: The first filter branch includes: a first resistor and a first capacitor; The first end of the first resistor is configured to receive a first frequency signal; the second end of the first resistor is connected to the first end of the first capacitor and is configured to output a first voltage signal; the second end of the first capacitor is grounded; The second filter branch includes: a second resistor and a second capacitor; The first end of the second resistor is configured to receive a second frequency signal; the second end of the second resistor is connected to the first end of the second capacitor and is configured to output a second voltage signal; the second end of the second capacitor is grounded.
4. The frequency comparator circuit according to claim 3, characterized in that: The resistance value of the first resistor is the same as the resistance value of the second resistor; the capacitance value of the first capacitor is the same as the capacitance value of the second capacitor.
5. The frequency comparator circuit according to claim 4, characterized in that: The frequency of the first frequency signal and the frequency of the second frequency signal are both not 0 and are less than the cutoff frequency of the first filter branch; the cutoff frequency of the first filter branch is the same as the cutoff frequency of the second filter branch.
6. The frequency comparator circuit according to claim 1, characterized in that: The subtractor circuit includes: a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and an operational amplifier; The first end of the third resistor is configured to receive a first voltage signal; the second end of the third resistor and the first end of the fifth resistor are both connected to the positive input terminal of the operational amplifier; the first end of the fourth resistor is configured to receive a second voltage signal; the second end of the fourth resistor and the first end of the sixth resistor are both connected to the negative input terminal of the operational amplifier; the second end of the sixth resistor is grounded; the output terminal of the operational amplifier is connected to the second end of the fifth resistor and is configured to output the calculation result.
7. The frequency comparator circuit according to claim 1, characterized in that: The hysteresis circuit includes: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first NPN transistor, and a second NPN transistor; The base of the first NPN transistor is connected to the first end of the eleventh resistor and is configured to receive the calculation result; the collector of the first NPN transistor is connected to the first end of the seventh resistor and the first end of the eighth resistor; the emitter of the first NPN transistor is connected to the first end of the twelfth resistor and the emitter of the second NPN transistor; the second end of the seventh resistor is connected to the power supply; the second end of the eighth resistor and the first end of the tenth resistor are connected to the base of the second NPN transistor; the first end of the ninth resistor is connected to the power supply; the second end of the ninth resistor is connected to the collector of the second NPN transistor and is configured to output the comparison result; the second end of the tenth resistor, the second end of the eleventh resistor, and the second end of the twelfth resistor are all grounded.
8. The frequency comparator circuit according to claim 7, characterized in that: The current flowing through the first NPN transistor is smaller than the current flowing through the second NPN transistor.
9. The frequency comparator circuit according to claim 7, characterized in that: The first threshold voltage LTP=I VT1 ×R 12 , the second threshold voltage UTP=I VT2 ×R 12 ; Among them, I VT1 is the conduction current of the first NPN transistor, I VT2 is the conduction current of the second NPN transistor, R 12 is the resistance value of the twelfth resistor.
10. A frequency comparator, characterized in that: include: A frequency comparator circuit as claimed in any one of claims 1 to 9.