Power-down reset circuit based on SRAM (Static Random Access Memory) array

Abstract

The invention discloses a power-down reset circuit based on an SRAM (Static Random Access Memory) array, which comprises a starting control circuit for generating a starting signal according to a power supply voltage; the starting circuit enables the current reference circuit to work stably according to a starting signal so as to get rid of a degeneracy point; the current reference circuit is used for generating load current of the SRAM according to the power supply voltage under the influence of the starting circuit; a current mirror that copies a load current to each SRAM in the SRAM array; each SRAM respectively compares the load current with the latch current of a latch of the SRAM, and outputs a respective comparison result; and the output logic circuit is used for outputting a control signal according to all comparison results so as to control whether the FPGA chip is reset or not. A starting control circuit and a starting circuit are introduced to get rid of a degeneracy point; the SRAM output value is changed by comparing the load current with the SRAM latch current, and a reference voltage and a resistor string are omitted, so that the circuit area is reduced, and the power consumption is reduced.

Description

Technical Field

[0001] The invention belongs to the field of power management integrated circuits, and in particular relates to a power-off reset circuit based on an SRAM array. Background Art

[0002] In the power management system of FPGA (Field Programmable Gate Array) chip, the brown-out reset circuit can provide the FPGA with an early warning signal of power drop. Once the VCC power drops to a certain threshold (trip point), the FPGA is reset in time to prevent the system from losing control. It is mainly to ensure that the FPGA can be restored to the initial state after power failure, thereby avoiding problems such as uncertain circuit state or data loss caused by power failure.

[0003] The existing power-off reset circuit mainly uses a comparator structure to compare the power supply voltage. When the power supply voltage drops to the trip point, the comparator flips and generates a reset signal to the circuit. However, when comparing the power supply voltage, the existing comparator requires a reference voltage and uses a resistor string to divide the voltage, which requires a large power consumption and area. In addition, in the circuit of the reference current that is independent of the power supply, there is a "degenerate point" problem, that is, for the reference current generation circuit, if all transistors transmit zero current when the power supply is powered on, since the branches on both sides of the loop allow zero current, they can remain off indefinitely, which is difficult to predict. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a power-off reset circuit based on an SRAM array. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides a power-off reset circuit based on an SRAM array, comprising:

[0006] A startup control circuit, a startup circuit, a current reference circuit, a current mirror, an SRAM array and an output logic circuit; the SRAM array includes a plurality of SRAMs; wherein,

[0007] The startup control circuit is used to generate a startup signal startup according to the power supply voltage VCC;

[0008] The startup circuit is used to make the current reference circuit work stably to get rid of the degeneracy point according to the startup signal startup;

[0009] The current reference circuit is used to generate a load current of the SRAM according to the power supply voltage VCC under the influence of the startup circuit;

[0010] The current mirror is used to copy the load current to each SRAM in the SRAM array;

[0011] The SRAM array is used to compare the load current with the latch current of its own latch by using each SRAM, and output respective comparison results;

[0012] The output logic circuit is used to output a reset signal por_n according to all comparison results to control whether the FPGA chip is reset.

[0013] Beneficial effects of the present invention:

[0014] In the solution provided by the present invention, by introducing a startup control circuit and a startup circuit, the current reference circuit can be driven to get rid of the degeneracy point when the power supply is powered on, so that the current reference circuit works stably, and the startup circuit can be turned off after the circuit is normally started; the load current is compared with the SRAM latch current in the SRAM array to change the SRAM output value, and then a reset signal is given, and the reference voltage and the resistor string used for voltage division are omitted, thereby greatly reducing the circuit area. After enabling the shutdown of the power supply voltage detection, it is used as a low-power circuit for detecting the drop of the power supply voltage, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of a power-off reset circuit based on an SRAM array provided by an embodiment of the present invention;

[0016] Figure 2 is an example schematic diagram of a degenerate point;

[0017] Figure 3 A partial structural diagram of an SRAM detection circuit with a startup circuit provided by an embodiment of the present invention;

[0018] Figure 4 A schematic diagram of the structure of a startup control circuit provided by an embodiment of the present invention;

[0019] Figure 5 A schematic diagram of a startup signal changing with VCC provided by an embodiment of the present invention;

[0020] Figure 6 A schematic diagram of the structure of an output logic circuit provided by an embodiment of the present invention;

[0021] Figure 7 A schematic diagram of power supply and circuit output provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0023] The embodiment of the present invention provides a power-off reset circuit based on an SRAM array, such as Figure 1 As shown, this may include:

[0024] A startup control circuit, a startup circuit, a current reference circuit, a current mirror, an SRAM array and an output logic circuit; the SRAM array includes a plurality of SRAMs; wherein,

[0025] The startup control circuit is used to generate a startup signal startup according to the power supply voltage VCC;

[0026] The startup circuit is used to make the current reference circuit work stably to get rid of the degeneracy point according to the startup signal startup;

[0027] The current reference circuit is used to generate the load current of the SRAM according to the power supply voltage VCC under the influence of the startup circuit;

[0028] The current mirror is used to copy the load current to each SRAM in the SRAM array;

[0029] The SRAM array is used to compare the load current with the latch current of its own latch using each SRAM, and output respective comparison results;

[0030] The output logic circuit is used to output a reset signal por_n according to all comparison results to control whether the FPGA chip is reset.

[0031] After the chip is powered on, the power detection circuit is usually turned off to save power. The embodiment of the present invention detects the power supply voltage drop based on the SRAM (Static Random-Access Memory) array. The main purpose of designing the SRAM array to detect the VCC power supply is to detect the power supply voltage drop after the power supply voltage detection circuit is turned off after the power is powered on. There is a very important problem in the reference current circuit that is independent of the power supply, that is, there is a "degenerate point". Figure 2As shown, for the reference current generating circuit, if all transistors transmit zero current when the power is turned on, since the branches on both sides of the loop allow zero current, they can remain off indefinitely, which is difficult to predict. In other words, the circuit can be stable in two different working states. This problem is called the startup problem of the circuit, which can be solved by introducing a startup control circuit and a startup circuit. When the power is turned on, the current reference circuit can be driven out of the degeneracy point, so that the current reference circuit works stably, and the startup circuit can be turned off after the circuit is started normally; the load current is compared with the SRAM latch current in the SRAM array to change the SRAM output value, and then a reset signal is given, the reference voltage and the resistor string used for voltage division are omitted, thereby greatly reducing the circuit area, and after enabling the power supply voltage detection, it is used as a low-power circuit for detecting the power supply voltage drop, thereby reducing power consumption.

[0032] Figure 3 It is a partial structural diagram of an SRAM detection circuit with a startup circuit added. Figure 4 This is a schematic diagram of a startup control circuit provided by an embodiment of the present invention. For ease of understanding, the following will be combined with Figure 3 and Figure 4 The various modules of the power-off reset circuit based on the SRAM array provided in the embodiment of the present invention are introduced.

[0033] Start control circuit

[0034] Start control circuit such as Figure 4 As shown, this may include:

[0035] MOS tube M1, MOS tube M2, MOS tube M3, first inverter T1, second inverter T2, coupling capacitor C1, coupling capacitor C2, coupling capacitor C3, voltage divider resistor R1 and voltage divider resistor R2; wherein,

[0036] The source of the MOS tube M1 is connected to the power supply voltage VCC, the gate is connected to its own source, and the drain is connected to the second end of the coupling capacitor C1;

[0037] The source of the MOS tube M2 is grounded, the gate is connected to the first end of the coupling capacitor C2, and the drain is connected to the second end of the coupling capacitor C1;

[0038] The source of the MOS tube M3 is connected to the source of the MOS tube M2, the gate is connected to its own source, and the drain serves as the output end of the startup control circuit;

[0039] The input end of the first inverter T1 is connected to the drain of the MOS tube M3, the output end is connected to the second end of the coupling capacitor C1, the first end is connected to the power supply voltage VCC, and the second end is grounded;

[0040] The input end of the second inverter T2 is connected to the second end of the coupling capacitor C1, the output end is connected to the drain of the MOS tube M3, the first end is connected to the power supply voltage VCC, and the second end is grounded;

[0041] The first end of the coupling capacitor C1 is connected to the source of the MOS tube M1;

[0042] The first end of the coupling capacitor C2 is connected to the second end of the voltage-dividing resistor R1, and the second end is connected to the source of the MOS tube M2;

[0043] A first end of the coupling capacitor C3 is connected to the drain of the MOS tube M3, and a second end is connected to the source of the MOS tube M3;

[0044] The first end of the voltage dividing resistor R1 is connected to the power supply voltage VCC, and the second end is connected to the first end of the voltage dividing resistor R2;

[0045] The second end of the voltage dividing resistor R2 is connected to the second end of the coupling capacitor C2.

[0046] The startup control circuit is used to generate a startup signal startup according to the power supply voltage VCC. Specifically, Figure 5 A schematic diagram of a startup signal changing with VCC provided by an embodiment of the present invention, from Figure 5 As can be seen from the figure, the startup control circuit uses a cross-inverter to latch structure (Latch), voltage divider resistors and coupling capacitors, so that the startup signal startup changes during the power-on process as shown in the figure. Figure 5 As shown, Figure 5 In the expression, low_level indicates low level.

[0047] Startup Circuit

[0048] Startup circuit such as Figure 3 As shown, this may include:

[0049] MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7 and MOS tube M8; wherein,

[0050] The source of the MOS tube M4 is connected to the power supply voltage VCC, the gate is connected to the startup signal startup, and the drain is connected to the source of the MOS tube M5;

[0051] The gate of the MOS tube M5 is connected to its own drain, and the drain is connected to the drain of the MOS tube M7;

[0052] The source of the MOS tube M6 is grounded, the gate is connected to the gate of the MOS tube M7, and the drain serves as the output end of the startup circuit;

[0053] The source of the MOS tube M7 is connected to the source of the MOS tube M8, and the gate is connected to its own drain;

[0054] The source of the MOS transistor M8 is connected to the source of the MOS transistor M6 , the gate is connected to the startup signal startup , and the drain is connected to the gate of the MOS transistor M7 .

[0055] The startup circuit is used to make the current reference circuit work stably to get rid of the degeneracy point according to the startup signal startup. Specifically, the startup signal startup is kept low at the beginning of the power rise, and the PMOS tubes M4 and M5 are turned on, so that the rightmost branch of the startup circuit generates a small current, which is copied to the current reference circuit through the current mirror formed by the NMOS tubes M6 and M7, forcing the circuit to get rid of zero current. As the power supply voltage VCC rises to a sufficiently high level, the startup signal startup turns off the PMOS tubes M4 and M5 according to the increase of the power supply voltage VCC, and turns on the NMOS tube M8 under the current mirror, thereby turning off the startup circuit. It can be understood that the embodiment of the present invention can drive the current reference circuit to get rid of the degeneracy point when the power supply is powered on by introducing the startup control circuit and the startup circuit, so that the current reference circuit works stably, and the startup circuit can be turned off after the circuit is started normally.

[0056] Current reference circuit

[0057] Current reference circuit such as Figure 3 As shown, this may include:

[0058] MOS tube M9, MOS tube M10, MOS tube NMs, MOS tube NMb and resistor R3; wherein,

[0059] The source of the MOS tube M9 is connected to the source of the MOS tube M10, the gate is connected to the gate of the MOS tube M10, and the drain is connected to the drain of the MOS tube NMs;

[0060] The source of the MOS tube M10 is connected to the power supply voltage VCC, the gate is connected to its own drain, and the drain is connected to the drain of the MOS tube NMb;

[0061] The source of the MOS tube NMs is grounded, and the gate is connected to the gate of the MOS tube NMb;

[0062] The source of the MOS tube NMb is connected to the first end of the resistor R3, the gate is connected to the current mirror, and the drain is connected to the output end of the startup circuit;

[0063] A second terminal of the resistor R3 is grounded.

[0064] The current reference circuit is used to generate the load current of the SRAM according to the power supply voltage VCC under the influence of the startup circuit. Specifically, the load current of the SRAM is very small, which is generated by a current reference circuit that is independent of the power supply voltage, and then copied as the load current of the SRAM through a current mirror. The current is generated by two MOS tubes (NMs and NMb) of different sizes and resistors. The size of the MOS tube NMs is smaller than that of the MOS tube NMb. The different sizes of MOS tubes produce a gate-source voltage difference ΔVgs. The source series resistor of the large-sized MOS tube, that is, the source series resistor R3 of the MOS tube NMb, so Vgs(NMb)=Vgs(NMs)+I*R3 ， I = ΔVgs / R3 ； Among them, Vgs(NMb) represents the gate-source voltage of MOS tube NMb, and Vgs(NMs) represents the gate-source voltage of MOS tube NMs. According to the circuit structure and size, this current is very small, I is about 320nA. Because ΔVgs is very small, a large width-to-length ratio W / L should be selected in circuit design to reduce the impact of mismatch.

[0065] Current Mirror

[0066] Current mirror Figure 3 As shown, this may include:

[0067] MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17 and MOS tube M18; wherein,

[0068] The source of the MOS tube M11 is connected to the source of the MOS tube M9 and connected to the power supply voltage VCC, the gate is connected to the gate of the MOS tube M13, and the drain is connected to the drain of the MOS tube M12;

[0069] The source of the MOS tube M12 is connected to the source of the MOS tube NMs, the gate is connected to the gate of the MOS tube NMs, and the drain is connected to the gate of the MOS tube M11;

[0070] The source of the MOS tube M13 is connected to the source of the MOS tube M11, the gate is connected to the drain of the MOS tube M11, and the drain is connected to the SRAM array accordingly;

[0071] The source of the MOS tube M14 is connected to the source of the MOS tube M12, the gate is connected to the gate of the MOS tube M12, and the drain is connected to the SRAM array accordingly;

[0072] The source of the MOS tube M15 is connected to the source of the MOS tube M13, the gate is connected to the gate of the MOS tube M13, and the drain is connected to the SRAM array accordingly;

[0073] The source of the MOS tube M16 is connected to the source of the MOS tube M14, the gate is connected to the gate of the MOS tube M14, and the drain is connected to the SRAM array accordingly;

[0074] The source of the MOS tube M17 is connected to the source of the MOS tube M15, the gate is connected to the gate of the MOS tube M15, and the drain is connected to the SRAM array accordingly;

[0075] The source of the MOS tube M18 is connected to the source of the MOS tube M16 , the gate is connected to the gate of the MOS tube M16 , and the drain is connected to the SRAM array accordingly.

[0076] A current mirror is used to copy the load current to each SRAM in the SRAM array.

[0077] SRAM Array

[0078] SRAM arrays such as Figure 3 As shown, this may include:

[0079] SRAM1, SRAM2 and SRAM3; among them,

[0080] The d terminal of SRAM1 is connected to the source of MOS tube M11, the dn terminal is connected to the source of MOS tube M12, the qb terminal is connected to the drain of MOS tube M13, and the q terminal is connected to the drain of MOS tube M14;

[0081] The d terminal of SRAM2 is connected to the source of MOS tube M13, the dn terminal is connected to the source of MOS tube M14, the qb terminal is connected to the drain of MOS tube M15, and the q terminal is connected to the drain of MOS tube M16;

[0082] The d terminal of SRAM3 is connected to the source of the MOS tube M15, the dn terminal is connected to the source of the MOS tube M16, the qb terminal is connected to the drain of the MOS tube M17, and the q terminal is connected to the drain of the MOS tube M18.

[0083] The SRAM array is used to compare the load current with the latch current of its own latch by using each SRAM, and output the respective comparison results. Specifically, the main function of the embodiment of the present invention to detect the power supply voltage VCC by designing the SRAM array is to detect the power supply voltage drop after the power supply voltage detection circuit is turned off after power-on is completed.

[0084] Output logic circuit

[0085] Output logic circuit such as Figure 6 As shown, this may include:

[0086] A first NOR gate, an AND gate, and a second NOR gate; wherein,

[0087] The first input terminal of the first NOR gate is connected to the q terminal of SRAM1, the second input terminal is connected to the q terminal of SRAM2, the third input terminal is connected to the q terminal of SRAM3, and the output terminal is connected to the first input terminal of the second NOR gate;

[0088] The first input terminal of the AND gate is connected to the qb terminal of SRAM1, the second input terminal is connected to the qb terminal of SRAM2, the third input terminal is connected to the qb terminal of SRAM3, and the output terminal is connected to the second input terminal of the second NOR gate;

[0089] The output end of the second NOR gate serves as the output end of the output logic circuit, and outputs a reset signal por_n.

[0090] The output logic circuit is used to output a reset signal por_n according to all comparison results to control whether the FPGA chip is reset.

[0091] Specifically, after the FPGA chip is powered on, the addr0 signal of the SRAM array is low, the SRAM in the circuit is in storage function, and the three-way SRAM array outputs q1=q2=q3=1.2 (the high level value of VCC is 1.2), q1b=q2b=q3b=0 (the low level value of VCC is 0), and their output relationship satisfies Figure 6 As shown in the output logic circuit structure diagram, the reset signal por_n=1.2, the FPGA chip is released from the reset state and works normally. The SRAM output has a load current, the q end has a pull-down current, and the qb has a pull-up current. When the power supply voltage drops, the load current of the SRAM compares the current capability of the latch in the SRAM. When the driving capability of the load current is greater than the driving capability of the latch, the output value of the SRAM will be changed, the current at the q end will be pulled down, and the current at the qb end will be pulled up, that is, q1=q2=q3=0, q1b=q2b=q3b=1.2, the reset signal por_n=0, when the power supply voltage drops to the trip point, the FPGA chip is reset. It can be understood that the embodiment of the present invention chooses to use three-way SRAM to form an SRAM array, which can ensure that the SRAM eliminates the risk of accidentally changing the state when only one way is used, that is, soft errors may cause unexpected flips of the SRAM. When making the layout, a single-channel SRAM needs to add 8 SRAMdummies (dummy elements) to surround the SRAM in the center, and the three-channel SRAM adopts this layout. The three-channel SRAM is placed as far as possible to avoid the risk of soft errors, which may cause the SRAM to flip unexpectedly. The SRAM unit and load current are initialized after the power supply is powered on, so the SRAM does not detect the power-on process of VCC; Figure 7 The power supply and circuit output diagram provided by the embodiment of the present invention is as follows: Figure 7It can be seen that during the power-on process, its output follows the rise of the power supply voltage VCC. When VCC drops and reaches the SRAM jump point, it outputs a low-level reset signal por_n to control the reset of the FPGA chip.

[0092] It is understandable that it is very difficult to model the flip of SRAM. The embodiment of the present invention is based on the leakage current of SRAM. The leakage current of SRAM is quite small, and it will change greatly with the change of process, power supply voltage, and temperature. The load current generated by the reference current generation method in the embodiment of the present invention will be significantly larger than the leakage current of SRAM, which is convenient for detecting the flip of SRAM. Most existing methods generate reference currents through bandgap reference circuits. Compared with the embodiment of the present invention, the reference current generated by the existing method will be much larger than the reference current generated by the embodiment of the present invention. Moreover, the reference current generated by bandgap must also be copied to SRAM through several sets of current mirrors, and the area and power consumption are significantly larger than the embodiment of the present invention, which loses the original intention of saving power consumption. Moreover, the bandgap circuit needs to introduce bipolar transistors (BJT) and clamp structure circuits, etc., which requires a higher power supply voltage. The dynamic range of the power supply voltage VCC used for SRAM does not meet the bandgap structure. Therefore, the use of the bandgap structure to generate the reference current requires the introduction of an additional higher power supply voltage. If the bandgap is forced to close, the circuit loses the detection function. The embodiment of the present invention introduces a startup control circuit and a startup circuit, which can drive the current reference circuit to get rid of the degeneracy point when the power is turned on, so that the current reference circuit works stably, and the startup circuit can be turned off after the circuit is normally started; the load current is compared with the SRAM latch current in the SRAM array to change the SRAM output value, and then a reset signal is given, and the reference voltage and the resistor string used for voltage division are omitted, thereby greatly reducing the circuit area. After enabling the shutdown of the power supply voltage detection, it is used as a low-power circuit for detecting the drop of the power supply voltage, thereby reducing power consumption.

[0093] It should be noted that in the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0094] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A power-off reset circuit based on an SRAM array, characterized in that: include: Startup control circuit, startup circuit, current reference circuit, current mirror, SRAM array and output logic circuit; The SRAM array includes a plurality of SRAMs; wherein, The startup control circuit is used to generate a startup signal startup according to the power supply voltage VCC; The startup circuit is used to make the current reference circuit work stably to get rid of the degeneracy point according to the startup signal startup; The current reference circuit is used to generate a load current of the SRAM according to the power supply voltage VCC under the influence of the startup circuit; The current mirror is used to copy the load current to each SRAM in the SRAM array; The SRAM array is used to compare the load current with the latch current of its own latch by using each SRAM, and output respective comparison results; The output logic circuit is used to output a reset signal por_n according to all comparison results to control whether the FPGA chip is reset.

2. A power-off reset circuit based on an SRAM array according to claim 1, characterized in that: The startup control circuit comprises: MOS tube M1, MOS tube M2, MOS tube M3, first inverter T1, second inverter T2, coupling capacitor C1, coupling capacitor C2, coupling capacitor C3, voltage divider resistor R1 and voltage divider resistor R2; wherein, The source of the MOS tube M1 is connected to the power supply voltage VCC, the gate is connected to its own source, and the drain is connected to the second end of the coupling capacitor C1; The source of the MOS transistor M2 is grounded, the gate is connected to the first end of the coupling capacitor C2, and the drain is connected to the second end of the coupling capacitor C1; The source of the MOS tube M3 is connected to the source of the MOS tube M2, the gate is connected to its own source, and the drain serves as the output end of the startup control circuit; The input end of the first inverter T1 is connected to the drain of the MOS tube M3, the output end is connected to the second end of the coupling capacitor C1, the first end is connected to the power supply voltage VCC, and the second end is grounded; The input end of the second inverter T2 is connected to the second end of the coupling capacitor C1, the output end is connected to the drain of the MOS tube M3, the first end is connected to the power supply voltage VCC, and the second end is grounded; The first end of the coupling capacitor C1 is connected to the source of the MOS tube M1; The first end of the coupling capacitor C2 is connected to the second end of the voltage-dividing resistor R1, and the second end is connected to the source of the MOS transistor M2; The first end of the coupling capacitor C3 is connected to the drain of the MOS transistor M3, and the second end is connected to the source of the MOS transistor M3; The first end of the voltage-dividing resistor R1 is connected to the power supply voltage VCC, and the second end is connected to the first end of the voltage-dividing resistor R2; The second end of the voltage-dividing resistor R2 is connected to the second end of the coupling capacitor C2.

3. A power-off reset circuit based on an SRAM array according to claim 1, characterized in that: The starting circuit comprises: MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7 and MOS tube M8; wherein, The source of the MOS tube M4 is connected to the power supply voltage VCC, the gate is connected to the startup signal startup, and the drain is connected to the source of the MOS tube M5; The gate of the MOS tube M5 is connected to its own drain, and the drain is connected to the drain of the MOS tube M7; The source of the MOS tube M6 is grounded, the gate is connected to the gate of the MOS tube M7, and the drain serves as the output end of the startup circuit; The source of the MOS tube M7 is connected to the source of the MOS tube M8, and the gate is connected to its own drain; The source of the MOS transistor M8 is connected to the source of the MOS transistor M6 , the gate is connected to the startup signal startup , and the drain is connected to the gate of the MOS transistor M7 .

4. A power-off reset circuit based on an SRAM array according to claim 1, characterized in that: The current reference circuit comprises: MOS tube M9, MOS tube M10, MOS tube NMs, MOS tube NMb and resistor R3; wherein, The source of the MOS tube M9 is connected to the source of the MOS tube M10, the gate is connected to the gate of the MOS tube M10, and the drain is connected to the drain of the MOS tube NMs; The source of the MOS transistor M10 is connected to the power supply voltage VCC, the gate is connected to its own drain, and the drain is connected to the drain of the MOS transistor NMb; The source of the MOS transistor NMs is grounded, and the gate is connected to the gate of the MOS transistor NMb; The source of the MOS transistor NMb is connected to the first end of the resistor R3, the gate is connected to the current mirror, and the drain is connected to the output end of the startup circuit; The second end of the resistor R3 is grounded.

5. A power-off reset circuit based on an SRAM array according to claim 4, characterized in that: The current mirror comprises: MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17 and MOS tube M18; wherein, The source of the MOS tube M11 is connected to the source of the MOS tube M9 and connected to the power supply voltage VCC, the gate is connected to the gate of the MOS tube M13, and the drain is connected to the drain of the MOS tube M12; The source of the MOS tube M12 is connected to the source of the MOS tube NMs, the gate is connected to the gate of the MOS tube NMs, and the drain is connected to the gate of the MOS tube M11; The source of the MOS tube M13 is connected to the source of the MOS tube M11, the gate is connected to the drain of the MOS tube M11, and the drain is correspondingly connected to the SRAM array; The source of the MOS tube M14 is connected to the source of the MOS tube M12, the gate is connected to the gate of the MOS tube M12, and the drain is correspondingly connected to the SRAM array; The source of the MOS tube M15 is connected to the source of the MOS tube M13, the gate is connected to the gate of the MOS tube M13, and the drain is correspondingly connected to the SRAM array; The source of the MOS tube M16 is connected to the source of the MOS tube M14, the gate is connected to the gate of the MOS tube M14, and the drain is correspondingly connected to the SRAM array; The source of the MOS tube M17 is connected to the source of the MOS tube M15, the gate is connected to the gate of the MOS tube M15, and the drain is correspondingly connected to the SRAM array; The source of the MOS tube M18 is connected to the source of the MOS tube M16 , the gate is connected to the gate of the MOS tube M16 , and the drain is correspondingly connected to the SRAM array.

6. A power-off reset circuit based on an SRAM array according to claim 5, characterized in that: The SRAM array comprises: SRAM1, SRAM2 and SRAM3; among them, The d terminal of the SRAM1 is connected to the source of the MOS tube M11, the dn terminal is connected to the source of the MOS tube M12, the qb terminal is connected to the drain of the MOS tube M13, and the q terminal is connected to the drain of the MOS tube M14; The d terminal of the SRAM2 is connected to the source of the MOS tube M13, the dn terminal is connected to the source of the MOS tube M14, the qb terminal is connected to the drain of the MOS tube M15, and the q terminal is connected to the drain of the MOS tube M16; The d end of the SRAM3 is connected to the source of the MOS tube M15, the dn end is connected to the source of the MOS tube M16, the qb end is connected to the drain of the MOS tube M17, and the q end is connected to the drain of the MOS tube M18.

7. A power-off reset circuit based on an SRAM array according to claim 6, characterized in that: The output logic circuit comprises: A first NOR gate, an AND gate, and a second NOR gate; wherein, The first input terminal of the first NOR gate is connected to the q terminal of the SRAM1, the second input terminal is connected to the q terminal of the SRAM2, the third input terminal is connected to the q terminal of the SRAM3, and the output terminal is connected to the first input terminal of the second NOR gate; The first input terminal of the AND gate is connected to the qb terminal of the SRAM1, the second input terminal is connected to the qb terminal of the SRAM2, the third input terminal is connected to the qb terminal of the SRAM3, and the output terminal is connected to the second input terminal of the second NOR gate; The output end of the second NOR gate serves as the output end of the output logic circuit to output a reset signal por_n.

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