Reconfigurable all-digital transmitter combining digital-analog interpolation filtering

Abstract

The invention relates to an all-digital transmitter combining digital-analog interpolation filtering. The all-digital transmitter comprises a signal processing module, a multi-phase interpolation filtering module, a delay integration module, an image rejection preprocessing module, a frequency divider, a linear interpolation all-digital power amplifier, an SPI module and the like. According to the invention, various high-bandwidth communication protocols are supported, various working modes can be configured, the sampling rate is adjustable, and the reconfigurable characteristic is realized; a multi-phase architecture is adopted for multi-phase interpolation filtering and delay integration, the filtering function is achieved while interpolation sampling is completed, and the circuit works in a low-frequency state and has the advantage of being low in power consumption. A mirror image suppression preprocessing technology is adopted to realize a mirror image suppression effect on the frequency spectrum of the final transmitted data; on the basis of a linear interpolation DPA module, the data rate can be further improved while power synthesis is carried out, and the mirror signal suppression degree of an emission spectrum is ensured. The multi-mode low-power-consumption ultra-wideband antenna supports high bandwidth and wide frequency band, is configurable in structure, and has the characteristics of low power consumption, multiple modes, high out-of-band image rejection degree and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of wireless communication, and more specifically, relates to a reconfigurable all-digital transmitter with joint digital-analog interpolation filtering. Background Art

[0002] With the continuous rise of technologies such as artificial intelligence, automotive electronics, and remote assistance, wireless communication technology has developed rapidly and is constantly changing people's lifestyles. With the emergence of more and more application scenarios, such as smart driving, remote office, and smart home, the rapid development of wireless communication technology has become an indispensable part of people's industrial production and daily life. At the same time, human demand for larger bandwidth and higher data rates has not stopped. In particular, the number of application scenarios requiring high transmission speeds, such as video conferencing and remote classrooms, has increased. The vigorous development of video, voice, and virtual reality technologies has put forward more stringent requirements on wireless network bandwidth and latency.

[0003] Wi-Fi breaks through the limitations of wired network transmission lines and has the characteristics of high reliability. Channel bandwidth directly affects the data transmission rate, which is also the main reason why the signal bandwidth supported by the Wi-Fi protocol continues to increase during its evolution. Although Wi-Fi 5 networks can provide high channel bandwidth, the throughput performance of Wi-Fi 5 networks still cannot meet the further improvement of access density. Based on Wi-Fi 5, Wi-Fi 6 takes into account high-density wireless access and high-capacity wireless services, and adds many new features, which not only supports higher access density, but also reasonably allocates bandwidth to each user.

[0004] In traditional digital transmitters, sampling operations inevitably generate sampling images, which will threaten the MASK requirements and are undesirable, especially when the sampling rate is low, the image signals of the out-of-band spectrum are more dense. In addition, the interpolation and filtering modules in the traditional architecture all work in a high-speed digital clock state, which will significantly increase the power consumption of the digital circuit. In addition, in order to support multi-protocol and wide-band coverage, a multi-link architecture is usually optimized separately to match different frequency bands respectively, which will increase the chip area and design cost. The traditional method of eliminating images is to add an analog filter after the output signal of the transmitter, but this can generally only filter out high-order harmonics. For sampling images, especially those located in the near-sideband, it is difficult for the filter to achieve a sufficiently steep transition band to filter them out, and as the signal sampling rate increases, the power consumption of the circuit will also increase. Another method is to increase the sampling frequency of the baseband signal in the digital domain. The larger the sampling rate, the farther the sampling image is pushed, and the better the suppression. However, this method is limited by the implementation frequency of the digital circuit. Too high an operating frequency will not only bring difficulties to the digital backend, but may even be impossible to implement in hardware, and will also increase the power consumption of the circuit.

[0005] High bandwidth and high rate are important development directions of Wi-Fi protocol. Transmitter is an important module in wireless communication system. Therefore, transmitter circuits with high data throughput, low power consumption, wide coverage, high reliability and other performance have also become the direction of people's pursuit and research. In order to support higher RF bandwidth and higher-order modulation methods, Wi-Fi 5 / Wi-Fi 6 protocols have put forward more stringent requirements on signal quality. Therefore, it is necessary to study all-digital transmitter circuits suitable for broadband applications. In response to the above problems, the present invention proposes an improved broadband Q-DTX architecture, which introduces joint interpolation technology and adopts a single path to match wide-band coverage. In order to meet various application requirements and reduce costs, the transmitter circuit implemented also has the characteristics of low power consumption, compatible and configurable architecture, etc. Summary of the invention

[0006] The purpose of the present invention is to provide a high-bandwidth, low-power consumption, joint digital-analog interpolation filtering reconfigurable all-digital transmitter. The transmitter of the present invention only needs to provide a clock, has a highly integrated structure, and has the characteristics of wide bandwidth, low power consumption, multi-mode configurability, and multi-protocol compatibility.

[0007] The present invention proposes a reconfigurable all-digital transmitter with combined digital-analog interpolation filtering, comprising a signal processing module 110, a polyphase interpolation filtering module 120, a delay integration module 150, an image suppression preprocessing module 160, a frequency divider 130, a linear interpolation all-digital power amplifier 140, an antenna 210 and a serial peripheral interface 410; wherein:

[0008] The signal processing module 110 processes the communication protocol signal, including amplitude quantization and data frame clipping, to meet the sampling rate, amplitude range and multiplexing coding requirements of the transmitter baseband for the input signal and the linear interpolation full digital power amplifier 140;

[0009] The multiphase interpolation filtering module 120 includes configurable sampling and multiphase interpolation filtering, and performs configurable sampling rate conversion, multiphase interpolation, and image filtering on the baseband I / Q signal; in the multiphase interpolation filtering module 120, the order of interpolation and filtering operations is exchanged to reduce the circuit operating frequency;

[0010] The delay integration module 150 includes delay integration and signal integration, which integrates scattered high-frequency delays to form a low-frequency delay module, and integrates and adds multiple signals to match the coefficients of the image suppression preprocessing module 160;

[0011] The image suppression preprocessing module 160 is used to solve the image of the final transmission signal spectrum. By preprocessing the baseband data, the filter in the analog domain is transferred to the digital domain, which can effectively suppress the image generated by analog interpolation;

[0012] The serial peripheral interface 410 writes serial control words and reads them out to the parallel control port in sequence, providing reset, enable and gain control signals for the transmitter system, which are used to configure the working mode of the transmitter, so that the transmitter can be flexibly applied to different working scenarios and compatible with multiple protocols;

[0013] The input end of the signal processing module 110 is connected to the I / Q signal, and the output end is connected to the input end of the multi-phase interpolation filter module 120. Each output end of the multi-phase interpolation filter module 120 is connected to the input end of the corresponding delay integration module 150. The output end of each delay integration module 150 is connected to the input end of the corresponding image suppression preprocessing module 160. The output end of each image suppression preprocessing module 160 is connected to the input end of the linear interpolation full digital power amplifier 140. The output end of the linear interpolation full digital power amplifier 140 is connected to the antenna 210. The serial peripheral interface 410 is respectively connected to the linear interpolation full digital power amplifier 140 and the signal processing module 110; the clock is respectively connected to the linear interpolation full digital power amplifier 140 and the frequency divider 130, and the frequency divider 130 is respectively connected to the multi-phase interpolation filter module 120 and the delay integration module 150;

[0014] The signal processing flow of the reconfigurable all-digital transmitter is as follows: the baseband modulated I / Q signal is subjected to amplitude quantization and data clipping by the signal processing module 110 to meet the digital baseband's requirements for the amplitude, sampling rate and multiplexing coding of the input data of the linear interpolation all-digital power amplifier 140; the baseband modulated I / Q signal after preliminary processing is sent to the multi-phase interpolation filter module 120: after configurable sampling processing, the signal meets the application requirements of different protocols, and then the signal is sent to the multi-phase interpolation filter module 120 for multi-phase interpolation and filtering processing to push the spectrum image away from the center frequency band, improve the signal-to-noise ratio and anti-interference level of the signal, and meet the out-of-band suppression specified by the protocol. requirements; then the signal is sent to the delay integration module 150, which simplifies the circuit structure and reduces the system power consumption; the integrated baseband modulated I / Q signal is sent to the image suppression preprocessing module 160 to solve the problem of spectrum image at the transmitting end of the antenna 210. At the same time, the modulated signal of the delay integration module 150 meets the out-of-band suppression and EVM requirements specified by the protocol, while ensuring the integrity and effectiveness of the original modulated signal; then, the preprocessed baseband signal is sent to the linear interpolation full digital power amplifier 140 for linear interpolation to further increase the data rate, and at the same time complete the multiplexing logic coding and power synthesis operations; finally, the baseband modulated I / Q signal is transmitted through the antenna 210.

[0015] In the present invention, the signal processing module 110 is composed of a serial-to-parallel conversion module 520, a configurable sampling module 530 and a data selector 540. The digital selector 540 selects an unsampled signal or an I / Q signal that has been processed by configurable sampling to meet the transmitter requirements under different working modes; wherein: the input end of the serial-to-parallel conversion module 520 is connected to the I / Q signal, the I end and the Q end of the output end are respectively connected to the input end of the configurable sampling module 530, the output end of the configurable sampling module 530 is connected to the input end of the data selector 540, and the output end of the data selector 540 is respectively connected to the input end of the corresponding multi-phase interpolation filter module 120.

[0016] In the present invention, the output end of the image suppression preprocessing module 160 is connected to the input end of the gain adjustment module 580, and the output end of the gain adjustment module 580 is connected to the input end of the linear interpolation full digital power amplifier 140; the gain adjustment module 580 adjusts the gain of the transmitter system through a control signal; through the SPI configuration control signal, the baseband circuit outputs signals of different amplitudes, thereby adjusting the output power of the entire transmission and controlling the gain output range of the transmitter system so as to be suitable for different working modes.

[0017] In the present invention, the multi-phase interpolation filter module 120, the delay integration module 150 and the image suppression preprocessing module 160 adopt a configurable architecture. For some protocol signals with high sampling rate requirements, the external hardware processing module cannot adjust the signal sampling rate to the target frequency and send it to the chip input end. Therefore, the signal sampling rate is improved by configuring the opening and closing of the first-stage configurable sampling module 530. Combined with the multi-phase interpolation filter module 120, the baseband modulated I / Q signal sampling rate is increased to the target frequency, and the signal-to-noise ratio, anti-interference degree and out-of-band suppression of the spectrum are improved; for protocol signals with low sampling rate requirements, the first-stage configurable sampling module 530 is turned off, and only the multi-phase interpolation filter module 120 is turned on to increase the signal sampling rate to the target frequency. At the same time, the first-stage configurable sampling module 530 is set to 0 to reduce system power consumption.

[0018] In the present invention, the multi-phase interpolation filter module 120 adopts a multi-path architecture, each path works in a low-frequency state, and different data phases of multiple paths are obtained by controlling different delays between multiple paths. Through data synthesis, the filtering function can be realized while realizing interpolation sampling; different from the traditional structure of interpolation first and then filtering, this multi-phase interpolation filter module 120 can realize interpolation and filtering functions at the same time, and the circuit works in a low-frequency state, so the system has lower power consumption.

[0019] In the present invention, the linear interpolation all-digital power amplifier 140 combines power synthesis and linear interpolation together, and further improves the data rate by simulating linear interpolation, thereby suppressing the image signal of the transmission spectrum.

[0020] In the present invention, the image suppression preprocessing module 160 is used to solve the problem of spectrum images at the final transmitting antenna 210; although the introduction of linear interpolation in the linear interpolation all-digital power amplifier 140 can suppress spectrum images to a certain extent, for some wider bandwidth signals, in order to ensure the cleanliness of the out-of-band spectrum, the image suppression preprocessing module is used to filter the final transmission signal to suppress the image; the data synthesized by DPA has a very high rate. If filtering is performed after the DPA module, the power consumption and design complexity will be very high.

[0021] In the present invention, the image suppression preprocessing module 160 adopts a FIR filter with a simple structure. By optimizing the filter coefficients, the image suppression preprocessing module 160 only needs a simple shift operation to achieve complete suppression of the image.

[0022] In the present invention, the delay integration module 150 simplifies the circuit structure by integrating the delays of different paths; since the multi-phase interpolation filter module 120 requires different delays to control the phase difference, and the image suppression preprocessing module also requires different path delays to achieve the filtering effect, multiple high-frequency delays of the same path are integrated into a low-frequency delay, thereby reducing the operating frequency of the circuit and reducing the power consumption of the transmitter system.

[0023] In the present invention, the frequency divider 130 divides the external high-frequency clock signal multiple times to provide an internal operation clock for the multi-phase interpolation filter module 120 and the delay integration module 150; the serial peripheral interface (SPI) 410 configures the transmitter architecture through a serial input control word to meet the working mode required by different communication protocols. The beneficial effects of the present invention are:

[0024] The reconfigurable all-digital transmitter of the joint digital-analog interpolation filtering of the present invention is based on an orthogonal architecture, and has a simple structure and good symmetry. The I and Q signals are completely symmetrical and easy to match, and have good linearity, and there is no problem of spectrum expansion, thereby avoiding threats to the spectrum mask (MASK).

[0025] The transmitter involved in the present invention has a wide radio frequency band coverage range and can support different high-bandwidth modulation signals. By controlling the switch signal of the transmitter through the serial peripheral interface (SPI) 410, the working mode of the transmitter can be flexibly configured for different protocol signals, which can not only be flexibly applied to various scenarios, but also save resources and reduce system power consumption.

[0026] The transmitter involved in the present invention adopts a multi-phase interpolation filter. Different from the traditional structure of interpolation first and then filtering, this interpolation filter adopts a multi-phase architecture, exchanges the order of interpolation and filtering, and completes the filtering function while realizing interpolation by controlling the phase delay between different paths. The circuit works in a low-frequency state, which greatly reduces the circuit power consumption.

[0027] The image suppression preprocessing module 160 described in the present invention is to solve the problem of spectrum mirroring at the final transmitting antenna 210. Although the introduction of linear interpolation in the linear interpolation all-digital power amplifier 140 can suppress spectrum mirroring to a certain extent, this suppression effect is not obvious for some signals with wider bandwidths. In view of this situation, in order to ensure the cleanliness of the out-of-band spectrum, an image suppression preprocessing module is introduced to filter the final transmission signal to suppress the image. The data synthesized by DPA has a very high rate. If filtering is performed after the DPA module, the power consumption and design complexity will be very high. Therefore, this filtering function is transferred to the front processing, that is, the image suppression preprocessing module 160. This module adopts an FIR structure and optimizes the coefficients. The image of the final transmission signal can be suppressed by a simple shift operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 : Structure diagram of reconfigurable all-digital transmitter with joint digital-analog interpolation filtering.

[0029] Figure 2 : Structure diagram of multi-phase interpolation filtering, delay integration, and preprocessing modules.

[0030] Figure 3 : Application example 1 of a reconfigurable all-digital transmitter with joint digital-analog interpolation filtering.

[0031] Figure 4 : Output spectrum of different protocol bandwidths. Among them: Figure 4 (a) Bandwidth 160MHz, LO = 5.12GHz output spectrum, Figure 4 (b) Output spectrum with bandwidth of 20MHz and LO=1.28GHz.

[0032] The numbers in the figure are: 110 is a signal processing module, 120 is a multiphase interpolation filter module, 130 is a frequency divider, 140 is a linear interpolation all-digital power amplifier, 150 is a delay integration module, 160 is an image suppression preprocessing module, 210 is an antenna, 410 is a serial peripheral interface, 520 is a serial-to-parallel conversion module, 530 is a configurable sampling module, 540 is a data selector, and 580 is a gain adjustment module. 610 is a digital signal processing chip, 620 is a fully digital transmitter, 630 is a clock source, and 640 is a control unit. DETAILED DESCRIPTION

[0033] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings.

[0034] Embodiment 1:

[0035] The present invention provides a reconfigurable all-digital transmitter with a combined digital-analog interpolation filter, and its system architecture is as follows: Figure 1 As shown. The transmitter of the present invention only needs to provide a clock, and the structure is highly integrated, with the characteristics of wide bandwidth, low power consumption, multi-mode configurability, and multi-protocol compatibility. The transmitter covers a wide frequency band and is compatible with a variety of high-speed communication protocols, such as LTE / WiFi5 / WiFi6, etc., and can support modulated signals of different bandwidths. The all-digital transmitter of the present invention includes a signal processing module 110, a multi-phase interpolation filter 120, a delay integration module 150, an image suppression preprocessing module 160, a frequency divider 130, a linear interpolation all-digital power amplifier 140, an antenna 210 and a serial peripheral interface 410.

[0036] like Figure 1As shown, the baseband modulation signal I / Q is subjected to amplitude quantization and data clipping by the baseband signal processing module 110 to meet the multiplexing coding requirements of the digital baseband for the amplitude, sampling rate and linear interpolation full digital power amplifier 140 of the input data; the baseband modulation signal after preliminary processing is sent to the multi-phase interpolation filter 120 module: after the signal is subjected to configurable sampling processing, it meets the application requirements of different protocols, and then the signal is sent to the multi-phase interpolation filter module for multi-phase interpolation and filtering processing, which pushes the spectrum image away from the center frequency band, improves the signal-to-noise ratio and anti-interference degree of the signal, and meets the requirements of the out-of-band suppression degree specified by the protocol. Request; then the signal is sent to the delay integration 150 module, which simplifies the circuit structure and reduces the system power consumption; the integrated signal is sent to the image suppression preprocessing module 160 to solve the problem of spectrum image at the transmitting end of the antenna 210. At the same time, the modulated signal of the delay integration technology at this time meets the out-of-band suppression and EVM requirements specified by the protocol, while ensuring the integrity and effectiveness of the original modulated signal; then, the preprocessed baseband signal is sent to the linear interpolation full digital power amplifier 140 for linear interpolation to further increase the data rate, and complete the multiplexing logic coding and power synthesis operations; finally, the signal is transmitted through the antenna 210. The baseband signal preprocessing module performs amplitude quantization and data frame clipping on the modulated signal to meet the input sampling rate and digital coding requirements of the baseband signal. Its preprocessing process for the modulated signal must ensure the integrity of the signal and achieve better signal characteristics. According to the bit width of the different input signals, the signal processing process quantizes the modulated signal to the amplitude corresponding to the bit width. In addition, according to the coding logic of the multiplexed modulation module, the modulated signal needs to be limited to the range specified by the linear interpolation full digital power amplifier 140 coding to ensure the correctness of the coding logic and realize the module multiplexing function.

[0037] like Figure 2 As shown, the input baseband signal is divided into two signals, I and Q, through the serial-to-parallel conversion module 520, and the two signals are completely symmetrical. The configurable sampling module 530 performs configurable sampling rate conversion on the signal and completes the filtering function, which increases the sampling rate of the signal, pushes the mirror signal away from the in-band signal, and improves the anti-interference ability and signal-to-noise ratio of the signal. Through the data selector 540, it is selected whether to turn on the configurable sampling module, so that the sampling rate of the system can be flexibly configured according to different communication protocol requirements and different application scenarios. This operation can be compatible with different communication protocols and save resources and reduce power consumption as much as possible.

[0038] like Figure 2As shown, in order to reduce power consumption as much as possible, the multi-phase interpolation filter module 120 adopts a multi-path architecture, each path works in a low-frequency state, and different data phases are obtained by controlling different delays between multiple paths. Through data synthesis, the filtering function can be realized while realizing interpolation sampling. Different from the traditional structure of interpolation first and then filtering, this multi-phase interpolation filter module 120 can realize interpolation and filtering functions at the same time, and the circuit works in a low-frequency state, so the system has lower power consumption.

[0039] like Figure 2 As shown, the delay and preprocessing module includes delay integration and image suppression preprocessing. The delay integration module 150 integrates multiple high-frequency delays on the path into a few low-frequency delays, which not only reduces the operating frequency of the circuit and reduces power consumption, but also simplifies the circuit structure, which is simple and easy to implement. In addition, the image suppression preprocessing module 160 is introduced to solve the problem of spectral mirroring generated by the signal after the linear interpolation DPA. The filtering operation is moved before the interpolation DPA, and the filter coefficients are optimized, and the image suppression effect of the final transmitter is achieved through a simple shift operation.

[0040] like Figure 2 As shown, the gain adjustment module 580 adjusts the gain of the system through the control signal. By configuring the control signal through SPI, the baseband circuit outputs signals of different amplitudes, thereby adjusting the output power of the entire transmission and controlling the gain output range of the transmitter system to adapt to different working modes.

[0041] like Figure 1 As shown in the figure, the power amplifier introduces a linear interpolation function to further improve the sampling rate of the signal and reduce the spectrum image and spurious after mixing. This linear interpolation DPA can achieve interpolation sampling while improving the signal sampling rate. It has a simple structure and good linearity.

[0042] The application example of the reconfigurable all-digital transmitter with joint digital-analog interpolation filtering of the present invention is as follows: Figure 3As shown, it is compatible with multiple communication protocols such as LTE, WiFi5 or WiFi6. At this time, the transmitter controls the shutdown or conduction of the configurable sampling module through SPI. The on-chip circuit modules used in this mode include: baseband signal processing module 110, multi-phase interpolation filter 120, delay integration module 150, image suppression preprocessing module 160, divider 130, linear interpolation full digital power amplifier 140, antenna 210, serial peripheral interface 410 and other circuit modules. The specific implementation process is: the digital signal processing chip WiFi5 / 6 sends the modulated signal to the all-digital transmitter 620 with a configured mode, performs signal processing, interpolation filtering, delay integration, image suppression, power amplification and other processing in the transmitter chip, and then transmits the processed signal through the off-chip antenna 210. In this application mode, the off-chip modules include: digital signal processing chip 610, clock source 630, control unit 640 and antenna 210.

[0043] In order to verify the beneficial effects of the above transmitter, the different results of different bandwidth protocol signals are shown as follows Figure 4 shown. Figure 4 a shows the output spectrum results of 160MHz bandwidth and 5.12GHz frequency; Figure 4 b shows the output spectrum diagram results of 20MHz bandwidth and 1.28GHz frequency. The results show that there is no image signal in the far sideband of the spectrum, the suppression effect is good, the integrity of the signal is guaranteed, and the spectrum MASK requirements specified in the protocol are met, with a large margin, and the all-digital transmitter of the present invention is compatible with multiple bandwidths and covers a wide range of frequencies.

[0044] The reconfigurable transmitter of the joint digital-analog interpolation filter of the present invention is compatible with multiple communication protocols and supports multiple application scenarios. The transmitter has a simple architecture, good symmetry, can cover a wide frequency band, can support multiple high-bandwidth communication protocols, and has the characteristics of low power consumption and configurability.

[0045] Although the present invention is described above in conjunction with the accompanying drawings, the present invention is not limited to the above specific embodiments. The above embodiments are only illustrative and non-restrictive. Under the inspiration of the present invention, ordinary technicians in this field can make many modifications without departing from the purpose of the present invention, all of which belong to the protection of the present invention.

Claims

1. A reconfigurable all-digital transmitter with joint digital-analog interpolation filtering, characterized in that: It comprises a signal processing module (110), a polyphase interpolation filter module (120), a delay integration module (150), an image suppression preprocessing module (160), a frequency divider (130), a linear interpolation all-digital power amplifier (140), an antenna (210) and a serial peripheral interface (410); wherein: The signal processing module (110) processes the communication protocol signal, including amplitude quantization and data frame clipping, so as to meet the sampling rate, amplitude range and multiplexing coding requirements of the transmitter baseband for the input signal and the linear interpolation full digital power amplifier (140); The multiphase interpolation filtering module (120) includes configurable sampling and multiphase interpolation filtering, and performs configurable sampling rate conversion, multiphase interpolation, and image filtering on the baseband I / Q signal; in the multiphase interpolation filtering module (120), the order of interpolation and filtering operations is exchanged to reduce the circuit operating frequency; The delay integration module (150) includes delay integration and signal integration, which integrates scattered high-frequency delays to form a low-frequency delay module, and integrates and adds multiple signals to match the coefficients of the image suppression preprocessing module (160); The image suppression preprocessing module (160) is used to solve the image of the final transmission signal spectrum, and is implemented by preprocessing the baseband data and transferring the filter in the analog domain to the digital domain, so as to effectively suppress the image generated by analog interpolation; The serial peripheral interface (410) writes serial control words and reads them out to the parallel control port in sequence, providing reset, enable and gain control signals for the transmitter system, which are used to configure the working mode of the transmitter, so that the transmitter can be flexibly applied to different working scenarios and is compatible with multiple protocols; The input end of the signal processing module (110) is connected to the I / Q signal, and the output end is connected to the input end of the multiphase interpolation filter module (120); each output end of the multiphase interpolation filter module (120) is connected to the input end of the corresponding delay integration module (150); the output end of each delay integration module (150) is connected to the input end of the corresponding image suppression preprocessing module (160); the output end of each image suppression preprocessing module (160) is connected to the input end of the linear interpolation full digital power amplifier (140); the output end of the linear interpolation full digital power amplifier (140) is connected to the antenna (210); the serial peripheral interface (410) is respectively connected to the linear interpolation full digital power amplifier (140) and the signal processing module (110); the clock is respectively connected to the linear interpolation full digital power amplifier (140) and the frequency divider (130); the frequency divider (130) is respectively connected to the multiphase interpolation filter module (120) and the delay integration module (150); The signal processing flow of the reconfigurable all-digital transmitter is as follows: the baseband modulated I / Q signal is subjected to amplitude quantization and data clipping by the signal processing module (110) to meet the digital baseband's requirements for the amplitude, sampling rate and multiplexing coding of the input data of the linear interpolation all-digital power amplifier (140); the baseband modulated I / Q signal after preliminary processing is sent to the multi-phase interpolation filter module (120): the signal is subjected to configurable sampling processing to meet the application requirements of different protocols, and then the signal is sent to the multi-phase interpolation filter module (120) to perform multi-phase interpolation and filtering processing to push the spectrum image away from the center frequency band, thereby improving the signal-to-noise ratio and anti-interference degree of the signal and meeting the out-of-band suppression degree specified by the protocol. requirements; then the signal is sent to the delay integration module (150) to reduce the power consumption of the reconfigurable all-digital transmitter; the integrated signal is sent to the image suppression preprocessing module (160) to solve the spectrum image problem at the transmitting end of the antenna (210), and at the same time the modulated signal of the delay integration module (150) meets the out-of-band suppression and EVM requirements specified by the protocol, while ensuring the integrity and validity of the original modulated signal; then, the preprocessed baseband modulated I / Q signal is sent to the linear interpolation all-digital power amplifier (140) for linear interpolation to further increase the data rate, while completing the multiplexing logic coding and power synthesis operations; finally, the processed baseband modulated I / Q signal is transmitted through the antenna (210).

2. The reconfigurable all-digital transmitter with joint digital-analog interpolation filtering according to claim 1, characterized in that: The signal processing module (110) is composed of a serial-to-parallel conversion module (520), a configurable sampling module (530) and a data selector (540), wherein the digital selector (540) selects an unsampled signal or an I / Q signal that has been processed by configurable sampling to meet the transmitter requirements in different working modes; wherein: the input end of the serial-to-parallel conversion module (520) is connected to the baseband modulated I / Q signal, the I end and the Q end of the output end are respectively connected to the input end of the configurable sampling module (530), the output end of the configurable sampling module (530) is connected to the input end of the data selector (540), and the output end of the data selector (540) is respectively connected to the input end of the corresponding multi-phase interpolation filter module (120).

3. The reconfigurable all-digital transmitter with joint digital-analog interpolation filtering according to claim 1, characterized in that: The output end of the image suppression preprocessing module (160) is connected to the input end of the gain adjustment module (580), and the output end of the gain adjustment module (580) is connected to the input end of the linear interpolation all-digital power amplifier (140); the gain adjustment module (580) adjusts the gain of the transmitter system through a control signal; the baseband circuit outputs signals of different amplitudes through SPI configuration control signals, thereby adjusting the output power of the entire transmission and controlling the gain output range of the reconfigurable all-digital transmitter so as to be suitable for different working modes.

4. The reconfigurable all-digital transmitter with joint digital-analog interpolation filtering according to claim 2, characterized in that: The multi-phase interpolation filter module (120), the delay integration module (150) and the image suppression pre-processing module (160) adopt a configurable architecture. For some protocol signals with high sampling rate requirements, the external hardware processing module cannot adjust the signal sampling rate to the target frequency and send it to the chip input end. Therefore, the signal sampling rate is increased by configuring the opening and closing of the first-level configurable sampling module (530). In combination with the multi-phase interpolation filter module (120), the baseband modulated I / Q signal sampling rate is increased to the target frequency, thereby improving the signal-to-noise ratio, anti-interference degree and out-of-band suppression degree of the spectrum. For protocol signals with low sampling rate requirements, the first-level configurable sampling module (530) is turned off, and only the multi-phase interpolation filter module (120) is turned on to increase the signal sampling rate to the target frequency. At the same time, the first-level configurable sampling module (530) is set to 0 to reduce system power consumption.

5. The reconfigurable all-digital transmitter with joint digital-analog interpolation filtering according to claim 1, characterized in that: The multi-phase interpolation filter module (120) adopts a multi-path architecture, each path works in a low-frequency state, and different data phases of multiple paths are obtained by controlling different delays between multiple paths. Through data synthesis, the filtering function can be realized while realizing interpolation sampling; this multi-phase interpolation filter module (120) can realize interpolation and filtering functions at the same time, and the circuit works in a low-frequency state, so the reconfigurable all-digital transmitter has lower power consumption.

6. The reconfigurable all-digital transmitter with joint digital-analog interpolation filtering according to claim 1, characterized in that: The linear interpolation all-digital power amplifier (140) combines power synthesis and linear interpolation together, and further increases the data rate by simulating linear interpolation, thereby suppressing the image signal of the transmission spectrum.

7. The reconfigurable all-digital transmitter with joint digital-analog interpolation filtering according to claim 1, characterized in that: The image suppression preprocessing module (160) is used to solve the problem of spectrum images at the final transmitting end antenna (210); although the introduction of linear interpolation in the linear interpolation all-digital power amplifier (140) can suppress spectrum images to a certain extent, for some signals with wider bandwidths, in order to ensure the cleanliness of the out-of-band spectrum, the image suppression preprocessing module is used to filter the final transmission signal to suppress the image; the data synthesized by DPA has a very high rate. If filtering is performed after the DPA module, the power consumption and design complexity will be very high.

8. The reconfigurable all-digital transmitter with joint digital-analog interpolation filtering according to claim 7, characterized in that: The image suppression preprocessing module (160) adopts an FIR filter, and by optimizing the filter coefficients, the image suppression preprocessing module (160) only needs a simple shift operation to achieve complete suppression of the image.

9. The reconfigurable all-digital transmitter with joint digital-analog interpolation filtering according to claim 1, characterized in that: The delay integration module (150) simplifies the circuit structure by integrating the delays of different paths; since the multi-phase interpolation filter module (120) requires different delays to control the phase difference, and the image suppression preprocessing module (160) also requires different path delays to achieve the filtering effect, multiple high-frequency delays of the same path are integrated into a low-frequency delay, thereby reducing the operating frequency of the circuit and reducing the power consumption of the reconfigurable all-digital transmitter.

10. The reconfigurable all-digital transmitter with joint digital-analog interpolation filtering according to claim 1, characterized in that: The frequency divider (130) divides the external high-frequency clock signal multiple times to provide an internal operation clock for the multi-phase interpolation filter module (120) and the delay integration module (150); the serial peripheral interface (SPI) (410) configures the transmitter architecture through a serial input control word to meet the working modes required by different communication protocols.

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