Anti-fuse one-time programmable memory and related bias control method thereof

Abstract

The invention discloses an anti-fuse type one-time programming memory and a related bias voltage control method thereof. The anti-fuse type one-time programming memory comprises a first memory unit. The first storage unit is provided with an anti-fuse transistor. The anti-fuse transistor includes a first nanowire, a first gate structure, a first drain / source structure and a second drain / source structure. The first nanowire is surrounded by the first gate structure. The first gate structure comprises a first gap wall, a second gap wall, a first gate dielectric layer and a first gate layer. The first drain / source structure is electrically contacted with the first end of the first nanowire. The second drain / source structure is electrically contacted with the second end of the first nanowire.

Description

Technical Field

[0001] The invention relates to a non-volatile memory and a control method thereof, and in particular to an anti-fuse type one-time programming memory and a related bias control method thereof. Background Art

[0002] As is known to all, the antifuse-type one time programming memory (OTP memory) is a non-volatile memory. Before the program action is performed on the memory cell of the antifuse-type OTP memory, it is in a storage state of high resistance value. After the program action is performed on the memory cell of the antifuse-type OTP memory, it is in a storage state of low resistance value. Once the antifuse-type OTP memory cell is programmed, its stored data cannot be modified.

[0003] Generally speaking, an anti-fuse OTP memory includes a peripheral circuit and an array structure. The peripheral circuit and the array structure are designed on a semiconductor substrate. The array structure includes a plurality of memory cells, each of which includes a storage transistor. In addition, the peripheral circuit also includes a control circuit and a power circuit. The control circuit can control the power circuit to provide an appropriate bias voltage to a selected memory cell in the array structure, and perform a programming action or a reading action on the selected memory cell. For example, the power circuit is a charge pump.

[0004] Due to the continuous evolution of semiconductor manufacturing technology, today's transistors have shifted from early planar structure transistors to fin field effect transistors (Fin-FET). In more advanced manufacturing processes, smaller-sized surround gate transistors (Gate-All-Around, referred to as GAA transistors) can be produced. GAA transistors are small in size. Furthermore, the channel region of the GAA transistor is surrounded by the gate, so the GAA transistor has excellent gate control capabilities and low source / drain leakage current, and has a tendency to gradually replace traditional transistors. Summary of the invention

[0005] The present invention relates to an anti-fuse type one-time programming memory having a first storage unit, the first storage unit comprising: a P-type semiconductor substrate; a P-type well region located on a surface of the P-type semiconductor substrate; an N-type region formed in the P-type semiconductor substrate and located below the P-type well region, wherein the P-type semiconductor substrate below the N-type region and the P-type well region are not in contact with each other through the N-type region, and the P-type well region is an isolated P-type well region; a first nanowire; a first gate structure, comprising a first spacer, a second spacer, a first gate dielectric layer and a first gate layer; wherein the first gate dielectric layer surrounds a middle region of the first nanowire, the first gate The electrode layer surrounds the first gate dielectric layer, the first gate layer is electrically connected to a first word line, a first end of the first nanowire is surrounded by the first spacer, a second end of the first nanowire is surrounded by the second spacer, and the first spacer and the second spacer are located above the P-type well region; a first drain / source structure is located above the P-type well region, electrically contacts the first end of the first nanowire, and is electrically connected to a first bit line; a second drain / source structure is located above the P-type well region, and electrically contacts the second end of the first nanowire; wherein the first nanowire, the first gate structure, the first drain / source structure and the second drain / source structure form a first selection transistor; a second nanowire; A second gate structure, comprising a third spacer, a fourth spacer, a second gate dielectric layer and a second gate layer; wherein the second gate dielectric layer surrounds a middle region of the second nanowire, the second gate layer surrounds the second gate dielectric layer, the second gate layer is electrically connected to a first anti-fuse control line, a first end of the second nanowire is surrounded by the third spacer, a second end of the second nanowire is surrounded by the fourth spacer, and the third spacer and the fourth spacer are located above the P-type well region; a third drain / source structure is located above the P-type well region and electrically contacts the first end of the second nanowire, wherein the third drain / source structure is coupled to the second drain / source structure; and a fourth A drain / source structure is located above the P-type well region and electrically contacts the second end of the second nanowire, wherein the second nanowire, the second gate structure, the third drain / source structure and the fourth drain / source structure form a first anti-fuse transistor; wherein, during a programming action, the P-type well region receives a negative programming voltage, the N-type region receives a first voltage, and the P-type semiconductor substrate receives a second voltage; there is a reverse bias between the P-type well region and the N-type region; and there is the reverse bias or a zero bias between the P-type semiconductor substrate and the N-type region; wherein the first voltage is greater than or equal to a ground voltage, the second voltage is greater than or equal to the negative programming voltage, and the second voltage is less than or equal to the first voltage.

[0006] In order to better understand the above and other aspects of the present invention, preferred embodiments are described in detail below in conjunction with the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A , Figure 1B and Figure 1C It is a three-dimensional view, a cross-sectional view along the ab dotted line, and a top view of the GAA transistor of the present invention;

[0008] Figure 2A and Figure 2B The three-dimensional diagram and the top view of two GAA transistors of the present invention;

[0009] Figure 3A , Figure 3B and Figure 3C 1. A top view of the array structure of the anti-fuse one-time programming memory according to the first embodiment of the present invention, a cross-sectional view along the dotted line cd, and a cross-sectional view along the dotted line ef;

[0010] Figure 3D A schematic diagram showing the bias voltages for programming and reading the OTP memory of the first embodiment of the present invention;

[0011] Figure 4A , Figure 4B and Figure 4C 1 is a top view of the array structure of an anti-fuse one-time programming memory according to a second embodiment of the present invention, a cross-sectional view along the dashed line gh, and a cross-sectional view along the dashed line ij;

[0012] Figure 4D A schematic diagram showing the bias voltage for performing programming and reading operations on an OTP memory according to a second embodiment of the present invention;

[0013] Figure 5A and Figure 5B A top view of the array structure and a bias table of an anti-fuse one-time programming memory according to a third embodiment of the present invention; and

[0014] Fig. 6A and Figure 6B It is a top view of the array structure of the anti-fuse one-time programming memory and a bias table according to the fourth embodiment of the present invention.

[0015] Explanation of symbols

[0016] 110,123,124,125,126,215,217,221,222,245,247,251,252,265,267,271,272,285,287,291,292,315,317,321,322,345,347,351,352,365,367,371,372,385,387,391,392,403,404, 413,414,423,424,433,434,443,444,453,454,463,464,473,474,483,484,493,494,503,504,513,514,523,524,533,534,543,544,553,554,563,564,573,574,583,584,593,594: Gate dielectric layer

[0017] 120: Gate structure

[0018] 128,229,259,279,299,329,359,379,399,407,417,427,437,447,457,467,477,487,497: Gate layer

[0019] 130,140,150,160,211,212,214,216,241,242,244,246,261,262,264,266,281,282,284,286,311,312,314,316,341,342,344,346,361,362,364,366,381,382,384,386,401,402,4 11,412,421,422,431,432,441,442,451,452,461,462,471,472,481,482,491,492,501,502,511,512,521,522,531,532,541,542,551,552,561,562,571,572,581,582,591,592: Nanowires

[0020] 132,136,182,186,231,232,233,234,235,236,237,238,239,331,332,333,334,335,336,337,338,339,408,409,419,429,439,449,459,469,479,489,499,508,509,519,529,539,549,559,569,579,589,599: drain / source structure

[0021] 172,174,226,227,256,257,276,277,296,297,326,327,356,357,376,377,396,397,405,406,415,416,425,426,435,436,445,446,455,456,465,466,475,476,485,486,495,496: gap wall DETAILED DESCRIPTION

[0022] The present invention provides an anti-fuse OTP memory and a related bias control method thereof. The anti-fuse OTP memory is made of GAA transistors. For example, the peripheral circuit and array structure of the anti-fuse OTP memory are composed of GAA transistors and are made on a semiconductor substrate.

[0023] Generally speaking, since the GAA transistor is small in size and has a low withstand voltage, for example, the withstand voltage of the GAA transistor is 2.5 V, some problems may occur when using the GAA transistor to manufacture an anti-fuse OTP memory.

[0024] For example, when performing programming, the anti-fuse OTP memory needs to provide a higher voltage difference, such as a voltage difference of 5V, to the storage transistor in the selected memory cell, and the storage transistor is a GAA transistor. That is to say, during the programming action, the power supply circuit will provide a higher voltage difference to the two sides of the gate dielectric layer of the storage transistor. When the voltage difference is greater than the voltage stress that the gate dielectric layer can withstand, the gate dielectric layer will rupture, causing the memory cell to present a storage state with a low resistance value. For example, a charge pump is designed in the power supply circuit to receive the supply voltage (V DD ) and generates a 5V output voltage for programming. DD Greater than or equal to 0.4V and supply voltage V DD Less than or equal to 1.6V.

[0025] Generally speaking, since GAA transistors cannot withstand excessive voltage stress, if a single power circuit is designed to directly output 5V, the GAA crystal in the charge pump will not be able to withstand this voltage stress, which will cause the charge pump to be damaged and unable to operate normally. Therefore, in OTP memory, multiple power circuits are required to generate multiple voltages, and multiple voltages are combined to generate a large enough voltage difference to perform programming operations.

[0026] In order to meet the above requirements, the present invention proposes an anti-fuse OTP memory and a related bias control method. The anti-fuse OTP memory includes multiple power circuits, one power circuit provides a positive voltage, and the other power circuit provides a negative voltage. The magnitude of the voltage provided by each power circuit is smaller than the withstand voltage of the GAA transistor, so the power circuit can operate normally. Furthermore, the positive voltage and the negative voltage provided by the two power circuits can become programming voltages with a large voltage difference, which are used for programming operations.

[0027] Please refer to Figure 1A , Figure 1B and Figure 1C , which depicts a three-dimensional view of the GAA transistor of the present invention, a cross-sectional view along the ab dashed line, and a top view. The GAA transistor of the present invention can form a memory cell and an array structure of an OTP memory.

[0028] like Figure 1A and Figure 1B As shown, an insulating structure STI, such as a shallow trench isolation (STI) structure, is formed on the surface of the P-type well region PW of the P-type semiconductor substrate P_sub. Furthermore, a gate structure 120 is formed on the surface of the P-type well region PW and the insulating structure STI, and nanowires 130 and 140 pass through the gate structure 120. In other words, the nanowires 130 and 140 are surrounded by the gate structure 120 and supported by the gate structure 120. Among them, the nanowires 130 and 140 can be rectangular nanowires or cylindrical nanowires. In addition, two drain / source structures 132 and 136 are electrically in contact with the nanowires 130 and 140, and the nanowires 130 and 140 pass through the two drain / source structures 132 and 136. Alternatively, the nanowires 130 and 140 do not pass through the two drain / source structures 132 and 136, and only the two ends of the nanowires 130 and 140 are electrically in contact with the two drain / source structures 132 and 136. Basically, the two drain / source structures 132 and 136, the gate structure 120 and the nanowires 130 and 140 constitute a GAA transistor.

[0029] It is worth noting that the number of nanowires in a GAA transistor is not limited to only two. For example, the number of nanowires in a GAA transistor may be only one or more than two. Figure 1A and Figure 1BAs shown, an N-type region (N-type region) is formed in a P-type semiconductor substrate P_sub and is located below a P-type well region PW. The N-type region may be a deep N-well region (DNW) or an N-buried layer (NBL). In addition, the P-type semiconductor substrate P_sub and the P-type well region PW are isolated by the N-type region (N-type region), so that the P-type semiconductor substrate P_sub and the P-type well region PW do not contact each other. In other words, the P-type well region PW is an isolated P-well region (isolated P-well).

[0030] like Figure 1B As shown, the gate structure 120 is located above the P-type well region PW and the insulating structure STI. The gate structure 120 includes: two spacers 172, 174, three gate dielectric layers 110, 123, 124 and a gate layer 128. Among them, the two spacers 172, 174 are located above the P-type well region PW. In addition, the two spacers 172, 174 and the gate dielectric layers 110, 123, 124 are electrical insulators. The gate dielectric layer 110 contacts the surface of the P-type well region PW and the insulating structure STI, the gate dielectric layer 123 surrounds the middle region of the nanowire 130, and the gate dielectric layer 124 surrounds the middle region of the nanowire 140. The gate dielectric layer 110 contacts the first side surface of the spacers 172, 174. The gate layer 128 covers the gate dielectric layers 110, 123, 124. Furthermore, spacers 172 and 174 are formed on the surface of the P-type well region PW and the insulating structure STI. The first ends of the nanowires 130 and 140 are surrounded by the spacers 172 and supported by the spacers 172. The second ends of the nanowires 130 and 140 are surrounded by the spacers 174 and supported by the spacers 174. Furthermore, the nanowires 130 and 140 surrounded by the gate structure 120 are the nanowire channel regions of the GAA transistor.

[0031] Furthermore, the drain / source structures 132 and 136 are located above the P-type well region PW and the insulating structure STI. The drain / source structure 132 contacts the second side surface of the spacer 172, and the drain / source structure 136 contacts the second side surface of the spacer 174. The drain / source structure 132 electrically contacts the first end of the nanowires 130 and 140, and the drain / source structure 136 electrically contacts the second end of the nanowires 130 and 140. In one embodiment, the drain / source structures 132 and 136 have the same doping type as the nanowires 130 and 140. For example, the drain / source structures 132 and 136 and the nanowires 130 and 140 are both n-type doping structures or p-type doping structures.

[0032] Therefore, if Figure 1B As shown, the GAA transistor includes: a gate structure 120 , nanowires 130 , 140 and drain / source structures 132 , 136 . In addition, the gate structure 120 includes at least two spacers 172 , 174 , gate dielectric layers 123 , 124 and a gate layer 128 .

[0033] Please refer to Figure 2A and Figure 2B , which shows a three-dimensional view and a top view of two GAA transistors of the present invention. Figure 1A and Figure 1C , and a GAA transistor is added. The two GAA transistors have the same structure, and the two GAA transistors share the spacers 172, 174 and the gate layer 128. The structure of the newly added GAA transistor is briefly introduced below.

[0034] The newly added GAA transistor includes two drain / source structures 182 and 186, a gate structure and nanowires 150 and 160. The gate structure of the newly added GAA transistor includes spacers 172 and 174, gate dielectric layers 125 and 126 and a gate layer 128. The gate dielectric layer 125 surrounds the middle region of the nanowire 150, and the gate dielectric layer 126 surrounds the middle region of the nanowire 160. The gate layer 128 covers the gate dielectric layers 125 and 126. The first end of the nanowire 150 and 160 is surrounded and supported by the spacer 172. The second end of the nanowire 150 and 160 is surrounded and supported by the spacer 174. Furthermore, the drain / source structure 182 is electrically in contact with the first end of the nanowire 150 and 160, and the other drain / source structure 186 is electrically in contact with the second end of the nanowire 150 and 160.

[0035] exist Figure 2A In the embodiment, two GAA transistors are fabricated on a P-type semiconductor substrate P_sub. The drain / source structure 132 is not in electrical contact with the drain / source structure 182, and the drain / source structure 136 is not in electrical contact with the drain / source structure 186. Furthermore, the two GAA transistors share the spacers 172, 174 and the gate layer 128. Of course, technicians in this field can also fabricate more GAA transistors on the P-type semiconductor substrate P_sub, sharing the spacers 172, 174 and the gate layer 128.

[0036] Please refer to Figure 3A , Figure 3B and Figure 3C , which illustrates a top view of the array structure of the anti-fuse one-time programming memory according to the first embodiment of the present invention, a cross-sectional view along the dotted line cd, and a cross-sectional view along the dotted line ef.

[0037] The array structure includes four memory cells Cell1 to Cell4, forming a 2×2 array structure, and the structure of each memory cell Cell1 to Cell4 is similar. Furthermore, the array structure is designed above the P-type well region PW in the P-type semiconductor substrate P_sub. The N-type region is formed in the P-type semiconductor substrate P_sub and is located below the P-type well region PW. Among them, the N-type region can be a deep N-type well region (DNW) or an N-type buried layer (NBL). In addition, the P-type semiconductor substrate P_sub and the P-type well region PW are isolated by the N-type region.

[0038] The array structure is connected to at least bit lines BL1, BL2, word lines WL1, WL2 and anti-fuse control lines AF1, AF2. Each memory cell Cell1 to Cell4 in the array structure includes at least three GAA transistors. The structure of each GAA transistor is the same as Figure 1A The GAA transistor shown.

[0039] The first storage cell Cell1 includes: a selection transistor M SEL1 , switching transistor M SW1 With the anti-fuse transistor M AF1 . Select transistor M SEL1 Through the switching transistor M SW1 Coupled to the anti-fuse transistor M AF1 Among them, the anti-fuse transistor M AF1 As a storage transistor.

[0040] Select transistor M SEL1 The present invention comprises a drain / source structure 233, a drain / source structure 234, a gate structure, and nanowires 261 and 262. The gate structure comprises two spacers 276 and 277, gate dielectric layers 271 and 272, and a gate layer 279. The gate dielectric layer 271 surrounds the middle region of the nanowire 261, the gate dielectric layer 272 surrounds the middle region of the nanowire 262, and the gate layer 279 surrounds the gate dielectric layers 271 and 272. The first ends of the nanowires 261 and 262 are surrounded by the spacers 276, and the second ends of the nanowires 261 and 262 are surrounded by the spacers 277. The nanowires 261 and 262 surrounded by the gate structure are the selection transistors M. SEL1 The nanowire channel region. Furthermore, two drain / source structures 233 and 234 are located on two sides of the gate structure. The drain / source structure 233 is electrically in contact with the first ends of the nanowires 261 and 262, and the drain / source structure 234 is electrically in contact with the second ends of the nanowires 261 and 262. Furthermore, the drain / source structure 234 is electrically connected to the bit line BL1, and the gate layer 279 is electrically connected to the word line WL1.

[0041] Switching transistor M SW1The present invention comprises a drain / source structure 232, a drain / source structure 233, a gate structure, and nanowires 241 and 242. The gate structure comprises two spacers 256 and 257, gate dielectric layers 251 and 252, and a gate layer 259. The gate dielectric layer 251 surrounds the middle region of the nanowire 241, the gate dielectric layer 252 surrounds the middle region of the nanowire 242, and the gate layer 259 surrounds the gate dielectric layers 251 and 252. The first ends of the nanowires 241 and 242 are surrounded by the spacers 256, and the second ends of the nanowires 241 and 242 are surrounded by the spacers 257. The nanowires 241 and 242 surrounded by the gate structure are switch transistors M. SW1 The gate layer 259 is electrically connected to the word line WL1.

[0042] Anti-fuse transistor M AF1 The present invention comprises a drain / source structure 231, a drain / source structure 232, a gate structure, and nanowires 211 and 212. The gate structure comprises two spacers 226 and 227, gate dielectric layers 221 and 222, and a gate layer 229. The gate dielectric layer 221 surrounds the middle region of the nanowire 211, the gate dielectric layer 222 surrounds the middle region of the nanowire 212, and the gate layer 229 surrounds the gate dielectric layers 221 and 222. The first ends of the nanowires 221 and 222 are surrounded by the spacers 226, and the second ends of the nanowires 221 and 222 are surrounded by the spacers 227. The nanowires 221 and 222 surrounded by the gate structure are anti-fuse transistors M. AF1 The nanowire channel region. Furthermore, two drain / source structures 231 and 232 are located on two sides of the gate structure. The drain / source structure 231 is electrically in contact with the first ends of the nanowires 211 and 212, and the drain / source structure 232 is electrically in contact with the second ends of the nanowires 211 and 212. Furthermore, the gate layer 229 is electrically connected to the anti-fuse control line AF1.

[0043] In addition, in the first memory cell Cell1, the transistor M is selected. SEL1 With the switching transistor M SW1 Shared drain / source structure 233, switch transistor M SW1 With the anti-fuse transistor M AF1 The drain / source structure 232 is shared. The drain / source structure 233 is connected to the switch transistor M via the switch transistor SW1Coupled to the drain / source structure 232. Furthermore, the drain / source structures 231, 232, 233 in the first memory cell Cell1 have the same doping type as the nanowires 211, 212, 241, 242, 261, 262. For example, the drain / source structures 231, 232, 233 and the nanowires 211, 212, 241, 242, 261, 262 are all n-type doping structures or p-type doping structures.

[0044] The second storage cell Cell2 includes: a selection transistor M SEL2 , switching transistor M SW2 With the anti-fuse transistor M AF2 Among them, the anti-fuse transistor M AF2 as a storage transistor.

[0045] Select transistor M SEL2 The structure includes a drain / source structure 234, a drain / source structure 235, a gate structure, and nanowires 361 and 362. The gate structure includes two spacers 376 and 377, gate dielectric layers 371 and 372, and a gate layer 379. Furthermore, the drain / source structure 234 is electrically connected to the bit line BL1, and the gate layer 379 is electrically connected to the word line WL2.

[0046] Switching transistor M SW2 The structure includes drain / source structure 235, drain / source structure 236, a gate structure, and nanowires 341 and 342. The gate structure includes two spacers 356 and 357, gate dielectric layers 351 and 352, and a gate layer 359. Furthermore, the gate layer 359 is electrically connected to the word line WL2.

[0047] Anti-fuse transistor M AF2 The structure includes drain / source structure 236, drain / source structure 237, a gate structure, and nanowires 311 and 312. The gate structure includes two spacers 326 and 327, gate dielectric layers 321 and 322, and a gate layer 329. Furthermore, the gate layer 329 is electrically connected to the anti-fuse control line AF2.

[0048] In addition, in the second memory cell Cell2, the transistor M is selected. SEL2 With the switching transistor M SW2 Shared drain / source structure 235, switch transistor M SW2 With the anti-fuse transistor M AF2 The drain / source structure 236 is shared. Furthermore, the drain / source structures 235, 236, 237 and the nanowires 311, 312, 341, 342, 361, 362 in the second memory cell Cell2 have the same doping type.

[0049] The third storage cell Cell3 includes: a selection transistor M SEL3, switching transistor M SW3 With the anti-fuse transistor M AF3 Among them, the anti-fuse transistor M AF3 as a storage transistor.

[0050] Select transistor M SEL3 The device includes a drain / source structure 333, a drain / source structure 334, a gate structure, and nanowires 264 and 266. The gate structure includes two spacers 276 and 277, gate dielectric layers 265 and 267, and a gate layer 279. Furthermore, the drain / source structure 334 is electrically connected to the bit line BL2, and the gate layer 279 is electrically connected to the word line WL1. The select transistor M of the third memory cell Cell3 SEL3 The selection transistor M of the first memory cell Cell1 SEL1 The spacers 276 , 277 and the gate layer 279 are shared.

[0051] Switching transistor M SW3 The gate structure includes: a drain / source structure 332, a drain / source structure 333, a gate structure, and nanowires 244 and 246. The gate structure includes: two spacers 256 and 257, gate dielectric layers 245 and 247, and a gate layer 259. Furthermore, the gate layer 259 is electrically connected to the word line WL1. The switch transistor M of the third memory cell Cell3 SW3 The switch transistor M of the first storage cell Cell1 SW1 The spacers 256 , 257 and the gate layer 259 are shared.

[0052] Anti-fuse transistor M AF3 The device includes a drain / source structure 331, a drain / source structure 332, a gate structure, and nanowires 214 and 216. The gate structure includes two spacers 226 and 227, gate dielectric layers 215 and 217, and a gate layer 229. Furthermore, the gate layer 229 is electrically connected to the anti-fuse control line AF1. AF3 The anti-fuse transistor M of the first memory cell Cell1 AF1 The spacers 226 , 227 and the gate layer 229 are shared.

[0053] In addition, in the third storage cell Cell3, the transistor M is selected. SEL3 With the switching transistor M SW3 Shared drain / source structure 333, switch transistor M SW3 With the anti-fuse transistor M AF3 The drain / source structure 332 is shared. Furthermore, the drain / source structures 331, 332, 333 in the third memory cell Cell3 and the nanowires 214, 216, 244, 246, 264, 266 have the same doping type.

[0054] The fourth storage cell Cell4 includes: a selection transistor M SEL4 , switching transistor M SW4 With the anti-fuse transistor M AF4 Among them, the anti-fuse transistor M AF4 as a storage transistor.

[0055] Select transistor M SEL4 The fourth memory cell Cell4 has a select transistor M2. SEL4 The selection transistor M of the second memory cell Cell2 SEL2 The spacers 376 , 377 and the gate layer 379 are shared.

[0056] Switching transistor M SW4 The fourth memory cell Cell4 has a switch transistor M2. SW4 The switch transistor M of the second storage cell Cell2 SW2 The spacers 356 , 357 and the gate layer 359 are shared.

[0057] Anti-fuse transistor M AF4 The fourth memory cell Cell4 includes a drain / source structure 336, a drain / source structure 337, a gate structure, and nanowires 314 and 316. The gate structure includes two spacers 326 and 327, gate dielectric layers 315 and 317, and a gate layer 329. Furthermore, the gate layer 329 is electrically connected to the anti-fuse control line AF2. AF4 The anti-fuse transistor M of the second storage cell Cell2 AF2 The spacers 326 , 327 and the gate layer 329 are shared.

[0058] In addition, in the fourth storage cell Cell4, the transistor M is selected. SEL4 With the switching transistor M SW4 Shared drain / source structure 335, switch transistor M SW4 With the anti-fuse transistor M AF4The drain / source structure 336 is shared. Furthermore, the drain / source structures 335, 336, 337 in the fourth memory cell Cell4 and the nanowires 314, 316, 344, 346, 364, 366 have the same doping type.

[0059] In addition, in order to prevent the array structure from generating a large leakage during operation, a dummy transistor may be added to the peripheral memory cell of the array structure. Figure 3A , Figure 3B and Figure 3C As shown, each of the four storage cells Cell1 to Cell4 includes a dummy transistor M DUMMY1 ~M DUMMY4 .

[0060] In the first memory cell Cell1, the dummy transistor M DUMMY1 The structure includes drain / source structure 238, drain / source structure 231, a gate structure, nanowires 281, 282. The gate structure includes two spacers 296 and 297, gate dielectric layers 291, 292 and a gate layer 299.

[0061] In the second storage cell Cell2, the dummy transistor M DUMMY2 The structure includes drain / source structure 237, drain / source structure 239, a gate structure, nanowires 381, 382. The gate structure includes two spacers 396 and 397, gate dielectric layers 391, 392 and a gate layer 399.

[0062] In the third storage cell Cell3, the dummy transistor M DUMMY3 The structure includes drain / source structure 338, drain / source structure 331, a gate structure, nanowires 284 and 286. The gate structure includes two spacers 296 and 297, gate dielectric layers 285 and 287, and a gate layer 299.

[0063] In the fourth storage cell Cell4, the dummy transistor M DUMMY4 The gate structure includes: a drain / source structure 337, a drain / source structure 339, a gate structure, and nanowires 384 and 386. The gate structure includes: two spacers 396 and 397, gate dielectric layers 385 and 387, and a gate layer 399. In addition, four dummy transistors M DUMMY1 ~M DUMMY4 The gate layers 229 and 339 are connected to a dummy gate control line Gd, and the four M DUMMY1 ~M DUMMY4 The drain / source structures 238, 239, 338, 339 are floating.

[0064] Please refer to Figure 3D , which is a schematic diagram showing the bias voltages for programming and reading operations of the OTP memory according to the first embodiment of the present invention.

[0065] In the following description of the programming operation (PGM) and the reading operation (READ), the first memory cell Cell1 is regarded as a selected memory cell, and the other memory cells Cell2 to Cell4 are regarded as unselected memory cells.

[0066] According to the first embodiment of the present invention, when the array structure performs a programming operation (PGM), the array structure receives a negative programming voltage (-V BB To prevent negative programming voltage (-V BB ) affects other peripheral circuits in the OTP memory. The array structure is designed on the P-type well region PW, and the N-type region (N_region) is used to isolate the P-type semiconductor substrate P_sub and the P-type well region PW, so that the P-type well region PW becomes an isolated P-type well region.

[0067] Furthermore, during the programming operation (PGM), the P-type well region PW receives a negative programming voltage (-V BB ), the N-type region (N_region) receives the first voltage V1, and the P-type semiconductor substrate P_sub receives the second voltage V2. Among them, the negative programming voltage (-V BB ) is less than or equal to -1V, and the negative programming voltage (-V BB ) is greater than or equal to -2.5V. The first voltage V1 is greater than or equal to 0V, and the first voltage V1 is less than or equal to 1.6V. Therefore, there is a reverse bias between the N-type region (N_region) and the P-type well region PW. In addition, the second voltage V2 is greater than or equal to the negative programming voltage (-V BB ), and the second voltage V2 is less than or equal to the first voltage V1. Therefore, there is a reverse bias between the N-type region (N_region) and the P-type semiconductor substrate P_sub or there is no voltage difference between the N-type region (N_region) and the P-type semiconductor substrate P_sub, that is, zero bias.

[0068] like Figure 3D As shown, during the programming action (PGM), the word line WL1 receives the third voltage V3, and the word line WL2 receives the negative programming voltage (-V BB). Therefore, the word line WL1 is the selected word line, and the word line WL2 is the unselected word line. The third voltage V3 can be regarded as an on voltage, the third voltage V3 is greater than or equal to -1V, and the first voltage V1 is less than or equal to the power supply voltage V DD In addition, the negative programming voltage (-V BB ) can be regarded as the off voltage.

[0069] Furthermore, the bit line BL1 receives a negative programming voltage (-V BB ), the bit line BL2 receives the third voltage V3. The anti-fuse control line AF1 receives the positive programming voltage V PP , the anti-fuse control line AF2 receives a fourth voltage V4. Among them, the programming voltage V PP Greater than or equal to 1V, programming voltage V PP The fourth voltage V4 is greater than or equal to the negative programming voltage (-V BB ), the fourth voltage V4 is less than or equal to 0V.

[0070] In the first memory cell Cell1 (selected memory cell) of the array structure, the word line WL1 receives the third voltage V3, so the transistor M is selected. SEL1 With the switching transistor M SW1 Therefore, through the selection transistor M SEL1 With the switching transistor M SW1 , the negative programming voltage (-V BB ) is passed to the anti-fuse transistor M AF1 Furthermore, since the anti-fuse control line AF1 receives the positive programming voltage V PP , so the anti-fuse transistor M AF1 The total voltage stress on both sides of the gate dielectric layers 221 and 222 is the total programming voltage. The total programming voltage is approximately equal to the positive programming voltage (V PP ) minus the negative programming voltage (-V BB ), that is, (V PP +V BB ). Therefore, one of the gate dielectric layers 221 and 222 is ruptured, so that the storage state of the first memory cell Cell1 is changed from an unruptured state to a ruptured state.

[0071] In the second memory cell Cell2 (non-selected memory cell) of the array structure, the word line WL2 receives a negative programming voltage (off voltage), so the selection transistor M SEL2 With the switching transistor M SW2Therefore, the anti-fuse transistor M AF2 The two sides of the gate dielectric layers 321 and 322 are not subjected to voltage stress, so the gate dielectric layers 321 and 322 are not broken, so that the storage state of the second memory cell Cell2 is maintained in an unbroken state.

[0072] In the third memory cell Cell3 (non-selected memory cell) of the array structure, the word line WL1 receives the third voltage V3, and the bit line BL2 receives the third voltage V3. Therefore, the transistor M is selected. SEL3 With the switching transistor M SW3 Turn off. Anti-fuse transistor M AF3 The two sides of the gate dielectric layers 215 and 217 are not subjected to voltage stress, so the gate dielectric layers 215 and 217 are not broken, so that the storage state of the third memory cell Cell3 is maintained in an unbroken state.

[0073] In the fourth memory cell Cell4 (non-selected memory cell) of the array structure, the word line WL2 receives a negative programming voltage (-V BB ), and the bit line BL2 receives the third voltage V3. Therefore, the transistor M is selected. SEL4 With the switching transistor M SW4 Turn off (turn off). Anti-fuse transistor M AF4 The two sides of the gate dielectric layers 315 and 317 are not subjected to voltage stress, so the gate dielectric layers 315 and 317 are not broken, so that the storage state of the fourth memory cell Cell4 is maintained in an unbroken state.

[0074] In addition, during the programming operation (PGM), the voltage received by the gate control line Gd is less than or equal to the negative programming voltage (-V BB ). Therefore, it can be ensured that the four dummy transistors M DUMMY1 ~M DUMMY4 When turned off, no leakage current will be generated.

[0075] According to the first embodiment of the present invention, during the read operation (READ), the P-type well region PW receives the ground voltage (0V), the N-type region (N_region) receives the first voltage V1, and the P-type semiconductor substrate P_sub receives the second voltage V2. Therefore, there is a reverse bias between the N-type region (N_region) and the P-type well region PW or there is no voltage difference between the N-type region (N_region) and the P-type well region PW, that is, zero bias. Similarly, there is a reverse bias between the N-type region (N_region) and the P-type semiconductor substrate P_sub or there is no voltage difference between the N-type region (N_region) and the P-type semiconductor substrate P_sub, that is, zero bias.

[0076] like Figure 3D As shown, during the read operation (READ), the word line WL1 receives the supply voltage V DD , word line WL2 receives the ground voltage (0V). Therefore, word line WL1 is the selected word line, and word line WL2 is the unselected word line. DD It can be regarded as the on voltage, and the ground voltage (0V) can be regarded as the off voltage.

[0077] Furthermore, the bit line BL1 receives a ground voltage (0V), and the bit line BL2 receives a supply voltage V DD The anti-fuse control line AF1 receives the read voltage V READ , the anti-fuse control line AF2 receives the read voltage V READ Among them, the read voltage V READ Greater than or equal to 0.4V, read voltage V READ Less than or equal to 1.6V.

[0078] In the first memory cell Cell1 (selected memory cell) of the array structure, the word line WL1 receives the supply voltage V DD , so select transistor M SEL1 With the switching transistor M SW1 Turn on. A read current is generated between the anti-fuse control line AF1 and the bit line BL1, and the magnitude of the read current can be determined by the storage state of the first memory cell Cell1. For example, when the first memory cell Cell1 is in a broken state, the read current of the first memory cell Cell1 is relatively large, such as 2 mA. When the first memory cell Cell1 is in a broken but unbroken state, the read current of the first memory cell Cell1 is very small (almost zero). Therefore, the storage state of the first memory cell Cell1 can be determined according to the magnitude of the read current.

[0079] In the second memory cell Cell2 (non-selected memory cell) of the array structure, the word line WL2 receives the ground voltage (0V), so the selection transistor M SEL2 With the switching transistor M SW2 Turn off. No read current can be generated between the anti-fuse control line AF2 and the bit line BL1.

[0080] In the third memory cell Cell3 (non-selected memory cell) of the array structure, the word line WL1 receives the supply voltage V DD , bit line BL2 receives supply voltage V DD , so select transistor M SEL3 With the switching transistor M SW3 Turn off. No read current can be generated between the anti-fuse control line AF1 and the bit line BL2.

[0081] In the fourth memory cell Cell4 (non-selected memory cell) of the array structure, the word line WL2 receives the ground voltage (0V), so the selection transistor M SEL4 With the switching transistor M SW4 Turn off. No read current can be generated between the anti-fuse control line AF2 and the bit line BL2.

[0082] In addition, during the reading operation (READ), the gate control line Gd receives the ground voltage (0 V). Therefore, the four dummy transistors M can be ensured to be DUMMY1 ~M DUMMY4 When turned off, no leakage current will be generated.

[0083] Please refer to Figure 4A , Figure 4B and Figure 4C , which illustrates a top view of the array structure of an anti-fuse one-time programming memory according to a second embodiment of the present invention, a cross-sectional view along the dotted line gh, and a cross-sectional view along the dotted line ij.

[0084] The array structure includes four memory cells Cell1 to Cell4, forming a 2×2 array structure, and the structure of each memory cell Cell1 to Cell4 is similar. Furthermore, the array structure is designed above the P-type well region PW in the P-type semiconductor substrate P_sub. Furthermore, an N-type region (N-type region) is formed in the P-type semiconductor substrate P_sub and is located below the P-type well region PW. Among them, the N-type region can be a deep N-well region (Deep N-Well, referred to as DNW) or an N-buried layer (N-buried layer, referred to as NBL). In addition, the P-type semiconductor substrate P_sub and the P-type well region PW are isolated by the N-type region (N-type region).

[0085] According to the second embodiment of the present invention, the array structure is connected to at least the bit lines BL1, BL2, the word lines WL1, WL2 and the anti-fuse control lines AF1, AF2. Each memory cell Cell1 to Cell4 in the array structure includes at least five GAA transistors. The structure of each GAA transistor is the same as Figure 1A The GAA transistor shown.

[0086] The first storage cell Cell1 includes: a selection transistor M SEL11 , switching transistor M SW11 , anti-fuse transistor M AF1 , switching transistor M SW12 With the selection transistor M SEL12 Among them, the anti-fuse transistor M AF1 As a storage transistor.

[0087] Select transistor M SEL11 The present invention comprises: a drain / source structure 408, a drain / source structure 409, a gate structure, and nanowires 401 and 402. The gate structure comprises: two spacers 405 and 406, gate dielectric layers 403 and 404, and a gate layer 407. The gate dielectric layer 403 surrounds the middle region of the nanowire 401, the gate dielectric layer 404 surrounds the middle region of the nanowire 402, and the gate layer 407 surrounds the gate dielectric layers 403 and 404. The first ends of the nanowires 401 and 402 are surrounded by the spacers 405, and the second ends of the nanowires 401 and 402 are surrounded by the spacers 406. The nanowires 401 and 402 surrounded by the gate structure are the selection transistors M. SEL11The nanowire channel region. Furthermore, two drain / source structures 408 and 409 are located on both sides of the gate structure. The drain / source structure 408 is electrically connected to the first end of the nanowires 401 and 402, and the drain / source structure 409 is electrically connected to the second end of the nanowires 401 and 402. Furthermore, the drain / source structure 408 is electrically connected to the bit line BL1, and the gate layer 407 is electrically connected to the word line WL1.

[0088] Switching transistor M SW11 The present invention comprises a drain / source structure 409, a drain / source structure 419, a gate structure, and nanowires 411 and 412. The gate structure comprises two spacers 415 and 416, gate dielectric layers 413 and 414, and a gate layer 417. The gate dielectric layer 413 surrounds the middle region of the nanowire 411, the gate dielectric layer 414 surrounds the middle region of the nanowire 412, and the gate layer 417 surrounds the gate dielectric layers 413 and 414. The first ends of the nanowires 411 and 412 are surrounded by the spacers 415, and the second ends of the nanowires 411 and 412 are surrounded by the spacers 416. The nanowires 411 and 412 surrounded by the gate structure are switch transistors M. SW11 The gate layer 417 is electrically connected to the word line WL1.

[0089] Anti-fuse transistor M AF1 The present invention comprises a drain / source structure 419, a drain / source structure 429, a gate structure, and nanowires 421 and 422. The gate structure comprises two spacers 425 and 426, gate dielectric layers 423 and 424, and a gate layer 427. The gate dielectric layer 423 surrounds the middle region of the nanowire 421, the gate dielectric layer 424 surrounds the middle region of the nanowire 422, and the gate layer 427 surrounds the gate dielectric layers 423 and 424. The first ends of the nanowires 421 and 422 are surrounded by the spacers 425, and the second ends of the nanowires 421 and 422 are surrounded by the spacers 426. The nanowires 421 and 422 surrounded by the gate structure are anti-fuse transistors M. AF1 The nanowire channel region. Furthermore, two drain / source structures 419 and 429 are located on two sides of the gate structure. The drain / source structure 419 is electrically in contact with the first ends of the nanowires 421 and 422, and the drain / source structure 429 is electrically in contact with the second ends of the nanowires 421 and 422. Furthermore, the gate layer 427 is electrically connected to the anti-fuse control line AF1.

[0090] Switching transistor M SW12The present invention comprises a drain / source structure 429, a drain / source structure 439, a gate structure, and nanowires 431 and 432. The gate structure comprises two spacers 435 and 436, gate dielectric layers 433 and 434, and a gate layer 437. The gate dielectric layer 433 surrounds the middle region of the nanowire 431, the gate dielectric layer 434 surrounds the middle region of the nanowire 432, and the gate layer 437 surrounds the gate dielectric layers 433 and 434. The first ends of the nanowires 431 and 432 are surrounded by the spacers 435, and the second ends of the nanowires 431 and 432 are surrounded by the spacers 436. The nanowires 431 and 432 surrounded by the gate structure are switch transistors M. SW12 The gate layer 437 is electrically connected to the word line WL1.

[0091] Select transistor M SEL12 The present invention comprises a drain / source structure 439, a drain / source structure 449, a gate structure, and nanowires 441 and 442. The gate structure comprises two spacers 445 and 446, gate dielectric layers 443 and 444, and a gate layer 447. The gate dielectric layer 443 surrounds the middle region of the nanowire 441, the gate dielectric layer 444 surrounds the middle region of the nanowire 442, and the gate layer 447 surrounds the gate dielectric layers 443 and 444. The first ends of the nanowires 441 and 442 are surrounded by the spacers 445, and the second ends of the nanowires 441 and 442 are surrounded by the spacers 446. The nanowires 441 and 442 surrounded by the gate structure are the selection transistors M. SEL12 The nanowire channel region. Furthermore, two drain / source structures 439 and 449 are located on both sides of the gate structure. The drain / source structure 439 is electrically in contact with the first ends of the nanowires 441 and 442, and the drain / source structure 449 is electrically in contact with the second ends of the nanowires 441 and 442. Furthermore, the drain / source structure 449 is electrically connected to the bit line BL1, and the gate layer 447 is electrically connected to the word line WL1.

[0092] In addition, in the first memory cell Cell1, the transistor M is selected. SEL11 With the switching transistor M SW11 Shared drain / source structure 409, switch transistor M SW11 With the anti-fuse transistor M AF1 Shared drain / source structure 419, anti-fuse transistor M AF1 With the switching transistor M SW12 Shared drain / source structure 429, switch transistor M SW12 With the selection transistor M SEL12and a shared drain / source structure 439. Furthermore, the drain / source structures 408, 409, 419, 429, 439, 449 in the first memory cell Cell1 and the nanowires 401, 402, 411, 412, 421, 422, 431, 432, 441, 442 have the same doping type.

[0093] The second storage cell Cell2 includes: a selection transistor M SEL21 , switching transistor M SW21 , anti-fuse transistor M AF2 , switching transistor M SW22 With the selection transistor M SEL22 Among them, the anti-fuse transistor M AF2 as a storage transistor.

[0094] Select transistor M SEL21 It includes drain / source structure 449, drain / source structure 459, a gate structure, nanowires 451, 452. The gate structure includes two spacers 455 and 456, gate dielectric layers 453, 454 and a gate layer 457. Furthermore, the gate layer 457 is electrically connected to the word line WL2.

[0095] Switching transistor M SW21 It includes drain / source structure 459, drain / source structure 469, a gate structure, nanowires 461, 462. The gate structure includes two spacers 465 and 466, gate dielectric layers 463, 464 and a gate layer 467. Furthermore, the gate layer 467 is electrically connected to the word line WL2.

[0096] Anti-fuse transistor M AF2 The structure includes a drain / source structure 469, a drain / source structure 479, a gate structure, and nanowires 471 and 472. The gate structure includes two spacers 475 and 476, gate dielectric layers 473 and 474, and a gate layer 477. Furthermore, the gate layer 477 is electrically connected to the anti-fuse control line AF2.

[0097] Switching transistor M SW22 It includes drain / source structure 479, drain / source structure 489, a gate structure, nanowires 481, 482. The gate structure includes two spacers 485 and 486, gate dielectric layers 483, 484 and a gate layer 487. Furthermore, the gate layer 487 is electrically connected to the word line WL2.

[0098] Select transistor M SEL22It includes: drain / source structure 489, drain / source structure 499, a gate structure, nanowires 491, 492. The gate structure includes: two spacers 495 and 496, gate dielectric layers 493, 494 and a gate layer 497. Furthermore, the drain / source structure 499 is electrically connected to the bit line BL1, and the gate layer 497 is electrically connected to the word line WL2.

[0099] In addition, in the second memory cell Cell2, the transistor M is selected. SEL21 With the switching transistor M SW21 Shared drain / source structure 459, switch transistor M SW21 With the anti-fuse transistor M AF2 Shared drain / source structure 469, anti-fuse transistor M AF2 With the switching transistor M SW22 Shared drain / source structure 479, switch transistor M SW22 With the selection transistor M SEL22 The drain / source structure 489 is shared. Furthermore, the drain / source structures 449, 459, 469, 479, 489, 499 in the second memory cell Cell2 have the same doping type as the nanowires 451, 452, 461, 462, 471, 472, 481, 482, 491, 492.

[0100] The third storage cell Cell3 includes: a selection transistor M SEL31 , switching transistor M SW31 , anti-fuse transistor M AF3 , switching transistor M SW32 With the selection transistor M SEL32 Among them, the anti-fuse transistor M AF3 as a storage transistor.

[0101] Select transistor M SEL31 The gate structure includes: a drain / source structure 508, a drain / source structure 509, a gate structure, and nanowires 501 and 502. The gate structure includes: two spacers 405 and 406, gate dielectric layers 503 and 504, and a gate layer 407. The selection transistor M of the third memory cell Cell3 SEL31 The selection transistor M of the first memory cell Cell1 SEL11 The spacers 405 , 406 and the gate layer 407 are shared.

[0102] Switching transistor M SW31 The gate structure includes: a drain / source structure 509, a drain / source structure 519, a gate structure, and nanowires 511 and 512. The gate structure includes: two spacers 415 and 416, gate dielectric layers 513 and 514, and a gate layer 417. The switch transistor M of the third memory cell Cell3 SW31The switch transistor M of the first storage cell Cell1 SW11 The spacers 415 , 416 and the gate layer 417 are shared.

[0103] Anti-fuse transistor M AF3 The anti-fuse transistor M of the third memory cell Cell3 is shown in FIG. 4 . The anti-fuse transistor M of the third memory cell Cell3 is shown in FIG. 4 . The anti-fuse transistor M of the third memory cell Cell3 is shown in FIG. 4 . The anti-fuse transistor M of the third memory cell Cell3 is shown in FIG. 4 . AF3 The anti-fuse transistor M of the first memory cell Cell1 AF1 The spacers 425 , 426 and the gate layer 427 are shared.

[0104] Switching transistor M SW32 The gate structure includes: a drain / source structure 529, a drain / source structure 539, a gate structure, and nanowires 531 and 532. The gate structure includes: two spacers 435 and 436, gate dielectric layers 533 and 534, and a gate layer 437. The switch transistor M of the third memory cell Cell3 SW32 The switch transistor M of the first storage cell Cell1 SW12 The spacers 435 , 436 and the gate layer 437 are shared.

[0105] Select transistor M SEL32 The gate structure includes: a drain / source structure 539, a drain / source structure 549, a gate structure, and nanowires 541 and 542. The gate structure includes: two spacers 445 and 446, gate dielectric layers 543 and 544, and a gate layer 447. The selection transistor M of the third memory cell Cell3 SEL32 The selection transistor M of the first memory cell Cell1 SEL12 The spacers 445 , 446 and the gate layer 447 are shared.

[0106] In addition, in the third storage cell Cell3, the transistor M is selected. SEL31 With the switching transistor M SW31 Shared drain / source structure 509, switch transistor M SW31 With the anti-fuse transistor M AF3 Shared drain / source structure 519, anti-fuse transistor M AF3 With the switching transistor M SW32 Shared drain / source structure 529, switch transistor M SW32 With the selection transistor M SEL32The drain / source structure 539 is shared. Furthermore, the drain / source structures 508, 509, 519, 529, 539, 549 in the third memory cell Cell3 have the same doping type as the nanowires 501, 502, 511, 512, 521, 522, 531, 532, 541, 542.

[0107] The fourth storage cell Cell4 includes: a selection transistor M SEL41 , switching transistor M SW41 , anti-fuse transistor M AF4 , switching transistor M SW42 With the selection transistor M SEL42 Among them, the anti-fuse transistor M AF4 as a storage transistor.

[0108] Select transistor M SEL41 The gate structure includes: a drain / source structure 549, a drain / source structure 559, a gate structure, and nanowires 551 and 552. The gate structure includes: two spacers 455 and 456, gate dielectric layers 553 and 554, and a gate layer 457. The selection transistor M of the fourth memory cell Cell4 SEL41 The selection transistor M of the second memory cell Cell2 SEL21 The spacers 455 , 456 and the gate layer 457 are shared.

[0109] Switching transistor M SW41 The fourth memory cell Cell4 includes a drain / source structure 559, a drain / source structure 569, a gate structure, and nanowires 561 and 562. The gate structure includes two spacers 465 and 466, gate dielectric layers 563 and 564, and a gate layer 467. SW41 The switch transistor M of the second storage cell Cell2 SW21 The spacers 465 , 466 and the gate layer 467 are shared.

[0110] Anti-fuse transistor M AF4 The fourth memory cell Cell4 includes a drain / source structure 569, a drain / source structure 579, a gate structure, and nanowires 571 and 572. The gate structure includes two spacers 475 and 476, gate dielectric layers 573 and 574, and a gate layer 477. AF4 The anti-fuse transistor M of the second storage cell Cell2 AF2 The spacers 475 , 476 and the gate layer 477 are shared.

[0111] Switching transistor M SW42The fourth memory cell Cell4 has a switch transistor M4. SW42 The switch transistor M of the second storage cell Cell2 SW22 The spacers 485 , 486 and the gate layer 487 are shared.

[0112] Select transistor M SEL42 The gate structure includes: a drain / source structure 589, a drain / source structure 599, a gate structure, and nanowires 591 and 592. The gate structure includes: two spacers 495 and 496, gate dielectric layers 593 and 594, and a gate layer 497. The selection transistor M of the fourth memory cell Cell4 SEL42 The selection transistor M of the second memory cell Cell2 SEL22 The spacers 495 , 496 and the gate layer 497 are shared.

[0113] In addition, in the fourth storage cell Cell4, the transistor M is selected. SEL41 With the switching transistor M SW41 Shared drain / source structure 559, switch transistor M SW41 With the anti-fuse transistor M AF4 Shared drain / source structure 569, anti-fuse transistor M AF4 With the switching transistor M SW42 Shared drain / source structure 579, switch transistor M SW42 With the selection transistor M SEL42 The drain / source structure 589 is shared. Furthermore, the drain / source structures 549, 559, 569, 579, 589, 599 in the fourth memory cell Cell4 and the nanowires 551, 552, 561, 562, 571, 572, 581, 582, 591, 592 have the same doping type.

[0114] Similar to the array structure of the first embodiment, in order to prevent the array structure from generating a large leakage during operation, a dummy transistor (not shown) may be added to the peripheral memory cells of the array structure.

[0115] Please refer to Figure 4D , which illustrates a bias voltage representation diagram of the OTP memory performing programming and reading operations according to the second embodiment of the present invention.

[0116] In the following description of the programming operation (PGM) and the reading operation (READ), the first memory cell Cell1 is used as the selected memory cell, and the other memory cells Cell2 to Cell4 are used as the non-selected memory cells.

[0117] According to the second embodiment of the present invention, when the array structure performs a programming operation (PGM), the P-type well region PW receives a negative programming voltage (-V BB ), the N-type region (N_region) receives the first voltage V1, and the P-type semiconductor substrate P_sub receives the second voltage V2. Among them, the negative programming voltage (-V BB ) is less than or equal to -1V, and the negative programming voltage (-V BB ) is greater than or equal to -2.5V. The first voltage V1 is greater than or equal to 0V, and the first voltage V1 is less than or equal to 1.6V. In addition, the second voltage V2 is greater than or equal to the negative programming voltage (-V BB ), and the second voltage V2 is less than or equal to the first voltage V1.

[0118] like Figure 4D As shown, during the programming action (PGM), the word line WL1 receives the third voltage V3, and the word line WL2 receives the negative programming voltage (-V BB ). Therefore, the word line WL1 is the selected word line, and the word line WL2 is the unselected word line. The third voltage V3 can be regarded as an on voltage, the third voltage V3 is greater than or equal to -1V, and the first voltage V1 is less than or equal to the power supply voltage V DD In addition, the negative programming voltage (-V BB ) can be regarded as the off voltage.

[0119] Furthermore, the bit line BL1 receives a negative programming voltage (-V BB ), the bit line BL2 receives the third voltage V3. The anti-fuse control line AF1 receives the positive programming voltage V PP , the anti-fuse control line AF2 receives a fourth voltage V4. Among them, the programming voltage V PP Greater than or equal to 1V, programming voltage V PP The fourth voltage V4 is greater than or equal to the negative programming voltage (-V BB ), the fourth voltage V4 is less than or equal to 0V.

[0120] In the first memory cell Cell1 (selected memory cell) of the array structure, the word line WL1 receives the third voltage V3, so the transistor M is selected. SEL11 , select transistor M SEL12 , switching transistor M SW11 With the switching transistor M SW12 Therefore, through the selection transistor M SEL11 With the switching transistor M SW11 and through the selection transistor M SEL12 With the switching transistor M SW12, the negative programming voltage (-V BB ) is passed to the anti-fuse transistor M AF1 Furthermore, since the anti-fuse control line AF1 receives the positive programming voltage V PP , so the anti-fuse transistor M AF1 The total voltage stress on both sides of the gate dielectric layers 423 and 424 is the total programming voltage, which is approximately equal to the positive programming voltage (V PP ) minus the negative programming voltage (-V BB ), that is, (V PP +V BB ), causing one of the gate dielectric layers 423, 424 to be broken, so that the storage state of the first memory cell Cell1 is changed from an unbroken state to a broken state.

[0121] In the second memory cell Cell2 (non-selected memory cell) of the array structure, the word line WL2 receives a negative programming voltage (off voltage), so the selection transistor M SEL21 , select transistor M SEL22 , switching transistor M SW21 With the switching transistor M SW22 Therefore, the anti-fuse transistor M AF2 The two sides of the gate dielectric layers 473 and 474 are not subjected to voltage stress, so the gate dielectric layers 473 and 474 are not broken, so that the storage state of the second memory cell Cell2 is maintained in an unbroken state.

[0122] In the third memory cell Cell3 (non-selected memory cell) of the array structure, the word line WL1 receives the third voltage V3, and the bit line BL2 receives the third voltage V3. Therefore, the transistor M is selected. SEL31 , select transistor M SEL32 , switching transistor M SW31 With the switching transistor M SW32 Turn off. Anti-fuse transistor M AF3 The two sides of the gate dielectric layers 523 and 524 are not subjected to voltage stress, so the gate dielectric layers 523 and 524 are not broken, so that the storage state of the third memory cell Cell3 is maintained in an unbroken state.

[0123] In the fourth memory cell Cell4 (non-selected memory cell) of the array structure, the word line WL2 receives a negative programming voltage (-V BB ), and the bit line BL2 receives the third voltage V3. Therefore, the transistor M is selected. SEL41 , select transistor M SEL42 , switching transistor M SW41 With the switching transistor MSW42 Turn off. Anti-fuse transistor M AF4 The two sides of the gate dielectric layers 573 and 574 are not subjected to voltage stress, so the gate dielectric layers 573 and 574 are not broken, so that the storage state of the fourth memory cell Cell4 is maintained in an unbroken state.

[0124] According to the second embodiment of the present invention, during a programming action (READ), the P-type well region PW receives a ground voltage (0V), the N-type region (N_region) receives a first voltage V1 , and the P-type semiconductor substrate P_sub receives a second voltage V2 .

[0125] like Figure 4D As shown, during the read operation (READ), the word line WL1 receives the supply voltage V DD , word line WL2 receives the ground voltage (0V). Therefore, word line WL1 is the selected word line, and word line WL2 is the unselected word line. DD It can be regarded as the on voltage, and the ground voltage (0V) can be regarded as the off voltage.

[0126] Furthermore, the bit line BL1 receives a ground voltage (0V), and the bit line BL2 receives a supply voltage V DD The anti-fuse control line AF1 receives the read voltage V READ , the anti-fuse control line AF2 receives the read voltage V READ Among them, the read voltage V READ Greater than or equal to 0.4V, read voltage V READ Less than or equal to 1.6V.

[0127] In the first memory cell Cell1 (selected memory cell) of the array structure, the word line WL1 receives the supply voltage V DD , so select transistor M SEL11 , select transistor M SEL12 , switching transistor M SW11 With the switching transistor M SW12 Turn on. A read current is generated between the anti-fuse control line AF1 and the bit line BL1, and the magnitude of the read current can be determined by the storage state of the first memory cell Cell1. For example, when the first memory cell Cell1 is in a broken state, the read current of the first memory cell Cell1 is relatively large, such as 2 mA. When the first memory cell Cell1 is in a broken but unbroken state, the read current of the first memory cell Cell1 is very small (almost zero). Therefore, the storage state of the first memory cell Cell1 can be determined according to the magnitude of the read current.

[0128] In the second memory cell Cell2 (non-selected memory cell) of the array structure, the word line WL2 receives the ground voltage (0V), so the selection transistor M SEL21 , select transistor M SEL22 , switching transistor M SW21 With the switching transistor M SW22 Turn off. No read current can be generated between the anti-fuse control line AF2 and the bit line BL1.

[0129] In the third memory cell Cell3 (non-selected memory cell) of the array structure, the word line WL1 receives the supply voltage V DD , bit line BL2 receives supply voltage V DD , so select transistor M SEL31 , select transistor M SEL32 , switching transistor M SW31 With the switching transistor M SW32 Turn off. No read current can be generated between the anti-fuse control line AF1 and the bit line BL2.

[0130] In the fourth memory cell Cell4 (non-selected memory cell) of the array structure, the word line WL2 receives the ground voltage (0V), so the selection transistor M SEL41 , select transistor M SEL42 , switching transistor M SW41 With the switching transistor M SW42 Turn off. No read current can be generated between the anti-fuse control line AF2 and the bit line BL2.

[0131] Furthermore, in order to save the layout area of ​​the anti-fuse OTP memory, the bias voltage of the array structure of the first embodiment and the second embodiment can be modified. PP The supply voltage V DD That is to say, during the programming operation, the total programming voltage is approximately (V DD +V BB ) can also cause the gate dielectric layer of the anti-fuse transistor in the selected memory cell to break. Since the anti-fuse OTP memory does not have a power supply circuit to generate a positive programming voltage V PP , so the layout area of ​​the anti-fuse type OTP memory can be reduced.

[0132] In addition, the present invention can further modify the connection lines in the array structures of the first embodiment and the second embodiment according to actual needs.

[0133] Please refer to Figure 5A and Figure 5B, which shows a top view of the array structure of the anti-fuse one-time programming memory and a bias table of the third embodiment of the present invention. Compared with the first embodiment, the difference is that in the array structure of the third embodiment, the switch transistor M SW1 、M SW3 、M SW2 、M SW4 The following only introduces the differences between the third embodiment and the first embodiment, and the rest will not be described in detail.

[0134] like Figure 5A As shown, in the first storage cell Cell1 and the third storage cell Cell3, the transistor connected to the selection transistor M SEL1 、M SEL3 The conducting line of the gate layer 279 is used as the word line WL1, which is connected to the switch transistor M SW1 、M SW3 The conductive line of the gate layer 259 serves as a following line (FL), and the word line WL1 and the following line FL are not connected to each other. Similarly, in the second memory cell Cell2 and the fourth memory cell Cell4, the gate layer 259 is connected to the selection transistor M SEL2 、M SEL4 The conductive line of the gate layer 379 is used as the word line WL2, which is connected to the switch transistor M SW2 、M SW4 The conductive line of the gate layer 359 serves as the following line FL, and the word line WL2 and the following line FL are not connected to each other. SW1 、M SW3 The conductive line of the gate layer 259 is connected to the switch transistor M SW2 、M SW4 The conductive lines of the gate layer 359 are connected to each other and serve as following lines FL.

[0135] like Figure 5B As shown, during the programming operation (PGM), the following line FL receives the following voltage V FL . Follow voltage V FL Greater than or equal to 0V, and following voltage V FL Less than or equal to 1.5V. Following voltage V FL The switching transistor M SW1 、M SW2 、M SW3 、M SW4Keep in the conducting state, or called the open state. Similarly, during the programming action (PGM), the first memory cell Cell1 is the selected memory cell, and its storage state can be changed to the rupture state. The other memory cells Cell2 to Cell4 are non-selected memory cells, and their storage states will not change.

[0136] like Figure 5B As shown, during the read operation (READ), the following line FL receives the supply voltage V DD . V DD The switching transistor M SW1 、M SW2 、M SW3 、M SW4 Similarly, during a read operation (READ), the first memory cell Cell1 can generate a read current, while the other memory cells Cell2 to Cell4 cannot generate a read current.

[0137] Please refer to Fig. 6A and Figure 6B , which is a top view of the array structure of the anti-fuse one-time programming memory and a bias table of the fourth embodiment of the present invention. Compared with the second embodiment, the difference is that in the array structure of the fourth embodiment, the switch transistor M SW11 、M SW12 、M SW21 、M SW22 、M SW31 、M SW32 、M SW41 、M SW42 The following only introduces the differences between the fourth embodiment and the second embodiment, and the rest will not be described in detail.

[0138] like Fig. 6A As shown, in the first storage cell Cell1 and the third storage cell Cell3, the transistor connected to the selection transistor M SEL11 、M SEL12 、M SEL31 、M SEL32 The conducting lines of the gate layers 407 and 447 are used as word lines WL1 and connected to the switch transistor M SW11 、M SW12 、M SW31 、M SW32 The conductive lines of the gate layers 417 and 437 serve as the following lines FL, and the word line WL1 and the following lines FL are not connected to each other. Similarly, in the second memory cell Cell2 and the fourth memory cell Cell4, the gate lines connected to the selection transistors M SEL21 、MSEL22 、M SEL41 、M SEL42 The conductive lines of the gate layers 457 and 497 are used as word lines WL2 and connected to the switch transistor M SW21 、M SW22 、M SW41 、M SW42 The conductive lines of the gate layers 467 and 487 serve as the following lines FL, and the word line WL2 and the following lines FL are not connected to each other. SW11 、M SW12 、M SW31 、M SW32 The wires of the gate layers 417 and 437 are connected to the switch transistor M SW21 、M SW22 、M SW41 、M SW42 The conductive lines of the gate layers 467 and 487 are connected to each other and serve as a following line FL.

[0139] like Figure 6B As shown, during the programming action (PGM), the following line FL receives the following voltage V FL . Follow voltage V FL The switching transistor M SW11 、M SW12 、M SW21 、M SW22 、M SW31 、M SW32 、M SW41 、M SW42 Similarly, during the programming operation (PGM), the first memory cell Cell1 is a selected memory cell, and its storage state can be changed to a rupture state. The other memory cells Cell2 to Cell4 are non-selected memory cells, and their storage states will not be changed.

[0140] like Figure 6B As shown, during the read operation (READ), the following line FL receives the supply voltage V DD . V DD The switching transistor M SW11 、M SW12 、M SW21 、M SW22 、M SW31 、M SW32 、M SW41 、M SW42Similarly, during a read operation (READ), the first memory cell Cell1 can generate a read current, while the other memory cells Cell2 to Cell4 cannot generate a read current.

[0141] In summary, the present invention proposes an anti-fuse type OTP memory and a related bias control method. In the above four embodiments, by using the bias control table disclosed in the present invention, any memory cell in the array structure can be determined as a selected memory cell during a programming action (PGM) and a reading action (READ), and a programming action or a reading action can be performed on the selected memory cell. Furthermore, the present invention further utilizes a positive programming voltage (V PP ) and the negative programming voltage (-V BB ) are combined into a total programming voltage. The voltage stress of the total programming voltage can cause the gate dielectric layer of the anti-fuse transistor in the selected memory cell to rupture, thus successfully completing the programming operation. Furthermore, since the power supply circuit of the present invention supplies a negative programming voltage (-V BB ) and the positive programming voltage (V PP ), so all GAA transistors in the anti-fuse OTP memory can operate normally in the safe operating area (SOA) without causing damage to the GAA transistors.

[0142] In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the definition of the attached claims.

Claims

1. An anti-fuse type one-time programming memory has a first storage unit, the first storage unit comprising: P-type semiconductor substrate; A P-type well region is located on the surface of the P-type semiconductor substrate; An N-type region is formed in the P-type semiconductor substrate and is located below the P-type well region, wherein the P-type semiconductor substrate below the N-type region and the P-type well region are not in contact with each other due to the N-type region, and the P-type well region is an isolated P-type well region; The first nanowire; A first gate structure, comprising a first spacer, a second spacer, a first gate dielectric layer and a first gate layer; wherein the first gate dielectric layer surrounds the middle region of the first nanowire, the first gate layer surrounds the first gate dielectric layer, the first gate layer is electrically connected to the first word line, the first end of the first nanowire is surrounded by the first spacer, the second end of the first nanowire is surrounded by the second spacer, and the first spacer and the second spacer are located above the P-type well region; A first drain / source structure, located above the P-type well region, electrically contacting the first end of the first nanowire, and electrically connected to a first bit line; A second drain / source structure is located above the P-type well region and electrically contacts the second end of the first nanowire; wherein the first nanowire, the first gate structure, the first drain / source structure and the second drain / source structure form a first selection transistor; a second nanowire; A second gate structure, comprising a third spacer, a fourth spacer, a second gate dielectric layer and a second gate layer; wherein the second gate dielectric layer surrounds the middle region of the second nanowire, the second gate layer surrounds the second gate dielectric layer, the second gate layer is electrically connected to the first anti-fuse control line, the first end of the second nanowire is surrounded by the third spacer, the second end of the second nanowire is surrounded by the fourth spacer, and the third spacer and the fourth spacer are located above the P-type well region; A third drain / source structure, located above the P-type well region and electrically contacting the first end of the second nanowire, wherein the third drain / source structure is coupled to the second drain / source structure; and a fourth drain / source structure located above the P-type well region and electrically contacting the second end of the second nanowire, wherein the second nanowire, the second gate structure, the third drain / source structure and the fourth drain / source structure form a first anti-fuse transistor; Wherein, during the programming action, the P-type well region receives a negative programming voltage, the N-type region receives a first voltage, and the P-type semiconductor substrate receives a second voltage; there is a reverse bias voltage between the P-type well region and the N-type region; and there is the reverse bias voltage or zero bias voltage between the P-type semiconductor substrate and the N-type region; The first voltage is greater than or equal to the ground voltage, the second voltage is greater than or equal to the negative programming voltage, and the second voltage is less than or equal to the first voltage. 2 . The anti-fuse one-time programming memory as claimed in claim 1 , wherein the N-type region is a deep N-type well region or an N-type buried layer.

3. The anti-fuse one-time programming memory as described in claim 1, wherein during a read operation, the P-type well region receives the ground voltage, the N-type region receives the first voltage, and the P-type semiconductor substrate receives the second voltage; the reverse bias voltage or the zero bias voltage is between the P-type well region and the N-type region; and the reverse bias voltage or the zero bias voltage is between the P-type semiconductor substrate and the N-type region.

4. The anti-fuse one-time programming memory as claimed in claim 1, wherein the third drain / source structure is coupled to the second drain / source structure via a first switch transistor, and the first switch transistor comprises: The third nanowire; A third gate structure, comprising a fifth spacer, a sixth spacer, a third gate dielectric layer and a third gate layer; wherein the third gate dielectric layer surrounds the middle region of the third nanowire, the third gate layer surrounds the third gate dielectric layer, the third gate layer is electrically connected to the first wire, the first end of the third nanowire is surrounded by the fifth spacer, the second end of the third nanowire is surrounded by the sixth spacer, and the fifth spacer and the sixth spacer are located above the P-type well region; The second drain / source structure is located above the P-type well region and electrically contacts the first end of the third nanowire; and The third drain / source structure is located above the P-type well region and electrically contacts the second end of the third nanowire.

5. The anti-fuse one-time programming memory as claimed in claim 1, wherein the first memory cell further comprises a dummy transistor, the dummy transistor comprising: a fourth nanowire; A fourth gate structure, comprising a seventh spacer, an eighth spacer, a fourth gate dielectric layer and a fourth gate layer; wherein the fourth gate dielectric layer surrounds the middle region of the fourth nanowire, the fourth gate layer surrounds the fourth gate dielectric layer, the fourth gate layer is electrically connected to a dummy gate control line, a first end of the fourth nanowire is surrounded by the seventh spacer, a second end of the fourth nanowire is surrounded by the eighth spacer, and the seventh spacer and the eighth spacer are located above the P-type well region; The fourth drain / source structure is located above the P-type well region and electrically contacts the first end of the fourth nanowire; and a fifth drain / source structure, located above the P-type well region and electrically contacting the second end of the fourth nanowire; During the programming operation, the dummy control line receives a third voltage, and the third voltage is less than or equal to the negative programming voltage.

6. The anti-fuse one-time programming memory as described in claim 4, wherein during the programming action, the first bit line receives the negative programming voltage, the first anti-fuse control line receives the positive programming voltage, the first selection transistor and the first switch transistor are turned on, the total voltage stress borne on both sides of the first gate dielectric layer of the first anti-fuse transistor is the total programming voltage, and the total programming voltage is approximately equal to the positive programming voltage minus the negative programming voltage, so that the first gate dielectric layer is ruptured, and the first storage unit is changed from an unruptured state to a ruptured state.

7. The anti-fuse one-time programming memory according to claim 4, further comprising: A second storage unit, wherein the second storage unit comprises: a fourth nanowire, wherein the first drain / source structure is electrically in contact with a first end of the fourth nanowire; A fourth gate structure, comprising a seventh spacer, an eighth spacer, a fourth gate dielectric layer and a fourth gate layer; wherein the fourth gate dielectric layer surrounds the middle region of the fourth nanowire, the fourth gate layer surrounds the fourth gate dielectric layer, the fourth gate layer is electrically connected to the second word line, the first end of the fourth nanowire is surrounded by the seventh spacer, the second end of the fourth nanowire is surrounded by the eighth spacer, and the seventh spacer and the eighth spacer are located above the P-type well region; a fifth drain / source structure, located above the P-type well region and electrically contacting the second end of the fourth nanowire; wherein the fourth nanowire, the fourth gate structure, the first drain / source structure and the fifth drain / source structure form a second selection transistor; a fifth nanowire, wherein the fifth drain / source structure is electrically contacted to the first end of the fifth nanowire; A fifth gate structure, comprising a ninth spacer, a tenth spacer, a fifth gate dielectric layer and a fifth gate layer; wherein the fifth gate dielectric layer surrounds the middle region of the fifth nanowire, the fifth gate layer surrounds the fifth gate dielectric layer, the fifth gate layer is electrically connected to the second wire, the first end of the fifth nanowire is surrounded by the ninth spacer, the second end of the fifth nanowire is surrounded by the tenth spacer, and the ninth spacer and the tenth spacer are located above the P-type well region; a sixth drain / source structure, located above the P-type well region and electrically contacting the second end of the fifth nanowire; wherein the fifth nanowire, the fifth gate structure, the fifth drain / source structure and the sixth drain / source structure form a second switch transistor; a sixth nanowire, wherein the sixth drain / source structure is electrically in contact with the first end of the sixth nanowire; A sixth gate structure, comprising an eleventh spacer, a twelfth spacer, a sixth gate dielectric layer and a sixth gate layer; wherein the sixth gate dielectric layer surrounds the middle region of the sixth nanowire, the sixth gate layer surrounds the sixth gate dielectric layer, the sixth gate layer is electrically connected to a second anti-fuse control line, the first end of the sixth nanowire is surrounded by the eleventh spacer, the second end of the sixth nanowire is surrounded by the twelfth spacer, and the eleventh spacer and the twelfth spacer are located above the P-type well region; and The seventh drain / source structure is located above the P-type well region and electrically contacts the second end of the sixth nanowire; wherein the sixth nanowire, the sixth gate structure, the sixth drain / source structure and the seventh drain / source structure form a second anti-fuse transistor.

8. The anti-fuse one-time programming memory according to claim 7, further comprising: A third storage unit, and the third storage unit includes: Seventh nanowire; A seventh gate structure, comprising the first spacer, the second spacer, a seventh gate dielectric layer and the first gate layer; wherein the seventh gate dielectric layer surrounds the middle region of the seventh nanowire, the first gate layer surrounds the seventh gate dielectric layer, the first end of the seventh nanowire is surrounded by the first spacer, and the second end of the seventh nanowire is surrounded by the second spacer; an eighth drain / source structure, located above the P-type well region, electrically contacting the first end of the seventh nanowire, and electrically connected to the second bit line; a ninth drain / source structure, located above the P-type well region and electrically contacting the second end of the seventh nanowire; wherein the seventh nanowire, the seventh gate structure, the eighth drain / source structure and the ninth drain / source structure form a third selection transistor; an eighth nanowire, wherein the ninth drain / source structure is electrically in contact with the first end of the eighth nanowire; an eighth gate structure, comprising the fifth spacer, the sixth spacer, an eighth gate dielectric layer and the third gate layer; wherein the eighth gate dielectric layer surrounds the middle region of the eighth nanowire, the third gate layer surrounds the eighth gate dielectric layer, the first end of the eighth nanowire is surrounded by the fifth spacer, and the second end of the eighth nanowire is surrounded by the sixth spacer; a tenth drain / source structure, located above the P-type well region, and electrically contacting the second end of the eighth nanowire; wherein the eighth nanowire, the eighth gate structure, the ninth drain / source structure, and the tenth drain / source structure form a third switch transistor; a ninth nanowire, wherein the tenth drain / source structure is electrically in contact with the first end of the ninth nanowire; a ninth gate structure, comprising the third spacer, the fourth spacer, a ninth gate dielectric layer and the second gate layer; wherein the ninth gate dielectric layer surrounds the middle region of the ninth nanowire, the second gate layer surrounds the ninth gate dielectric layer, the first end of the ninth nanowire is surrounded by the third spacer, and the second end of the ninth nanowire is surrounded by the fourth spacer; and The eleventh drain / source structure is located above the P-type well region and electrically contacts the second end of the ninth nanowire; wherein the ninth nanowire, the ninth gate structure, the tenth drain / source structure and the eleventh drain / source structure form a third anti-fuse transistor. 9 . The anti-fuse one-time programming memory as claimed in claim 7 , wherein the first conductive line is connected to the first word line, and the second conductive line is connected to the second word line.

10. An anti-fuse one-time programming memory as described in claim 9, wherein during the programming action, the first word line receives a third voltage, the second word line receives the negative programming voltage, the first anti-fuse control line receives a positive programming voltage, the second anti-fuse control line receives a fourth voltage, the first bit line receives the negative programming voltage, and the second bit line receives the third voltage; the third voltage is less than or equal to a supply voltage, and the third voltage is greater than or equal to -1V; the fourth voltage is greater than or equal to the negative programming voltage, and the fourth voltage is less than or equal to the ground voltage; and, during the reading action, the third storage cell is a non-selected storage cell, and the second bit line receives the supply voltage.

11. The anti-fuse one-time programming memory as claimed in claim 7, wherein the first conductive line and the second conductive line serve as follower lines respectively.

12. An anti-fuse one-time programming memory as described in claim 11, wherein during the programming action, the first word line receives a third voltage, the second word line receives the negative programming voltage, the first anti-fuse control line receives a positive programming voltage, the second anti-fuse control line receives a fourth voltage, the first bit line receives the negative programming voltage, and the second bit line receives the third voltage, and the follower line receives a follower voltage; the third voltage is less than or equal to the supply voltage, and the third voltage is greater than or equal to -1V; the fourth voltage is greater than or equal to the negative programming voltage, and the fourth voltage is less than or equal to the ground voltage; and the supply voltage is greater than or equal to 0.4V, and the supply voltage is less than or equal to 1.6V; the follower voltage is greater than or equal to the ground voltage, and the follower voltage is less than or equal to 1.5V.

13. The anti-fuse one-time programming memory as claimed in claim 4, wherein the first storage unit further comprises: a fourth nanowire, wherein the fourth drain / source structure is electrically contacted with the first end of the fourth nanowire; A fourth gate structure, comprising a seventh spacer, an eighth spacer, a fourth gate dielectric layer and a fourth gate layer; wherein the fourth gate dielectric layer surrounds the middle region of the fourth nanowire, the fourth gate layer surrounds the fourth gate dielectric layer, the fourth gate layer is electrically connected to the first wire, the first end of the fourth nanowire is surrounded by the seventh spacer, the second end of the fourth nanowire is surrounded by the eighth spacer, and the seventh spacer and the eighth spacer are located above the P-type well region; a fifth drain / source structure, located above the P-type well region and electrically contacting the second end of the fourth nanowire; wherein the fourth nanowire, the fourth gate structure, the fourth drain / source structure and the fifth drain / source structure form a second switch transistor; a fifth nanowire, wherein the fifth drain / source structure is electrically contacted to the first end of the fifth nanowire; a fifth gate structure, comprising a ninth spacer, a tenth spacer, a fifth gate dielectric layer and a fifth gate layer; wherein the fifth gate dielectric layer surrounds the middle region of the fifth nanowire, the fifth gate layer surrounds the fifth gate dielectric layer, the fifth gate layer is electrically connected to the first word line, the first end of the fifth nanowire is surrounded by the ninth spacer, the second end of the fifth nanowire is surrounded by the tenth spacer, and the ninth spacer and the tenth spacer are located above the P-type well region; and The sixth drain / source structure is located above the P-type well region, electrically contacts the second end of the fifth nanowire, and is electrically connected to the first bit line; wherein the fifth nanowire, the fifth gate structure, the fifth drain / source structure and the sixth drain / source structure form a second selection transistor.

14. The anti-fuse one-time programming memory according to claim 13, further comprising a second storage unit, the second storage unit comprising: a sixth nanowire, wherein the first drain / source structure is electrically in contact with a first end of the sixth nanowire; A sixth gate structure, comprising an eleventh spacer, a twelfth spacer, a sixth gate dielectric layer and a sixth gate layer; wherein the sixth gate dielectric layer surrounds the middle region of the sixth nanowire, the sixth gate layer surrounds the sixth gate dielectric layer, the sixth gate layer is electrically connected to the second word line, the first end of the sixth nanowire is surrounded by the eleventh spacer, the second end of the sixth nanowire is surrounded by the twelfth spacer, and the eleventh spacer and the twelfth spacer are located above the P-type well region; a seventh drain / source structure, located above the P-type well region and electrically contacting the second end of the sixth nanowire; wherein the sixth nanowire, the sixth gate structure, the first drain / source structure and the seventh drain / source structure form a third selection transistor; a seventh nanowire, wherein the seventh drain / source structure is electrically in contact with the first end of the seventh nanowire; A seventh gate structure, comprising a thirteenth spacer, a fourteenth spacer, a seventh gate dielectric layer and a seventh gate layer; wherein the seventh gate dielectric layer surrounds the middle region of the seventh nanowire, the seventh gate layer surrounds the seventh gate dielectric layer, the seventh gate layer is electrically connected to the second wire, the first end of the seventh nanowire is surrounded by the thirteenth spacer, the second end of the seventh nanowire is surrounded by the fourteenth spacer, and the thirteenth spacer and the fourteenth spacer are located above the P-type well region; an eighth drain / source structure, located above the P-type well region, and electrically contacting the second end of the seventh nanowire; wherein the seventh nanowire, the seventh gate structure, the seventh drain / source structure and the eighth drain / source structure form a third switch transistor; an eighth nanowire, wherein the eighth drain / source structure is electrically in contact with the first end of the eighth nanowire; An eighth gate structure, comprising a fifteenth spacer, a sixteenth spacer, an eighth gate dielectric layer and an eighth gate layer; wherein the eighth gate dielectric layer surrounds the middle region of the eighth nanowire, the eighth gate layer surrounds the eighth gate dielectric layer, the eighth gate layer is electrically connected to the second anti-fuse control line, the first end of the eighth nanowire is surrounded by the fifteenth spacer, the second end of the eighth nanowire is surrounded by the sixteenth spacer, and the fifteenth spacer and the sixteenth spacer are located above the P-type well region; The ninth drain / source structure is located above the P-type well region and electrically contacts the second end of the eighth nanowire; wherein the eighth nanowire, the eighth gate structure, the eighth drain / source structure and the ninth drain / source structure form a second anti-fuse transistor; a ninth nanowire, wherein the ninth drain / source structure is electrically in contact with the first end of the ninth nanowire; A ninth gate structure, comprising a seventeenth spacer, an eighteenth spacer, a ninth gate dielectric layer and a ninth gate layer; wherein the ninth gate dielectric layer surrounds the middle region of the ninth nanowire, the ninth gate layer surrounds the ninth gate dielectric layer, the ninth gate layer is electrically connected to the second wire, the first end of the ninth nanowire is surrounded by the seventeenth spacer, the second end of the ninth nanowire is surrounded by the eighteenth spacer, and the seventeenth spacer and the eighteenth spacer are located above the P-type well region; a tenth drain / source structure, located above the P-type well region and electrically contacting the second end of the ninth nanowire; wherein the ninth nanowire, the ninth gate structure, the ninth drain / source structure and the tenth drain / source structure form a fourth switch transistor; a tenth nanowire, wherein the tenth drain / source structure is electrically in contact with the first end of the tenth nanowire; a tenth gate structure, comprising a nineteenth spacer, a twentieth spacer, a tenth gate dielectric layer and a tenth gate layer; wherein the tenth gate dielectric layer surrounds the middle region of the tenth nanowire, the tenth gate layer surrounds the tenth gate dielectric layer, the tenth gate layer is electrically connected to the second word line, the first end of the tenth nanowire is surrounded by the nineteenth spacer, the second end of the tenth nanowire is surrounded by the twentieth spacer, and the nineteenth spacer and the twentieth spacer are located above the P-type well region; and The eleventh drain / source structure is located above the P-type well region, electrically contacts the second end of the tenth nanowire, and is electrically connected to the first bit line; wherein the tenth nanowire, the tenth gate structure, the tenth drain / source structure and the eleventh drain / source structure form a fourth selection transistor.

15. The anti-fuse one-time programming memory according to claim 14, further comprising a third storage unit, the third storage unit comprising: eleventh nanowire; An eleventh gate structure, comprising the first spacer, the second spacer, an eleventh gate dielectric layer and the first gate layer; wherein the eleventh gate dielectric layer surrounds the middle region of the eleventh nanowire, the first gate layer surrounds the eleventh gate dielectric layer, the first end of the eleventh nanowire is surrounded by the first spacer, and the second end of the eleventh nanowire is surrounded by the second spacer; a twelfth drain / source structure, located above the P-type well region, electrically contacting the first end of the eleventh nanowire, and electrically connected to a second bit line; a thirteenth drain / source structure located above the P-type well region and electrically contacting the second end of the eleventh nanowire; wherein the eleventh nanowire, the eleventh gate structure, the twelfth drain / source structure and the thirteenth drain / source structure form a fifth selection transistor; A twelfth nanowire, wherein the thirteenth drain / source structure is electrically in contact with a first end of the twelfth nanowire; A twelfth gate structure, comprising the fifth spacer, the sixth spacer, a twelfth gate dielectric layer and the third gate layer; wherein the twelfth gate dielectric layer surrounds the middle region of the twelfth nanowire, the third gate layer surrounds the twelfth gate dielectric layer, the first end of the twelfth nanowire is surrounded by the fifth spacer, and the second end of the twelfth nanowire is surrounded by the sixth spacer; a fourteenth drain / source structure, located above the P-type well region, and electrically contacting the second end of the twelfth nanowire; wherein the twelfth nanowire, the twelfth gate structure, the thirteenth drain / source structure, and the fourteenth drain / source structure form a fifth switch transistor; A thirteenth nanowire, wherein the fourteenth drain / source structure is electrically in contact with the first end of the thirteenth nanowire; A thirteenth gate structure, comprising the third spacer, the fourth spacer, a thirteenth gate dielectric layer and the second gate layer; wherein the thirteenth gate dielectric layer surrounds the middle region of the thirteenth nanowire, the second gate layer surrounds the thirteenth gate dielectric layer, the first end of the thirteenth nanowire is surrounded by the third spacer, and the second end of the thirteenth nanowire is surrounded by the fourth spacer; a fifteenth drain / source structure, located above the P-type well region, and electrically contacting the second end of the thirteenth nanowire; wherein the thirteenth nanowire, the thirteenth gate structure, the fourteenth drain / source structure, and the fifteenth drain / source structure form a third anti-fuse transistor; A fourteenth nanowire, wherein the fifteenth drain / source structure is electrically in contact with a first end of the fourteenth nanowire; A fourteenth gate structure, comprising the seventh spacer, the eighth spacer, a fourteenth gate dielectric layer and the fourth gate layer; wherein the fourteenth gate dielectric layer surrounds the middle region of the fourteenth nanowire, the fourth gate layer surrounds the fourteenth gate dielectric layer, the first end of the fourteenth nanowire is surrounded by the seventh spacer, and the second end of the fourteenth nanowire is surrounded by the eighth spacer; a sixteenth drain / source structure, located above the P-type well region, and electrically contacting the second end of the fourteenth nanowire; wherein the fourteenth nanowire, the fourteenth gate structure, the fifteenth drain / source structure, and the sixteenth drain / source structure form a sixth switch transistor; A fifteenth nanowire, wherein the sixteenth drain / source structure is electrically in contact with a first end of the fifteenth nanowire; A fifteenth gate structure, comprising the ninth spacer, the tenth spacer, a fifteenth gate dielectric layer and the fifth gate layer; wherein the fifteenth gate dielectric layer surrounds the middle region of the fifteenth nanowire, the fifth gate layer surrounds the fifteenth gate dielectric layer, the first end of the fifteenth nanowire is surrounded by the ninth spacer, and the second end of the fifteenth nanowire is surrounded by the tenth spacer; and The seventeenth drain / source structure is located above the P-type well region, electrically contacts the second end of the fifteenth nanowire, and is electrically connected to the second bit line; wherein the fifteenth nanowire, the fifteenth gate structure, the sixteenth drain / source structure and the seventeenth drain / source structure form a sixth selection transistor. 16 . The anti-fuse one-time programming memory as claimed in claim 15 , wherein the first conductive line is connected to the first word line, and the second conductive line is connected to the second word line.

17. The anti-fuse one-time programming memory as claimed in claim 16, wherein during the programming operation, the first word line receives a third voltage, the second word line receives the negative programming voltage, the first anti-fuse control line receives a positive programming voltage, the second anti-fuse control line receives a fourth voltage, the first bit line receives the negative programming voltage, and the second bit line receives the third voltage; the third voltage is less than or equal to the supply voltage, and the third voltage is greater than or equal to -1V; The fourth voltage is greater than or equal to the negative programming voltage, and the fourth voltage is less than or equal to the ground voltage; Furthermore, the supply voltage is greater than or equal to 0.4V, and the supply voltage is less than or equal to 1.6V.

18. The anti-fuse one-time programming memory as claimed in claim 15, wherein the first conductive line and the second conductive line serve as follower lines respectively.

19. An anti-fuse one-time programming memory as described in claim 18, wherein during the programming action, the first word line receives a third voltage, the second word line receives the negative programming voltage, the first anti-fuse control line receives a positive programming voltage, the second anti-fuse control line receives a fourth voltage, the first bit line receives the negative programming voltage, and the second bit line receives the third voltage, and the follower line receives a follower voltage; the third voltage is less than or equal to the supply voltage, and the third voltage is greater than or equal to -1V; the fourth voltage is greater than or equal to the negative programming voltage, and the fourth voltage is less than or equal to the ground voltage; and the supply voltage is greater than or equal to 0.4V, and the supply voltage is less than or equal to 1.6V; the follower voltage is greater than or equal to the ground voltage, and the follower voltage is less than or equal to 1.5V.

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