Microelectronic devices and memory devices including vertically spaced transistors and memory devices, and related electronic systems

Abstract

The invention relates to microelectronic devices and memory devices including vertically spaced transistors and memory devices, and related electronic systems. A microelectronic device includes a first die and a second die vertically overlying and attached to the first die. The first die includes an array region and a peripheral region horizontally adjacent to the array region. The array region includes memory cells each including a first transistor structure, a second transistor structure horizontally adjacent to the first transistor structure, and a memory device vertically underlying and coupled to the first transistor structure and the second transistor structure. The peripheral region includes sub-word line driver circuitry. The second die includes sense amplifier regions and CMOS regions horizontally adjacent some of the sense amplifier regions. The sense amplifier region is within a horizontal region of the array region of the first die and includes sense amplifier circuitry.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. patent application serial number 63 / 520,060, filed on August 16, 2023, entitled “MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING VERTICALLY SPACED TRANSISTORS AND STORAGE DEVICES, AND RELATED ELECTRONIC SYSTEMS” and also claims the benefit of the filing date of U.S. patent application serial number 18 / 754,884, filed on June 26, 2024, entitled “MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING VERTICALLY SPACED TRANSISTORS AND STORAGE DEVICES, AND RELATED ELECTRONIC SYSTEMS”. Technical Field

[0003] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to microelectronic devices including memory cells that individually include vertically spaced transistors and storage devices and related memory devices and electronic systems. Background Art

[0004] Microelectronic device designers generally desire to increase the integration or density of features within a microelectronic device by reducing the size of individual features and by reducing the spacing distance between adjacent features. In addition, microelectronic device designers generally seek to design architectures that are not only small but also provide performance advantages and simplified design.

[0005] One example of a semiconductor device is a memory device. A memory device is typically provided as an internal integrated circuit in a computer or other electronic device. There are many types of memory, including, but not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, and resistance variable memory. Non-limiting examples of resistance variable memory include resistance random access memory (RRAM), conductive bridging random access memory (conductive bridging RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin torque transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.

[0006] A typical memory cell of a memory device includes one access device (e.g., a transistor) and one memory storage structure (e.g., a capacitor). Modern applications of semiconductor devices may employ a significant number of memory cells arranged in a memory array showing rows and columns of memory cells. The memory cells may be electrically accessed by digit lines (e.g., bit lines, data lines) and word lines (e.g., access lines) arranged along the rows and columns of memory cells of the memory array. The memory array may be two-dimensional (2D) so as to show a single level (e.g., a single level, a single tier) of memory cells, or may be three-dimensional (3D) so as to show multiple levels (e.g., multiple levels, multiple tiers) of memory cells.

[0007] In order to improve the operating parameters of the memory cell, some have formed a so-called 2-transistor 1-capacitor memory cell in which the memory device is connected to two transistors, and some have desired to increase the capacitance of the memory device. However, increasing the number of transistors per memory cell undesirably increases the area occupied by the memory cell and reduces the packing density of the memory cells of the array. In addition, increasing the capacitance of the memory device increases the area occupied by the memory cell. Summary of the invention

[0008] In some embodiments, a microelectronic device includes a first die and a second die vertically overlying and attached to the first die. The first die includes an array area and a peripheral area horizontally adjacent to the array area. The array area includes memory cells, which respectively include a first transistor structure, a second transistor structure horizontally adjacent to the first transistor structure, and a storage device vertically underlying and coupled to the first transistor structure and the second transistor structure. The peripheral area includes a sub-word line driver circuit system configured to implement control operations on the memory cells. The second die includes a sense amplifier area and a CMOS area horizontally adjacent to some of the sense amplifier areas. The sense amplifier area is within a horizontal region of the array area of ​​the first die and includes a sense amplifier circuit system configured to implement additional control operations on the memory cells. The CMOS area is horizontally adjacent to some of the sense amplifier areas and includes a CMOS circuit system configured to implement additional control operations on the memory cells.

[0009] In an additional embodiment, a memory device includes a first microelectronic device structure and a second microelectronic device structure joined to the first microelectronic device structure. The first microelectronic device structure includes a memory cell array, each of the memory cells of the memory cell array respectively including: a transistor including four vertically stacked channel regions; an additional transistor including four additional vertically stacked channel regions; and a capacitor vertically overlying the first transistor and the second transistor and electrically communicating with each of the transistor and the additional transistor. The first microelectronic device structure further includes a peripheral region horizontally adjacent to the memory cell array and including a sub-word line driver (SWD) circuit, the SWD circuit individually including another transistor including four additional vertically stacked channel regions. The second microelectronic device structure includes a sense amplifier (SA) circuit vertically overlying the memory cell array and within a horizontal boundary of the memory cell array.

[0010] In another embodiment, an electronic system includes: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device. The memory device includes a first die and a second die vertically overlying the first die. The first die includes a memory cell and a sub-word line driver (SWD) circuit coupled to the memory cell. The memory cell includes two transistors vertically overlapping each other and horizontally adjacent to each other and a capacitor vertically underlying and coupled to the two transistors. Each of the two transistors includes a plurality of channel regions and a plurality of gate electrodes vertically adjacent to the plurality of channel regions. The SWD circuit is within a peripheral region horizontally adjacent to an array region. Each of the SWD circuits including additional transistors includes a plurality of additional channel regions and a plurality of additional gate electrodes vertically adjacent to the plurality of additional channel regions. The second die includes a sense amplifier (SA) circuit coupled to the memory cell and within a horizontal region of the array region. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A to Figure 1M is a simplified partial top view illustrating a method of forming a first microelectronic device structure according to an embodiment of the present disclosure ( Figure 1A and Figure 1D ), simplified vertical cross-section diagram ( Figure 1B , Figure 1C , Figure 1E to Figure 1I , Figure 1L and Figure 1M ), simplified electrical schematics ( Figure 1J ) and simplified horizontal cross-section diagram of part ( Figure 1K );

[0012] Figure 2A to Figure 2G is a simplified partial top view illustrating a method of forming a second microelectronic device structure according to an embodiment of the present disclosure ( Figure 2A ) and simplified vertical cross-section diagram ( Figure 2B to Figure 2G );

[0013] FIG. 3A to FIG. 3F is a simplified partial vertical cross-sectional view illustrating a method of forming a microelectronic device from a first microelectronic device structure and a second microelectronic device structure; and

[0014] Figure 4 is a block diagram of an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] The illustrations included with this document are not meant to be actual diagrams of any particular system, microelectronic structure, microelectronic device, or integrated circuit thereof, but are merely idealized representations used to describe the embodiments herein. Common elements and features between the figures may retain the same numerical designation, but only for ease of following the description, the reference number begins with the number of the figure on which the element is introduced or most completely described.

[0016] The following description provides specific details such as material type, material thickness, and processing conditions in order to provide a detailed description of the embodiments described herein. However, it should be understood by those skilled in the art that the embodiments disclosed herein can be practiced without adopting these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. In addition, the description provided herein does not form a complete process flow for manufacturing microelectronic devices (e.g., semiconductor devices, memory devices, such as DRAM memory devices), equipment, memory devices, or electronic systems, or a complete microelectronic device, device, memory device, or electronic system including a conductive contact structure. The structure described below does not form a complete microelectronic device, device, memory device, or electronic system. Only those process actions and structures required to understand the embodiments described herein are described in detail below. Additional actions for forming a complete microelectronic device, device, memory device, or electronic system from a structure can be performed by conventional techniques.

[0017] The drawings presented herein are for illustration only and do not imply actual drawings of any particular material, component, structure, device, or system. Changes in the shapes depicted in the drawings due to, for example, manufacturing techniques and / or tolerances may be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or regions described, but rather include shape deviations due to, for example, manufacturing. For example, a region described or described as a frame may have rough and / or nonlinear features, and a region described or described as a circle may include some rough and / or linear features. In addition, the sharp angles described may be rounded, and vice versa. Therefore, the regions described in the figures are schematic and their shapes do not wish to illustrate the precise shape of the regions and do not limit the scope of the claims of the present invention. The drawings are not necessarily drawn to scale. In addition, common elements between the figures may retain the same numerical symbols.

[0018] As used herein, the term "memory device" means and includes a microelectronic device that exhibits memory functionality but is not necessarily limited to memory functionality. In other words and by way of example only, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application specific integrated circuits (ASICs) such as single chip systems (SoCs), microelectronic devices combining logic and memory, and graphics processing units (GPUs) incorporating memory.

[0019] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of one or more of the structure and device in a predetermined manner.

[0020] As used herein, the terms "vertical," "longitudinal," "horizontal," and "lateral" are referenced to a principal plane of a structure and are not necessarily defined by the earth's gravitational field. A "horizontal" or "lateral" direction is a direction substantially parallel to a principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to a principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively larger area than other surfaces of the structure. With reference to the figures, a "horizontal" or "lateral" direction may be perpendicular to the indicated "Z" axis and may be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; and a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, may be perpendicular to the indicated "X" axis, and may be perpendicular to the indicated "Y" axis.

[0021] As used herein, features (e.g., regions, materials, structures, devices) described as being "adjacent" to each other mean and include features of one (or several) disclosed entities that are positioned closest (e.g., closest) to each other. Additional features (e.g., additional regions, additional materials, additional structures, additional devices) of one (or several) disclosed entities that do not match the "adjacent" features may be disposed between the "adjacent" features.

[0022] As used herein, for ease of description, spatially relative terms (e.g., "below," "beneath," "bottom," "above," "up," "top," "front," "rear," "left," "right," and the like) may be used to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the figures. For example, if the material in the figure is reversed, an element described as being "below" or "beneath" or "under" or "on the bottom" of other elements or features would be oriented to be "above" or "on the top" of the other elements or features. Thus, one of ordinary skill in the art would understand that the term "below" may encompass both above and below orientations, depending on the context in which the term is used. The material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped, etc.) and the spatially relative descriptors used herein interpreted accordingly.

[0023] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0024] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] As used herein, the phrase "coupled to" refers to structures being operatively connected to each other, such as electrically connected through a direct ohmic connection or through an indirect connection (such as through another structure).

[0026] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition is satisfied within a certain degree of variation (e.g., within an acceptable tolerance) as understood by one of ordinary skill in the art. For example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied by at least 90.0%, satisfied by at least 95.0%, satisfied by at least 99.0%, satisfied by at least 99.9%, or even satisfied by 100%.

[0027] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes the numerical value and the degree of variation of the numerical value within an acceptable tolerance for the particular parameter as understood by one of ordinary skill in the art. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​within a range from 90.0% to 110.0% of the numerical value, such as within a range from 95.0% to 105.0% of the numerical value, within a range from 97.5% to 102.5% of the numerical value, within a range from 99.0% to 101.0% of the numerical value, within a range from 99.5% to 100.5% of the numerical value, or within a range from 99.9% to 100.1% of the numerical value.

[0028] A chemical formula (e.g., SiO x 、AlO x , HfO x 、NbO x 、TiO x 、SiN y 、SiO x N y 、SiO x C z N y ) represents a material containing an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since the chemical formula represents relative atomic ratios rather than absolute chemical structures, the insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds having elemental compositions that cannot be represented by well-defined natural number ratios and that violate the law of definite proportions. In addition, an "insulating structure" means and includes a structure formed of and including an insulating material.

[0029] Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth.

[0030] According to embodiments described herein, a microelectronic device includes a first microelectronic device structure (e.g., a first die) attached to a second microelectronic device structure. The first microelectronic device structure includes an array region including memory cells, each memory cell including a pair of transistor structures that are operably connected to a storage device (e.g., a capacitor) vertically overlying the pair of transistor structures. Since the memory cell includes two transistor structures and one storage device, it may include and is referred to herein as a 2-transistor 1-capacitor (2T-1C) memory cell. The first microelectronic device structure further includes a peripheral region horizontally adjacent to the array region. The peripheral region includes a sub-word line driver (SWD) circuit system configured to implement control operations of memory cells of the memory cell array. The second microelectronic device structure may vertically overlie the first microelectronic device structure and include a sense amplifier (SA) region, the SA region including sense amplifier circuits configured to implement control operations of memory cells of the memory array. The sense amplifier region may vertically overlie the array region and be positioned within the horizontal boundary of the array region. The second microelectronic device structure may further include an additional complementary metal oxide semiconductor (CMOS) region including CMOS circuitry configured for implementing control operations of the memory cells of the memory array, the additional CMOS region being horizontally offset from the memory array region and positioned within a horizontal boundary of the peripheral region.

[0031] Forming a microelectronic device to include a first microelectronic device structure that includes memory cells and sub-word line driver circuitry and a second microelectronic device structure vertically overlying the first microelectronic device structure and including a sense amplifier region and additional CMOS circuitry facilitates forming a microelectronic device to include a greater density of memory cells in a relatively small horizontal area (e.g., a horizontal footprint) than conventional microelectronic devices.

[0032] Figure 1A to Figure 1L 1 is a diagram illustrating various views of a microelectronic device structure at different processing stages of a method of forming a microelectronic device (e.g., a memory device, such as a DRAM memory device) according to an embodiment of the present disclosure (described in more detail below). From the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods described herein can be used to form a variety of devices. In other words, the methods of the present disclosure can be used whenever it is desired to form a microelectronic device.

[0033] Figure 1A is a simplified partial top view of a first microelectronic device structure 100 (also referred to herein as a "first die") according to an embodiment of the present disclosure. Figure 1B is through Figure 1A A simplified partial vertical cross-sectional view of the first microelectronic device structure 100 taken along section line BB. Figure 1A and Figure 1B, the first microelectronic device structure 100 includes an array region 101 and a peripheral region 103 horizontally adjacent (eg, in the X direction) to the array region 101. In some embodiments, the array region 101 is horizontally positioned between two (2) adjacent peripheral regions 103 (eg, in the X direction).

[0034] In the array region 101, the first microelectronic device structure 100 includes an active region 105 ( Figure 1A ), which are separated from each other by a first trench 107 extending in a first horizontal direction (e.g., in the X direction) and including a first insulating material 110 and a second trench 109 extending in a second horizontal direction (e.g., in the Y direction) and including the first insulating material 110. The active regions 105 may be separated from each other by the first trench 107 and the second trench 109. Figure 1A In the view, it should be understood that the Z axis is the direction of entry and exit of the page view.

[0035] although Figure 1A Only twenty-four (24) active areas 105 are illustrated, but the disclosure is not so limited. It should be understood that the array area 101 includes a greater number of active areas 105, such as greater than 1 million active areas 105, greater than 10 million active areas 105, or greater than 1 billion active areas 105.

[0036] The first insulating material 110 may be formed of and include one or more of at least one insulating material, such as one or more of the following: at least one dielectric oxide material (such as one or more of the following: silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x )), at least one dielectric nitride material (e.g. silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )) and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO x C z N y In some embodiments, the first insulating material 110 is formed of a dielectric oxide material and includes a dielectric oxide material, such as SiO x (e.g. SiO2).

[0037] refer to Figure 1B , the first microelectronic device structure 100 includes a stacked structure 112 that includes a vertically alternating (eg, in the Z direction) sequence of a second insulating material 114 and a semiconductive material 116 arranged in a level 118 and vertically overlying (eg, in the Z direction) the first base structure 102 .

[0038] The stacked structure 112 may be formed to include any desired number of levels 118. By way of non-limiting example, the stacked structure 112 may be formed to include eight (8) levels 118. In other embodiments, the stacked structure 112 may be formed to include less than eight (8) levels 118, such as less than or equal to four (4) levels 118. In some embodiments, the stacked structure 112 is formed to include two (2) levels 118. As described in more detail herein, the number of levels 118 may correspond to the number of memory cells (e.g., memory cell 160 ( Fig. 1I )) of a transistor structure (e.g., transistor structure 142 ( Fig. 1I ))'s equivalent channel length.

[0039] The first base structure 102 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate including a semiconductive material. As used herein, the term "bulk substrate" means and includes not only a silicon substrate, but also a silicon-on-insulator (SOI) substrate, such as a silicon-on-sapphire (SOS) substrate and a silicon-on-glass (SOG) substrate, an epitaxial silicon layer on a base semiconductive pedestal, and other substrates formed of and including one or more semiconductive materials (e.g., one or more of the following: silicon material, such as single crystal silicon or polycrystalline silicon; silicon germanium; germanium; gallium arsenide; gallium nitride; and indium phosphide). In some embodiments, the first base structure 102 includes a silicon wafer.

[0040] The second insulating material 114 may be formed of and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 110. In some embodiments, the second insulating material 114 is formed of and includes a dielectric oxide material, such as SiO x (e.g. SiO2).

[0041] Semiconductive material 116 may be formed of and include at least one semiconductive material, such as silicon (e.g., single crystal silicon, polycrystalline silicon). In some embodiments, semiconductive material 116 is formed of and includes epitaxially grown silicon. In additional embodiments, semiconductive material 116 is formed of and includes single crystal silicon.

[0042] The third insulating material 120 may vertically overlie (e.g., in the Z direction) the stacked structure 112. The third insulating material 120 may be formed of an insulating material and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 110. In some embodiments, the third insulating material 120 is formed of a dielectric oxide material (e.g., SiO x , such as SiO2) and includes the dielectric oxide material.

[0043] Common Reference Figure 1A and Figure 1B , a vertical stack of channel regions 125 may be formed to extend vertically (e.g., in the Z direction) through the stack structure 112. The vertical stack of channel regions 125 may include vertically spaced (e.g., in the Z direction) channel regions 125, each of which is formed by and includes the semiconductive material 116.

[0044] In the horizontal region of the array region 101, the semiconductive material 116 may be doped with one or more conductivity enhancing species (eg, dopants) to form a channel region 125 ( Figure 1B ). In some embodiments, within the channel region 125, the semiconductive material 116 is doped with one or more N-type dopants, such as one or more of arsenic ions, phosphorus ions, and antimony ions. In other embodiments, within the channel region 125, one or more P-type dopants, such as one or more of boron ions, aluminum ions, and gallium ions, are doped. In some embodiments, each channel region 125 is horizontally positioned between the source region and the drain region of the semiconductive material 116 (e.g., in the X direction, in the Y direction).

[0045] The first conductive structures 126 (e.g., first conductive line structures, word lines, access lines) can vertically overlie (e.g., in the Z direction) and vertically underlie (e.g., in the Z direction) each of the channel regions 125 within the array region 101. In some embodiments, the channel regions 125 are vertically surrounded by the first conductive structures 126. Vertically adjacent (e.g., in the Z direction) first conductive structures 126 between vertically adjacent (e.g., in the Z direction) channel regions 125 can be spaced apart from each other by the fourth insulating material 128. Although the first conductive structures 126 vertically underlie (e.g., in the Z direction) the vertically uppermost (e.g., in the Z direction) surface of the first microelectronic device structure 100, the first conductive structures 126 are vertically disposed on the first microelectronic device structure 100. Figure 1A 1 to illustrate the relative horizontal position of the first conductive structure 126 relative to other features of the first microelectronic device structure 100. The first conductive structure 126 is Figure 1A Illustrated by dotted lines.

[0046] The first conductive structures 126 may be individually formed of and include conductive materials such as, for example, one or more of the following: metals (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), metal alloys, metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), titanium nitride (TiN y ), Tantalum Nitride (TaN y ), tungsten nitride (WN y ), titanium aluminum nitride (TiAl x N y ), iridium oxide (IrO x ), ruthenium oxide (RuO x ), a material of at least one of its alloys, a conductive doped semiconductor material (such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.), polysilicon, or other materials exhibiting conductivity.

[0047] The first conductive structure 126 may extend horizontally (e.g., substantially linearly horizontally) in a first horizontal direction (e.g., in the X direction) through the array region 101 and into the peripheral region 103 horizontally adjacent to the array region 101. The first conductive structure 126 may extend horizontally and parallelly in the first horizontal direction. In some embodiments, the first conductive structure 126 is used as a word line.

[0048] The first conductive structures 126 may collectively form a vertical stack structure 135 ( Figure 1A ). The vertical stacked structure 135 extends horizontally (e.g., in the X direction) from the peripheral region 103 and passes through the array region 101. The vertical stacked structure 135 includes levels of first conductive structures 126 that are vertically (e.g., in the Z direction) spaced apart from each other. In some embodiments, the vertical stacked structure 135 terminates horizontally (e.g., in the X direction) within a horizontal region of the peripheral region 103.

[0049] The fourth insulating material 128 may be formed of and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 110. In some embodiments, the fourth insulating material 128 is formed of and includes an oxide material, such as silicon dioxide.

[0050] refer to Figure 1B , each of the channel regions 125 is at least partially surrounded by a dielectric material 130 (which may also be referred to herein as a “gate dielectric material”). A portion of an individual first conductive structure 126 (e.g., a word line) that is directly vertically adjacent (e.g., in the Z direction) to the dielectric material 130 and positioned within a horizontal region of the dielectric material 130 may be referred to as a “gate electrode.” In some embodiments, the first conductive structure 126 is separated from the channel region 125 by the dielectric material 130.

[0051] The dielectric material 130 may be formed of and include an insulating material. By way of non-limiting example, the dielectric material 130 may be formed of and include one or more of phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, a nitride material such as silicon nitride (Si3N4), an oxynitride such as silicon oxynitride, another gate dielectric material, a dielectric carbon nitride material such as silicon carbon nitride (SiCN), or a dielectric carbon oxynitride material such as silicon oxycarbon nitride (SiOCN).

[0052] Vertically adjacent (eg, in the Z direction) channel regions 125 are spaced apart from each other by fifth insulating material 132. In some embodiments, fifth insulating material 132 surrounds at least a portion of dielectric material 130 and is horizontally interposed (eg, in the Y direction) between dielectric material 130 and second insulating material 114.

[0053] The fifth insulating material 132 may be formed of and include an insulating material having an etching selectivity with respect to the second insulating material 114. In some embodiments, the fifth insulating material 132 includes a dielectric nitride material (e.g., silicon nitride (Si3N4)) or a dielectric oxynitride material (e.g., silicon oxynitride). In some embodiments, the fifth insulating material 132 includes silicon nitride.

[0054] refer to Figure 1A and Figure 1B , a conductive pillar structure 136 (e.g., a digit line contact structure, a bit line contact structure) can extend vertically (e.g., in the Z direction) through the first microelectronic device structure 100 and horizontally adjacent (e.g., in the Y direction) to the level of the semiconductive material 116 and each of the dielectric material 130, the fourth insulating material 128, and the fifth insulating material 132. The conductive pillar structure 136 can be in electrical communication with the channel region 125. The conductive pillar structure 136 can be horizontally adjacent (e.g., in the Y direction) to the source region or the drain region of the semiconductive material 116. In some embodiments, the conductive pillar structure 136 is used as a digit line contact structure (e.g., a bit line contact structure, also referred to as a "BITCON" structure), as described in more detail below.

[0055] refer to Figure 1A and Figure 1B, the conductive pillar structures 136 may contact the sidewalls of the steps of the semiconductive material 116 and the sides of each of the dielectric material 130, the fourth insulating material 128, and the fifth insulating material 132. The conductive pillar structures 136 may individually contact the vertically stacked channel regions 125 of the channel regions 125. In use and operation, the conductive pillar structures 136 may be in electrical communication with the semiconductive material 116 to provide a voltage to the semiconductive material 116. The voltage may be applied from a conductive line structure (e.g., a digit line structure, a bit line structure) that is subsequently formed to be in operative communication with the corresponding conductive pillar structure 136, as described below with reference to Fig. 1I and 1J Describe in more detail.

[0056] The conductive pillar structures 136 may be formed of and include one or more conductive materials, such as one or more of the conductive materials previously described with reference to the first conductive structure 126. In some embodiments, portions of the individual conductive pillar structures 136 horizontally adjacent to the sidewalls of the step of semiconductive material 116 and the sides of each of the dielectric material 130, the fourth insulating material 128, and the fifth insulating material 132 are formed of and include conductively doped polysilicon, such as N+ doped polysilicon. In additional embodiments, the conductive pillar structures 136 do not include conductively doped polysilicon horizontally adjacent to the sidewalls of the step of semiconductive material 116 and the sides of each of the dielectric material 130, the fourth insulating material 128, and the fifth insulating material 132.

[0057] Figure 1C is Figure 1A and Figure 1B 1 is a simplified partial vertical cross-sectional view of a first microelectronic device structure 100 at a processing stage subsequent to the processing stage illustrated in FIG. Figure 1C A simplified partial vertical cross-section diagram is obtained by comparing Figure 1B The planes described in the reference are cut from the same planes, but Figure 1A and Figure 1B In a processing stage following the processing stage illustrated and described.

[0058] refer to Figure 1C , a masking material can be formed over the first microelectronic device structure 100, and portions of the vertically upper (e.g., in the Z direction) level 118 of the second insulating material 114 and the semiconductive material 116 of the channel region 125 can be removed. Removal of portions of the vertically upper (e.g., in the Z direction) level 118 of the second insulating material 114 and the level 118 of the semiconductive material 116 of the channel region 125 can form an upper channel region 125 having a relatively smaller horizontal dimension (e.g., in the Y direction) than the channel region 125 at the relatively vertically lower (e.g., in the Z direction) level 118.

[0059] A corresponding group of channel regions 125 vertically above (e.g., in the Z direction) (e.g., the vertically upper half of the vertically stacked channel regions 125) may form a first transistor structure 142A (also referred to herein as “upper transistor structure 142A”); and a corresponding group of channel regions 125 vertically below (e.g., in the Z direction) (e.g., the vertically lower half of the vertically stacked channel regions 125) may form a second transistor structure 142B (also referred to herein as “second transistor structure 142B”) vertically underlying (e.g., in the Z direction) the first transistor structure 142A. The first transistor structure 142A may be vertically above the second transistor structure 142B (e.g., in the Z direction). One of the first transistor structures 142A is Figure 1C and one of the second transistor structures 142B is in Figure 1C 142B. The first transistor structure 142A and the second transistor structure 142B are collectively referred to herein as "transistor structures 142". In some embodiments, the transistor structures 142 individually have one of a dual-gate (G2S) configuration, a triple-gate (G3S) configuration, and a gate-all-around (GAA) configuration, so that multiple boundaries of their respective channel regions 125 are at least partially covered (e.g., surrounded) by the first conductive structure 126.

[0060] Each of the first transistor structures 142A may include substantially the same number of channel regions 125 as each other of the first transistor structures 142A. Additionally, each of the second transistor structures 142B may include substantially the same number of channel regions 125 as each other of the second transistor structures 142B. Each first transistor structure 142A may include the same number of channel regions 125 as each second transistor structure 142B. In some embodiments, each of the first transistor structures 142A individually includes four (4) levels of channel regions 125; and each of the second transistor structures 142B individually includes four (4) levels of channel regions 125.

[0061] After removing portions of the vertically upper (e.g., in the Z direction) level 118 of the second insulating material 114 and the semiconductive material 116 to form a first transistor structure 142A having a relatively smaller horizontal dimension (e.g., in the Y direction) than the second transistor structure 142B, the opening may be filled with an insulating material, such as one or more of the materials described above with reference to the first insulating material 110. Since the opening is filled with the insulating material, which may be the same as the first insulating material 110, the insulating material filling the opening is Figure 1C is illustrated as being the same as the first insulating material 110 .

[0062] Figure 1D to Figure 1F Instructions in reference Figure 1C The first microelectronic device structure 100 is in a processing stage subsequent to the processing stage described. Figure 1D is a simplified partial top view of a first microelectronic device structure 100; Figure 1E is through Figure 1D A simplified partial vertical cross-sectional view of the first microelectronic device structure 100 along section line EE; and Figure 1F is through Figure 1D FF is a simplified partial vertical cross-sectional view of the first microelectronic device structure 100 taken along section line FF.

[0063] Common Reference Figure 1D and 1E After forming the first transistor structure 142A and the second transistor structure 142B, the first conductive contact structure 144 may be individually formed to extend vertically (e.g., in the Z direction) through at least a portion of the first microelectronic device structure 100, and the second conductive contact structure 146 may be individually formed to extend vertically (e.g., in the Z direction) through another portion of the first microelectronic device structure 100. Each first conductive contact structure 144 may respectively contact (e.g., electrically contact) one of the transistor structures 142, such as one of the first transistor structures 142A. Each second conductive contact structure 146 may respectively contact (e.g., electrically contact) an additional one of the transistor structures 142, such as one of the second transistor structures 142B. In some embodiments, the first conductive contact structure 144 contacts the first transistor structure 142A, and the second conductive contact structure 146 contacts the second transistor structure 142B. The first microelectronic device structure 100 may include an equal number of first conductive contact structures 144 and second conductive contact structures 146.

[0064] like Figure 1E , in some embodiments, the vertical upper (e.g., in the Z direction) surface of the first conductive contact structure 144 is vertically offset (e.g., in the Z direction) from the vertical upper (e.g., in the Z direction) surface of the second conductive contact structure 146. For example, the vertical upper surface of the second conductive contact structure 146 may vertically overlie (e.g., in the Z direction) the vertical upper surface of the first conductive contact structure 144.

[0065] refer to Figure 1E The first routing structure 148 may be formed to contact (e.g., electrically contact) the first conductive contact structure 144 that is in contact (e.g., electrically contact) with the first transistor structure 142A. In addition, the second routing structure 150 may be formed to contact (e.g., electrically contact) the second conductive contact structure 146 that is in contact (e.g., electrically contact) with the second transistor structure 142B.

[0066] The first routing structure 148 and the second routing structure 150 may be electrically insulated from each other by means of the seventh insulating material 152. The first routing structure 148 and the second routing structure 150 may be arranged within and covered by the seventh insulating material 152. The first routing structure 148 and the second routing structure 150 may be individually configured to reroute a corresponding one of the first conductive contact structure 144 and the second conductive contact structure 146 to a subsequently formed memory device (e.g., the memory device 158 ( Figure 1G The first routing structure 148 and the second routing structure 150 may also be referred to herein as a “redistribution layer (RDL)” structure or a “redistribution material (RDM)” structure.

[0067] like Figure 1D , a first group (e.g., a column) of the first conductive contact structures 144 may be formed to extend in parallel in the X direction, and a second group (e.g., a row) of the first conductive contact structures 144 may be formed to extend in parallel in the Y direction. Additionally, a first group (e.g., a column) of the second conductive contact structures 146 may be formed to extend in parallel in the X direction, and a second group (e.g., a row) of the second conductive contact structures 146 may be formed to extend in parallel in the Y direction. A respective first group (e.g., a column) of the first conductive contact structures 144 may horizontally overlap (e.g., substantially horizontally align) with a respective first group (e.g., a column) of the second conductive contact structures 146 in the X direction. Additionally, each second group (e.g., a row) of the first conductive contact structures 144 may be horizontally offset from a second group (e.g., a row) of the second conductive contact structures 146 in the Y direction. A respective first group of the first conductive contact structures 144 and a respective first group of the second conductive contact structures 146 may horizontally overlap (e.g., substantially horizontally align) with a respective first group (e.g., a column) of the conductive pillar structures 136.

[0068] In some embodiments, the first conductive contact structure 144 and the second conductive contact structure 146 are formed continuously relative to each other. Figure 1E, a first conductive contact structure 144 may be formed through a portion of the first microelectronic device structure 100, and then a first routing structure 148 may be formed to contact the first conductive contact structure 144. Thereafter, a second conductive contact structure 146 may be formed, and then a second routing structure 150 may be formed to contact the second conductive contact structure 146. After forming the first conductive contact structure 144 and the first routing structure 148, a seventh insulating material 152 may be formed vertically over the first conductive contact structure 144 and the first routing structure 148 (e.g., in the Z direction). After forming the seventh insulating material 152, a second conductive contact structure 146 may be formed through the seventh insulating material 152 and in contact with the channel region 125 of the second transistor structure 142B, and then a second routing structure 150 may be formed vertically over the second conductive contact structure 146 and in contact with the second conductive contact structure 146.

[0069] Each of the first conductive contact structure 144, the second conductive contact structure 146, the first routing structure 148, and the second routing structure 150 may be individually formed of and include a conductive material, such as one or more of the materials described above with reference to the conductive structure 126. In some embodiments, each of the first conductive contact structure 144, the second conductive contact structure 146, the first routing structure 148, and the second routing structure 150 individually includes a metal material, such as tungsten.

[0070] The seventh insulating material 152 may be formed of and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 110. In some embodiments, the seventh insulating material 152 is formed of and includes a dielectric oxide material, such as SiO x (e.g. SiO2).

[0071] refer to Figure 1F , the peripheral region 103 includes a stacked structure 112 of a layer 118 of a second insulating material 114 and a semiconductive material 116. The peripheral region 103 may include an additional vertical stacked structure 156 of conductive structures 126. The additional vertical stacked structure 156 may include a vertical stacked structure 135 ( Figure 1D ) has substantially the same number of levels of conductive structure 126.

[0072] In some embodiments, within the peripheral region 103, the third conductive contact structure 153 may be formed to contact (e.g., be electrically connected to) the conductive pillar structure 136; and the third routing structure 155 may be formed to contact (e.g., be electrically connected to) the third conductive contact structure 153. In use and operation, applying a voltage to the conductive pillar structure 136 that is in contact (e.g., electrically connected to) the channel region 125 of the additional vertical stack structure 156 may facilitate control operations of the transistor structure of the additional vertical stack structure 156.

[0073] Each of the third conductive contact structure 153 and the third routing structure 155 may be individually formed of and include a conductive material, such as one or more of the materials described above with reference to the conductive structure 126. In some embodiments, each of the third conductive contact structure 153 and the third routing structure 155 individually includes a metal material, such as tungsten.

[0074] As described in further detail herein, the additional vertical stacking structure 156 of the conductive structure 126 of the peripheral region 103 may include a conductive structure 156 for subsequent formation in the array region 101 ( Figure 1D ) within a memory cell (e.g., memory cell 160 ( Fig. 1I )) of the sub-word line driver (SWD). The conductive structure 126 of the additional vertical stacked structure 156 may be electrically connected to the memory cells in the array region 101. For example, the conductive structure 126 of the additional vertical stacked structure 156 may include the same conductive structure 126 of the array region 101, so that applying a voltage to the conductive structure 126 may induce a current in a channel region 125 in the peripheral region 103 and another channel region 125 in the array region 101. In some embodiments, the peripheral region 103 horizontally adjacent to the corresponding array region 101 (for example, in the X direction) includes a memory cell (for example, memory cell 160 ( Fig. 1I )) wherein each memory cell includes two (2) transistor structures 142 and a storage node structure (eg, capacitor) formed later. Since the peripheral region 103 includes the SWD circuitry, the peripheral region 103 may also be referred to herein as a SWD region.

[0075] Figure 1G is Figure 1D to Figure 1F 1 is a simplified partial vertical cross-sectional view of a first microelectronic device structure 100 at a processing stage subsequent to the processing stage illustrated in FIG. Figure 1G A simplified partial vertical cross-section diagram is obtained by comparing Figure 1E The cross-section diagram is taken from the same plane, but Figure 1E In a processing stage following the processing stage described in . Figure 1H is Figure 1D to Figure 1F 1 is a simplified partial vertical cross-sectional view of a first microelectronic device structure 100 at a processing stage subsequent to the processing stage illustrated in FIG. Figure 1H A simplified partial vertical cross-section diagram is obtained by comparing Figure 1F The cross-section diagram is taken from the same plane, but Figure 1F In a processing stage following the processing stage described in .

[0076] refer to Figure 1GAfter forming the first conductive contact structure 144, the second conductive contact structure 146, the first routing structure 148, and the second routing structure 150, a storage device 158 (eg, a capacitor) may be formed in the array region 101 ( Figure 1D ). The storage device 158 may be formed to vertically overlie (e.g., in the Z direction) the transistor structure 142, and may be electrically connected to the transistor structure 142 by means of the first routing structure 148 and the second routing structure 150. The storage device 158 and the transistor structure 142 together may form a memory cell 160. An individual memory cell 160 may include one (1) storage device 158 and two (2) transistor structures 142. Since the memory cells 160 each include two (2) transistor structures 142 and one (1) storage device 158, the memory cells 160 may be referred to herein as 2-transistor 1-capacitor (2T-1C) memory cells. One (1) memory cell 160 in Figure 1G This is illustrated by a dashed box 160 .

[0077] The storage devices 158 may individually include a first electrode 162 (also referred to herein as an "outer electrode", "first electrode plate" or "first node structure"), a second electrode 164 (also referred to herein as an "inner electrode", "second electrode plate" or "second node structure"), and a dielectric material 166 between the first electrode 162 and the second electrode 164. In some such embodiments, the storage devices 158 individually include capacitors. However, the present disclosure is not limited thereto and in other embodiments, the storage devices 158 may each individually include different storage node structures.

[0078] The first electrode 162 may be formed of a conductive material and include a conductive material such as, for example, one or more of the following: a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), a material including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), a material of at least one of their alloys, a conductive doped semiconductor material (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon germanium), polysilicon, or other materials exhibiting conductivity. In some embodiments, the first electrode 162 is formed of and includes titanium nitride.

[0079] The second electrode 164 may be formed of and include a conductive material. The second electrode 164 may be formed of and include, for example, one or more of the materials described above with reference to the first electrode 162. In some embodiments, the second electrode 164 has substantially the same material composition as the first electrode 162.

[0080] The dielectric material 166 may be formed of and include one or more dielectric materials, such as one or more of the following: silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, titanium dioxide (TiO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), oxide-nitride-oxide materials (such as silicon dioxide-silicon nitride-silicon dioxide), strontium titanate (SrTiO3) (STO), barium titanate (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), ferroelectric materials (such as ferroelectric hafnium oxide, ferroelectric zirconium oxide, lead zirconate titanate (PZT)) and high-k dielectric materials.

[0081] Each memory device 158 may be configured to electrically communicate with two transistor structures 142 (e.g., by means of one or both of the first routing structure 148 and the second routing structure 150 and one or both of the first conductive contact structure 144 and the second conductive contact structure 146). In some embodiments, an individual memory device 158 is configured to electrically communicate with two (2) first transistor structures 142A (and thus two (2) first routing structures 148 and two (2) first conductive contact structures 144) or two (2) second transistor structures 142B (and thus two (2) second routing structures 150 and two (2) second conductive contact structures 146) to form a memory cell 160. In some such embodiments, the transistor structures 142 of the memory cell 160 are horizontally offset from one another (e.g., in the Y direction) and substantially vertically aligned with one another (e.g., in the Z direction). In some embodiments, the first transistor structure 142A and the second transistor structure 142B horizontally overlapping each other (eg, in the X direction, in the Y direction) and vertically offset from each other (eg, in the Z direction) are components of memory cells 160 different from each other.

[0082] In some embodiments, each memory device 158 (and thus each corresponding memory cell 160 including memory device 158) includes a first electrode 162 configured to be in electrical communication with one of the transistor structures 142 and a second electrode 164 configured to be in electrical communication with another of the transistor structures 142. In some such embodiments, each electrode of an individual memory device 158 is configured to be in electrical communication with a different one of the transistor structures 142 (e.g., a different one of the first transistor structures 142A or a different one of the second transistor structures 142B).

[0083] The memory devices 158 may be formed within the eighth insulating material 168 to electrically isolate the memory devices 158 from each other. The eighth insulating material 168 may be formed of an insulating material and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 110. In some embodiments, the eighth insulating material 168 includes a dielectric oxide material, such as SiO x (e.g. SiO2).

[0084] refer to Figure 1H In the peripheral region 103, the capacitor structure 170 may be vertically formed on the additional vertical stacked structure 156 (eg, in the Z direction). In some embodiments, the capacitor structure 170 is similar to the array region 101 ( Figure 1D ) within the storage device 158. For example, each capacitor structure 170 may include a first electrode 162, a second electrode 164, and a dielectric material 166 between the first electrode 162 and the second electrode 164, as described above with reference to the storage device 158 ( Figure 1G ) is described. However, the geometric configuration (eg, shape, size) of the first electrode 162, the second electrode 164, and the dielectric material 166 of the corresponding capacitor structure 170 may be different from the corresponding storage device 158 ( Figure 1G ) have different geometric configurations.

[0085] In some embodiments, conductive plate structures 161 including material of first electrodes 162 extend horizontally (e.g., in the X direction, in the Y direction) between horizontally adjacent (e.g., in the Y direction) columns 163 of capacitor structures 170. As described in more detail herein, capacitor structures 170 may include a microelectronic device (e.g., microelectronic device 300 ( Figure 3D to Figure 3F ))'s decoupling capacitor.

[0086] Figure 1I to Figure 1M is Figure 1G and Figure 1H 1. A simplified partial vertical cross-sectional view of the first microelectronic device structure 100 at a processing stage subsequent to the processing stage illustrated in FIG. Fig. 1I , Figure 1L and Figure 1M ), simplified electrical schematics ( Figure 1J ) and simplified horizontal cross-section diagram of part ( Figure 1K ). Fig. 1I A simplified partial vertical cross-section diagram is obtained by comparing Figure 1G The cross-section diagram is taken from the same plane, but Figure 1G In a processing stage following the processing stage described in . Figure 1J The simplified partial electrical schematic corresponds to Fig. 1I1 and 1 , wherein for clarity and ease of understanding of the drawings and associated descriptions, Figure 1J Simplified parts of the electrical schematic are not depicted Fig. 1I Some features are shown in a simplified partial vertical cross-section. Figure 1K The simplified partial horizontal cross-sectional view is about the line GG depicted in 1I. Figure 1L A simplified partial vertical cross-section diagram is obtained by comparing Figure 1H The cross-section diagram is taken from the same plane, but Figure 1H In a processing stage following the processing stage described in . Figure 1M A simplified partial vertical cross-section diagram is obtained by comparing Fig. 1I A simplified partial vertical cross-sectional view is taken relative to a portion of the peripheral region 103 .

[0087] Common Reference Fig. 1I , Figure 1L and Figure 1M , after forming the memory devices 158 to form the memory cells 160 and the capacitor structures 170, a carrier wafer 172 including a second base structure 174 and an oxide material 176 can be formed over the first microelectronic device structure 100, such as over the memory devices 158 and the capacitor structures 170. The carrier wafer 172 can be configured to facilitate safe handling of the first microelectronic device structure 100 for further processing of the first microelectronic device structure 100. The carrier wafer 172 can comprise a conventional carrier structure and therefore is not described in detail herein.

[0088] The oxide material 176 may be formed of and include one or more of: silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x In some embodiments, the eighth insulating material 168 includes SiO x (eg, SiO 2 ). The oxide material 176 and the seventh insulating material 152 may have substantially the same material composition as each other.

[0089] The carrier wafer 172 can be attached to the first microelectronic device structure 100 by contacting the eighth insulating material 168 of the first microelectronic device structure 100 with the oxide material 176 of the carrier wafer 172. After the eighth insulating material 168 and the oxide material 176 are contacted, the first microelectronic device structure 100 and the carrier wafer 172 can be exposed to an annealing condition to form a bond (e.g., oxide-to-oxide bond) between the eighth insulating material 168 of the first microelectronic device structure 100 and the oxide material 176 of the carrier wafer 172 to form a microelectronic device structure assembly. In some embodiments, the first microelectronic device structure 100 and the carrier wafer 172 are exposed to a temperature greater than, for example, 800° C. to form the oxide-to-oxide bond and attach the first microelectronic device structure 100 to the carrier wafer 172.

[0090] After the carrier wafer 172 is attached to the first microelectronic device structure 100, the carrier wafer 172 and the first microelectronic device structure 100 can be vertically inverted (eg, in the Z direction) (eg, flipped) and the first base structure 102 ( Figure 1G and 1H ) may be removed, for example, by exposing the first substrate structure 102 to a chemical mechanical planarization (CMP) process.

[0091] Common Reference Figure 1L and Figure 1M , the first microelectronic device structure 100 is vertically inverted (eg, in the Z direction) and the first base structure 102 is removed ( Figure 1G and 1H ), the semiconductive material 116 of the channel region 125 in the peripheral region 103 may be removed (e.g., Figure 1L and Figure 1M 170; for example, a horizontally extending (e.g., in the Y direction) portion of a level 118 of the now vertically upper (e.g., in the Z direction) level of the semiconductive material 116 that is relatively farther away from the capacitor structure 170 than other vertical levels of the semiconductive material 116. The removal of the second insulating material 114 and the portion of the level 118 of the channel region 125 of the now vertically upper (e.g., in the Z direction) level 118 can form an upper channel region 125 within the peripheral region 103 having a relatively smaller horizontal dimension (e.g., in the Y direction) than the channel region 125 of the now relatively vertically lower (e.g., in the Z direction) level 118 within the peripheral region 103.

[0092] The channel region 125 in the peripheral region 103 may form a first additional transistor structure 178A and a second additional transistor structure 178B. The first additional transistor structure 178A may be similar to the array region 101 ( Fig. 1I ) of the first transistor structure 142A ( Fig. 1I) but is vertically offset therefrom (eg, in the Z direction). The second additional transistor structure 178B may be similar to array region 101 ( Fig. 1I ) of the second transistor structure 142B ( Fig. 1I ) but vertically offset therefrom (e.g., in the Z direction). Each of the first additional transistor structure 178A and the second additional transistor structure 178B may individually include four vertically spaced (e.g., in the Z direction) levels of the channel region 125. In additional embodiments, the first additional transistor structure 178A further includes an additional channel region 125 relative to the second additional transistor structure 178B. The first additional transistor structure 178A and the second additional transistor structure 178B are collectively referred to herein as "additional transistor structures 178". The additional transistor structures 178 may be used within a sub-word line driver (SWD) circuit system within a horizontal region of the peripheral region 103. In some embodiments, the additional transistor structures 178 individually have one of a G2S configuration, a G3S configuration, and a GAA configuration, so that multiple boundaries of their individual channel regions 125 are at least partially covered (e.g., surrounded) by the first conductive structure 126.

[0093] After removing the portion of the now vertically upper (e.g., in the Z direction) level 118 of the second insulating material 114 and the semiconductive material 116 within the peripheral region 103 to form a first additional transistor structure 178A having a relatively smaller horizontal dimension (e.g., in the Y direction) than the second additional transistor structure 178B, the opening may be filled with an insulating material, such as one or more of the materials described above with reference to the first insulating material 110. Since the opening is filled with the insulating material, which may be the same as the first insulating material 110, the insulating material filling the opening is Figure 1L and Figure 1M is illustrated as being the same as the first insulating material 110 .

[0094] Still refer to Figure 1L and Figure 1M , a third conductive contact structure 180 can be formed to extend vertically (e.g., in the Z direction) through the first microelectronic device structure 100 within the peripheral region 103 and contact the channel region 125 of the first additional transistor structure 178A. Additionally, a fourth conductive contact structure 182 can be formed to extend vertically (e.g., in the Z direction) through the first microelectronic device structure 100 within the peripheral region 103 and contact the channel region 125 of the second additional transistor structure 178B.

[0095] refer to Figure 1L , one or more fifth conductive contact structures 183 may be formed to extend vertically (eg, in the Z direction) through the first insulating material 110 and contact (eg, electrically communicate with) the conductive plate structure 161 within at least one of the peripheral regions 103. Figure 1MAs shown in FIG. 4 , the fifth conductive contact structure 183 may be omitted from (eg, not formed within) one or more others of the peripheral region 103 .

[0096] After forming the third conductive contact structure 180 and the fourth conductive contact structure 182, a conductive routing level 185 may be formed on the stacked structure 112. Figure 1L and Figure 1M , within the peripheral region 103, a conductive routing level 185 can be formed to include a third routing structure 184 and a fourth routing structure 186. The third routing structure 184 can be formed to contact (e.g., electrically contact) the third conductive contact structure 180. The fourth routing structure 186 can be formed to contact (e.g., electrically contact) the fourth conductive contact structure 182.

[0097] refer to Fig. 1I In the array region 101, the conductive routing level 185 may be formed to include additional conductive structures 138 (e.g., digit lines, bit lines). Individual additional conductive structures 138 may be formed to contact (e.g., electrically contact) respective groups of conductive pillar structures 136 (e.g., digit line contact structures, BITCON structures) within the respective array region 101. Fig. 1I , different additional conductive structures 138 may be horizontally offset from each other (e.g., in the Y direction) and may be coupled to different groups of conductive pillar structures 136. The additional conductive structures 138 within the array region 101 may be coupled to the peripheral region 103 ( Figure 1L and Figure 1M ) within the third routing structure 184 ( Figure 1L and Figure 1M ) and the fourth routing structure 186 ( Figure 1L and Figure 1M ) are substantially vertically aligned (e.g., in the Z direction).

[0098] refer to Figure 1K , which shows a simplified partial horizontal cross-sectional view of the first microelectronic device structure 100 about the line GG depicted in 1I, the additional conductive structures 138 can be individually formed to include a first segment 138A and a plurality of second segments 138B that individually protrude horizontally from the first segment 138A and are continuous with the first segment 138A. The first segments 138A of the additional conductive structures 138 can extend horizontally substantially linearly in substantially the same direction (e.g., the X direction) as each other and the conductive structures 126 vertically therebelow. The first segments 138A of the additional conductive structures 138 can extend horizontally parallel to each other and the conductive structures 126 (e.g., the X direction). In Figure 1K, some of the conductive structures 126 are depicted using dashed lines to identify that the conductive structure 126 vertically underlies (e.g., in the Z direction) the additional conductive structure 138. The second segment 138B of the additional conductive structure 138 may extend substantially linearly horizontally orthogonal to (e.g., in the Y direction) the conductive structure 126 and the first segment 138A of the additional conductive structure 138. Each additional conductive structure 138 may, for example, include a single (e.g., only one) first segment 138A extending in the X direction and a plurality (e.g., more than one) second segments 138B that are integrated with the first segment 138A and extend in the Y direction. Each second segment 138B of an individual additional conductive structure 138 may extend horizontally (e.g., in the Y direction) from the first segment 138A to one of the conductive pillar structures 136. In Figure 1K , some of the conductive pillar structures 136 are depicted using dashed lines to identify that the conductive pillar structures 136 vertically underlie (e.g., in the Z direction) the additional conductive structures 138. Individual second segments 138B of the additional conductive structures 138 may horizontally overlap (e.g., in the Y direction) the individual conductive pillar structures 136 and may couple the additional conductive structures 138 to the conductive pillar structures 136. An individual additional conductive structure 138 may be coupled to a plurality (e.g., a group) of conductive pillar structures 136 by means of a plurality of second segments 138B of the additional conductive structures 138. The configuration of the additional conductive structures 138 may facilitate a horizontal footprint reduction and / or an increase in feature density compared to conventional configurations.

[0099] Common Reference Figure 1I to Figure 1M , the third conductive contact structure 180, the fourth conductive contact structure 182, the fifth conductive contact structure 138, the additional conductive structure 138, the third routing structure 184, and the fourth routing structure 186 may be individually formed of and include a conductive material, such as one or more of the materials described above with reference to the conductive structure 126. In some embodiments, the third conductive contact structure 180, the fourth conductive contact structure 182, the fifth conductive contact structure 183, the additional conductive structure 138, the third routing structure 184, and the fourth routing structure 186 individually include a metal material, such as tungsten.

[0100] In forming the third conductive contact structure 180 ( Figure 1L and Figure 1M )、the fourth conductive contact structure 182 ( Figure 1L and Figure 1M ) and conductive routing level 185 (including third routing structure 184 ( Figure 1L and Figure 1M ))、the fourth routing structure 186 ( Figure 1L and Figure 1M ) and additional conductive structure 138 ( Figure 1I to Figure 1K), one or more additional routing levels may be formed above the conductive routing level 185. For example, a fifth routing structure 188 may be formed above the conductive routing level 185, such as in the array region 101 ( Figure 1I to Figure 1K ) within the additional conductive structure 138 ( Figure 1I to Figure 1K ) and in the peripheral area 103 ( Figure 1L and Figure 1M ) in the third routing structure 184 ( Figure 1L and Figure 1M ), the fourth routing structure 186 ( Figure 1L and Figure 1M ). At least some of the fifth routing structures 188 may be electrically connected to the conductive routing level 185 (including the third routing structure 184 ( Figure 1L and Figure 1M ), the fourth routing structure 186 ( Figure 1L and Figure 1M ) and additional conductive structure 138 ( Figure 1I to Figure 1K )). In addition, optionally, a sixth routing structure 190 can be formed on the fifth routing structure 188. At least some of the sixth routing structures 190 (if present) can be electrically connected to at least some of the fifth routing structures 188 by means of an additional conductive interconnect structure 191. The fifth routing structure 188, the conductive interconnect structure 189, the sixth routing structure 190 (if present), and the additional conductive interconnect structure 191 (if present) can be formed within a ninth insulating material 192.

[0101] The fifth routing structure 188, the conductive interconnect structure 189, the sixth routing structure 190 (if present), and the additional conductive interconnect structure 191 (if present) may be individually formed of and include a conductive material, such as one or more of the materials described above with reference to the conductive structure 126. In some embodiments, the fifth routing structure 188, the conductive interconnect structure 189, the sixth routing structure 190, and the additional conductive interconnect structure 191 individually include a metal material, such as tungsten.

[0102] The ninth insulating material 192 may be formed of and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 110. In some embodiments, the ninth insulating material 192 is formed of and includes a dielectric oxide material, such as SiO x (e.g. SiO2).

[0103] Figure 2A is a simplified partial top view of a second microelectronic device structure 200 according to an embodiment of the present disclosure. Figure 2B is through Figure 2A 1 is a simplified partial vertical cross-sectional view of the second microelectronic device structure 200 taken along section line BB.

[0104] Figure 2C is through Figure 2A 1 and 2 are simplified partial vertical cross-sectional views of the second microelectronic device structure 200 taken along each of the section lines CC of FIG. Figure 2D is through Figure 2A DD is a simplified partial vertical cross-sectional view of the second microelectronic device structure 200 taken along each of the section lines DD.

[0105] refer to Figure 2A The second microelectronic device structure 200 includes: a socket region 202 configured to include one or more conductive interconnects for electrically connecting one or more components of the first microelectronic device structure 100 to a back-end-of-line (BEOL) structure; a complementary metal oxide semiconductor (CMOS) region 204 including one or more CMOS circuits; a sense amplifier region 206 including a sense amplifier region configured to facilitate the first microelectronic device structure 100 ( Fig. 1I ) of the memory cell 160 ( Fig. 1I ) of the sense amplifier (SA) circuit for operation; a conductive line socket area 208 (such as a digital line socket area, a bit line socket area), which is configured to include a first microelectronic device structure 100 ( Fig. 1I ) of the conductive structure 138 ( Fig. 1I ) electrically connected to the sense amplifier circuitry of the sense amplifier region 206. The sense amplifier region 206 may also include a micro-gap region 210 including additional conductive interconnects operably associated with the sense amplifier circuitry and / or additional control logic circuitry (e.g., additional CMOS circuitry) within the sense amplifier region 206.

[0106] In some embodiments, the sense amplifier region 206 is horizontally inserted (e.g., in the X direction) between the socket region 202 and the CMOS region 204. The conductive line socket region 208 can be horizontally inserted (e.g., in the X direction, in the Y direction) between horizontally adjacent (e.g., in the X direction, in the Y direction) sense amplifier regions 206, respectively. In some embodiments and as described in more detail herein, before attaching the second microelectronic device structure 200 to the first microelectronic device structure 100 ( Figures 1I to 1L ) After that, the sense amplifier region 206 and the conductive line socket region 208 may be positioned in the array region 101 ( Fig. 1I ) within the horizontal boundary (eg, in the X direction, in the Y direction); and the socket region 202 and the CMOS region 204 may be positioned within the first microelectronic device structure 100 ( Figures 1I to 1L ) of the peripheral area 103 ( Figure 1K and 1L )’s horizontal boundaries (e.g., in the X direction, in the Y direction).

[0107] Common Reference Figure 2B to Figure 2D , within each of the socket region 202, the CMOS region 204, and the sense amplifier region 206, the second microelectronic device structure 200 may be formed to include a transistor 214 at least partially positioned within the second base structure 212. A tenth insulating material 213 may vertically overlie (e.g., in the Z direction) the transistor 214. The transistor 214 may be included within and may form part of control logic circuitry (e.g., CMOS circuitry) of the second microelectronic device structure 200 (e.g., sense amplifier circuitry of the sense amplifier region 206).

[0108] The second substrate structure 212 can be obtained by referring to the first substrate structure 102 ( Figure 1B ) is formed from and includes one or more of the materials described in the foregoing. In some embodiments, the second substrate structure 212 is formed from and includes a semiconductive material, such as silicon (eg, single crystal silicon, polycrystalline silicon).

[0109] The tenth insulating material 213 may be formed of an insulating material and include an insulating material, such as the first insulating material 110 ( Figure 1B ) described above. In some embodiments, the tenth insulating material 213 is formed of a dielectric oxide material and includes a dielectric oxide material, such as SiO x (e.g. SiO2).

[0110] The transistors 214 may be individually formed to include a conductive doped region 216, a channel region 218, a gate structure 220, and a gate dielectric material 222. The conductive doped region 216 may be formed within the second base structure 212; the channel region 218 may be formed within the second base structure 212 and may be horizontally interposed (e.g., in the Y direction) between the conductive doped regions 216; the gate structure 220 may vertically overlie (e.g., in the Z direction) the channel region 218; and the gate dielectric material 222 (e.g., a dielectric oxide material) may be vertically interposed (e.g., in the Z direction) between the gate structure 220 and the channel region 218. The conductive doped region 216 of the individual transistors 214 may include a source region 216A and a drain region 216B, collectively referred to herein as the conductive doped region 216.

[0111] For individual transistors 214, their conductive doped regions 216 may include semiconductor material of the second base structure 212 doped with one or more desired conductivity enhancing species. In some embodiments, the conductive doped regions 216 of transistors 214 include semiconductor material (e.g., silicon) doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In some such embodiments, the channel region 218 of transistors 214 includes semiconductor material doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In some other such embodiments, the channel region 218 of transistors 214 includes substantially undoped semiconductor material (e.g., substantially undoped silicon). In additional embodiments, for individual transistors 214, their conductive doped regions 216 include semiconductor material (e.g., silicon) doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In some such additional embodiments, the channel region 218 of transistors 214 includes semiconductor material doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In some other such additional embodiments, the channel region 218 of the transistor 214 includes a substantially undoped semiconductor material (eg, substantially undoped silicon).

[0112] The gate structures 220 (eg, gate electrodes) may be individually extended horizontally (eg, in the X direction) between and employed by the plurality of transistors 214. The gate structures 220 may be formed of and include conductive materials, such as those described above with reference to the conductive structures 126 ( Figure 1B ) described in one or more materials.

[0113] Continue to refer Figure 2B to Figure 2D , a first contact structure 224 may be formed over and in contact with the gate structure 220 (and thus the transistor 214), and a seventh routing structure 225 may be formed over and in contact with the first contact structure 224. In addition, a second contact structure 226 may be formed over and in contact with the conductive doped region 216, and an eighth routing structure 227 may be formed over and in contact with the second contact structure 226. Each of the first contact structure 224, the seventh routing structure 225, the second contact structure 226, and the eighth routing structure 227 may be individually formed of and include a conductive material, such as one or more of the materials described above with reference to the conductive structure 126. In some embodiments, each of the first contact structure 224, the seventh routing structure 225, the second contact structure 226, and the eighth routing structure 227 individually includes a metal material, such as tungsten.

[0114] Transistor 214, first contact structure 224, seventh routing structure 225, second contact structure 226, and eighth routing structure 227 may be used to form a structure that facilitates the memory cell 160 ( Fig. 1I ) of various control logic circuits (e.g., CMOS circuits) for the desired control operation. For example, within the sense amplifier region 206, the aforementioned features may be formed and included in the sense amplifier circuit 229 ( Figure 2B ) for memory unit 160 ( Fig. 1I As another example, within CMOS region 204, the aforementioned features may be formed and included in additional circuitry 231 ( Figure 2C and Figure 2D ) (eg, advanced circuitry) for use in memory cell 160 ( Fig. 1I ) operations, such as driver (e.g., column drivers, block switches, and voltage pumps) circuits, data path circuits, I / O circuits, charge pumps (e.g., V CCP Charge pump, V NEGWL Charge pump, DVC2 charge pump) circuit, DLL circuit, V dd One or more of regulator circuits, string driver circuits, page buffer circuits, decoder (e.g., local level decoder, column decoder) circuits, repair circuits (e.g., row repair circuits), memory test circuits, MUX circuits, ECC circuits, and self-refresh / wear leveling circuits and various chip / level control circuits.

[0115] Figure 2E to Figure 2G It is in reference Figures 2A to 2D A simplified partial vertical cross-sectional view of the second microelectronic device structure 200 at a processing stage subsequent to the processing stage depicted. Figure 2E is through Figure 2B The planes described in the reference are cut from the same planes, but Figures 2A to 2D In a processing stage following the processing stage illustrated and described. Figure 2F is through Figure 2C The planes described in the reference are cut from the same planes, but Figures 2A to 2D In a processing stage following the processing stage illustrated and described. Figure 2G is through Figure 2D The planes described in the reference are cut from the same planes, but Figures 2A to 2D In a processing stage following the processing stage illustrated and described.

[0116] Common Reference Figure 2E to Figure 2G, a carrier wafer 228 including a third base structure 230 and an oxide material 232 can be formed over the transistor 214 of the second microelectronic device structure 200. The carrier wafer 228 can be configured to facilitate safe handling of the second microelectronic device structure 200 for further processing of the second microelectronic device structure 200. The carrier wafer 228 can include a conventional carrier structure and is therefore not described in detail herein. The oxide material 232 can include the oxide material 176 ( Fig. 1I ) described in one or more materials.

[0117] The carrier wafer 228 can be attached to the second microelectronic device structure 200 by contacting the tenth insulating material 213 of the second microelectronic device structure 200 with the oxide material 232 of the carrier wafer 228. After the tenth insulating material 213 is in contact with the oxide material 232, the second microelectronic device structure 200 and the carrier wafer 228 can be exposed to an annealing condition to form a bond (e.g., oxide-to-oxide bond) between the tenth insulating material 213 and the oxide material 232. In some embodiments, the tenth insulating material 213 and the oxide material 232 are exposed to a temperature greater than, for example, 800° C. to form the oxide-to-oxide bond and attach the carrier wafer 228.

[0118] After attaching the carrier wafer 228, the resulting assembly can be inverted vertically (eg, in the Z direction) (eg, flipped) and the second base structure 212 ( Figure 2B to Figure 2D ) can be removed (eg, vertically thinned), for example, by exposing the second substrate structure 212 to a chemical mechanical planarization (CMP) process. The remaining portions of the second substrate structure 212 can be isolated from each other by the remaining portions of the tenth insulating material 213.

[0119] After removing a portion of the second base structure 212, the eleventh insulating material 234 may be formed on or over the remaining portions of the second base structure 212 and the tenth insulating material 213. The eleventh insulating material 234 may be formed of and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 110.

[0120] Figures 3A to 3C The second microelectronic device structure 200 ( Figure 2E to Figure 2G ) is attached to the first microelectronic device structure 100 ( Figure 1I to Figure 1M ) is a simplified partial vertical cross-sectional view of a microelectronic device 300 formed by. Figure 3A Description and Fig. 1I and Figure 2E but after attaching the second microelectronic device structure 200 to the first microelectronic device structure 100. Figure 3B Description and Figure 1L and Figure 2Fbut after attaching the second microelectronic device structure 200 to the first microelectronic device structure 100. Figure 3C Description and Figure 1M and Figure 2G but after attaching the second microelectronic device structure 200 to the first microelectronic device structure 100.

[0121] Common Reference Figures 3A to 3C , the second microelectronic device structure 200 ( Figure 2E to Figure 2G ) can be vertically inverted (eg, in the Z direction) (eg, flipped) and attached to the first microelectronic device structure 100 to form a microelectronic device 300 including the first microelectronic device structure 100 and the second microelectronic device structure 200.

[0122] refer to Figure 3A , the microelectronic device 300 includes a sense amplifier region 206 and a conductive line socket region 208 vertically overlying (eg, in the Z direction) the array region 101 and within a horizontal region of the array region 101. Figure 3B and Figure 3C The microelectronic device 300 further includes a socket region 202 and a CMOS region 204 vertically above the peripheral region 103 (eg, in the Z direction) and within a horizontal region of the peripheral region 103 .

[0123] Attaching the second microelectronic device structure 200 to the first microelectronic device structure 100 can include vertically inverting (e.g., in the Z direction) the second microelectronic device structure 200 and contacting the ninth insulating material 192 of the first microelectronic device structure 100 with the tenth insulating material 213 of the second microelectronic device structure 200. Thereafter, the ninth insulating material 192 and the tenth insulating material 213 can be subjected to annealing conditions to form bonds (e.g., oxide-to-oxide bonds) between at least the ninth insulating material 192 and the tenth insulating material 213 and attaching the second microelectronic device structure 200 to the first microelectronic device structure 100.

[0124] like Figures 3A to 3C, in some embodiments, the second microelectronic device structure 200 is attached to the first microelectronic device structure 100 such that the back side of the second microelectronic device structure 200 is attached to the front side of the first microelectronic device structure 100. The front side of the second microelectronic device structure 200 can be considered as the side (e.g., the end face) closest to the transistor 214, and the back side of the second microelectronic device structure 200 can be considered as an additional side (e.g., the additional end face) of the second microelectronic device structure 200 that is relatively farther away from the transistor 214 than the front side. Additionally, the front side of the first microelectronic device structure 100 can be considered as the side (e.g., the end face) closest to the transistor structure 142 of the memory cell 160, and the back side of the first microelectronic device structure 100 can be considered as an additional side (e.g., the additional end face) of the first microelectronic device structure 100 that is closest to the storage device 158 of the memory cell 160. Thus, in Figures 3A to 3C In the configuration shown in , the microelectronic device 300 can be formed to have a so-called “back-to-front (B2F)” arrangement of the second microelectronic device structure 200 relative to the first microelectronic device structure 100 .

[0125] In additional embodiments, the second microelectronic device structure 200 is attached to the first microelectronic device structure 100 such that the front side of the second microelectronic device structure 200 is attached to the front side of the first microelectronic device structure 100. In such embodiments, the orientation of the transistor 214 may be relative to Figures 3A to 3C 100. The orientation shown in FIG. 100 is vertically reversed (e.g., flipped). Thus, transistor 214 can be vertically positioned relatively closer to transistor structure 142 of memory cell 160. Thus, microelectronic device 300 can be formed to have a so-called "front-to-front (F2F)" arrangement of second microelectronic device structure 200 relative to first microelectronic device structure 100. Additional carrier structures can be used to provide second microelectronic device structure 200 in an F2F arrangement relative to first microelectronic device structure 100.

[0126] Figure 3D to Figure 3F is Figures 3A to 3C 3. A simplified partial vertical cross-sectional view of a microelectronic device 300 at a processing stage subsequent to the processing stage illustrated in FIG. Figure 3D Description and Figure 3A The same plane as described in Figures 3A to 3C In a processing stage following the processing stage described in . Figure 3E Description and Figure 3B The same plane as described in Figures 3A to 3C In a processing stage following the processing stage described in . Figure 3F Description and Figure 3C The same plane as described in Figures 3A to 3C In a processing stage following the processing stage described in .

[0127] Common Reference Figure 3D to Figure 3F After attaching the second microelectronic device structure 200 to the first microelectronic device structure 100, the carrier wafer 228 ( Figures 3A to 3C ) of the third base structure 230 ( Figures 3A to 3C ) may be removed (eg, by CMP, for example).

[0128] Before removing the carrier wafer 228 ( Figures 3A to 3C ) of the third base structure 230 ( Figures 3A to 3C ), the fifth conductive contact structure 236 may be formed to extend vertically (e.g., in the Z direction) through the oxide material 232, the eleventh insulating material 234, and the ninth insulating material 192 and reach or enter the sixth routing structure 190. The fifth conductive contact structure 236 may be individually formed of and include a conductive material, such as the conductive structure 126 ( Fig. 1I ) In some embodiments, the fifth conductive contact structures 236 individually include a metal material, such as tungsten.

[0129] After the fifth conductive contact structure 236 is formed, the ninth routing structure 302 may be formed vertically above the fifth conductive contact structure 236 (e.g., in the Z direction) and in contact with (e.g., electrically connected to) the fifth conductive contact structure 236. In addition, the conductive interconnect structure 303 may be formed to extend vertically (e.g., in the Z direction) between the ninth routing structure 302 and at least some of the seventh routing structure 225 and / or at least some of the eighth routing structure 227 (and thus at least some of the transistors 214, at least some of the sense amplifier circuits 229 ( Figure 3D ) and at least some additional circuitry 231 ( Figure 3E and Figure 3F )) and electrically connect them.

[0130] After forming the ninth routing structure 302, a back-end of the line (BEOL) region 304 may be formed vertically thereon. The BEOL region 304 may include, for example, a tenth routing structure 306 and a conductive pad structure 308 vertically overlying (e.g., in the Z direction) the tenth routing structure 306. Additional conductive interconnect structures 307 may be formed to extend vertically (e.g., in the Z direction) between at least some of the tenth routing structures 306 and at least some of the ninth routing structures 302 and electrically connect at least some of the tenth routing structures 306 with at least some of the ninth routing structures 302, and further conductive interconnect structures 309 may be formed to extend vertically (e.g., in the Z direction) between at least some of the conductive pad structures 308 and at least some of the tenth routing structures 306 and electrically connect at least some of the tenth routing structures 306.

[0131] The ninth routing structure 302, the conductive interconnect structure 303, the tenth routing structure 306, the additional conductive interconnect structure 307, the conductive pad structure 308, and the further conductive interconnect structure 309 may be individually formed of and include conductive materials, such as those described above with reference to the conductive structure 126 ( Figure 1B In some embodiments, the ninth routing structure 302, the conductive interconnect structure 303, the tenth routing structure 306, the additional conductive interconnect structure 307, the conductive pad structure 308, and the further conductive interconnect structure 309 may be individually formed of and include a metal material, such as tungsten.

[0132] The ninth routing structure 302, the conductive interconnect structure 303, the tenth routing structure 306, the additional conductive interconnect structure 307, the conductive pad structure 308, and the further conductive interconnect structure 309 are vertically underlying the twelfth insulating material 310. The twelfth insulating material 310 is formed of and includes an insulating material, such as one or more of the materials described above with reference to the first insulating material 110. In some embodiments, the twelfth insulating material 310 is formed of and includes a dielectric oxide material, such as SiO x (e.g. SiO2).

[0133] Forming the microelectronic device 300 to include the sense amplifier region 206 (including its sense amplifier circuitry 229) vertically above the array region 101 (e.g., in the Z direction) and within the horizontal boundaries (e.g., in the X direction, in the Y direction) of the array region 101 and forming the microelectronic device 300 to include the socket region 202 and the CMOS region 204 vertically above the peripheral region 103 (e.g., in the Z direction) and within the horizontal boundaries (e.g., in the X direction, in the Y direction) of the peripheral region 103 facilitates placing advanced CMOS circuitry in a wafer (e.g., the second microelectronic device structure 200) that is separate from the memory cells 160 of the array region 101 formed in the first microelectronic device structure 100. Additionally, forming at least some CMOS circuitry (e.g., sense amplifier circuitry 229 of sense amplifier region 206, additional circuitry 231 of CMOS region 204) in a wafer separate from memory cells 160 and vertically overlying (e.g., in the Z direction) the wafer in which memory cells 160 are formed facilitates forming microelectronic device 300 to include a greater density of memory cells 160 than conventional microelectronic devices.

[0134] Therefore, according to some embodiments of the present disclosure, a microelectronic device includes a first die and a second die vertically overlying and attached to the first die. The first die includes an array area and a peripheral area horizontally adjacent to the array area. The array area includes memory cells, which respectively include a first transistor structure, a second transistor structure horizontally adjacent to the first transistor structure, and a storage device vertically underlying and coupled to the first transistor structure and the second transistor structure. The peripheral area includes a sub-word line driver circuit system configured to implement control operations on the memory cells. The second die includes a sense amplifier area and a CMOS area horizontally adjacent to some of the sense amplifier areas. The sense amplifier area is within the horizontal area of ​​the array area of ​​the first die and includes a sense amplifier circuit system configured to implement additional control operations on the memory cells. The CMOS area is horizontally adjacent to some of the sense amplifier areas and includes a CMOS circuit system configured to implement additional control operations on the memory cells.

[0135] In addition, according to some embodiments of the present disclosure, a memory device includes a first microelectronic device structure and a second microelectronic device structure joined to the first microelectronic device structure. The first microelectronic device structure includes a memory cell array, each of the memory cells of the memory cell array respectively including: a transistor including four vertically stacked channel regions; an additional transistor including four additional vertically stacked channel regions; and a capacitor vertically overlying the first transistor and the second transistor and electrically connected to each of the transistor and the additional transistor. The first microelectronic device structure further includes a peripheral region horizontally adjacent to the memory cell array and including a sub-word line driver (SWD) circuit, the SWD circuit individually including another transistor including four additional vertically stacked channel regions. The second microelectronic device structure includes a sense amplifier (SA) circuit vertically overlying the memory cell array and within the horizontal boundary of the memory cell array.

[0136] The microelectronic device of the present disclosure (such as microelectronic device 300) may be included in an embodiment of the electronic system of the present disclosure. For example, Figure 4 403 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet computer (e.g., or Tablet computers), electronic books, navigation devices, etc. The electronic system 403 includes at least one memory device 405. For example, the memory device 405 may include a microelectronic device previously described herein (e.g., a microelectronic device previously described in reference Figure 3D to Figure 3F An embodiment of a microelectronic device 300 is described.

[0137] The electronic system 403 may further include at least one electronic signal processor device 407 (commonly referred to as a "microprocessor"). The electronic signal processor device 407 may optionally include an embodiment of one or more of the microelectronic devices and microelectronic device structures previously described herein. The electronic system 403 may further include one or more input devices 409 for inputting information into the electronic system 403 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 403 may further include one or more output devices 411 for outputting information (such as visual or audio output) to the user, such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 409 and the output device 411 may constitute a single touch screen device that can be used both to input information to the electronic system 403 and to output visual information to the user. The input device 409 and the output device 411 may be in electrical communication with one or more of the memory device 405 and the electronic signal processor device 407.

[0138] Therefore, according to an embodiment of the present disclosure, an electronic system includes: an input device; an output device; a processor device, which is operably coupled to the input device and the output device; and a memory device, which is operably coupled to the processor device. The memory device includes a first die and a second die vertically overlying the first die. The first die includes a memory cell and a sub-word line driver (SWD) circuit coupled to the memory cell. The memory cell includes two transistors vertically overlapping each other and horizontally adjacent to each other and a capacitor vertically underlying and coupled to the two transistors. Each of the two transistors includes a plurality of channel regions and a plurality of gate electrodes vertically adjacent to the plurality of channel regions. The SWD circuit is within a peripheral region horizontally adjacent to an array region. Each of the SWD circuits including additional transistors includes a plurality of additional channel regions and a plurality of additional gate electrodes vertically adjacent to the plurality of additional channel regions. The second die includes a sense amplifier (SA) circuit coupled to the memory cell and within a horizontal region of the array region.

[0139] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0140] Embodiment 1: A microelectronic device, comprising: a first die, comprising: an array area, comprising memory cells, the memory cells respectively comprising: a first transistor structure; a second transistor structure, which is horizontally adjacent to the first transistor structure; and a storage device, which is vertically underlying and coupled to the first transistor structure and the second transistor structure; and a peripheral area, which is horizontally adjacent to the array area and includes a sub-word line driver (SWD) circuit system configured to implement control operations on the memory cells; and a second die, which is vertically overlying and attached to the first die, the second die comprising: a sense amplifier (SA) area, which is within a horizontal area of ​​the array area of ​​the first die and includes an SA circuit system configured to implement additional control operations on the memory cells; and a complementary metal oxide semiconductor (CMOS) area, which is horizontally adjacent to some of the sense amplifier (SA) areas and includes a CMOS circuit system configured to implement additional control operations of the memory cells.

[0141] Embodiment 2: A microelectronic device according to embodiment 1, wherein: the first transistor structure includes: a semiconductive channel region; a gate electrode, which is vertically adjacent to the semiconductive channel region; and a gate dielectric material, which is vertically inserted between the semiconductive channel region and the gate electrode; and the second transistor structure vertically overlaps with the first transistor structure and includes: an additional semiconductive channel region; an additional gate electrode, which is vertically adjacent to the additional semiconductive channel region; and an additional gate dielectric material, which is vertically inserted between the additional semiconductive channel region and the additional gate electrode.

[0142] Embodiment 3: According to the microelectronic device described in Embodiment 2, it further includes: a digit line structure, which is vertically inserted between the memory cell and the SA circuit system; and a digit line contact structure, which is vertically underlying and contacting the digit line structure, and the digit line contact structure includes: a first digit line contact structure, which vertically extends to the first transistor structure and is electrically connected to the first transistor structure; and a second digit line contact structure, which is horizontally adjacent to the first digit line contact structure, vertically extends to the second transistor structure, and is electrically connected to the second transistor structure.

[0143] Embodiment 4: A microelectronic device according to embodiment 3, wherein the digital line structures individually include: a first segment, which extends horizontally in a first direction; and a second segment, which is integrated with the first segment and protrudes horizontally from the first segment in a second direction orthogonal to the first direction, each of the second segments horizontally overlapping and contacting one of the digital line contact structures.

[0144] Embodiment 5: A microelectronic device according to embodiment 2, wherein the SWD circuit system within the peripheral region includes a third transistor structure vertically overlapping the first transistor structure and the second transistor structure of the corresponding ones of the memory cells, and the third transistor structure respectively includes: another semiconductive channel region; another gate electrode, which is vertically adjacent to the other semiconductive channel region; and another gate dielectric material, which is vertically inserted between the other semiconductive channel region and the other gate electrode.

[0145] Embodiment 6: The microelectronic device of Embodiment 5, wherein the third transistor structure of the SWD circuitry and each of the first and second transistor structures of the respective ones of the memory cells exhibit substantially identical geometric gate configurations to one another.

[0146] Embodiment 7: The microelectronic device of any one of Embodiments 1 to 6, wherein the first die further includes a capacitor structure within the peripheral region and vertically underlying the SWD circuitry.

[0147] Embodiment 8: The microelectronic device of Embodiment 7, wherein the capacitor structures within the peripheral region vertically overlap the storage devices of corresponding ones of the memory cells within the array region.

[0148] Embodiment 9: A microelectronic device according to embodiment 1, wherein the storage device of a corresponding one of the memory cells includes a capacitor structure, the capacitor structure comprising: a first electrode, which is electrically connected to the first transistor structure; a second electrode, which is electrically connected to the second transistor structure; and a dielectric material, which is inserted between the first electrode and the second electrode.

[0149] Embodiment 10: A memory device comprising: a first microelectronic device structure comprising: a memory cell array, each of the memory cells of the memory cell array respectively comprising: a transistor comprising four vertically stacked channel regions; an additional transistor comprising four additional vertically stacked channel regions; and a capacitor vertically underlying the transistor and each of the additional transistors and electrically connected to each of the transistors; and a peripheral region horizontally adjacent to the memory cell array and comprising a sub-word line driver (SWD) circuit, the SWD circuit individually comprising another transistor comprising four additional vertically stacked channel regions; and a second microelectronic device structure joined to the first microelectronic device structure and comprising a sense amplifier (SA) circuit vertically overlying the memory cell array and within the horizontal boundary of the memory cell array.

[0150] Embodiment 11: The memory device of Embodiment 10, wherein the peripheral region of the first microelectronic device structure further includes an additional capacitor at a vertical elevation of the capacitor of each of the memory cells of the memory cell array.

[0151] Embodiment 12: The memory device of one of embodiments 10 and 11, wherein: the transistor is in electrical communication with a first electrode of the capacitor; and the additional transistor is in electrical communication with a second electrode of the capacitor.

[0152] Embodiment 13: The memory device of any one of Embodiments 10 to 12, further comprising a digit line electrically connected to the memory cell array and vertically interposed between the SA circuit and the memory cell array.

[0153] Embodiment 14: The memory device of any one of Embodiments 10 to 13, wherein the second microelectronic device structure further comprises additional complementary metal oxide semiconductor (CMOS) circuitry outside the horizontal boundary of the memory cell array.

[0154] Embodiment 15: The memory device of Embodiment 14, wherein the additional CMOS circuitry is within a horizontal area of ​​the peripheral region.

[0155] Embodiment 16: The memory device of any of Embodiments 10-15, wherein the transistor and the additional transistor of a first one of the memory cells are each vertically offset from the transistor and the additional transistor of a second one of the memory cells horizontally adjacent to the first one of the memory cells.

[0156] Embodiment 17: An electronic system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising: a first die comprising: a memory cell within an array region and respectively comprising: two transistors vertically overlapping each other and horizontally adjacent, each of the two transistors respectively comprising: a plurality of channel regions; and a plurality of gate electrodes vertically adjacent to the plurality of channel regions; and a capacitor vertically underlying and coupled to the two transistors; a sub-word line driver (SWD) circuit coupled to the memory cell and within a peripheral region horizontally adjacent to the array region, each of the SWD circuits comprising an additional transistor, the additional transistor comprising: a plurality of additional channel regions; and a plurality of additional gate electrodes vertically adjacent to the plurality of additional channel regions; and a second die vertically overlying the first die, the second die comprising a sense amplifier (SA) circuit coupled to the memory cell and within a horizontal region of the array region.

[0157] Embodiment 18: The electronic system of Embodiment 17, wherein the first die further comprises a conductive digit line structure vertically overlying and coupled to the memory cell.

[0158] Embodiment 19: The electronic system of one of Embodiments 17 and 18, wherein the second die further comprises additional control logic circuitry outside the horizontal region of the array area and configured to implement control operations on the memory cells of the first die.

[0159] Embodiment 20: The electronic system of any one of Embodiments 17 to 19, wherein the SA circuit of the second die comprises horizontally-oriented transistors.

[0160] Although certain illustrative embodiments have been described in conjunction with the accompanying drawings, it will be recognized and appreciated by those of ordinary skill in the art that the embodiments encompassed by the present disclosure are not limited to those embodiments explicitly shown and described herein. Specifically, many additions, deletions, and modifications may be made to the embodiments described herein without departing from the scope of the embodiments encompassed by the present disclosure, such as the scope claimed in the claims, including legal equivalents. Additionally, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the present disclosure.

Claims

1. A microelectronic device comprising: A first die comprising: An array region includes memory cells, each of which includes: a first transistor structure; a second transistor structure horizontally adjacent to the first transistor structure; and a memory device vertically underlying and coupled to the first transistor structure and the second transistor structure; and a peripheral region horizontally adjacent to the array region and including a sub-word line driver SWD circuitry configured to implement control operations on the memory cells; and a second die vertically overlying and attached to the first die, the second die comprising: a sense amplifier SA region within a horizontal area of ​​the array region of the first die and including SA circuitry configured to enable additional control operations for the memory cells; and A complementary metal oxide semiconductor (CMOS) region is horizontally adjacent to some of the sense amplifier (SA) regions and includes CMOS circuitry configured to implement additional control operations for the memory cells.

2. The microelectronic device according to claim 1, wherein: The first transistor structure comprises: a semiconducting channel region; a gate electrode vertically adjacent to the semiconducting channel region; and a gate dielectric material vertically interposed between the semiconducting channel region and the gate electrode; and The second transistor structure vertically overlaps the first transistor structure and includes: an additional semiconducting channel region; an additional gate electrode vertically adjacent to the additional semiconducting channel region; and An additional gate dielectric material is vertically interposed between the additional semiconducting channel region and the additional gate electrode.

3. The microelectronic device according to claim 2, further comprising: a digit line structure vertically interposed between the memory cell and the SA circuitry; and a digit line contact structure vertically underlying and contacting the digit line structure, the digit line contact structure comprising: a first digit line contact structure extending vertically to and in electrical communication with the first transistor structure; and A second digit line contact structure is horizontally adjacent to the first digit line contact structure, vertically extends to the second transistor structure, and is in electrical communication with the second transistor structure.

4. The microelectronic device of claim 3 , wherein the digit line structures individually comprise: a first section extending horizontally in a first direction; and Second sections are integrated with the first sections and protrude horizontally from the first sections in a second direction orthogonal to the first direction, each of the second sections horizontally overlapping and contacting one of the digit line contact structures.

5. The microelectronic device of claim 2 , wherein the SWD circuitry within the peripheral region includes a third transistor structure vertically overlapping the first and second transistor structures of corresponding ones of the memory cells, the third transistor structures respectively comprising: Additionally, a semiconducting channel region; a further gate electrode vertically adjacent to the further semiconducting channel region; and A further gate dielectric material is vertically interposed between the further semiconducting channel region and the further gate electrode.

6. The microelectronic device of claim 5, wherein the third transistor structure of the SWD circuitry and each of the first and second transistor structures of the corresponding ones of the memory cells exhibit substantially identical geometric gate configurations to one another.

7. The microelectronic device of any one of claims 1 to 6, wherein the first die further comprises a capacitor structure within the peripheral region and vertically underlying the SWD circuitry.

8. The microelectronic device of claim 7, wherein the capacitor structures within the peripheral region vertically overlap the storage devices of corresponding ones of the memory cells within the array region.

9. The microelectronic device of any one of claims 1 to 6, wherein the storage device of a respective one of the memory cells comprises a capacitor structure, the capacitor structure comprising: a first electrode in electrical communication with the first transistor structure; a second electrode in electrical communication with the second transistor structure; and A dielectric material is interposed between the first electrode and the second electrode.

10. A memory device comprising: A first microelectronic device structure comprising: A memory cell array, each of the memory cells of the memory cell array respectively comprising: a transistor comprising four vertically stacked channel regions; an additional transistor comprising four additional vertically stacked channel regions; and a capacitor vertically underlying and in electrical communication with each of the transistor and the additional transistor; and a peripheral region horizontally adjacent to the memory cell array and including sub-word line driver SWD circuits, the SWD circuits individually including another transistor including four additional vertically stacked channel regions; and A second microelectronic device structure is bonded to the first microelectronic device structure and includes a sense amplifier SA circuit vertically overlying the memory cell array and within a horizontal boundary of the memory cell array.

11. The memory device of claim 10, wherein the peripheral region of the first microelectronic device structure further comprises additional capacitors at the vertical elevation of the capacitor of each of the memory cells of the memory cell array.

12. The memory device of claim 10, wherein: The transistor is in electrical communication with a first electrode of the capacitor; and The additional transistor is in electrical communication with a second electrode of the capacitor.

13. The memory device of any one of claims 10 to 12, further comprising a digit line in electrical communication with the memory cell array and vertically interposed between the SA circuit and the memory cell array.

14. The memory device of any one of claims 10-12, wherein the second microelectronic device structure further comprises additional complementary metal oxide semiconductor (CMOS) circuitry outside the horizontal boundary of the memory cell array.

15. The memory device of claim 14, wherein the additional CMOS circuitry is within a horizontal area of ​​the peripheral region.

16. The memory device of any one of claims 10-12, wherein the transistor of a first one of the memory cells and the additional transistor are each vertically offset from the transistor of a second one of the memory cells horizontally adjacent to the first one of the memory cells.

17. An electronic system comprising: Input device; Output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and comprising: A first die comprising: Memory cells are within the array region and each comprises: Two transistors vertically overlap each other and are horizontally adjacent to each other, each of the two transistors respectively comprising: Multiple access areas; and a plurality of gate electrodes vertically adjacent to the plurality of channel regions; and a capacitor vertically underlying and coupled to the two transistors; sub-word line driver SWD circuits coupled to the memory cells and within a peripheral region horizontally adjacent to the array region, each of the SWD circuits comprising an additional transistor comprising: Multiple additional access areas; and a plurality of additional gate electrodes vertically adjacent to the plurality of additional channel regions; and A second die vertically overlying the first die includes sense amplifier SA circuits coupled to the memory cells and within a horizontal region of the array area.

18. The electronic system of claim 17, wherein the first die further comprises a conductive digit line structure vertically overlying and coupled to the memory cell.

19. The electronic system of one of claims 17 and 18, wherein the second die further comprises additional control logic circuitry outside the horizontal region of the array area and configured to implement control operations on the memory cells of the first die.

20. The electronic system of one of claims 17 and 18, wherein the SA circuit of the second die comprises horizontally-oriented transistors.

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