Light-emitting diode capable of improving cracking of insulating layer and preparation method of light-emitting diode

Abstract

The invention provides a light-emitting diode for improving cracking of an insulating layer and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The light-emitting diode comprises an epitaxial layer, an electrode and an insulating layer, the electrode is located on the surface of the epitaxial layer, and the insulating layer is located on the surface of the electrode; the insulating layer comprises an insulating material layer and a metal barrier layer, and the metal barrier layer is located in the insulating material layer. According to the embodiment of the invention, the problem of electric leakage failure of the light-emitting diode caused by easy breakage of the insulating layer in the bonding process can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved insulation layer cracking and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is a common product. LED is usually manufactured by manufacturing various film layers on a substrate, performing graphic processing, and then cutting to form individual LED core particles.

[0003] In the related art, when preparing a light-emitting diode, first, an epitaxial layer and a first electrode located on the surface of the epitaxial layer are formed on a substrate; then, an insulating layer wrapping the first electrode is formed on the epitaxial layer, and the insulating layer also has a via hole exposing the epitaxial layer; then, a bonding metal is formed on the surface of the conductive substrate and the surface of the insulating layer, the conductive substrate and the insulating layer are bonded together by the bonding metal, and the substrate is removed.

[0004] During the preparation of LEDs, more or less fine particles will remain on the surface of some LEDs. Under high-voltage bonding conditions, these fine particles will squeeze and break the insulating layer, causing the metal materials on both sides of the insulating layer to conduct, thus causing leakage failure of the LEDs. Summary of the invention

[0005] The embodiment of the present disclosure provides a light-emitting diode with improved insulation layer cracking and a method for manufacturing the same, which can improve the problem of leakage failure of the light-emitting diode caused by the insulation layer being easily cracked during the bonding process. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes: an epitaxial layer, an electrode and an insulating layer, wherein the electrode is located on the surface of the epitaxial layer, and the insulating layer is located on the surface of the electrode; the insulating layer includes: an insulating material layer and a metal barrier layer, and the metal barrier layer is located in the insulating material layer.

[0007] Optionally, the metal barrier layer includes two adhesion metal layers and a pressure-resistant metal layer, and the pressure-resistant metal layer is sandwiched between the two adhesion metal layers.

[0008] Optionally, the metal barrier layer further includes an intercepting metal layer, and the intercepting metal layer is sandwiched between the pressure-resistant metal layer and any one of the adhesion metal layers.

[0009] Optionally, the intercepting metal layer includes at least one of a Pt layer and a Ti layer.

[0010] Optionally, the adhesion metal layer includes a Ti layer, and the pressure-resistant metal layer includes at least one of an Au layer and an Al layer.

[0011] Optionally, the thickness of the adhesion metal layer is 1 nm to 20 nm, the thickness of the pressure-resistant metal layer is 100 nm to 300 nm, and the thickness of the interception metal layer is 50 nm to 150 nm.

[0012] Optionally, the insulating layer includes at least two metal barrier layers.

[0013] Optionally, the orthographic projection of the metal barrier layer on the surface of the epitaxial layer away from the electrode is a first projection, and the orthographic projection of the insulating material layer on the surface of the epitaxial layer away from the electrode is a second projection; the ratio of the area of ​​the first projection to the area of ​​the second projection is greater than or equal to 0.8.

[0014] Optionally, the light-emitting diode also includes a transparent conductive layer, a conductive substrate and a bonding metal layer; the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer stacked in sequence, the transparent conductive layer is located on the surface of the first semiconductor layer away from the second semiconductor layer, the electrode is located on the surface of the transparent conductive layer away from the second semiconductor layer, and is electrically connected to the transparent conductive layer; the surface of the first semiconductor layer away from the second semiconductor layer has a second groove exposing the second semiconductor layer, the insulating layer has a portion located in the second groove, and the portion of the insulating layer located in the second groove has a via exposing the second semiconductor layer, the bonding metal layer is located on the surface of the insulating layer away from the epitaxial layer, and is located in the second groove and is electrically connected to the second semiconductor layer, and the conductive substrate is located on the surface of the bonding metal layer away from the insulating layer.

[0015] An embodiment of the present disclosure provides a method for preparing a light-emitting diode, the method comprising: preparing an epitaxial layer on a substrate; forming an electrode and an insulating layer on the surface of the epitaxial layer, so that the insulating layer wraps the electrode, the insulating layer comprising: an insulating material layer and a metal barrier layer, the insulating material layer having a first surface and a second surface opposite to each other, the first surface being connected to the surface of the epitaxial layer, the metal barrier layer being located within the insulating material layer, and the metal barrier layer being located between the first surface and the second surface; coating a bonding metal layer on the second surface of the insulating layer and the surface of a conductive substrate, bonding the conductive substrate to the side where the second surface of the insulating layer is located, and removing the substrate.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] The insulating layer in the light-emitting diode provided in the embodiment of the present disclosure includes an insulating material layer and a metal barrier layer. By embedding the metal barrier layer in the insulating material layer, the metal barrier layer is used to resist fine particles on the surface of the insulating material layer. Prevent fine particles from penetrating the insulating layer under high-voltage bonding conditions, so as to avoid the metal materials on both sides of the insulating layer from being turned on, which may cause leakage failure of the light-emitting diode. At the same time, the metal barrier layer is wrapped with an insulating material layer, which can also avoid the problem of short circuit caused by the metal barrier layer connecting with other film layers, thereby improving the reliability of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 It is a bonding schematic diagram of a light emitting diode provided by the related technology;

[0020] Figure 2 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 3 is a schematic structural diagram of an insulating layer provided by an embodiment of the present disclosure;

[0022] Figure 4 is a schematic structural diagram of an insulating layer provided by an embodiment of the present disclosure;

[0023] Figure 5 is a schematic structural diagram of an insulating layer provided by an embodiment of the present disclosure;

[0024] Figure 6 is a flow chart of manufacturing a light emitting diode provided by an embodiment of the present disclosure;

[0025] Figure 7 It is a preparation state diagram of a light emitting diode provided by the present disclosure;

[0026] Figure 8 It is a preparation state diagram of a light emitting diode provided by the implementation of the present disclosure.

[0027] The descriptions of the marks in the figure are as follows:

[0028] 10. Substrate;

[0029] 20, epitaxial layer; 21, first semiconductor layer; 211, second groove; 22, multi-quantum well layer; 23, second semiconductor layer; 231, first groove;

[0030] 30. Electrode;

[0031] 40. insulating layer; 41. insulating material layer;

[0032] 42. Metal barrier layer; 421. Adhesion metal layer; 422. Compression metal layer; 423. Interception metal layer;

[0033] 50. transparent conductive layer; 51. reflective layer;

[0034] 60. Solder pad;

[0035] 70. Conductive substrate;

[0036] 80. Bonding metal layer;

[0037] 90. Fine particles. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0039] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] Figure 1 This is a schematic diagram of a light-emitting diode bonding provided by the related technology. Figure 1 As shown, before bonding, an epitaxial layer 20 is grown on the substrate 10 , an electrode 30 is provided on the surface of the epitaxial layer 20 , an insulating layer 40 is located on the surface of the epitaxial layer 20 away from the substrate 10 , and the insulating layer 40 wraps the electrode 30 .

[0041] During the bonding process, a bonding metal layer 80 is formed on the surface of the insulating layer 40 away from the substrate 10 and the surface of the conductive substrate 70 ; then, under high temperature and high pressure conditions, the two bonding metal layers 80 are bonded together.

[0042] like Figure 1 As shown, during the process of LED bonding, fine particles 90 will remain on the surface of some LEDs to a greater or lesser extent. Under high-voltage bonding conditions, these fine particles 90 will squeeze and break the insulating layer 40, causing the metal materials on both sides of the insulating layer 40 to be conductive, thereby causing the LED to fail due to leakage.

[0043] To this end, an embodiment of the present disclosure provides a light emitting diode. Figure 2 Schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 2 As shown, the light emitting diode includes: an epitaxial layer 20 , an electrode 30 and an insulating layer 40 . The electrode 30 is located on the surface of the epitaxial layer 20 , and the insulating layer 40 is located on the surface of the electrode 30 .

[0044] Figure 3 Schematic diagram of the structure of an insulating layer 40 provided in an embodiment of the present disclosure. Figure 3 As shown, the insulating layer 40 includes an insulating material layer 41 and a metal barrier layer 42 , and the metal barrier layer 42 is located in the insulating material layer 41 .

[0045] Exemplarily, the insulating material layer 41 has a first surface and a second surface opposite to each other, the first surface is connected to the surface of the epitaxial layer 20 , and the metal barrier layer 42 is located in the insulating material layer 41 and between the first surface and the second surface.

[0046] The insulating layer 40 in the light-emitting diode provided in the embodiment of the present disclosure includes an insulating material layer 41 and a metal barrier layer 42. By embedding the metal barrier layer 42 in the insulating material layer 41, the metal barrier layer 42 is used to resist fine particles on the surface of the insulating material layer 41. Prevent fine particles from penetrating the insulating layer 40 under high-voltage bonding conditions, so as to avoid the metal materials on both sides of the insulating layer 40 being turned on, which may cause leakage failure of the light-emitting diode. At the same time, the metal barrier layer 42 is wrapped with the insulating material layer 41, which can also avoid the problem of short circuit caused by the metal barrier layer 42 connecting with other film layers, thereby improving the reliability of the light-emitting diode.

[0047] Alternatively, if Figure 3 As shown, the metal barrier layer 42 includes two adhesion metal layers 421 and a pressure-resistant metal layer 422 , and the pressure-resistant metal layer 422 is sandwiched between the two adhesion metal layers 421 .

[0048] The elongation of the pressure-resistant metal layer 422 is higher than that of the adhesion metal layer 421 , and the adhesion force between the adhesion metal layer 421 and the insulating material layer 41 is higher than that between the pressure-resistant metal layer 422 and the insulating material layer 41 .

[0049] An adhesion metal layer 421 is provided in the metal barrier layer 42, and the metal barrier layer 42 can be stably connected to the insulating material layer 41 by utilizing the good adhesion between the adhesion metal layer 421 and the insulating material layer 41. A compression metal layer 422 with a high elongation is provided, and the compression metal layer 422 with good ductility is utilized to buffer the bonding pressure, and can resist the extrusion force exerted on the insulating layer 40 by fine particles during the bonding process, so that the insulating material layer 41 is not easy to break.

[0050] Exemplarily, the adhesion metal layer 421 includes a Ti layer. Metal Ti has good adhesion and can firmly connect the metal barrier layer 42 and the insulating material layer 41 together.

[0051] Optionally, the pressure-resistant metal layer 422 includes at least one of an Au layer and an Al layer.

[0052] Exemplarily, the compression-resistant metal layer 422 includes an Au layer. Au with good ductility is used to buffer the bonding pressure, so as to resist the extrusion force exerted by fine particles on the insulating layer 40 during the bonding process.

[0053] Alternatively, if Figure 3 As shown, the metal barrier layer 42 further includes an intercepting metal layer 423 , and the intercepting metal layer 423 is sandwiched between the pressure-resistant metal layer 422 and any adhesion metal layer 421 .

[0054] like Figure 2 As shown, since the bonding metal layer 80 needs to fill the holes on the surface of the epitaxial layer 20 during the bonding process, the bonding metal layer 80 has good fluidity. Therefore, the intercepting metal layer 423 is provided to block the migration of the bonding metal of the metal, so as to prevent the metal from migrating to other film layers and causing leakage failure.

[0055] Optionally, the intercepting metal layer 423 includes at least one of a Pt layer and a Ti layer.

[0056] Exemplarily, the intercepting metal layer 423 may be a Pt layer.

[0057] Optionally, the insulating material layer 41 may be at least one of a silicon oxide layer, a titanium oxide layer and an aluminum oxide layer.

[0058] Exemplarily, the insulating material layer 41 may be a silicon oxide layer.

[0059] Optionally, the thickness of the adhesion metal layer 421 is 1 nm to 20 nm. Providing a thinner adhesion metal layer 421 can save costs.

[0060] Exemplarily, the thickness of the adhesion metal layer 421 is 10 nm.

[0061] Optionally, the thickness of the pressure-resistant metal layer 422 is 100 nm to 300 nm. Providing a thicker pressure-resistant metal layer 422 can enhance the ability of the metal barrier layer 42 to buffer the bonding pressure and prevent the insulating layer 40 from being easily damaged.

[0062] Exemplarily, the thickness of the pressure-resistant metal layer 422 is 200 nm.

[0063] Optionally, the intercepting metal layer 423 has a thickness of 50 nm to 150 nm. Providing a thicker intercepting metal layer 423 can block metal migration and prevent the metal from migrating to other film layers and causing leakage failure.

[0064] Exemplarily, the thickness of the intercepting metal layer 423 is 100 nm.

[0065] Optionally, the insulating layer 40 includes at least two metal barrier layers 42 , and the at least two metal barrier layers 42 are arranged between the first surface and the second surface.

[0066] In one implementation of the present disclosure, Figure 4 Schematic diagram of the structure of an insulating layer 40 provided in an embodiment of the present disclosure. Figure 4 As shown, the insulating layer 40 includes two metal barrier layers 42 , and the two metal barrier layers 42 are arranged at an interval.

[0067] like Figure 4 As shown, one metal barrier layer 42 includes an adhesion metal layer 421, an anti-pressure metal layer 422 and an adhesion metal layer 421 stacked in sequence. Another metal barrier layer 42 includes an adhesion metal layer 421, an anti-pressure metal layer 422, an intercepting metal layer 423 and an adhesion metal layer 421 stacked in sequence.

[0068] Only one intercepting metal layer 423 is required to block metal migration. Therefore, when multiple metal barrier layers 42 are provided, the intercepting metal layer 423 can be provided in only one metal barrier layer 42 to save costs and improve preparation efficiency.

[0069] In another implementation of the present disclosure, Figure 5 Schematic diagram of the structure of an insulating layer 40 provided in an embodiment of the present disclosure. Figure 5 As shown, the insulating layer 40 includes two metal barrier layers 42 , and the two metal barrier layers 42 are arranged at an interval.

[0070] like Figure 5 As shown, the two metal barrier layers 42 each include an adhesion metal layer 421 , a pressure-resistant metal layer 422 , an interception metal layer 423 and an adhesion metal layer 421 which are stacked in sequence.

[0071] For example, one of the metal barrier layers 42 may be located on the first surface or the second surface, that is, the metal barrier layer 42 is directly in contact with the bonding metal layer 80 or the electrode 30 to prevent fine particles from squeezing the insulating material layer 41 and causing cracks during the bonding process.

[0072] Optionally, the orthographic projection of the metal barrier layer 42 on the surface of the epitaxial layer 20 away from the electrode 30 is the first projection, and the orthographic projection of the insulating material layer 41 on the surface of the epitaxial layer 20 away from the electrode 30 is the second projection.

[0073] In the embodiment of the present disclosure, the ratio of the area of ​​the first projection to the area of ​​the second projection is greater than or equal to 0.8.

[0074] By controlling the orthographic projection of the metal barrier layer 42 on the epitaxial layer 20 to occupy more than 80% of the orthographic projection area of ​​the insulating material layer 41 on the epitaxial layer 20, the metal barrier layer 42 can cover most of the insulating material layer 41. In this way, the metal barrier layer 42 protects most of the insulating material layer 41 and prevents the insulating material layer 41 from being easily squeezed by the bonding pressure.

[0075] Alternatively, if Figure 2 As shown, the light emitting diode further includes a transparent conductive layer 50 , a bonding pad 60 , a conductive substrate 70 and a bonding metal layer 80 .

[0076] like Figure 2 As shown, the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 stacked in sequence, the transparent conductive layer 50 is located on the surface of the first conductive layer away from the second semiconductor layer 23, the electrode 30 is located on the surface of the transparent conductive layer 50 away from the second semiconductor layer 23, and the electrode 30 is electrically connected to the transparent conductive layer 50.

[0077] Optionally, the transparent conductive layer 50 may be an indium tin oxide (ITO) layer, which has good transmittance and low resistivity.

[0078] For example, the transparent conductive layer 50 may be an indium zinc oxide (IZO) layer, which has good transmittance and low resistivity.

[0079] Among them, using an ITO layer or an IZO layer as the transparent conductive layer 50 can allow more light to be transmitted from the transparent conductive layer 50, thereby ensuring the light output effect; at the same time, due to the low resistivity, the electrode 30 is stacked on the transparent conductive layer 50, so that the carriers can be more efficiently conducted from the electrode 30 to the epitaxial layer 20, thereby improving the injection efficiency.

[0080] Exemplarily, the thickness of the transparent conductive layer 50 may be 600 angstroms to 2000 angstroms. For example, the thickness of the transparent conductive layer 50 is 1500 angstroms.

[0081] Optionally, one of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

[0082] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0083] Optionally, the n-type layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0084] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0085] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0086] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0087] Optionally, the p-type layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0088] like Figure 2 As shown, the surface of the second semiconductor layer 23 away from the first semiconductor layer 21 has a first groove 231 exposing the transparent conductive layer 50 . The pad 60 is located in the first groove 231 and is electrically connected to the transparent conductive layer 50 .

[0089] By providing the first groove 231, the pad 60 is electrically connected to the transparent conductive layer 50 through the first groove 231, so that the current on the pad 60 can be injected into the electrode 30. Since the pad 60 and the electrode 30 are respectively arranged on opposite sides of the transparent conductive layer 50, and the conductive substrate 70 is arranged on the same side as the electrode 30, by arranging the pad 60 on the other side of the transparent conductive layer 50, a vertical light emitting diode can be obtained, which can overcome the current congestion problem that is easy to occur in a horizontal structure or flip-chip structure light emitting diode, and improve the heat dissipation effect of the light emitting diode.

[0090] like Figure 2 As shown, the surface of the first semiconductor layer 21 away from the second semiconductor layer 23 has a second groove 211 exposing the second semiconductor layer 23, the insulating layer 40 is located on the surface of the first semiconductor layer 21 away from the second semiconductor layer 23 and is located in the second groove 211, the insulating layer 40 located in the second groove 211 has a via hole exposing the second semiconductor layer 23, the bonding metal layer 80 is located on the second surface of the insulating layer 40, and the bonding metal layer 80 is located in the second groove 211 and is electrically connected to the second semiconductor layer 23, and the conductive substrate 70 is located on the surface of the bonding metal layer 80 away from the insulating layer 40.

[0091] By opening the second groove 211 to expose the second semiconductor layer 23, the conductive substrate 70 can be electrically connected to the second semiconductor layer 23 through the bonding metal layer 80. When the light-emitting diode needs to be controlled to emit light, power is supplied to the conductive substrate 70 and the pad 60 respectively, and current can be injected into the first semiconductor layer 21 and the second semiconductor layer 23 respectively, so as to achieve the purpose of controlling the light-emitting diode to emit light.

[0092] Exemplarily, optionally, the bonding metal layer 80 may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0093] The thickness of the first Al layer is 8000 angstroms to 12000 angstroms, the thickness of the first Ti layer is 100 angstroms to 500 angstroms, the thickness of the second Al layer is 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms, and the thickness of the Au layer is 2000 angstroms to 5000 angstroms.

[0094] For example, the thickness of the first Al layer is 10000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10000 angstroms, the thickness of the second Ti layer is 1000 angstroms, and the thickness of the Au layer is 3000 angstroms.

[0095] Exemplarily, the conductive substrate 70 may be a silicon substrate.

[0096] Alternatively, if Figure 2As shown, the light emitting diode further includes a reflective layer 51 , which is located on a surface of the transparent conductive layer 50 away from the epitaxial layer 20 , and the electrode 30 is located on a surface of the transparent conductive layer 50 away from the epitaxial layer 20 , and the electrode 30 covers the reflective layer 51 .

[0097] The reflective layer can be used to reflect the light emitted from the epitaxial layer 20 , so that more light can be emitted from the light-emitting surface of the epitaxial layer 20 , thereby improving the light-emitting intensity of the light-emitting diode.

[0098] At the same time, the reflective layer is also covered with an electrode 30 which can prevent the metal in the reflective layer from migrating upwards, and the electrode 30 is used to connect to an external power source to supply electricity to the epitaxial layer 20 .

[0099] Optionally, the reflective layer includes an Ag layer, a Ni layer and a TiW layer stacked in sequence.

[0100] Since Ag has a good reflective effect, providing an Ag layer in the reflective layer can enhance the reflection of light by the reflective layer and improve the light emitting brightness of the light emitting surface of the light emitting diode.

[0101] The Ni layer has good corrosion resistance and wear resistance, and the TiW layer can be successfully deposited on other films as an adhesion layer without peeling or cracking. The alternating stacked Ni and TiW layers can act as a barrier layer to protect the silver mirror.

[0102] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0103] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0104] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0105] Optionally, the electrode 30 includes a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer and a Ti layer stacked in sequence, and the thickness of each metal layer is 30 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 500 angstroms, 2000 angstroms and 500 angstroms respectively.

[0106] Figure 6 FIG. 1 is a flow chart of manufacturing a light emitting diode according to an embodiment of the present disclosure. Figure 6 As shown, the preparation method comprises:

[0107] Step S11 : preparing an epitaxial layer 20 on the substrate 10 .

[0108] For example, the substrate may be a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the LED has good luminous effect and stability.

[0109] The process of preparing the epitaxial layer 20 may include the following steps:

[0110] The first step, such as Figure 7 As shown, the epitaxial layer 20 grown on the sapphire substrate includes a second semiconductor layer 23, a multi-quantum well layer 22 and a first semiconductor layer 21 which are stacked in sequence.

[0111] The sapphire substrate may be pre-treated, placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0112] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0113] For example, the first semiconductor layer 21 may be an n-type layer, and the second semiconductor layer 23 may be a p-type layer.

[0114] Optionally, the n-type layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0115] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 torr to 300 torr.

[0116] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0117] When growing the multi-quantum well layer 22, the pressure of the MOCVD reaction chamber is controlled at 200 torr. When growing the InGaN quantum well layer, the temperature of the reaction chamber is 760° C. to 780° C. When growing the GaN quantum barrier layer, the temperature of the reaction chamber is 860° C. to 890° C.

[0118] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0119] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0120] Optionally, the p-type layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0121] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0122] Step 2: etching the epitaxial layer 20 to form a second groove 211 on the surface of the first semiconductor layer 21 to expose the second semiconductor layer 23 .

[0123] Step 3: forming a transparent conductive layer 50 on the surface of the first semiconductor layer 21 .

[0124] The transparent conductive layer 50 is located outside the second groove 211 .

[0125] Exemplarily, the transparent conductive layer 50 is an indium tin oxide layer or an indium zinc oxide layer.

[0126] Exemplarily, the thickness of the transparent conductive layer 50 is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer 50 is 200 angstroms.

[0127] Step S12 : forming an electrode 30 and an insulating layer 40 on the surface of the epitaxial layer 20 , such that the insulating layer 40 wraps the electrode 30 .

[0128] Among them, the insulating layer 40 includes: an insulating material layer 41 and a metal barrier layer 42, the insulating material layer 41 has a first surface and a second surface opposite to each other, the first surface is connected to the surface of the epitaxial layer 20, the metal barrier layer 42 is located in the insulating material layer 41, and the metal barrier layer 42 is located between the first surface and the second surface.

[0129] like Figure 7 As shown, the method may specifically include: first, forming a reflective layer and an electrode 30 on the surface of the transparent conductive layer 50 , wherein the electrode 30 covers the reflective layer. Then, forming an insulating layer 40 , such that the insulating layer 40 wraps the electrode 30 and the transparent conductive layer 50 .

[0130] Step S13: evaporating or coating the bonding metal layer 80 on the second surface of the insulating layer 40 and the surface of the conductive substrate 70, bonding the conductive substrate 70 to the side where the second surface of the insulating layer 40 is located, and removing the substrate.

[0131] Specifically, it may include: first, Figure 8As shown, a bonding metal layer 80 is formed on the second surface of the insulating layer 40 and in the second groove 211 , so that the bonding metal layer 80 is electrically connected to the second semiconductor layer 23 through the second groove 211 .

[0132] Then, if Figure 8 As shown, a bonding metal layer 80 is formed on the conductive substrate 70 , and the bonding metal layer 80 of the conductive substrate 70 is bonded to the bonding metal layer 80 on the epitaxial layer 20 .

[0133] Exemplarily, the conductive substrate 70 may be a silicon substrate.

[0134] Next, the sapphire substrate is removed by laser lift-off to expose the second semiconductor layer 23 .

[0135] After step S13, the method further includes: etching the second semiconductor layer 23 to form a first groove 231 exposing the transparent conductive layer 50, and forming a pad 60 in the first groove 231, so as to obtain Figure 2 The light emitting diodes shown.

[0136] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light-emitting diode comprises: an epitaxial layer (20), an electrode (30) and an insulating layer (40), wherein the electrode (30) is located on the surface of the epitaxial layer (20), and the insulating layer (40) is located on the surface of the electrode (30); The insulating layer (40) comprises: an insulating material layer (41) and a metal barrier layer (42), wherein the metal barrier layer (42) is located inside the insulating material layer (41).

2. The light emitting diode according to claim 1, characterized in that: The metal barrier layer (42) comprises two layers of adhesion metal layers (421) and a pressure-resistant metal layer (422), and the pressure-resistant metal layer (422) is sandwiched between the two layers of adhesion metal layers (421).

3. The light emitting diode according to claim 2, characterized in that: The metal barrier layer (42) further comprises an intercepting metal layer (423), wherein the intercepting metal layer (423) is sandwiched between the pressure-resistant metal layer (422) and any one of the adhesion metal layers (421).

4. The light emitting diode according to claim 3, characterized in that: The intercepting metal layer (423) includes at least one of a Pt layer and a Ti layer.

5. The light emitting diode according to claim 2, characterized in that: The adhesion metal layer (421) includes a Ti layer, and the pressure-resistant metal layer (422) includes at least one of an Au layer and an Al layer.

6. The light emitting diode according to claim 3, characterized in that: The thickness of the adhesion metal layer (421) is 1 nm to 20 nm, the thickness of the pressure-resistant metal layer (422) is 100 nm to 300 nm, and the thickness of the interception metal layer (423) is 50 nm to 150 nm.

7. The light emitting diode according to any one of claims 1 to 6, characterized in that: The insulating layer (40) includes at least two metal barrier layers (42).

8. The light emitting diode according to any one of claims 1 to 6, characterized in that: The orthographic projection of the metal barrier layer (42) on the surface of the epitaxial layer (20) away from the electrode (30) is a first projection, and the orthographic projection of the insulating material layer (41) on the surface of the epitaxial layer (20) away from the electrode (30) is a second projection; A ratio of an area of ​​the first projection to an area of ​​the second projection is greater than or equal to 0.

8.

9. The light emitting diode according to any one of claims 1 to 6, characterized in that: The light-emitting diode further comprises a transparent conductive layer (50), a conductive substrate (70) and a bonding metal layer (80); The epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22) and a second semiconductor layer (23) which are stacked in sequence; the transparent conductive layer (50) is located on a surface of the first semiconductor layer (21) away from the second semiconductor layer (23); and the electrode (30) is located on a surface of the transparent conductive layer (50) away from the second semiconductor layer (23) and is electrically connected to the transparent conductive layer (50); The surface of the first semiconductor layer (21) away from the second semiconductor layer (23) has a second groove (211) exposing the second semiconductor layer (23); the insulating layer (40) has a portion located in the second groove (211); the portion of the insulating layer (40) located in the second groove (211) has a via hole exposing the second semiconductor layer (23); the bonding metal layer (80) is located on the surface of the insulating layer (40) away from the epitaxial layer (20), and is located in the second groove (211) and is electrically connected to the second semiconductor layer (23); and the conductive substrate (70) is located on the surface of the bonding metal layer (80) away from the insulating layer (40).

10. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: preparing an epitaxial layer on a substrate; An electrode and an insulating layer are formed on the surface of the epitaxial layer, so that the insulating layer wraps the electrode, the insulating layer comprises: an insulating material layer and a metal barrier layer, the insulating material layer has a first surface and a second surface opposite to each other, the first surface is connected to the surface of the epitaxial layer, the metal barrier layer is located in the insulating material layer, and the metal barrier layer is located between the first surface and the second surface; A bonding metal layer is coated on the second surface of the insulating layer and the surface of the conductive substrate, the conductive substrate is bonded to the side where the second surface of the insulating layer is located, and the substrate is removed.

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