Display panel

Abstract

A display panel is provided. The display panel includes a base layer including a first region including a display region and a transmissive region, and a second region surrounding at least a portion of the first region and having a lower light transmittance than a light transmittance of the first region, a plurality of first pixels, and a dummy electrode, each of the plurality of first pixels includes a plurality of sub-pixels in the display area, and the dummy electrode is located in the display area. Each of a plurality of sub-pixels of the first pixel includes a pixel circuit including a plurality of first transistors and a light emitting element connected to the plurality of first transistors, each of the plurality of first transistors including a semiconductor pattern unit and a gate electrode overlapping the semiconductor pattern unit, and the dummy electrode is spaced apart from the semiconductor pattern unit in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0108112 filed in the Korean Intellectual Property Office on August 18, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display panel having improved reliability and a method of manufacturing the display panel. Background Art

[0004] When light is incident on an active region of a transistor of a display panel, the transistor is degraded by the light. Summary of the invention

[0005] The present disclosure provides a display panel including a transistor having improved reliability.

[0006] The present disclosure provides a method of manufacturing a display panel including a transistor having improved reliability.

[0007] The embodiment of the present disclosure provides a display panel including a base layer, a plurality of first pixels and a dummy electrode, wherein the base layer includes a first region including a display region and a transmission region and a second region around at least a portion of the first region and having a light transmittance lower than that of the first region, each of the plurality of first pixels includes a plurality of sub-pixels and is positioned in the display region, and the dummy electrode is located in the display region. Each of the plurality of sub-pixels in the plurality of first pixels includes a pixel circuit including a plurality of first transistors and a light emitting element connected to the plurality of first transistors.

[0008] Each of the plurality of first transistors includes a semiconductor pattern unit and a gate electrode overlapping the semiconductor pattern unit.

[0009] The dummy electrode is spaced apart from the semiconductor pattern unit in a plan view.

[0010] The display panel also includes a first insulating layer, a second insulating layer and a third insulating layer, a gate electrode and a dummy electrode are positioned on the first insulating layer, the first insulating layer is located on the base layer, the second insulating layer is located on the first insulating layer and covers the gate electrode and the dummy electrode, and the third insulating layer is located on the second insulating layer and covers the second insulating layer.

[0011] The second insulating layer has a refractive index greater than that of the first insulating layer and that of the third insulating layer.

[0012] The second insulating layer includes silicon nitride (SiN x ), and each of the first insulating layer and the third insulating layer includes silicon oxide (SiOx ).

[0013] The dummy electrode extends in one direction and has a continuous shape in a plan view.

[0014] The dummy electrode includes a plurality of sub-dummy electrodes that are spaced apart from each other and at least partially overlap each other when viewed in a direction from the transmission area to the pixel circuit.

[0015] The dummy electrode includes a first portion extending in the second direction and overlapping at least one semiconductor pattern unit when viewed from the transmission area to the display area in the first direction, and a second portion extending in the first direction and connected to both ends of the first portion, respectively.

[0016] The display panel further includes a light blocking layer on the base layer, and the light blocking layer overlaps the display area and does not overlap the transmission area, and the dummy electrode overlaps the light blocking layer.

[0017] The display panel also includes a plurality of light blocking layers on the base layer and a light blocking layer connection line positioned between two of the plurality of light blocking layers and connecting the two light blocking layers to each other.

[0018] The display area includes a plurality of display areas, the first area further includes a line area positioned between the plurality of display areas, and the transmission area is around the display area and the line area.

[0019] The dummy electrode and the gate electrode include the same material.

[0020] The display panel also includes a plurality of second pixels, each of the plurality of second pixels includes a plurality of sub-pixels and is positioned in the second region, each of the plurality of sub-pixels in the plurality of second pixels includes a pixel circuit, the pixel circuit includes a plurality of second transistors and a light-emitting element connected to the plurality of second transistors, and the plurality of sub-pixels in the plurality of first pixels are larger than the plurality of sub-pixels included in the plurality of second pixels, and the plurality of sub-pixels included in the plurality of second pixels are configured to emit light of the same color as the plurality of sub-pixels in the plurality of first pixels.

[0021] Each of the plurality of first pixels includes a first sub-pixel configured to emit a first color light, a second sub-pixel configured to emit a second color light, and two third sub-pixels configured to emit a third color light, the first sub-pixel is spaced apart from the second sub-pixel in one direction, one of the two third sub-pixels is spaced apart from the other of the two third sub-pixels, the first sub-pixel is spaced apart from the one third sub-pixel in a first diagonal direction, the second sub-pixel is spaced apart from the one third sub-pixel in a second diagonal direction, and a light-emitting area of ​​each of the first sub-pixel, the second sub-pixel, and the two third sub-pixels increases in the order of the two third sub-pixels, the second sub-pixel, and the first sub-pixel.

[0022] The density of the plurality of first pixels in the first area is smaller than the density of the plurality of second pixels in the second area.

[0023] When viewed in a direction from the transmission area to the pixel circuit, the dummy electrode overlaps at least two semiconductor pattern units.

[0024] The display panel further includes an electronic module overlapping the first area and positioned below the display panel, and the electronic module includes at least one of a light emitting module and a light receiving module.

[0025] An embodiment of the present disclosure provides a display panel, which includes a base layer, a plurality of first pixels and a dummy electrode, the base layer including a first region including a display region and a transmission region and a second region surrounding at least a portion of the first region and having a light transmittance lower than that of the first region, each of the plurality of first pixels including a plurality of sub-pixels positioned in the display region, and the dummy electrode being located in the display region.

[0026] Each of the plurality of sub-pixels includes a pixel circuit, the pixel circuit includes a plurality of first transistors and a light-emitting element connected to the plurality of first transistors. Each of the plurality of first transistors includes a semiconductor pattern unit and a gate electrode overlapping the semiconductor pattern unit. When viewed in a direction from the transmission area to the pixel circuit, at least a portion of the semiconductor pattern unit is blocked by the dummy electrode.

[0027] The display panel also includes a first insulating layer, a second insulating layer and a third insulating layer, a gate electrode and a dummy electrode are positioned on the first insulating layer, the first insulating layer is located on the base layer, the second insulating layer is located on the first insulating layer and covers the gate electrode and the dummy electrode, and the third insulating layer is located on the second insulating layer and covers the second insulating layer.

[0028] The second insulating layer has a refractive index greater than that of the first insulating layer and that of the third insulating layer.

[0029] The second insulating layer includes at least one bent portion.

[0030] The bent portion overlaps with at least a portion of the dummy electrode.

[0031] When viewed in a direction from the transmission area to the pixel circuit, the number of semiconductor pattern units partially blocked by the dummy electrode is two or more.

[0032] According to the above, since the dummy electrode is provided to the display panel, the transistor is prevented from being photo-degraded. In addition, according to the manufacturing method of the display panel, the dummy electrode can be easily formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other aspects and features of embodiments of the present disclosure will become apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0034] Figure 1 is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0035] Figure 2A is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0036] Figure 2B is a block diagram of an electronic device according to one or more embodiments of the present disclosure;

[0037] Figure 3 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure;

[0038] Figure 4 is a plan view of an active area according to one or more embodiments of the present disclosure;

[0039] Figure 5 is a plan view of a portion of a display area and a portion of a line area according to one or more embodiments of the present disclosure;

[0040] Figure 6 is along Figure 4 A cross-sectional view taken along line II';

[0041] Figure 7 is along Figure 4 A cross-sectional view taken along line II-II';

[0042] Fig. 8A is a cross-sectional view of a display panel according to a comparative example;

[0043] Figure 8B is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0044] Fig. 9is a plan view of a semiconductor pattern according to one or more embodiments of the present disclosure;

[0045] Fig.10 is a plan view showing an overlapping relationship between a semiconductor pattern and a conductive layer according to one or more embodiments of the present disclosure;

[0046] Fig.11A , Fig. 11B and Fig. 11C are plan views respectively illustrating a semiconductor pattern, a conductive layer, and a stacked structure of the semiconductor pattern and the conductive layer according to one or more embodiments of the present disclosure;

[0047] Fig. 12A is a plan view of a display module according to one or more embodiments of the present disclosure;

[0048] Fig. 12B is a plan view of a display module according to one or more embodiments of the present disclosure; and

[0049] Fig. 12C is a plan view of a display module according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0050] The present disclosure can be variously modified and implemented in many different forms, and therefore specific embodiments will be illustrated in the drawings and described in detail below. However, the present disclosure should not be limited to the specific disclosed form, and can be interpreted as including all modifications, equivalents and / or substitutions included in the spirit and scope of the present disclosure.

[0051] In the present disclosure, it should be understood that when an element (or region, layer or portion) is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected to or coupled to the other element or layer, or intervening elements or layers may be present.

[0052] Throughout the specification, the same reference numerals refer to the same elements. In the accompanying drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0053] It should be understood that although the terms first, second, etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. Unless otherwise clearly indicated in the context, the singular forms "a", "an", and "the" as used herein are also intended to include plural forms.

[0054] For convenience of description, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar spatially relative terms may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures.

[0055] It should also be understood that the terms “include” and / or “including” when used in the present disclosure specify the presence of stated features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or clusters thereof.

[0056] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense.

[0057] As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0058] Hereinafter, one or more embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0059] Figure 1 is a perspective view of an electronic device 1000 according to one or more embodiments of the present disclosure. Figure 2A is an exploded perspective view of an electronic device 1000 according to one or more embodiments of the present disclosure. Figure 2B is a block diagram of an electronic device 1000 according to one or more embodiments of the present disclosure. Figure 3is an equivalent circuit diagram of a pixel PX according to one or more embodiments of the present disclosure.

[0060] The electronic device 1000 may be a device activated in response to an electrical signal. The electronic device 1000 may include various embodiments. For example, the electronic device 1000 may include a computer (e.g., a tablet computer, a notebook computer), a smart TV, or the like. In this embodiment, a smart phone will be described as a representative example of the electronic device 1000.

[0061] The electronic device 1000 may display an image IM toward the third direction DR3 through a display surface IS substantially parallel to each of the first direction DR1 and the second direction DR2. The display surface IS through which the image IM is displayed may correspond to a front surface of the electronic device 1000 and a front surface FS of the window WM.

[0062] Hereinafter, the display surface and the front surface of the electronic device 1000 and the front surface of the window WM will be given the same reference numerals. The image IM may include a still image as well as a video. Figure 1 A clock widget and application icons are shown as representative examples of the image IM.

[0063] In the present embodiment, the front (or upper) surface and the rear (or lower) surface of each member of the electronic device 1000 may be defined relative to the direction (e.g., the third direction DR3) in which the image IM is displayed. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3. The separation distance between the front surface and the rear surface may correspond to the thickness of the electronic device 1000 in the third direction DR3.

[0064] According to one or more embodiments, the electronic device 1000 may sense an external input TC applied thereto from the outside. The external input TC may include various types of external inputs, such as a part of the user's body, light, heat, or pressure. In the present embodiment, the external input TC is shown as a user's hand applied to the front surface FS of the electronic device 1000. However, this is merely an example, and the external input TC may be provided in various ways. In addition, the electronic device 1000 may sense an external input TC applied to a side surface or a rear surface of the electronic device 1000 according to its structure, and it should not be limited to a specific embodiment.

[0065] In the present embodiment, the electronic device 1000 may include a first area AA1 defined in the transmissive area TA. The first area AA1 may be an area of ​​the display module 300 to be described later that overlaps with the electronic module 400. Figure 2AA circular shape defined in the upper right end portion as the first area AA1 is shown, however, the present disclosure should not be limited thereto or thereby. The first area AA1 may be provided in the display module 300 in various numbers and shapes according to the number and shape of the electronic modules 400, however, the present disclosure should not be particularly limited thereto.

[0066] The electronic device 1000 may receive an external signal required by the electronic module 400 via the first area AA1, or may provide a signal output from the electronic module 400 to the outside via the first area AA1. According to one or more embodiments of the present disclosure, since the first area AA1 is defined in the transmission area TA, the size of the bezel area BZA defining the transmission area TA may be reduced.

[0067] Reference Figure 2A , the electronic device 1000 may include a window WM, a housing 200, a display module 300, and an electronic module 400. The window WM and the housing 200 may be coupled to each other to provide an exterior of the electronic device 1000.

[0068] The window WM may include an insulating panel. For example, the window WM may include a glass material, a plastic material, or a combination thereof.

[0069] As described above, the front surface FS of the window WM may define the front surface FS of the electronic device 1000. The transmissive area TA may be an optically transparent area. For example, the transmissive area TA may be an area having a visible light transmittance of about 90% or more.

[0070] The bezel area BZA may be an area having a relatively lower transmittance than the transmission area TA. The bezel area BZA may define the shape of the transmission area TA. The bezel area BZA may be adjacent to the transmission area TA and may be around the transmission area TA (eg, may surround the transmission area TA).

[0071] The bezel area BZA may have a desired color (eg, a predetermined color). The bezel area BZA may be defined by a bezel layer provided separately from the transparent substrate defining the transmissive area TA, or may be defined by an ink layer formed by inserting into or printing a color on the transparent substrate.

[0072] The display module 300 may include a display panel EP and a driving circuit IC.

[0073] The display panel EP may display an image IM and may sense an external input TC. The display panel EP may include a display surface IS in which an active area AA and a peripheral area NAA are defined. The active area AA may be an area activated in response to an electrical signal. In the present embodiment, the active area AA may be an area where an image IM is displayed and an external input TC is sensed. The active area AA may be an area in which a plurality of pixels PX are arranged.

[0074] The active area AA may overlap at least a portion of the transmissive area TA in the third direction DR3. As an example, the transmissive area TA may overlap all or at least a portion of the active area AA. Therefore, the user may observe the image IM or provide the external input TC via the transmissive area TA, however, this is only an example. That is, the area through which the image IM is displayed and the area through which the external input TC is sensed may be separated from each other in the active area AA, and they should not be limited to a specific embodiment.

[0075] The peripheral area NAA may be covered by the border area BZA. The peripheral area NAA may be disposed adjacent to the active area AA along an edge or periphery of the active area AA. The peripheral area NAA may be around the active area AA (e.g., may surround the active area AA). The peripheral area NAA may be an area through which the image IM is not displayed. A driving circuit or a driving line may be disposed in the peripheral area NAA to drive the active area AA.

[0076] In the present embodiment, the display panel EP is assembled in a flat state with the active area AA and the peripheral area NAA facing the window WM. However, this is only an example, and a portion of the peripheral area NAA of the display panel EP may be bent. As an example, a portion of the peripheral area NAA may be disposed on the rear surface of the electronic device 1000, and thus, a bezel area BZA observed from the front surface FS of the electronic device 1000 may be reduced. According to one or more embodiments, the display panel EP may be assembled in a state in which a portion of the active area AA is bent. The peripheral area NAA may be omitted from the display panel EP.

[0077] The active area AA may include a first area AA1 and a second area AA2. In the present disclosure, the first area AA1 may have a relatively high light transmittance compared to the second area AA2. The first area AA1 may be defined as an area of ​​the display module 300 that overlaps with an area where the electronic module 400 is disposed in the housing 200. In the present embodiment, the first area AA1 may have a circular shape, however, the first area AA1 may have various shapes, such as a polygonal shape, an elliptical shape, a shape including at least a curve, however, it should not be particularly limited.

[0078] The second area AA2 may be defined as being adjacent to the first area AA1. The second area AA2 may be around at least a portion of the first area AA1 (e.g., may surround at least a portion of the first area AA1). In the present embodiment, the second area AA2 may completely surround the first area AA1, however, this is only an example. According to one or more embodiments, the second area AA2 may be defined as being adjacent to only a portion of the edge of the first area AA1, and should not be particularly limited.

[0079] Reference Figure 2B , the display module 300 may include a display panel EP and an input sensor 320. The display panel EP may generate an image IM. The image IM generated by the display panel EP may be displayed on the display surface IS and may be visible to a user from the outside through the transmission area TA.

[0080] The input sensor 320 may sense the external input TC applied thereto from the outside. As described above, the input sensor 320 may sense the external input TC applied to the window WM.

[0081] Refer again Figure 2A , the display panel EP may include a flat portion FN and a bent portion BN. The flat portion FN may be assembled to be substantially parallel to a plane defined by the first direction DR1 and the second direction DR2. The active area AA may be defined in the flat portion FN.

[0082] The bent portion BN may extend from the flat portion FN and may be bent. The bent portion BN may be assembled to be bent from the flat portion FN and disposed on the rear side of the flat portion FN. Since the bent portion BN overlaps the flat portion FN in a plane when assembled, the bezel area BZA of the electronic device 1000 may be reduced. This is only an example, and the bent portion BN may be omitted from the display panel EP.

[0083] The driving circuit IC may be mounted on the bent portion BN. The driving circuit IC may be provided in a chip form, however, it should not be limited thereto or thereby. According to one or more embodiments, the driving circuit IC may be electrically connected to the display panel EP via a flexible film after being provided to a separate circuit board.

[0084] The driving circuit IC may be electrically connected to the active area AA, and may apply an electrical signal to the active area AA. As an example, the driving circuit IC may include a data driving circuit, and may apply a data signal to the pixel PX arranged in the active area AA. According to one or more embodiments, the driving circuit IC may include a touch driving circuit, and may be electrically connected to the input sensor 320 disposed in the active area AA. This is only an example, and according to one or more embodiments, the driving circuit IC may be designed to include a variety of circuits other than the above-mentioned circuits, or to apply a variety of electrical signals to the active area AA, and it should not be particularly limited.

[0085] In one or more embodiments, the electronic device 1000 may further include a main circuit board electrically connected to the display panel EP and the driving circuit IC. The main circuit board may include various driving circuits for driving the display panel EP or a connector for providing power. The main circuit board may be a rigid printed circuit board (PCB), however, according to one or more embodiments, the main circuit board may be a flexible circuit board, and it should not be particularly limited.

[0086] The electronic module 400 may be disposed below the display module 300. The electronic module 400 may receive an external input via the first area AA1, or may output a signal via the first area AA1. According to one or more embodiments of the present disclosure, since the first area AA1 having a relatively high transmittance is defined in the active area AA, the electronic module 400 may be disposed to overlap with the active area AA in the third direction DR3. Therefore, the size of the bezel area BZA may be prevented from increasing.

[0087] Reference Figure 2B , the electronic device 1000 may include a display module 300, a power module PM, a first electronic module EM1, and a second electronic module EM2. The display module 300, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other. Figure 2B A display panel EP and an input sensor 320 are shown among components of the display module 300 .

[0088] The power module PM may supply power required for overall operations of the electronic device 1000. The power module PM may include a conventional battery module.

[0089] The first and second electronic modules EM1 and EM2 may include various functional modules for operating the electronic device 1000. The first electronic module EM1 may be directly mounted on a motherboard electrically connected to the display panel EP, or may be electrically connected to the motherboard via a connector after being mounted on a separate substrate.

[0090] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and an external interface IF. Some of the modules may be electrically connected to the motherboard through a flexible circuit board without being mounted on the motherboard.

[0091] The control module CM may control the overall operation of the electronic device 1000. The control module CM may be, but is not limited to, a microprocessor. For example, the control module CM may activate or deactivate the display module 300. The control module CM may control other modules such as an image input module IIM, an audio input module AIM, or the like based on a touch signal provided from the display panel EP.

[0092] The wireless communication module TM may use a Bluetooth or WiFi link to send wireless signals to other terminals and / or receive wireless signals from other terminals. The wireless communication module TM may use a universal communication line to send and / or receive voice signals. The wireless communication module TM may include a transmitter TM1 that modulates a signal to be sent and sends the modulated signal and a receiver TM2 that demodulates a signal applied thereto.

[0093] The image input module IIM may process an image signal and may convert the image signal into image data that may be displayed through the display panel EP. The audio input module AIM may receive an external sound signal through a microphone in a recording mode or a voice recognition mode and may convert the external sound signal into electrical voice data.

[0094] The external interface IF may be used as an interface between the control module CM and external devices, such as an external charger, a wired / wireless data port, a card (eg, memory card and SIM / UIM card) socket, and the like.

[0095] The second electronic module EM2 may include an audio output module AOM, a light emitting module LM, a light receiving module LRM, and a camera module CMM. These components may be electrically connected to the display panel EP after being directly mounted on the motherboard, may be electrically connected to the display panel EP via a connector after being mounted on a separate substrate, or may be electrically connected to the first electronic module EM1.

[0096] The audio output module AOM may convert sound data provided from the wireless communication module TM or sound data stored in the memory MM, and may output the converted sound data to the outside.

[0097] The light emitting module LM may generate light and may output light. The light emitting module LM may emit infrared rays. The light emitting module LM may include a light emitting diode (LED) element. The light receiving module LRM may sense infrared rays. When infrared rays having an appropriate level (e.g., a predetermined level) or higher are sensed, the light receiving module LRM may be activated. The light receiving module LRM may include a complementary metal oxide semiconductor (CMOS) sensor. The infrared rays generated by and output from the light emitting module LM may be reflected by an external object (e.g., a finger or face of a user), and the reflected infrared rays may be incident into the light receiving module LRM. The camera module CMM may capture an image of an external object.

[0098] According to one or more embodiments, the electronic module 400 may include at least one of the components of the second electronic module EM2. For example, the electronic module 400 may include at least one of a camera, a speaker, a light sensing sensor, and a heat sensing sensor. The electronic module 400 may sense an external object via the first area AA1, or may provide a sound signal (such as voice) to the outside through the first area AA1. In addition, the electronic module 400 may include a plurality of components, and it should not be limited to a specific embodiment. In one or more embodiments, the electronic module 400 may be attached to the display panel EP by a separate adhesive.

[0099] Refer again Figure 2A, the housing 200 may be coupled with the window WM. The housing 200 may be coupled with the window WM to provide a proper internal space (eg, a predetermined internal space), and may define the exterior of the electronic device 1000. The display module 300 and the electronic module 400 may be accommodated in the internal space.

[0100] The housing 200 may include a material having relatively high rigidity. For example, the housing 200 may include a plurality of frames and / or plates of glass, plastic and / or metal materials, or a combination thereof. The housing 200 may stably protect the components of the electronic device 1000 accommodated in the internal space from external impacts.

[0101] Figure 3 is an equivalent circuit diagram of a pixel PX according to one or more embodiments of the present disclosure.

[0102] In the following, reference will be made to Figure 3 One pixel PX is described in detail.

[0103] The pixel PX may include a light emitting element LD and a pixel circuit PC. The pixel circuit PC may include a plurality of transistors T1 to T7, a storage capacitor Cst, and a boost capacitor Cbs. The transistors T1 to T7 and the storage capacitor Cst may be electrically connected to signal lines SL1, SL2, SLp, SLn, ECL, and DL, a first initialization voltage line VL1, a second initialization voltage line VL2 (or referred to as an anode initialization voltage line), and a drive voltage line PL. According to one or more embodiments, at least one of these lines (e.g., a drive voltage line PL) may be shared by pixels PX adjacent to each other.

[0104] Transistors T1 to T7 may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6, and a second initialization transistor T7 (hereinafter, for the convenience of explanation, transistor T1 and the driving transistor T1, transistor T2 and the switching transistor T2, transistor T3 and the compensation transistor T3, transistor T4 and the first initialization transistor T4, transistor T5 and the operation control transistor T5, transistor T6 and the emission control transistor T6, transistor T7 and the second initialization transistor T7, respectively indicate the same characteristics and are not particularly distinguished in the description).

[0105] The light emitting element LD may include a first electrode (eg, an anode electrode or a pixel electrode) and a second electrode (eg, a cathode electrode or a common electrode). The first electrode of the light emitting element LD may be connected to the driving transistor T1 via the emission control transistor T6 to receive the driving current I LD , and the second electrode can receive the low power supply voltage ELVSS. The light emitting element LD can generate a current having a same value as the driving current I LD The corresponding brightness of the light.

[0106] Some of the transistors T1 to T7 may be N-channel MOSFETs (NMOS), and other transistors of the transistors T1 to T7 may be P-channel MOSFETs (PMOS). As an example, the compensation transistor T3 and the first initialization transistor T4 among the transistors T1 to T7 may be N-channel MOSFETs (NMOS), and other transistors of the transistors T1 to T7 may be P-channel MOSFETs (PMOS).

[0107] According to one or more embodiments, among the transistors T1 to T7, the compensation transistor T3 and the first initialization transistor T4 may be NMOS, and the other transistors may be PMOS. According to one or more embodiments, among the transistors T1 to T7, only one transistor may be NMOS, and the other transistors may be PMOS. According to one or more embodiments, all transistors T1 to T7 may be NMOS or PMOS.

[0108] The signal line may include a first scan line SL1 that sends a first scan signal Sn, a second scan line SL2 that sends a second scan signal Sn', a previous scan line SLp that sends a previous scan signal Sn-1 to a first initialization transistor T4, an emission control line ECL that sends an emission control signal En to an operation control transistor T5 and an emission control transistor T6, a next scan line SLn that sends a next scan signal Sn+1 to a second initialization transistor T7, and a data line DL that crosses the first scan line SL1 and sends a data signal Dm.

[0109] The driving voltage line PL may transmit the driving voltage ELVDD to the driving transistor T1 , and the first initialization voltage line VL1 may transmit the initialization voltage Vint to initialize the driving transistor T1 and the pixel electrode.

[0110] The driving gate electrode of the driving transistor T1 may be connected to the storage capacitor Cst, the driving source region of the driving transistor T1 may be connected to the driving voltage line PL via the operation control transistor T5, and the driving drain region of the driving transistor T1 may be electrically connected to the first electrode of the light emitting element LD via the emission control transistor T6. The driving transistor T1 may receive the data signal Dm in response to the switching operation of the switching transistor T2, and may drive the driving current I LD Supplied to the light emitting element LD.

[0111] The switching gate electrode of the switching transistor T2 may be connected to the first scan line SL1 transmitting the first scan signal Sn, the switching source region of the switching transistor T2 may be connected to the data line DL, and the switching drain region of the switching transistor T2 may be connected to the driving source region of the driving transistor T1, and may be connected to the driving voltage line PL via the operation control transistor T5. The switching transistor T2 may be turned on in response to the first scan signal Sn provided through the first scan line SL1, and may perform a switching operation to transmit the data signal Dm applied to the data line DL to the driving source region of the driving transistor T1.

[0112] The compensation gate electrode of the compensation transistor T3 may be connected to the second scan line SL2. The compensation drain region of the compensation transistor T3 may be connected to the driving drain region of the driving transistor T1, and may be connected to the pixel electrode of the light emitting element LD via the emission control transistor T6. The compensation source region of the compensation transistor T3 may be connected to the first electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving transistor T1. In addition, the compensation source region of the compensation transistor T3 may be connected to the first initialization drain region of the first initialization transistor T4.

[0113] The compensation transistor T3 may be turned on in response to the second scan signal Sn′ applied thereto via the second scan line SL2 and may electrically connect the driving gate electrode and the driving drain region of the driving transistor T1 to allow the driving transistor T1 to be connected in a diode configuration (eg, the driving transistor T1 may be diode connected).

[0114] The first initialization gate electrode of the first initialization transistor T4 may be connected to the previous scan line SLp. The first initialization source region of the first initialization transistor T4 may be connected to the first initialization voltage line VL1. The first initialization drain region of the first initialization transistor T4 may be connected to the first electrode CE1 of the storage capacitor Cst, the compensation source region of the compensation transistor T3, and the driving gate electrode of the driving transistor T1. The first initialization transistor T4 may be turned on in response to the previous scan signal Sn-1 applied thereto through the previous scan line SLp, and may transmit the initialization voltage Vint to the driving gate electrode of the driving transistor T1 to perform an initialization operation of initializing the voltage of the driving gate electrode of the driving transistor T1.

[0115] The operation control gate electrode of the operation control transistor T5 can be connected to the emission control line ECL, the operation control source region of the operation control transistor T5 can be connected to the driving voltage line PL, and the operation control drain region of the operation control transistor T5 can be connected to the driving source region of the driving transistor T1 and the switching drain region of the switching transistor T2.

[0116] The emission control gate electrode of the emission control transistor T6 can be connected to the emission control line ECL, the emission control source region of the emission control transistor T6 can be connected to the driving drain region of the driving transistor T1 and the compensation drain region of the compensation transistor T3, and the emission control drain region of the emission control transistor T6 can be connected to the second initialization drain region of the second initialization transistor T7 and the pixel electrode of the light emitting element LD.

[0117] The operation control transistor T5 and the emission control transistor T6 may be turned on substantially simultaneously (eg, synchronously) in response to an emission control signal En applied thereto via the emission control line ECL, and a driving voltage ELVDD may be applied to the light emitting element LD to allow a driving current I LD Flows through the light emitting element LD.

[0118] The second initialization gate electrode of the second initialization transistor T7 may be connected to the next scan line SLn, the second initialization drain region of the second initialization transistor T7 may be connected to the emission control drain region of the emission control transistor T6 and the pixel electrode of the light emitting element LD, and the second initialization source region of the second initialization transistor T7 may be connected to the second initialization voltage line VL2 to receive the anode initialization voltage Aint. The second initialization transistor T7 may be turned on in response to the next scan signal Sn+1 applied thereto via the next scan line SLn to initialize the pixel electrode of the light emitting element LD.

[0119] According to one or more embodiments, the second initialization transistor T7 may be connected to the emission control line ECL and may be driven in response to the emission control signal En. Positions of the source region and the drain region may vary from each other according to the type of transistor (eg, p-type or n-type).

[0120] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 of the storage capacitor Cst may be connected to the driving gate electrode of the driving transistor T1, and the second electrode CE2 of the storage capacitor Cst may be connected to the driving voltage line PL. The storage capacitor Cst may be charged with charges corresponding to the difference between the voltage of the driving gate electrode of the driving transistor T1 and the driving voltage ELVDD.

[0121] The boosting capacitor Cbs may include a first electrode CE1' and a second electrode CE2'. The first electrode CE1' of the boosting capacitor Cbs may be connected to the first electrode CE1 of the storage capacitor Cst, and the second electrode CE2' of the boosting capacitor Cbs may receive the first scan signal Sn. The boosting capacitor Cbs may boost the voltage of the driving gate electrode of the driving transistor T1 at a time point when the supply of the first scan signal Sn is stopped, and thus, may compensate for a voltage drop of the driving gate electrode.

[0122] A detailed operation of each pixel PX according to one or more embodiments is as follows.

[0123] When a previous scan signal Sn-1 is supplied via the previous scan line SLp during the initialization period, the first initialization transistor T4 may be turned on in response to the previous scan signal Sn-1, and the driving transistor T1 may be initialized by the initialization voltage Vint supplied from the first initialization voltage line VL1.

[0124] When the first scan signal Sn and the second scan signal Sn' are provided via the first scan line SL1 and the second scan line SL2, respectively, during the data programming period, the switching transistor T2 and the compensation transistor T3 may be turned on in response to the first scan signal Sn and the second scan signal Sn', respectively. In this case, the driving transistor T1 may be connected in a diode configuration (e.g., the driving transistor T1 may be diode-connected) through the turned-on compensation transistor T3, and may be forward biased.

[0125] Then, a compensation voltage Dm+Vth (Vth is a negative (-) value) obtained by subtracting a threshold voltage Vth of the driving transistor T1 from the data signal Dm supplied from the data line DL may be applied to the driving gate electrode of the driving transistor T1.

[0126] The driving voltage ELVDD and the compensation voltage Dm+Vth may be applied to both ends of the storage capacitor Cst, respectively, and the storage capacitor Cst may be charged with charges corresponding to a voltage difference between both ends thereof.

[0127] During the light emission period, the operation control transistor T5 and the emission control transistor T6 may be turned on by the emission control signal En provided from the emission control line ECL. A driving current I according to the difference between the voltage of the driving gate electrode of the driving transistor T1 and the driving voltage ELVDD may be generated. LD , and the driving current I LD The light emitting diode LD can be supplied via the emission control transistor T6.

[0128] Figure 4 is a plan view of an active area AA according to one or more embodiments of the present disclosure. Figure 5 is a plan view of a portion of a display area and a portion of a line area according to one or more embodiments of the present disclosure. Figure 6 is along Figure 4 A cross-sectional view taken along line II'. Figure 7 is along Figure 4 A cross-sectional view taken along line II-II'.

[0129] In the following, reference is made to Figure 4 To describe the effective area AA.

[0130] The active area AA may include a first area AA1 and a second area AA2 .

[0131] The first pixel EP1 disposed in the first area AA1 and the second pixel EP2 disposed in the second area AA2 may have the same Figure 3 The pixel PX shown in FIG. 1 is substantially the same as the equivalent circuit diagram, differing only in size.

[0132] The second area AA2 may be defined adjacent to the first area AA1. The second area AA2 may be around at least a portion of the first area AA1 (eg, may surround at least a portion of the first area AA1).

[0133] The first area AA1 may be defined as a portion of the display module 300 and the electronic module 400 (see Figure 2A ) is disposed in the housing 200 and overlaps with the area. The first area AA1 may have a relatively high light transmittance compared to the second area AA2. Figure 2A The first area AA1 having a circular shape is shown, however, the present disclosure should not be limited thereto or thereby. According to one or more embodiments, the first area AA1 may have various shapes such as a polygonal shape, an elliptical shape, a shape including at least a curve, and it should not be particularly limited.

[0134] Reference Figure 4 , the first area AA1 may include a display area BA, a line area BL, and a transmission area BT.

[0135] The plurality of display areas BA may be arranged in the first and second directions DR1 and DR2 in the first area AA1. The plurality of display areas BA may be spaced apart from each other to secure a space defined with the transmission area BT within the first area AA1 in a plan view. Figure 4 A structure is shown in which a plurality of display areas BA are spaced apart from each other in the first direction DR1 and the second direction DR2 and are arranged along the first direction DR1 and the second direction DR2. However, the plurality of display areas BA may contact each other in one direction as long as a space for the transmission area BT to be defined is ensured on a plane. As an example, the plurality of display areas BA may be spaced apart from each other in the first direction DR1 and may contact each other in the second direction DR2.

[0136] Each of the plurality of display areas BA may have a quadrangular shape. Figure 4 A structure in which the display area BA has a rectangular shape with long sides extending in the second direction DR2 and short sides extending in the first direction DR1 is shown as a representative example, however, the shape of the display area BA should not be limited thereto or thereby.

[0137] The first pixel EP1 may be defined in the display area BA.

[0138] The first pixel EP1 may include a first subpixel E11, a second subpixel E12, a third-first subpixel E13a, and a third-second subpixel E13b. As an example, the first pixel EP1 may include one first subpixel E11, one second subpixel E12, and two third subpixels E13a and E13b.

[0139] When viewed in a plane, Figure 4 The two inclined diamond shapes and the two inclined rectangular shapes defined in the display area BA may be formed by a pixel defining layer PDL (refer to Figure 6 ) defined opening OP (refer to Figure 6 ) defined by the light emitting area PXA (refer to Figure 6 ) shape. However, for the convenience of explanation, Figure 4 The inclined diamond shapes in the display area BA in FIG. 1 are referred to as first sub-pixels E11 and second sub-pixels E12, and Figure 4 The inclined rectangular shapes in the display area BA are referred to as the third-first subpixel E13a and the third-second subpixel E13b (hereinafter, for the convenience of explanation, the third subpixel E13a and the third-first subpixel E13a, and the third subpixel E13b and the third-second subpixel E13b, respectively indicate the same features and are not particularly distinguished in the description).

[0140] According to one or more embodiments, a plurality of sub-pixels may be provided in one display area BA. As an example, four sub-pixels may be arranged in one display area BA, and at least two of the four sub-pixels may provide light having the same color.

[0141] As an example, the first subpixel E11, the second subpixel E12, the third-first subpixel E13a, and the third-second subpixel E13b may be arranged to be spaced apart from each other in one display area BA. As an example, the first subpixel E11 and the second subpixel E12 may be spaced apart from each other in the second direction DR2, the third-first subpixel E13a and the third-second subpixel E13b may be spaced apart from each other in the second direction DR2, the first subpixel E11 may be spaced apart from the third-first subpixel E13a in the fifth direction DR5, and the second subpixel E12 may be spaced apart from the third-first subpixel E13a in the fourth direction DR4.

[0142] The first subpixel E11 and the second subpixel E12 may have an inclined rhombus shape in a plan view. The third subpixels E13a and E13b may have an inclined rectangular shape in a plan view. However, the shapes of the first subpixel E11, the second subpixel E12, the third-first subpixel E13a, and the third-second subpixel E13b in a plan view should not be limited to or thereby, and according to one or more embodiments, they may have a polygonal shape (such as a quadrilateral shape) or a circular shape. The third subpixels E13a and E13b may include a third-first subpixel E13a having a rectangular shape with a long side extending in the fourth direction DR4 and a third-second subpixel E13b having a rectangular shape with a long side extending in the fifth direction DR5.

[0143] The first subpixel E11, the second subpixel E12, the third-first subpixel E13a, and the third-second subpixel E13b may have light emitting areas different from each other. As an example, the light emitting areas of the first subpixel E11, the second subpixel E12, the third-first subpixel E13a, and the third-second subpixel E13b may become larger in the order of the third subpixels E13a and E13b, the second subpixel E12, and the first subpixel E11.

[0144] The first subpixel E11, the second subpixel E12, and the third subpixels E13a and E13b may provide different lights from each other. As an example, the first subpixel E11 may be configured to emit red light, the second subpixel E12 may be configured to emit blue light, and the third subpixels E13a and E13b may be configured to emit green light.

[0145] The line area BL may be disposed between the plurality of display areas BA to connect the plurality of display areas BA. In the case where the plurality of display areas BA are spaced apart from each other in the first direction DR1 and the second direction DR2, four line areas BL adjacent to each other may be arranged adjacent to the display area BA. However, among the line areas BL adjacent to the display area BA disposed at the boundary of the first area AA1, some line areas BL adjacent to the second area AA2 may be omitted.

[0146] The display area BA and the line area BL may form a pixel PX (see Figure 3 ) of the conductive material is patterned, and therefore, when the electronic module 400 (refer to Figure 2A ) when emitting / receiving light, light reflected by the conductive material may deteriorate the performance of the electronic module 400. According to one or more embodiments of the present disclosure, since a light blocking layer BML (refer to Figure 7), thus the degradation of the performance of the electronic module 400 can be improved. This will be described in detail later. Figure 4 , the display area BA and the line area BL in which the light blocking layer BML is disposed in the first area AA1 are shown in a relatively darker color than the transmission area BT.

[0147] According to the present embodiment, the transmission area BT may have a shape defined by the display area BA and the line area BL included in the first area AA1 in a plan view. As an example, the transmission area BT may correspond to an area surrounded by four display areas BA arranged in the first direction DR1 and the second direction DR2 and the line area BL disposed between the four display areas BA.

[0148] In the present embodiment, the transmission region BT may have a shape obtained by removing a small square shape from each of two bottom corners of a larger square shape.

[0149] The transmission area BT may correspond to an area where a conductive material or an insulating layer is patterned or not deposited to improve its light transmittance. Since the first area AA1 includes the transmission area BT, the first area AA1 may have a relatively high light transmittance compared to the second area AA2 that does not include the transmission area BT. Figure 2A )The light emitted and / or received may travel through the transmission area BT.

[0150] Reference Figure 4 , the second pixel EP2 may be disposed in the second area AA2.

[0151] The second pixel EP2 may include a first sub-pixel E21, a second sub-pixel E22, a third-first sub-pixel E23a, and a third-second sub-pixel E23b. As an example, the second pixel EP2 may include one first sub-pixel E21, one second sub-pixel E22, and two third sub-pixels E23a and E23b. Figure 4 The two inclined diamond shapes and the two inclined rectangular shapes defined in the second area AA2 may be formed by a pixel defining layer PDL (refer to Figure 6 ) defined opening OP (refer to Figure 6 ) defined by the light emitting area PXA (refer to Figure 6 ) shape. However, for the convenience of explanation, Figure 4 The inclined diamond shapes in the second area AA2 in FIG. 8 are referred to as first sub-pixels E21 and second sub-pixels E22, and Figure 4 The inclined rectangular shapes in the second area AA2 in FIG. 8 are referred to as third-first subpixel E23a and third-second subpixel E23b.

[0152] According to one or more embodiments, a plurality of sub-pixels may be disposed in the second area AA2. As an example, four sub-pixels may be arranged in the second area AA2, and at least two of the four sub-pixels may provide light having the same color.

[0153] The first subpixel E21, the second subpixel E22, the third-first subpixel E23a, and the third-second subpixel E23b may be arranged to be spaced apart from each other. As an example, the first subpixel E21 and the second subpixel E22 may be spaced apart from each other in the second direction DR2, the third-first subpixel E23a and the third-second subpixel E23b may be spaced apart from each other in the second direction DR2, the first subpixel E21 may be spaced apart from the third-first subpixel E23a in the fifth direction DR5, and the second subpixel E22 may be spaced apart from the third-first subpixel E23a in the fourth direction DR4.

[0154] The arrangement of the first subpixel E21, the second subpixel E22, the third-first subpixel E23a, and the third-second subpixel E23b may be substantially the same as the arrangement of the first subpixel E11, the second subpixel E12, the third-first subpixel E13a, and the third-second subpixel E13b. However, the separation distance between the first subpixel E21, the second subpixel E22, the third-first subpixel E23a, and the third-second subpixel E23b may be smaller than the separation distance between the first subpixel E11, the second subpixel E12, the third-first subpixel E13a, and the third-second subpixel E13b.

[0155] The first subpixel E21 and the second subpixel E22 may have an inclined rhombus shape in a plan view. The third subpixels E23a and E23b may have an inclined rectangular shape in a plan view. However, the shapes of the first subpixel E21, the second subpixel E22, the third-first subpixel E23a, and the third-second subpixel E23b in a plan view should not be limited to or thereby, and may have a polygonal shape (such as a quadrilateral shape) or a circular shape according to one or more embodiments. The third subpixels E23a and E23b may include a third-first subpixel E23a having a rectangular shape with a long side extending in the fourth direction DR4 and a third-second subpixel E23b having a rectangular shape with a long side extending in the fifth direction DR5.

[0156] The first subpixel E21, the second subpixel E22, the third-first subpixel E23a, and the third-second subpixel E23b may have light emitting areas different from each other. As an example, the light emitting areas of the first subpixel E21, the second subpixel E22, the third-first subpixel E23a, and the third-second subpixel E23b may become larger in the order of the third subpixels E23a and E23b, the second subpixel E22, and the first subpixel E21.

[0157] The first subpixel E21, the second subpixel E22, and the third subpixels E23a and E23b may provide different light from each other. As an example, the first subpixel E21 may emit red light, the second subpixel E22 may emit blue light, and the third subpixels E23a and E23b may emit green light.

[0158] Since the first area AA1 includes not only the display area BA but also the transmission area BT, the density of the first pixels EP1 arranged in the first area AA1 is lower than the density of the second pixels EP2 arranged in the second area AA2.

[0159] However, the first pixel EP1 may have a relatively large light emitting area compared to the second pixel EP2. In the case where the subpixels emit light having the same color, the light emitting areas of the first subpixel E11, the second subpixel E12, the third-first subpixel E13a, and the third-second subpixel E13b included in the first pixel EP1 may be larger than the light emitting areas of the first subpixel E21, the second subpixel E22, the third-first subpixel E23a, and the third-second subpixel E23b included in the second pixel EP2. That is, the light emitting area of ​​the first subpixel E11 of the first pixel EP1 may be larger than the light emitting area of ​​the first subpixel E21 of the second pixel EP2, the light emitting area of ​​the second subpixel E12 of the first pixel EP1 may be larger than the light emitting area of ​​the second subpixel E22 of the second pixel EP2, and the light emitting area of ​​each of the third subpixels E13a and E13b of the first pixel EP1 may be larger than the light emitting area of ​​each of the third subpixels E23a and E23b of the second pixel EP2. Therefore, a difference in the amount of light emitted between the first area AA1 and the second area AA2 caused by the density of the first pixels EP1 in the first area AA1 being less than the density of the second pixels EP2 in the second area AA2 may be at least partially compensated.

[0160] Figure 5 is a plan view of a portion of a display area BA and a portion of a line area BL extending from the display area BA according to one or more embodiments of the present disclosure.

[0161] Reference Figure 5 , the first pixel EP1 may be disposed in the display area BA.

[0162] The first pixel EP1 may include a first subpixel E11, a second subpixel E12, a third-first subpixel E13a, and a third-second subpixel E13b. The first subpixel E11 may include a first light emitting element LD11 and a first pixel circuit PC11 electrically connected to the first light emitting element LD11, the second subpixel E12 may include a second light emitting element LD12 and a second pixel circuit PC12 electrically connected to the second light emitting element LD12, the third-first subpixel E13a may include a third-first light emitting element LD13a and a third-first pixel circuit PC13a electrically connected to the third-first light emitting element LD13a, and the third-second subpixel E13b may include a third-second light emitting element LD13b and a third-second pixel circuit PC13b electrically connected to the third-second light emitting element LD13b.

[0163] For the convenience of explanation, Figure 5 , the region in which the first pixel circuit PC11, the second pixel circuit PC12, the third-first pixel circuit PC13a, and the third-second pixel circuit PC13b are provided is shown as a dotted rectangle. The description of the first pixel circuit PC11, the second pixel circuit PC12, the third-first pixel circuit PC13a, and the third-second pixel circuit PC13b corresponds to the pixel circuit PC (refer to Figure 3 ) above, and therefore its details will be omitted.

[0164] Reference Figure 5 , the first pixel circuit PC11, the second pixel circuit PC12, the third-first pixel circuit PC13a and the third-second pixel circuit PC13b can be connected to the first light emitting element LD11, the second light emitting element LD12, the third-first light emitting element LD13a and the third-second light emitting element LD13b in a one-to-one correspondence. According to one or more embodiments of the present disclosure, the pixel circuits and the light emitting elements connected to each other may overlap with each other, however, they should not be limited to this or thereby. According to one or more embodiments, the pixel circuits and the light emitting elements connected to each other may be spaced apart from each other in a plan view and may be connected to each other via connection lines.

[0165] According to one or more embodiments of the present disclosure, the display panel EP may include a dummy electrode DE disposed in the display area BA. The dummy electrode DE may be included in the conductive layer CL (refer to Fig. 11B), which will be described later. The display area BA may have a rectangular shape defined by a short side extending in the first direction DR1 and a long side extending in the second direction DR2 and connected to the short side. The dummy electrode DE may be disposed adjacent to one of the long sides of the display area BA disposed at a lower portion of the display area BA. The dummy electrode DE may extend in the second direction DR2 and may overlap all of the first pixel circuit PC11, the second pixel circuit PC12, the third-first pixel circuit PC13a, and the third-second pixel circuit PC13b.

[0166] However, the present disclosure should not be limited thereto or thereby. According to one or more embodiments, the dummy electrode DE may be provided in plurality, and the plurality of dummy electrodes DE may be arranged to overlap with corresponding pixel circuits among the first pixel circuit PC11, the second pixel circuit PC12, the third-first pixel circuit PC13a, and the third-second pixel circuit PC13b.

[0167] The dummy electrode DE can block the transmission area BT (refer to Figure 4 ) to the display area BA (refer to Figure 8B ), and can protect the transistors T1 to T7 included in the first pixel circuit PC11, the second pixel circuit PC12, the third-first pixel circuit PC13a and the third-second pixel circuit PC13b (refer to Figure 3 The dummy electrode DE may block the light LE travelling from the transmission area BT adjacent to the long side disposed at the lower portion of the display area BA in the first direction DR1 to the display area BA.

[0168] Figure 6 is along Figure 4 A cross-sectional view taken along line II'. Figure 7 is along Figure 4 A cross-sectional view taken along line II-II'. Fig. 8A is a cross-sectional view of a display panel according to a comparative example. Figure 8B is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0169] In the following, reference will be made to Figure 6 The stacking structure in the second area AA2 of the display module 300 is described. For the convenience of explanation, Figure 6 Only one transistor TR-a is shown, and the other transistors are omitted. The transistor TR-a may correspond to the transistors T1 to T7 (e.g., the driving transistor T1, the switching transistor T2, the compensation transistor T3, the first initialization transistor T4, the operation control transistor T5, the emission control transistor T6, and the second initialization transistor T7 (refer to Figure 3 ))one of the.

[0170] The display module 300 may include a display panel EP, an input sensor 320 , a black matrix BM, a color filter 100 , and an overcoat layer OC in a region overlapping the second area AA2 .

[0171] The display panel EP may include a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer 80 .

[0172] The display panel EP may further include a functional layer such as an anti-reflection layer, a refractive index control layer and / or the like. The circuit element layer DP-CL may include at least a plurality of insulating layers and circuit elements. Hereinafter, the insulating layer may include an organic layer and / or an inorganic layer. The display panel EP may include a first insulating layer 10 to a seventh insulating layer 70, however, the present disclosure should not be limited thereto or thereby.

[0173] The insulating layer, the semiconductor layer, and the conductive layer may be formed by a coating or deposition process. Then, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a photolithography process. Thus, a semiconductor pattern, a conductive pattern, and a signal line may be formed.

[0174] The base layer BS may be used as a base layer on which other components of the circuit element layer DP-CL are disposed. The base layer BS may have a structure in which layers including organic materials and layers including inorganic materials are alternately stacked with each other. As an example, the base layer BS may include a first base layer PI1, a first barrier layer BI, and a second base layer PI2.

[0175] The first base layer PI1 may be disposed under the first barrier layer BI. The first base layer PI1 may include an organic material. As an example, the first base layer PI1 may include one or more of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate, polycarbonate (PC), polyetherimide (PEI), and polyethersulfone (PES).

[0176] The first barrier layer BI may be disposed on the first base layer PI1. The first barrier layer BI may include an inorganic material. As an example, the first barrier layer BI may include at least one of silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, silicon nitride, zirconium oxide, and hafnium oxide.

[0177] The second base layer PI2 may be disposed on the first barrier layer BI. The second base layer PI2 may include an organic material. The organic material included in the second base layer PI2 may be the same as the organic material included in the first base layer PI1.

[0178] However, according to one or more embodiments, the base layer BS may be provided as a single layer structure. In this case, the base layer BS may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, however, the material used for the synthetic resin layer should not be particularly limited. In addition, the base layer BS may include glass, metal, or an organic / inorganic composite material.

[0179] A second barrier layer BRL may be disposed on the base layer BS. The second barrier layer BRL may include an inorganic material. As an example, the second barrier layer BRL may include at least one of silicon oxide, aluminum oxide, titanium oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0180] A buffer layer BFL may be disposed on the second barrier layer BRL. The buffer layer BFL may improve adhesion between the second barrier layer BRL and the semiconductor pattern and / or between the second barrier layer BRL and the conductive pattern. The buffer layer BFL may include at least one of silicon oxide and silicon nitride. In addition, the buffer layer BFL may have a single-layer or multi-layer structure of silicon oxynitride, however, it should not be limited thereto or thereby.

[0181] A semiconductor pattern may be provided on the buffer layer BFL. Hereinafter, a semiconductor pattern directly provided on the buffer layer BFL may be defined as a first semiconductor pattern. The first semiconductor pattern may include a silicon semiconductor. As an example, the first semiconductor pattern may include polycrystalline silicon and / or amorphous silicon. The first semiconductor pattern may have different electrical properties depending on whether it is doped or whether it is doped with an N-type dopant or a P-type dopant. The first semiconductor pattern may include a doped region and an undoped region. The doped region may be doped with an N-type dopant or a P-type dopant.

[0182] The source SE, the active region AC, and the drain DR of the transistor TR-a may be formed of a semiconductor pattern. The source SE and the drain DR of the transistor TR-a may be formed to be spaced apart from each other with the active region AC interposed therebetween.

[0183] A connection signal line SCL may be provided on the buffer layer BFL. In a plan view, the connection signal line SCL may be connected to the emission control transistor T6 (refer to Figure 3 ) of the drain D6 (refer to Fig. 9 ).

[0184] The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single layer or a multilayer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0185] In this embodiment, the first insulating layer 10 may be disposed on the buffer layer BFL and may cover the first semiconductor pattern and the connection signal line SCL. In this embodiment, the first insulating layer 10 may include silicon oxide (SiO x ) of a single layer structure. Not only the first insulating layer 10 but also the insulating layer of the circuit element layer DP-CL described later may be an inorganic layer and / or an organic layer and may have a single layer or a multilayer structure. The inorganic layer may include at least one of the above materials.

[0186] The gate electrode GT of the transistor TR-a may be disposed on the first insulating layer 10. The gate electrode GT may be a portion of the metal pattern. The gate electrode GT of the transistor TR-a may overlap the active area AC of the transistor TR-a in the third direction DR3.

[0187] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate electrode GT. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. In the present embodiment, the second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a silicon nitride (SiN x ) single-layer structure.

[0188] An upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the gate electrode GT in the third direction DR3. The upper electrode UE may be a portion of a metal pattern or a portion of a doped semiconductor pattern. A portion of the gate electrode GT and the upper electrode UE overlapping the portion of the gate electrode GT may define a storage capacitor Cst (refer to Figure 3 ). According to one or more embodiments, the upper electrode UE may be omitted.

[0189] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE. In the present embodiment, the third insulating layer 30 may include silicon oxide (SiO x ) or may have a single layer structure in which a plurality of silicon oxides (SiO x ) layers and multiple silicon nitride (SiN x ) layers are alternately stacked. In this case, the layer disposed at the lowest position among the layers included in the third insulating layer 30 may be silicon oxide (SiO x )layer.

[0190] The semiconductor pattern may be disposed on the third insulating layer 30. Hereinafter, the semiconductor pattern directly disposed on the third insulating layer 30 may be defined as a second semiconductor pattern. The second semiconductor pattern may include a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0191] The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the second semiconductor pattern. In this embodiment, the fourth insulating layer 40 may be silicon nitride (SiN x )layer.

[0192] According to one or more embodiments, the fourth insulating layer 40 may be replaced by an insulating pattern. Figure 3 ) of the gate electrodes G31 and G32 (refer to Fig.10 ) may be disposed on the insulating pattern. In this embodiment, the gate electrodes G31 and G32 (see Fig.10 ) may have the same shape as that of the insulating pattern in a plan view.

[0193] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the gate electrodes G31 and G32 (see Fig.10 In this embodiment, the fifth insulating layer 50 may include a silicon oxide layer and a silicon nitride layer. The fifth insulating layer 50 may include a plurality of silicon oxide layers and a plurality of silicon nitride layers alternately stacked with the plurality of silicon oxide layers.

[0194] In one or more embodiments, the first initialization transistor T4 (see Figure 3 ) can be connected to the source, drain and gate electrodes G31 and G32 of the compensation transistor T3 (see Fig.10 ) is formed by the same process as the process of FIG.

[0195] At least one insulating layer may be further disposed on the fifth insulating layer 50. As the present embodiment, the sixth insulating layer 60 and the seventh insulating layer 70 may be disposed on the fifth insulating layer 50. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer and may have a single layer or a multi-layer structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may have a single layer structure of a polyimide-based resin layer.

[0196] However, it should not be limited thereto or thereby. According to one or more embodiments, each of the sixth insulating layer 60 and the seventh insulating layer 70 may include at least one of an acrylic-based resin, a methacrylic-based resin, a polyisoprene-based resin, a vinyl resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin.

[0197] A first connection electrode CNE1 may be disposed on the fifth insulating layer 50 . The first connection electrode CNE1 may be connected to a connection signal line SCL (or a connection electrode) via a first contact hole CH1 defined by the first to fifth insulating layers 10 to 50 .

[0198] A second connection electrode CNE2 may be disposed on the sixth insulating layer 60. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a second contact hole CH-60 defined by the sixth insulating layer 60.

[0199] A first light emitting element LD21 may be disposed on the seventh insulating layer 70. The first light emitting element LD21 may include a first electrode AE, a hole control layer HCL, a light emitting layer EML, an electron control layer eECL, and a second electrode CE sequentially stacked in the third direction DR3.

[0200] The display element layer DP-OLED may include at least a first light emitting element LD21 and a pixel defining layer PDL. The first electrode AE ​​of the first light emitting element LD21 may be disposed on the seventh insulating layer 70. The first electrode AE ​​may be connected to the second connection electrode CNE2 via a third contact hole CH-70 defined by the seventh insulating layer 70. The pixel defining layer PDL may be disposed on the seventh insulating layer 70. The pixel defining layer PDL may be provided with an opening OP defined therethrough. At least a portion of the first electrode AE ​​may be exposed through the opening OP of the pixel defining layer PDL.

[0201] like Figure 6 As shown in , the second area AA2 of the display module 300 may include a light-emitting area PXA and a non-light-emitting area NPXA adjacent to the light-emitting area PXA. The non-light-emitting area NPXA may be around the light-emitting area PXA (e.g., may surround the light-emitting area PXA). In the present embodiment, the light-emitting area PXA may be defined to correspond to the first electrode AE ​​exposed through the opening OP.

[0202] The first sub-pixel E21 may include a first light emitting element LD21 and a driving transistor T1 to a second initializing transistor T7 connected to the first light emitting element LD21 (refer to Figure 3 ).

[0203] In the present embodiment, the light emitting area PXA may be defined to correspond to the first electrode AE ​​exposed through the opening OP. In the present embodiment, the hole control layer HCL may be disposed on the first electrode AE. The hole control layer HCL may include a hole transport layer and a hole injection layer. The light emitting layer EML may be disposed on the hole control layer HCL. In the present embodiment, the patterned light emitting layer EML is shown as a representative example, however, the light emitting layer EML may be commonly disposed throughout a plurality of pixels PX. In this case, the light emitting layer EML may generate white light or green light. In addition, the light emitting layer EML may have a multilayer structure.

[0204] The electron control layer eECL may be disposed on the light emitting layer EML. The electron control layer eECL may include an electron transport layer and an electron injection layer. The second electrode CE may be disposed on the electron control layer eECL. The electron control layer eECL, the hole control layer HCL, and the second electrode CE may be commonly disposed in a plurality of pixels PX.

[0205] The thin film encapsulation layer 80 may be disposed on the second electrode CE. The thin film encapsulation layer 80 may be commonly disposed throughout the plurality of pixels PX. In the present embodiment, the thin film encapsulation layer 80 may directly cover the second electrode CE.

[0206] The thin film encapsulation layer 80 may be disposed on the first light emitting element LD21. The thin film encapsulation layer 80 may include a first inorganic layer 81, an organic layer 82, and a second inorganic layer 83, however, it should not be limited thereto or thereby. According to one or more embodiments, the thin film encapsulation layer 80 may also include a plurality of inorganic layers and a plurality of organic layers.

[0207] The first inorganic layer 81 may be in contact with the second electrode CE. The first inorganic layer 81 may prevent external moisture or oxygen from entering the light emitting layer EML. As an example, the first inorganic layer 81 may include silicon nitride, silicon oxide, or a combination thereof. The first inorganic layer 81 may be formed by a deposition process.

[0208] The organic layer 82 may be disposed on the first inorganic layer 81 and may be in contact with the first inorganic layer 81. The organic layer 82 may provide a flat surface on the first inorganic layer 81. An uneven shape formed on the upper surface of the first inorganic layer 81 or particles existing on the first inorganic layer 81 may be covered by the organic layer 82, and thus, the influence of the surface state of the upper surface of the first inorganic layer 81 on the components formed on the organic layer 82 may be blocked. The organic layer 82 may include an organic material and may be formed by a solution process such as spin coating, slit coating, or an inkjet process.

[0209] The second inorganic layer 83 may be disposed on the organic layer 82 to cover the organic layer 82. Compared with being disposed on the first inorganic layer 81, the second inorganic layer 83 may be stably formed on a relatively flat surface. The second inorganic layer 83 may encapsulate moisture leaked from the organic layer 82 to prevent moisture from flowing from the outside. The second inorganic layer 83 may include silicon nitride, silicon oxide, or a combination thereof. The second inorganic layer 83 may be formed by a deposition process.

[0210] The input sensor 320 may be directly disposed on the thin film encapsulation layer 80. The input sensor 320 may include a plurality of conductive patterns MS1 and MS2 and a sensing insulating layer 90. The sensing insulating layer 90 may include a first sensing insulating layer 91, a second sensing insulating layer 92, and a third sensing insulating layer 93.

[0211] Each of the first sensing insulating layer 91 , the second sensing insulating layer 92 , and the third sensing insulating layer 93 may include at least one of an inorganic material and an organic material.

[0212] The first sensing insulating layer 91 may be disposed on the thin film encapsulation layer 80. The first conductive pattern MS1 ​​may be disposed on the first sensing insulating layer 91 and may be covered by the second sensing insulating layer 92. The second conductive pattern MS2 may be disposed on the second sensing insulating layer 92 and may be covered by the third sensing insulating layer 93.

[0213] Each of the first conductive pattern MS1 ​​and the second conductive pattern MS2 may have conductivity. Each of the first conductive pattern MS1 ​​and the second conductive pattern MS2 may have a single layer structure or a multi-layer structure, and should not be limited thereto or thereby. At least one of the first conductive pattern MS1 ​​and the second conductive pattern MS2 may be provided as a mesh line in a plan view.

[0214] In a plan view, the grid lines forming the first conductive pattern MS1 ​​and the second conductive pattern MS2 may be spaced apart from the light emitting layer EML. Therefore, although the input sensor 320 is directly formed on the display panel EP, the pixels PX (refer to Figure 2B )The light generated can be provided to the user without interference from the input sensor 320.

[0215] The color filter 100 may overlap the light emitting layer EML in the third direction DR3. The color filter 100 may selectively transmit light corresponding to the light provided from the light emitting layer EML. As an example, when the light emitting layer EML provides green light, the color filter 100 may be a green color filter that transmits green light.

[0216] The color filter 100 may include a polymer photosensitive resin and a pigment or dye. As an example, the color filter 100 overlapping with the light-emitting layer EML providing green light may include a green pigment or dye, the color filter 100 overlapping with the light-emitting layer EML providing blue light may include a blue pigment or dye, and the color filter 100 overlapping with the light-emitting layer EML providing red light may include a red pigment or dye.

[0217] However, it should not be limited thereto or thereby, and the color filter 100 overlapping the emission layer EML providing green light may not include a pigment or dye. In this case, the color filter 100 may be transparent, and the color filter 100 may be formed of a transparent photosensitive resin.

[0218] The black matrix BM may be disposed between color filters that provide different light from each other. The black matrix BM may be a pattern having black, for example, a matrix having a lattice shape. The black matrix BM may include a black colorant. The black colorant may include a black pigment or a black dye. The black colorant may include a metal material such as chromium or an oxide thereof, or carbon black.

[0219] An overcoat layer OC may be disposed on the color filter 100 and the black matrix BM. The overcoat layer OC may cover the concavo-convex portions that appear when the color filter 100 and the black matrix BM are formed to provide a flat surface. That is, the overcoat layer OC may be a planarization layer. Figure 2A The described window WM may be coupled to an overcoat layer OC providing a flat surface via an adhesive layer.

[0220] Figure 7 is a cross-sectional view of a portion of each of the display area BA and the transmission area BT of the first area AA1 of the display module 300 . Fig. 8A is a cross-sectional view of a display panel according to a comparative example. Figure 8B is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0221] In the following, reference will be made to Figure 7 The stacking structure in the first area AA1 of the display module 300 is described. Figure 7 Only one transistor TR-b is shown, and other transistors are omitted. For convenience of explanation, the source SE, drain DR and active region AC of the transistor TR-b are shown as being directly disposed on the buffer layer BFL. The transistor TR-b may correspond to the reference Figure 3 One of the transistors T1 to T7 is described.

[0222] The display module 300 may include a display panel EP, an input sensor 320 , a black matrix BM, a color filter 100 , and an overcoat layer OC in a region overlapping the first area AA1 .

[0223] The display panel EP may include a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer 80 .

[0224] The first pixel EP1 (see FIG. Figure 4 ) may include a driving transistor T1 connected to the light emitting element LD13a to a second initialization transistor T7 (refer to Figure 3 ), and the stacked structure of the first pixel EP1 may correspond to the reference Figure 6 The stacked structure of the second pixel EP2 disposed in the second area AA2 is described. Figure 6 The details of the same components will not be described in Figure 7 Repeat in.

[0225] The light blocking layer BML may be disposed in the display area BA of the first area AA1. That is, the light blocking layer BML may overlap with the display area BA and may not overlap with the transmission area BT of the first area AA1. The light blocking layer BML may be disposed between the second barrier layer BRL and the buffer layer BFL. However, in the case where the second barrier layer BRL is omitted, the light blocking layer BML may be disposed between the base layer BS and the buffer layer BFL and should not be particularly limited. The light blocking layer BML may include a metal material.

[0226] Since the light blocking layer BML is disposed on the second barrier layer BRL, a defect in which the conductive material disposed on the base layer BS and the second barrier layer BRL is observed as the electronic module 400 due to external light can be prevented. Figure 2A ), interference between the electronic module 400 and the conductive material disposed on the base layer BS and the second barrier layer BRL may also be reduced or minimized, and thus, performance of the electronic module 400 of the electronic device 1000 may be improved.

[0227] In the transmission region BT, portions of the first to seventh insulation layers 10 to 70 that overlap with the transmission region BT may be omitted. As an example, portions of the first to seventh insulation layers 10 to 70 that overlap with the transmission region BT may not be deposited, or may be removed by a patterning process after being deposited. In the present embodiment, insulation layers other than the sixth insulation layer 60 among the first to seventh insulation layers 10 to 70 may be omitted in the transmission region BT.

[0228] According to the present embodiment, the upper surface BM-U of the black matrix BM adjacent to the transmission region BT may be exposed without being covered by the color filter 100 and may be in contact with the overcoat layer OC.

[0229] The organic layer 82 of the thin film encapsulation layer 80 may have different thicknesses according to its region to compensate for the step difference in a portion of the insulating layer that is not deposited in the transmission region BT or is removed by a patterning process after being deposited. As an example, the thickness of the organic layer 82 overlapping the transmission region BT may be greater than the thickness of the organic layer 82 overlapping the second region AA2 and the display region BA.

[0230] According to one or more embodiments of the present disclosure, since the electronic device 1000 includes the display panel EP in which portions of the insulating layers 10 to 70 are removed in the region overlapping the electronic module 400, light transmittance of the display module 300 may be improved. Figure 2A ), the performance of the electronic module 400 of the electronic device 1000 can also be improved.

[0231] The dummy electrode DE may be disposed on the same layer (e.g., at the same layer) as the gate electrode GT. The structure in which the dummy electrode DE and the gate electrode GT are disposed on the same layer (e.g., at the same layer) means that the layer on which the dummy electrode DE is directly disposed is the same as the layer on which the gate electrode GT is directly disposed, and does not mean that the position of the dummy electrode DE in the third direction DR3 is the same as the position of the gate electrode GT in the third direction DR3. The dummy electrode DE may be disposed closer to the transmission region BT than the gate electrode GT.

[0232] Figure 7 A structure is shown in which the dummy electrode DE and the gate electrode GT are disposed on the same first insulating layer 10 and the gate electrode GT is disposed in the first direction DR1 with respect to the dummy electrode DE.

[0233] When the transmission area BT is connected to the pixel circuit PC (refer to Figure 3 ) direction, the semiconductor pattern unit SCP-U (reference Fig. 9 ) may be blocked by the dummy electrode DE.

[0234] When viewed in a direction from the transmission region BT to the pixel circuit PC, the dummy electrode DE may overlap at least two semiconductor pattern units.

[0235] In the manufacturing process of the display module 300, the dummy electrode DE can be formed by the same process as the photolithography process for forming the gate electrode GT. In the case where the mask for forming the gate electrode GT includes not only the pattern required for forming the gate electrode GT but also the pattern required for forming the dummy electrode DE, both the gate electrode GT and the dummy electrode DE can be formed by one process. Therefore, the dummy electrode DE can be easily formed without adding a separate process, and therefore, the cost and time required for additionally forming the dummy electrode DE can be reduced. In addition, the shape of the dummy electrode DE can be easily designed by changing the shape of the pattern to form the dummy electrode DE. The dummy electrode DE and the gate electrode GT can be formed by the same photolithography process, and therefore, the dummy electrode DE and the gate electrode GT can include the same material.

[0236] The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate electrode GT and the dummy electrode DE, and the third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the second insulating layer 20 .

[0237] Since the second insulating layer 20 covers the dummy electrode DE, at least one bending portion CRP may be formed in the second insulating layer 20 at a position where at least a portion of the second insulating layer 20 overlaps with the dummy electrode DE in the third direction DR3 . Figure 72 shows a structure in which two bent portions CRP are formed at positions where the second insulating layer 20 overlaps the dummy electrode DE when viewed in cross section. However, the shape of the bent portion CRP should not be limited to Figure 7 The shape shown in , and may be provided in various ways according to the shape of the dummy electrode DE.

[0238] The bent portion CRP may provide a bent portion to the second insulating layer 20 and may effectively block the light LE (refer to Figure 8B ) enters the second insulating layer 20. This will be described in detail later.

[0239] Fig. 8A is a cross-sectional view of a display panel according to a comparative example. Figure 8B is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure. Fig. 8A and Figure 8B To describe the function and effect of the dummy electrode DE.

[0240] Fig. 8A The light LE passes through the second insulating layer 20 (refer to Figure 7 ) reaches the comparative example of transistor TR-b. Since the display module 300 (refer to Figure 7 ) includes a transmissive region BT in the first area AA1 (refer to Figure 7 ), so the light LE generated in the display module 300 or the light generated outside the display module 300 can reach the transistor TR-b. As an example, the light generated outside the display module 300 can enter the display module 300, or the light emitting module LM (refer to Figure 2B ) can reach the transistor TR-b after scattering, diffraction and reflection.

[0241] The second insulating layer 20 (see Figure 7 ) The light LE entering can reach the transistor TR-b. For example, the refractive index of the second insulating layer 20 can be greater than that of the first insulating layer 10 (refer to Figure 7 ) and the refractive index of the third insulating layer 30 (refer to Figure 7 ) has a refractive index of . In this case, since the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30 (refer to Figure 7 ) due to the total reflection phenomenon caused by the difference in refractive index between the two layers, the light LE entering the second insulating layer 20 can be reflected from the transmission area BT (refer to Figure 7 ) travels to the transistor TR-b. Therefore, the light LE entering the second insulating layer 20 can easily reach the transistor TR-b.

[0242] In the case where light LE reaches the transistor TR-b, the transistor TR-b may be photodegraded due to the energy of the light LE, and the characteristics of the transistor TR-b may be degraded. Figure 7 ) may reduce its reliability.

[0243] Figure 8B It shows that the second insulating layer 20 (refer to Figure 7 ) is blocked by the dummy electrode DE and does not reach the transistor TR-b.

[0244] Reference Figure 8B , the dummy electrode DE can block at least a portion of the path through which the light LE travels. Figure 7 ) may be absorbed by the dummy electrode DE or reflected by the dummy electrode DE. Therefore, the amount of light LE reaching the transistor TR-b may be significantly reduced by the dummy electrode DE.

[0245] When the dummy electrode DE is provided, in the second insulating layer 20 (refer to Figure 7 ) may form a bent portion CRP in the second insulating layer 20. The bent portion CRP of the second insulating layer 20 may increase the structural complexity of the second insulating layer 20. In this case, the expression "the structural complexity of the second insulating layer 20 increases" used in this document means that the second insulating layer 20 includes portions having various shapes in addition to the flat portion, rather than only including the flat portion. Since the structural complexity of the second insulating layer 20 is increased due to the bent portion CRP, the amount of light LE that enters the second insulating layer 20 and reaches the transistor TR-b may be significantly reduced. In addition, the bent portion may be formed in the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, the sixth insulating layer 60, and the seventh insulating layer 70 (refer to Figure 7 ), and therefore, the bent portion can block access to the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, the sixth insulating layer 60 and the seventh insulating layer 70 (refer to Figure 7 ) in the corresponding insulating layer.

[0246] Fig. 9 is a plan view of a semiconductor pattern according to one or more embodiments of the present disclosure. Fig.10 is a plan view illustrating an overlapping relationship between a semiconductor pattern and a conductive layer according to one or more embodiments of the present disclosure.

[0247] For the convenience of explanation, Fig. 9 Only one semiconductor pattern unit SCP-U forming a semiconductor pattern is shown. The semiconductor pattern may include a plurality of semiconductor pattern units SCP-U arranged in a certain regularity.

[0248] The semiconductor pattern may be disposed on a base layer BS (refer to Figure 6 The semiconductor pattern unit SCP-U may include transistors corresponding to the driving transistor T1 to the second initialization transistor T7 (refer to Figure 3 )'s first semiconductor region AC1 to seventh semiconductor region AC7.

[0249] Despite Figure 3 Not shown, but Fig. 9 As shown in, the compensation transistor T3 may include two transistors T3-1 (having S31, A31, D31 and G31) and T3-2 (having S32, A32, D32 and G32), and the first initialization transistor T4 may include two transistors T4-1 (having S41, A41, D41 and G41) and T4-2 (having S42, A42, D42 and G42).

[0250] Each of the first to seventh semiconductor regions AC1 to AC7 may include a corresponding source among the sources S1 to S7, a corresponding active region among the active regions A1 to A7, and a corresponding drain among the drains D1 to D7. The sources S1 to S7 and the drains D1 to D7 may have a high doping concentration and thus may be regions having conductivity. The active regions A1 to A7 may have a low doping concentration and may be disposed between the sources S1 to S7 and the drains D1 to D7. In this embodiment, when the compensation transistor T3 may include two transistors T3-1 and T3-2, the source S3 may include sources S31 and S32, the active area A3 may include active areas A31 and A32, and the drain D3 may include drains D31 and D32; when the first initialization transistor T4 may include two transistors T4-1 and T4-2, the source S4 may include sources S41 and S42, the active area A4 may include active areas A41 and A42, and the drain D4 may include drains D41 and D42.

[0251] In the following, reference will be made to Fig.10 The conductive layer CL (refer to Fig. 11B ) and the overlapping relationship between the semiconductor pattern and the conductive layer CL.

[0252] The display panel may include a conductive layer CL.

[0253] Conductive layer CL (refer to Fig. 11B ) may include scan lines SLi-1, SLi and SLi+1 extending in the second direction DR2, an emission control line ECLi and a first gate electrode G1. In addition, the conductive layer CL may further include a dummy electrode DE (refer to Fig. 11B ).

[0254] Fig.10Only a portion of the conductive layer CL overlapping one semiconductor pattern unit SCP-U is shown, however, the conductive layer CL may be Fig. 11B The conductive layer CL shown in FIG. 1 extends in the second direction DR2 and may overlap with the plurality of semiconductor pattern units SCP-U. This will be described in detail later.

[0255] A portion of the i-th scan line SLi overlapping with the semiconductor pattern unit SCP-U may be the gate electrode G2 of the switching transistor T2, another portion of the i-th scan line SLi overlapping with the semiconductor pattern unit SCP-U may be the gate electrode G31 of a compensation transistor T3-1, and another portion of the i-th scan line SLi overlapping with the semiconductor pattern unit SCP-U may be the gate electrode G32 of another compensation transistor T3-2.

[0256] Fig.10 The gate electrodes G41 and G42 of the first initialization transistors T4-1 and T4-2 set in the (i-1) scan line SLi-1, the gate electrode G7 of the second initialization transistor T7 set in the (i+1) scan line SLi+1, the gate electrode G5 of the operation control transistor T5 set in the i emission control line ECLi, and the gate electrode G6 of the emission control transistor T6 set in the i emission control line ECLi are shown.

[0257] Fig.11A , Fig. 11B and Fig. 11C are plan views respectively showing a semiconductor pattern, a conductive layer, and a stacked structure of the semiconductor pattern and the conductive layer according to one or more embodiments of the present disclosure. FIG. 11A to FIG. 11C An overlapping relationship among the light blocking layer BML, the semiconductor pattern unit SCP-U disposed on the light blocking layer BML, and the conductive layer CL is described.

[0258] For the convenience of explanation, Fig.11A and Fig. 11C In the figure, the dotted quadrilateral shape indicates that a reference Figure 5 The regions of the first pixel circuit PC11, the second pixel circuit PC12, the third-first pixel circuit PC13a and the third-second pixel circuit PC13b described above, and the dotted line quadrilateral shape may correspond to the ... Figure 5 The dashed lines shown in FIG. 4 indicate the quadrilateral shape.

[0259] The light blocking layer BML may be provided in plural, and the plural light blocking layers BML may be disposed on the base layer BS (refer to Figure 7 ). The light-blocking layer connection line BML-L may be disposed between a plurality of light-blocking layers BML, and may connect two light-blocking layers BML to each other. The light-blocking layer connection line BML-L may be connected to the line region BL (refer to Figure 4 )overlapping.

[0260] The semiconductor pattern including the semiconductor pattern unit SCP-U may be disposed on the light blocking layer BML. Four semiconductor pattern units SCP-U may be disposed on one light blocking layer BML. Fig.11A The description of each of the plurality of semiconductor pattern units SCP-U shown in Fig. 9 The description of the semiconductor pattern unit SCP-U is basically the same, and thus the details thereof will be omitted.

[0261] Fig. 11B Shows the settings in Fig.11A The conductive layer CL may include scan lines SLi-1, SLi, and SLi+1 extending in the second direction DR2, emission control lines ECLi, and dummy electrodes DE, and a first gate electrode G1. Fig. 11B The scan lines SLi-1, SLi and SLi+1 and the emission control line ECLi shown in FIG. Fig.10 The shapes of the scan lines SLi-1, SLi, and SLi+1 and the emission control line ECLi extending in the second direction DR2 are described.

[0262] Description and References of Scan Lines SLi-1, SLi and SLi+1, Emission Control Line ECLi and First Gate Electrode G1 Fig.10 Those described are substantially the same, and thus details thereof will be omitted.

[0263] In a plan view, the dummy electrode DE may be disposed on the same layer (e.g., at the same layer) as the scan lines SLi-1, SLi, and SLi+1, the emission control line ECLi, and the first gate electrode G1. In addition, in a plan view, the dummy electrode DE may be disposed in a direction opposite to the first direction DR1 relative to the scan lines SLi-1, SLi, and SLi+1, the emission control line ECLi, and the first gate electrode G1. Therefore, the dummy electrode DE may block the transmission area BT (refer to Figure 7 ) moves to the display area BA (refer to Figure 7 ) of light LE (refer to Figure 8B ), and the semiconductor pattern can be protected from the light LE.

[0264] The dummy electrode DE may extend in one direction in a plan view, and may have a continuous shape. Fig. 11B The dummy electrode DE extending in the second direction DR2 and having a continuous shape is illustrated as a representative example, however, the shape of the dummy electrode DE should not be limited thereto or thereby.

[0265] In a plan view, the scan lines SLi-1, SLi, and SLi+1, the emission control line ECLi, and the first gate electrode G1 may overlap the semiconductor pattern unit SCP-U, and the dummy electrode DE may be spaced apart from the semiconductor pattern unit SCP-U. Fig. 11C A structure in which the dummy electrode DE is spaced apart from the semiconductor pattern unit SCP-U in the first direction DR1 is shown as a representative example.

[0266] Fig. 12A is a plan view of a display module according to one or more embodiments of the present disclosure.

[0267] For the convenience of explanation, Fig. 12A In the figure, the dotted quadrilateral shape indicates that a reference Figure 5 The regions of the first pixel circuit PC11, the second pixel circuit PC12, the third-first pixel circuit PC13a and the third-second pixel circuit PC13b are described.

[0268] The display module may include a light blocking layer BML, a light blocking layer connection line BML-L, a semiconductor pattern unit SCP-U, scan lines SLi-1, SLi and SLi+1, an emission control line ECLi, a first gate electrode G1 and a dummy electrode DE-a. Fig. 12A In the description and reference of the light-blocking layer BML, the light-blocking layer connecting line BML-L, the semiconductor pattern unit SCP-U, the scanning lines SLi-1, SLi and SLi+1, the emission control line ECLi, and the first gate electrode G1 Figures 10 to 11C Those described are substantially the same, and therefore, the description hereinafter will focus on the different features of the dummy electrode DE-a.

[0269] The dummy electrode DE-a may include a plurality of sub-dummy electrodes DE-a1 and DE-a2. Fig. 12A A structure is shown in which the dummy electrode DE-a includes a first sub-dummy electrode DE-a1 and a second sub-dummy electrode DE-a2. However, the number of sub-dummy electrodes should not be limited to two, and may be three or more.

[0270] The sub-dummy electrodes DE-a1 and DE-a2 may be spaced apart from each other. Fig. 12A 1 shows a structure in which the first dummy electrode DE-a1 is spaced apart from the second dummy electrode DE-a2 in the first direction DR1. Figure 5 ) when viewed in a direction from the first pixel circuit PC11 to the second pixel circuit PC12, the third-first pixel circuit PC13a and the third-second pixel circuit PC13b, the sub-dummy electrodes DE-a1 and DE-a2 may partially overlap each other.

[0271] Fig. 12A A structure in which the first sub-dummy electrode DE-a1 and the second sub-dummy electrode DE-a2 have substantially the same shape in a plan view is shown as a representative example, however, the present disclosure should not be limited thereto or thereby. According to one or more embodiments, the sub-dummy electrodes DE-a1 and DE-a2 may have different shapes from each other.

[0272] Since the dummy electrode DE-a includes a plurality of sub-dummy electrodes DE-a1 and DE-a2, the dummy electrode DE-a1 is included in the second insulating layer 20 (refer to Figure 7 ) in the bending part CRP (refer to Figure 7 ) may be greater than when the dummy electrodes DE are provided in a single form (refer to Figure 7 Therefore, the structural complexity of the second insulating layer 20 caused by the bent portion CRP increases, and thus, the number of transistors that enter the second insulating layer 20 and reach the driving transistor T1 to the second initialization transistor T7 (refer to Figure 3 ) of light LE (refer to Figure 7 ) amount.

[0273] Fig. 12B is a plan view of a display module according to one or more embodiments of the present disclosure.

[0274] For the convenience of explanation, Fig. 12B In the figure, the dotted quadrilateral shape indicates that a reference Figure 5 The regions of the first pixel circuit PC11, the second pixel circuit PC12, the third-first pixel circuit PC13a and the third-second pixel circuit PC13b are described.

[0275] The display module may include a light blocking layer BML, a light blocking layer connection line BML-L, a semiconductor pattern unit SCP-U, scan lines SLi-1, SLi and SLi+1, an emission control line ECLi, a first gate electrode G1 and a dummy electrode DE-b. Fig. 12B , the description and references of the light blocking layer BML, the light blocking layer connecting line BML-L, the semiconductor pattern unit SCP-U, the scanning lines SLi-1, SLi and SLi+1, the emission control line ECLi and the first gate electrode G1 Figures 10 to 11C Those described are substantially the same, and therefore, the description hereinafter will focus on the different features of the dummy electrode DE-b.

[0276] The dummy electrode DE-b may include a plurality of sub-dummy electrodes DE-b1 and DE-b2. Fig. 12B A structure in which the dummy electrode DE-b includes a first sub-dummy electrode DE-b1 and a second sub-dummy electrode DE-b2 is shown as a representative example. However, the number of sub-dummy electrodes should not be limited to two, and may be three or more.

[0277] The sub-dummy electrodes DE-b1 and DE-b2 may be spaced apart from each other in one direction (eg, the second direction DR2), and may be disposed to be aligned with each other in a direction (eg, the first direction DR1) different from the one direction. Fig. 12B , the first sub-dummy electrode DE-b1 and the second sub-dummy electrode DE-b2 are spaced apart from each other in the second direction DR2, and are arranged to be aligned with each other in the first direction DR1. However, the present disclosure should not be limited thereto or thereby, and the first sub-dummy electrode DE-b1 and the second sub-dummy electrode DE-b2 may not be aligned with each other in one direction as long as they can block the light LE traveling to the semiconductor pattern (refer to Figure 8B )

[0278] Fig. 12B A structure in which the first sub-dummy electrode DE-b1 and the second sub-dummy electrode DE-b2 have substantially the same shape in a plan view is shown, however, the present disclosure should not be limited thereto or thereby. According to one or more embodiments, the sub-dummy electrodes DE-b1 and DE-b2 may have different shapes from each other.

[0279] Since the dummy electrode DE-b is discontinuous in one direction and includes the sub-dummy electrodes DE-b1 and DE-b2 spaced apart from each other, the cost of forming the sub-dummy electrodes DE-b1 and DE-b2 may be reduced.

[0280] Fig. 12C is a plan view of a display module according to one or more embodiments of the present disclosure.

[0281] The display module may include a light blocking layer BML, a light blocking layer connection line BML-L, a semiconductor pattern unit SCP-U, scan lines SLi-1, SLi and SLi+1, an emission control line ECLi, a first gate electrode G1 and a dummy electrode DE-c. Fig. 12C , the description and references of the light blocking layer BML, the light blocking layer connecting line BML-L, the semiconductor pattern unit SCP-U, the scanning lines SLi-1, SLi and SLi+1, the emission control line ECLi and the first gate electrode G1 Figures 10 to 11C Those described are substantially the same, and therefore, the description hereinafter will focus on the different features of the dummy electrode DE-c.

[0282] For the convenience of explanation, Fig. 12C In the figure, the dotted quadrilateral shape indicates that a reference Figure 5 The regions of the first pixel circuit PC11, the second pixel circuit PC12, the third-first pixel circuit PC13a and the third-second pixel circuit PC13b are described.

[0283] The dummy electrode DE-c may include a first portion PT1 and a second portion PT2.

[0284] The first portion PT1 of the dummy electrode DE-c may extend in the second direction DR2, and when extending from the transmission area BT (refer to FIG. 1 ) in the first direction DR1, the first portion PT1 of the dummy electrode DE-c may extend in the second direction DR2. Figure 5 ) to the display area BA (refer to Figure 5 ) when observed, the first portion PT1 may overlap with at least one semiconductor pattern unit SCP-U. Fig. 12C It shows that when the transmission area BT (refer to Figure 5 ) to the display area BA (refer to Figure 5 ) when observed, the first portion PT1 of a dummy electrode DE-c overlaps with two semiconductor pattern units SCP-U.

[0285] The second portion PT2 of the dummy electrode DE-c may extend in the first direction DR1 and may be connected to both ends of the first portion PT1. The number of the second portion PT2 included in one dummy electrode DE-c may be plural.

[0286] Entering the second insulating layer 20 (refer to Figure 8B ) of light LE (refer to Figure 8B ) may not enter in parallel with the first direction DR1, but may enter in a direction between the first direction DR1 and the second direction DR2.

[0287] In the case where the dummy electrode DE-c is provided in plurality and the dummy electrodes DE-c are spaced apart from each other in the second direction DR2, the second portion PT2 of the dummy electrode DE-c may effectively block the light LE entering in the direction between the first direction DR1 and the second direction DR2 between the dummy electrodes DE-c spaced apart from each other in the second direction DR2 (refer to Figure 8B ).

[0288] Although the embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these embodiments, but those skilled in the art will be able to make various changes and modifications within the spirit and scope of the present disclosure as defined by the appended claims.

[0289] Thus, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the disclosure should be determined in accordance with the following claims and their equivalents.

Claims

1. A display panel, comprising: a base layer including a first region including a display region and a transmission region and a second region around at least a portion of the first region and having a light transmittance lower than that of the first region; a plurality of first pixels, each of the plurality of first pixels comprising a plurality of sub-pixels and being positioned in the display area; as well as a dummy electrode, wherein the dummy electrode is located in the display area, Wherein, each of the multiple sub-pixels in the multiple first pixels includes a pixel circuit, the pixel circuit includes a plurality of first transistors and a light-emitting element connected to the plurality of first transistors, each of the plurality of first transistors includes a semiconductor pattern unit and a gate electrode overlapping the semiconductor pattern unit, and the dummy electrode is spaced apart from the semiconductor pattern unit in a plan view.

2. The display panel according to claim 1, further comprising: a first insulating layer, on which the gate electrode and the dummy electrode are positioned, and the first insulating layer is located on the base layer; a second insulating layer, the second insulating layer being located on the first insulating layer and covering the gate electrode and the dummy electrode; as well as A third insulating layer is located on the second insulating layer and covers the second insulating layer.

3. The display panel according to claim 2, wherein: The second insulating layer has a refractive index greater than that of the first insulating layer and the third insulating layer.

4. The display panel according to claim 2, wherein: The second insulating layer includes silicon nitride, and each of the first insulating layer and the third insulating layer includes silicon oxide.

5. The display panel according to claim 1, wherein: The dummy electrode extends in one direction and has a continuous shape in the plan view.

6. The display panel according to claim 1, wherein: The dummy electrode includes a plurality of sub-dummy electrodes that are spaced apart from each other and at least partially overlap each other when viewed in a direction from the transmission area to the pixel circuit.

7. The display panel according to claim 1, wherein: The dummy electrode includes a first portion extending in a second direction and overlapping at least one semiconductor pattern unit when viewed from the transmission area to the display area in the first direction, and a second portion extending in the first direction and connected to both ends of the first portion, respectively.

8. The display panel according to claim 1, further comprising: a light-blocking layer, the light-blocking layer being located on the base layer, The light blocking layer overlaps with the display area and does not overlap with the transmission area, and the dummy electrode overlaps with the light blocking layer.

9. The display panel according to claim 1, further comprising: A plurality of light-blocking layers, wherein the plurality of light-blocking layers are located on the base layer; as well as A light-blocking layer connection line is positioned between two light-blocking layers among the plurality of light-blocking layers and connects the two light-blocking layers to each other.

10. The display panel according to claim 1, wherein: The display region includes a plurality of display regions, the first region further includes a line region positioned between the plurality of display regions, and the transmission region is around the display region and the line region.

11. The display panel according to claim 1, wherein: The dummy electrode and the gate electrode include the same material.

12. The display panel according to claim 1, further comprising: a plurality of second pixels, each of the plurality of second pixels including a plurality of sub-pixels and positioned in the second region, Wherein, each of the multiple sub-pixels in the multiple second pixels includes a pixel circuit, the pixel circuit includes a plurality of second transistors and a light-emitting element connected to the multiple second transistors, and the multiple sub-pixels in the multiple first pixels are larger than the multiple sub-pixels in the multiple second pixels, and the multiple sub-pixels in the multiple second pixels are configured to emit light of the same color as the multiple sub-pixels in the multiple first pixels.

13. The display panel according to claim 12, wherein: Each of the multiple first pixels includes a first sub-pixel configured to emit a first color light, a second sub-pixel configured to emit a second color light, and two third sub-pixels configured to emit a third color light, the first sub-pixel is spaced apart from the second sub-pixel in one direction, one of the two third sub-pixels is spaced apart from the other of the two third sub-pixels, the first sub-pixel is spaced apart from the one third sub-pixel in a first diagonal direction, the second sub-pixel is spaced apart from the one third sub-pixel in a second diagonal direction, and the light-emitting area of ​​each of the first sub-pixel, the second sub-pixel and the two third sub-pixels increases in the order of the two third sub-pixels, the second sub-pixel and the first sub-pixel.

14. The display panel according to claim 1, wherein: A density of the plurality of first pixels in the first area is smaller than a density of the plurality of second pixels in the second area.

15. The display panel according to claim 1, wherein: When viewed in a direction from the transmission area to the pixel circuit, the dummy electrode overlaps at least two semiconductor pattern units.

16. The display panel according to claim 1, further comprising: An electronic module overlaps the first area and is positioned below the display panel, wherein the electronic module includes at least one of a light emitting module and a light receiving module.

17. A display panel, comprising: a base layer including a first region including a display region and a transmission region and a second region around at least a portion of the first region and having a light transmittance lower than that of the first region; a plurality of first pixels, each of the plurality of first pixels comprising a plurality of sub-pixels positioned in the display area; as well as A dummy electrode, wherein the dummy electrode is located in the display area; Wherein, each of the multiple sub-pixels includes a pixel circuit, the pixel circuit includes a plurality of first transistors and a light-emitting element connected to the plurality of first transistors, each of the plurality of first transistors includes a semiconductor pattern unit and a gate electrode overlapping the semiconductor pattern unit, and when viewed in a direction from the transmission area to the pixel circuit, at least a portion of the semiconductor pattern unit is blocked by the dummy electrode.

18. The display panel according to claim 17, further comprising: a first insulating layer, on which the gate electrode and the dummy electrode are positioned, and the first insulating layer is located on the base layer; a second insulating layer, the second insulating layer being located on the first insulating layer and covering the gate electrode and the dummy electrode; as well as A third insulating layer is located on the second insulating layer and covers the second insulating layer, wherein the second insulating layer has a refractive index greater than the refractive index of the first insulating layer and the refractive index of the third insulating layer.

19. The display panel according to claim 18, wherein: The second insulating layer includes at least one bent portion, and the bent portion overlaps at least a portion of the dummy electrode.

20. The display panel according to claim 17, wherein: When viewed in the direction from the transmission area to the pixel circuit, the number of the semiconductor pattern units partially blocked by the dummy electrode is two or more.

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