Piezoelectric heterostructure, preparation method and semiconductor device

Abstract

The invention discloses a piezoelectric heterostructure, a preparation method and a semiconductor device, the piezoelectric heterostructure comprises a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric functional layer, the dielectric layer is located between the substrate layer and the piezoelectric functional layer, the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected with the piezoelectric functional layer; the piezoelectric functional layer is provided with a first surface and a second surface deviating from each other, the first surface is a stripping surface, and the stripping surface is located on one side, deviating from the substrate layer, of the piezoelectric functional layer. According to the invention, the stress between the patterned electrode layer and the piezoelectric functional layer is reduced, the debonding condition of the piezoelectric functional layer is prevented, and the morphology accuracy, reliability, stability and durability of the piezoelectric heterostructure are improved; and when the material is applied to a semiconductor device, the electromechanical coupling coefficient, the spurious response, the working frequency and other performances can be improved under the condition of the same in-plane propagation angle, and the performance requirements of various semiconductor devices are met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a piezoelectric heterostructure, a preparation method and a semiconductor device. Background Art

[0002] With the development of wireless communication technology, 5G and 6G frequency bands have put forward higher requirements for RF front-end components. As the core component of RF front-end, RF filter needs to have higher frequency and larger bandwidth, which has a great impact on the sound velocity (v) and electromechanical coupling coefficient (k) of acoustic resonator. 2 ) puts forward higher requirements, requiring RF substrates with better performance. Surface acoustic wave (SAW) resonators and bulk acoustic wave (BAW) resonators are widely used in RF systems. Surface acoustic wave resonators based on lithium niobate or lithium tantalate piezoelectric heterogeneous substrates can achieve better acoustic energy confinement and temperature compensation, and bulk acoustic wave resonators based on aluminum nitride or scandium-doped aluminum nitride can achieve higher operating frequencies, but they are difficult to meet the frequency or bandwidth requirements in the 5G and 6G frequency bands.

[0003] By preparing a metal layer at the bottom of the piezoelectric functional layer and preparing electrodes on the surface, a higher sound speed and a larger electromechanical coupling coefficient can be achieved by utilizing the acoustic mode excited by the longitudinal electric field. At present, the ion beam stripping method is generally used to prepare high-quality piezoelectric single crystal films on the surface of the substrate layer. Usually, ions need to be implanted into the surface of the piezoelectric wafer substrate first, and then the metal layer and the dielectric layer are prepared. However, this process requires strict high-temperature temperature control of the piezoelectric wafer substrate to prevent bubbling on the surface of the piezoelectric wafer substrate from affecting the subsequent film transfer. At the same time, the surface-distributed metal electrode (i.e., the metal layer) has a large thermal mismatch with the piezoelectric functional layer, which may cause the piezoelectric functional layer to debond in the subsequent high-temperature treatment process, which imposes more restrictions on the subsequent preparation process, is not conducive to product yield, and is difficult to use in mass production processes. In addition, in the subsequent preparation process, the surface-distributed metal layer as the bottom electrode will increase the leakage of the acoustic resonator body wave energy and introduce strong noise. Summary of the invention

[0004] In view of the above problems in the prior art, the present application provides a piezoelectric heterostructure, a preparation method and a semiconductor device. The specific technical solution is as follows:

[0005] On the one hand, the present application provides a piezoelectric heterostructure, comprising a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric functional layer, wherein the dielectric layer is located between the substrate layer and the piezoelectric functional layer, the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected to the piezoelectric functional layer;

[0006] The piezoelectric functional layer has a first surface and a second surface which are opposite to each other. The first surface is a release surface which is located at a side of the piezoelectric functional layer which is opposite to the substrate layer.

[0007] Furthermore, the piezoelectric heterostructure further comprises an intermediate adhesion layer, wherein the intermediate adhesion layer is located between the patterned electrode layer and the dielectric layer, and / or

[0008] The intermediate adhesion layer is located between the patterned electrode layer and the piezoelectric functional layer.

[0009] Furthermore, the intermediate adhesive layer and the patterned electrode layer are arranged in conformity and alignment.

[0010] Furthermore, the intermediate adhesive layer satisfies at least one of the following characteristics:

[0011] The material of the intermediate adhesion layer includes at least one of titanium, tungsten, titanium tungsten, nickel, chromium and molybdenum;

[0012] The thickness of the intermediate adhesion layer is 1 nm to 15 nm.

[0013] Furthermore, the piezoelectric heterostructure has an air gap, and the air gap is located between the patterned electrode layer and the dielectric layer.

[0014] Furthermore, the thickness of the piezoelectric heterostructure satisfies at least one of the following characteristics:

[0015] The thickness of the dielectric layer is 10nm to 2000nm;

[0016] The thickness of the patterned electrode layer is 5nm to 150nm;

[0017] The thickness of the piezoelectric functional layer is 50nm-2200nm.

[0018] Furthermore, the material of the piezoelectric heterostructure satisfies at least one of the following characteristics:

[0019] The material of the substrate layer includes at least one of silicon, silicon oxide, quartz, sapphire, silicon carbide, silicon nitride, gallium nitride and diamond;

[0020] The material of the dielectric layer includes at least one of silicon oxide, silicon nitride, polysilicon, amorphous silicon, aluminum oxide and aluminum nitride;

[0021] The material of the patterned electrode layer includes at least one of gold, silver, copper, aluminum, nickel, platinum, titanium, tantalum, tungsten, chromium and molybdenum;

[0022] The material of the piezoelectric functional layer includes at least one of single crystal lithium niobate, single crystal lithium tantalate, aluminum nitride, scandium-doped aluminum nitride and lead zirconate titanate.

[0023] On the other hand, the present application also provides a method for preparing a piezoelectric heterostructure, comprising:

[0024] forming a patterned electrode layer on a piezoelectric wafer substrate;

[0025] forming a dielectric layer on the patterned electrode layer;

[0026] Performing ion implantation on the piezoelectric wafer substrate on which the patterned electrode layer and the dielectric layer are formed, and bonding a surface of one side of the piezoelectric wafer substrate having the patterned electrode layer to the substrate layer to form a bonding structure;

[0027] The bonding structure is subjected to a first heat treatment so that the piezoelectric wafer substrate is peeled off to form a piezoelectric functional layer, thereby obtaining the piezoelectric heterostructure; the piezoelectric heterostructure comprises a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric functional layer, the dielectric layer is located between the substrate layer and the piezoelectric functional layer, the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected to the piezoelectric functional layer; the piezoelectric functional layer has a first surface and a second surface which are opposite to each other, the first surface is a peeling surface, and the peeling surface is located on the side of the piezoelectric functional layer which is opposite to the substrate layer.

[0028] Furthermore, before ion implantation is performed on the piezoelectric wafer substrate having the patterned electrode layer and the dielectric layer, and a surface of the piezoelectric wafer substrate having the patterned electrode layer is bonded to the substrate layer to form a bonding structure, the method further comprises:

[0029] The piezoelectric wafer substrate is subjected to a second heat treatment; the temperature of the second heat treatment is greater than the formation temperature of the dielectric layer, and the time of the second heat treatment is greater than the formation time of the dielectric layer.

[0030] On the other hand, the present application also provides a semiconductor device, comprising the piezoelectric heterostructure as described in any one of the above items and a surface electrode, wherein the surface electrode is located on the piezoelectric functional layer and at least part of the surface electrode is arranged on the patterned electrode layer.

[0031] Based on the above technical solution, this application has the following beneficial effects:

[0032] 1. In the piezoelectric heterostructure of the present application, the patterned electrode layer is located in the dielectric layer, and one side exposes the dielectric layer and is electrically connected to the piezoelectric functional layer. On the one hand, compared with the traditional surface electrode layer, the patterned electrode layer occupies a small area, which is conducive to reducing the stress generated by thermal mismatch between the patterned electrode layer and the piezoelectric functional layer, thereby effectively preventing the piezoelectric functional layer from debonding, which is conducive to improving the quality of the piezoelectric heterostructure; on the other hand, the dielectric layer is filled in the gap of the patterned electrode layer, which can further reduce the stress deformation of the piezoelectric functional layer during the preparation process, which is conducive to improving the morphology accuracy, reliability, stability and durability of the piezoelectric heterostructure; further, in the piezoelectric heterostructure, the peeling surface of the piezoelectric functional layer is exposed on the side away from the substrate layer, and is applied to semiconductor devices, such as resonators, so that the semiconductor device based on the piezoelectric functional layer can effectively improve the electromechanical coupling coefficient, spurious response and operating frequency under the same in-plane propagation angle, meeting the performance requirements of various semiconductor devices.

[0033] 2. The preparation method of the present application first forms a patterned electrode layer before ion implantation into the piezoelectric wafer substrate, and uses a dielectric layer to fill the gaps in the patterned electrode layer. On the one hand, this reduces the strict temperature requirements of the ion implantation process, facilitates the optimization of the ion implantation process that is greatly affected by temperature, and prevents bubbles from appearing on the surface of the piezoelectric wafer substrate and affecting the subsequent bonding process; on the other hand, compared with the metal layer distributed on the entire surface, it can effectively reduce the stress caused by thermal mismatch between the piezoelectric wafer substrate (or piezoelectric functional layer) and the patterned electrode layer during the subsequent first heat treatment and second heat treatment and other heating processes, prevent the piezoelectric functional layer from debonding, and is beneficial to improving the accuracy, reliability and stability of the piezoelectric heterostructure.

[0034] 3. The introduction of the patterned electrode layer and the dielectric layer improves the convenience of the subsequent release of the dielectric layer to form an air gap, greatly reducing the process difficulty of preparing a variety of semiconductor devices (such as acoustic wave resonators), which is conducive to improving the preparation efficiency and yield, and improving the quality of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments or prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A cross-sectional view of a piezoelectric heterostructure provided in an embodiment of the present application;

[0037] Figure 2A cross-sectional view of another piezoelectric heterostructure provided in an embodiment of the present application;

[0038] Figure 3 A cross-sectional view of a piezoelectric heterostructure provided for some optional embodiments of the present application;

[0039] Figure 4 A cross-sectional view of a piezoelectric heterostructure provided for some other optional embodiments of the present application;

[0040] Figure 5 A cross-sectional view of a piezoelectric heterostructure provided for another optional embodiment of the present application;

[0041] Figure 6 A flow chart of a method for preparing a piezoelectric heterostructure provided in an embodiment of the present application;

[0042] Figure 7 A surface morphology image of a piezoelectric wafer substrate after patterning provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of a patterned electrode layer provided in an embodiment of the present application;

[0044] Fig. 9 A flow chart of a method for forming a dielectric layer provided in an embodiment of the present application;

[0045] Fig.10 A flow chart of a method for peeling a piezoelectric wafer substrate provided in an embodiment of the present application;

[0046] Fig.11 A flow chart of another method for preparing a piezoelectric heterostructure provided in an embodiment of the present application.

[0047] Wherein, the accompanying drawings are marked as follows:

[0048] 1-substrate layer, 2-dielectric layer, 21-step layer, 3-patterned electrode layer, 4-piezoelectric functional layer, 41-first surface, 42-second surface, 43-piezoelectric wafer substrate, 44-damage layer, 5-air gap. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments, and the structure in the drawings is only a technical solution of a specific embodiment of the present application. The structure of the present application may include fewer or more structural features and is not limited to the structure described in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0050] It should be noted that in the description of the present application, for the following defined terms, unless a different definition is given in the claims or elsewhere in this specification, these definitions should be applied. All numerical values, whether or not explicitly indicated, are defined herein as being modified by the term "about". The term "about" generally refers to a numerical range that a person of ordinary skill in the art would consider to be equivalent to the stated value to produce substantially the same properties, functions, results, etc. A numerical range indicated by a low value and a high value is defined to include all numerical values ​​included in the numerical range and all subranges included in the numerical range.

[0051] It should be noted that, in the description of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0052] It should be noted that, in the description of the present application, the meaning of the terms "on", "above", "above", and "above" should be interpreted in the broadest sense, meaning that the description containing these terms is interpreted as "the component can be set on another component in direct contact, or there can be an intermediate component or layer between the components". In addition, for the convenience of description, the present application may also use spatial relative terms such as "under", "below", "under", "on", "above", "above", "lower", "upper", etc. to describe the relationship between an element or component and another element or component shown in the drawings. In addition to the orientations described in the figures, the spatially relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatially relative descriptors used in the present application can be interpreted accordingly.

[0053] The term "layer" as used in this application refers to a portion of a material including an area having a certain thickness. A layer may extend over the entire underlying or superstructure, or may extend over a localized area of ​​the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. A layer may include multiple layers. For example, a redistribution layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0054] In view of at least one of the technical problems in the prior art, such as poor preparation yield of piezoelectric heterostructures, difficulty in mass production, and poor structural stability, the embodiments of the present application provide a piezoelectric heterostructure, a preparation method, and a semiconductor device, such as Figure 1 As shown, the piezoelectric heterostructure includes a substrate layer 1, a dielectric layer 2, a patterned electrode layer 3 and a piezoelectric functional layer 4, wherein the dielectric layer 2 is located between the substrate layer 1 and the piezoelectric functional layer 4, the patterned electrode layer 3 is located within the dielectric layer 2, and one side of the patterned electrode layer 3 is exposed to the dielectric layer 2 and is electrically connected to the piezoelectric functional layer 4; on the one hand, compared with the traditional surface electrode layer, the patterned electrode layer 3 occupies a small area, which is beneficial to reducing the stress generated by the thermal mismatch between the patterned electrode layer 3 and the piezoelectric functional layer 4, thereby effectively preventing the debonding of the piezoelectric functional layer 4, which is beneficial On the other hand, the dielectric layer 2 is filled in the gap of the patterned electrode layer 3, which can further reduce the stress deformation of the piezoelectric functional layer 4 during the preparation process, which is beneficial to improving the morphological accuracy, reliability, stability and durability of the piezoelectric heterostructure; in addition, the piezoelectric heterostructure can overcome the influence of the stress generated by the large difference in thermal expansion coefficients between different layers on the structural accuracy, structural reliability and structural stability of the piezoelectric heterostructure during the preparation process, which is beneficial to simplify the preparation complexity of the piezoelectric heterostructure and improve the preparation yield.

[0055] Specifically, the piezoelectric functional layer 4 has a first surface 41 and a second surface 42 which are opposite to each other. The first surface 41 is a peeling surface, which is located on the side of the piezoelectric functional layer 4 away from the substrate layer 1. In the piezoelectric heterostructure, the peeling surface is exposed to the surface of the piezoelectric heterostructure; the second surface 42 is the original exposed surface of the piezoelectric wafer substrate 43 used to prepare the piezoelectric functional layer 4, and the second surface 42 is electrically connected to the patterned electrode layer 3; that is, during the preparation process, by flipping and peeling, the crystal axis direction of the piezoelectric functional layer 4 is opposite to the crystal axis direction of the piezoelectric wafer substrate 43; in this way, the peeling surface of the piezoelectric functional layer 4 is exposed to the side away from the substrate layer 1, and is applied to semiconductor devices, such as resonators, so that the semiconductor device based on the piezoelectric functional layer 4 has the same in-plane propagation angle. The electromechanical coupling coefficient, stray response and operating frequency and other performances are effectively improved, meeting the performance requirements of various semiconductor devices.

[0056] Specifically, the material of the substrate layer 1 includes at least one of silicon, silicon oxide, quartz, sapphire, silicon carbide, silicon nitride, gallium nitride and diamond, which can effectively play a supporting role, improve the structural stability of the piezoelectric heterostructure, and is also beneficial to improving the electromechanical coupling coefficient of the piezoelectric heterostructure.

[0057] Specifically, the material of the dielectric layer 2 includes at least one of silicon oxide, silicon nitride, polycrystalline silicon, amorphous silicon, aluminum oxide and aluminum nitride, and has good insulation properties. The dielectric layer 2 is filled in the gap of the patterned electrode layer 3, which can effectively avoid debonding of the patterned electrode layer 3 and the piezoelectric functional layer 4 due to thermal mismatch during the preparation process, thereby greatly improving the structural accuracy and structural reliability of the piezoelectric heterostructure.

[0058] Specifically, the thickness of the dielectric layer 2 is 10nm to 2000nm; it can be understood that the thickness of the dielectric layer 2 can be any point value between 10nm and 2000nm; illustratively, the thickness of the dielectric layer 2 can be 10nm, 20nm, 50nm, 100nm, 500nm, 1000nm, 1500nm, 1800nm, 2000nm, etc.; within this thickness range, the thickness of the dielectric layer 2 is greater than the thickness of the patterned electrode layer 3, and can effectively wrap the peripheral side of the patterned electrode layer 3 and the side close to the substrate layer 1, effectively preventing undesirable stress deformation between the patterned electrode layer 3 and the piezoelectric functional layer 4, and greatly improving the structural accuracy and structural stability inside the piezoelectric heterostructure.

[0059] Specifically, the preset shape of the patterned electrode layer 3 includes at least one of a polygon and an interdigitated pattern; illustratively, Figure 2 As shown, the preset shape of the patterned electrode layer 3 can be a cross-finger pattern; as an example, the preset shape of the patterned electrode layer 3 can be a single polygon; as an example, the preset shape of the patterned electrode layer 3 can be a combination of a polygon and a cross-finger pattern; the preset shapes of the patterned electrode layer 3 are diverse and can meet the performance requirements of different semiconductor devices.

[0060] The material of the patterned electrode layer 3 includes at least one of gold, silver, copper, aluminum, nickel, platinum, titanium, tantalum, tungsten, chromium and molybdenum. In the semiconductor device prepared subsequently, together with the surface electrode on the surface of the piezoelectric functional layer 4, the acoustic mode excited by the longitudinal electric field can be used to greatly improve the sound velocity and electromechanical coupling coefficient of the semiconductor device, so that the semiconductor device can meet the frequency or bandwidth requirements in the 5G and 6G frequency bands as much as possible, thereby improving the applicability of the piezoelectric heterostructure and the semiconductor device having the piezoelectric heterostructure.

[0061] Specifically, the thickness of the patterned electrode layer 3 is 5nm to 150nm; it can be understood that the thickness of the patterned electrode layer 3 can be any point value in the range of 5nm to 150nm; illustratively, the thickness of the patterned electrode layer 3 can be 5nm, 10nm, 25nm, 50nm, 100nm, 125nm, 150nm, etc.; within this thickness range, on the one hand, it can provide good electromechanical coupling performance, which is beneficial to the improvement of the sound velocity of the piezoelectric heterostructure; on the other hand, the thickness of the patterned electrode layer 3 is less than the thickness of the dielectric layer 2, and can be protected and restricted by the dielectric layer 2 during the preparation process, effectively preventing the patterned electrode layer 3 from being affected by the high temperature conditions during the preparation process, resulting in stress caused by debonding and a series of structural precision reduction and poor stability, and also preventing the prepared piezoelectric heterostructure and semiconductor device from being prone to cracking during use, thereby improving its structural reliability and structural durability.

[0062] Specifically, the material of the piezoelectric functional layer 4 includes at least one of single-crystal lithium niobate, single-crystal lithium tantalate, aluminum nitride, scandium-doped aluminum nitride and lead zirconate titanate; the thickness of the piezoelectric functional layer 4 is 50nm~2200nm; it can be understood that the thickness of the piezoelectric functional layer 4 can be any point value between 50nm and 2200nm; illustratively, the thickness of the piezoelectric functional layer 4 can be 50nm, 100nm, 150nm, 500nm, 750nm, 1000nm, 1500nm, 2000nm, 2200nm, etc.; in this way, the piezoelectric functional layer 4 can provide a good breakdown field strength, which is beneficial to improving the electrical properties of the piezoelectric heterostructure.

[0063] The substrate layer 1, dielectric layer 2, patterned electrode layer 3 and piezoelectric functional layer 4 in the piezoelectric heterostructure work together to effectively improve the operating frequency, sound velocity, electromechanical coupling coefficient and temperature stability of the piezoelectric heterostructure and the semiconductor device having the piezoelectric heterostructure, so that the piezoelectric heterostructure and the semiconductor device can meet the frequency and bandwidth requirements in the 5G and 6G frequency bands.

[0064] Specifically, the piezoelectric heterostructure also includes an intermediate adhesion layer (not shown). In some exemplary embodiments, the intermediate adhesion layer is located between the patterned electrode layer 3 and the dielectric layer 2; in other exemplary embodiments, the intermediate adhesion layer is located between the patterned electrode layer 3 and the piezoelectric functional layer 4; in other exemplary embodiments, the piezoelectric heterostructure includes multiple intermediate adhesion layers, wherein there is at least one intermediate adhesion layer located between the patterned electrode layer 3 and the dielectric layer 2, and there is at least one intermediate adhesion layer located between the patterned electrode layer 3 and the piezoelectric functional layer 4; the intermediate adhesion layer is used to increase the adhesion between the patterned electrode layer 3 and the dielectric layer 2 and / or between the dielectric layer 2 and the piezoelectric functional layer 4, to prevent the dielectric layer 2 and the piezoelectric functional layer 4 from falling off, which is beneficial to improving the structural reliability and structural stability of the piezoelectric heterostructure.

[0065] Specifically, in some preferred embodiments, the intermediate adhesion layer is contoured and aligned with the patterned electrode layer 3, and the intermediate adhesion layer has good adhesion, which can greatly improve the adhesion reliability between the patterned electrode layer 3 and the adjacent layer structure; in addition, the material of the intermediate adhesion layer is metal, and the same preparation method as the patterned electrode layer 3 can be adopted during the preparation process, which simplifies the preparation difficulty and improves the alignment accuracy between the intermediate adhesion layer and the patterned electrode layer 3, which is further beneficial to improving the overall structural stability and durability of the piezoelectric heterostructure.

[0066] Specifically, the material of the intermediate adhesion layer includes at least one of titanium, tungsten, titanium tungsten, nickel, chromium and molybdenum. Compared with the adhesion between the patterned electrode layer 3 and the piezoelectric functional layer 4, the adhesion between the intermediate adhesion layer and the patterned electrode layer 3, between the intermediate adhesion layer and the dielectric layer 2, and between the intermediate adhesion layer and the piezoelectric functional layer 4 are better, which can effectively improve the adhesion reliability of the piezoelectric functional layer 4, the dielectric layer 2 and the patterned electrode layer 3, and is beneficial to improving the overall structural accuracy, structural reliability and structural stability of the piezoelectric heterostructure.

[0067] Specifically, the thickness of the intermediate adhesion layer is 1nm to 15nm; it can be understood that the thickness of the intermediate adhesion layer can be any point value between 1nm and 15nm; illustratively, the thickness of the intermediate adhesion layer can be 1nm, 3nm, 5nm, 6nm, 8nm, 10nm, 12nm, 13nm, 15nm, etc.; on the one hand, it can effectively improve the adhesion inside the piezoelectric heterostructure and improve the overall structural stability of the piezoelectric heterostructure, and on the other hand, it can avoid adverse effects on the performance optimization of the piezoelectric heterostructure.

[0068] Specifically, Figure 3 and Figure 4As shown, the piezoelectric heterostructure has an air gap 5, which is located between the patterned electrode layer 3 and the dielectric layer 2. The air gap 5 has an extremely high acoustic impedance and can confine the acoustic wave energy in the piezoelectric functional layer 4, so as to facilitate the preparation of various types of acoustic wave resonators, such as thin film bulk acoustic resonator (FBAR) and laser diode bar (YBAR) devices.

[0069] In some exemplary embodiments, the patterned electrode layer 3 has a preset shape, wherein an air gap 5 exists in at least a portion of the region between the patterned electrode layer 3 and the dielectric layer 2, so that the patterned electrode layer 3 on the portion of the region is suspended relative to the substrate layer 1, that is, at least a portion of the patterned electrode layer 3 is suspended above the substrate layer 1, and an air gap 5 exists between the portion of the patterned electrode layer 3 and the substrate layer 1 at the bottom and the dielectric layer 2 on the peripheral side; illustratively, as Figure 3 and Figure 4 As shown, in the entire piezoelectric heterostructure, there is an air gap 5 between the patterned electrode layer 3 and the dielectric layer 2; illustratively, there is an air gap 5 in a partial area between the patterned electrode layer 3 and the dielectric layer 2, as shown in FIG. Figure 1-4 The structures shown can coexist in the same piezoelectric heterostructure, but are located in different regions of the piezoelectric heterostructure. In this way, the piezoelectric heterostructure is more flexible and diverse, and can meet the performance requirements of a variety of different semiconductor devices, thereby expanding the scope of application of the piezoelectric heterostructure.

[0070] In addition, in some other exemplary embodiments, Figure 5 As shown, a suspended groove may be opened in the substrate layer 1, and the suspended groove is located below the patterned electrode layer 3 to form a suspended structure to meet the performance requirements of a specific semiconductor device and further expand the application scope of the piezoelectric heterostructure.

[0071] On the other hand, Figure 6 As shown, the embodiment of the present application also provides a method for preparing a piezoelectric heterostructure, comprising:

[0072] S1, forming a patterned electrode layer on a piezoelectric wafer substrate;

[0073] S2, forming a dielectric layer on the patterned electrode layer;

[0074] S3, performing ion implantation on the piezoelectric wafer substrate on which the patterned electrode layer and the dielectric layer are formed, and bonding a surface of the piezoelectric wafer substrate having the patterned electrode layer to the substrate layer to form a bonding structure;

[0075] S4, performing a first heat treatment on the bonding structure to peel off the piezoelectric wafer substrate to form a piezoelectric functional layer, thereby obtaining the piezoelectric heterostructure; the piezoelectric heterostructure comprises a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric functional layer, the dielectric layer is located between the substrate layer and the piezoelectric functional layer, the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected to the piezoelectric functional layer; the piezoelectric functional layer has a first surface and a second surface which are opposite to each other, the first surface is a peeling surface, and the peeling surface is located on the side of the piezoelectric functional layer which is opposite to the substrate layer.

[0076] First, if Figure 7 and Figure 8 As shown, in step S1, the patterned electrode layer 3 is formed by first forming a metal layer on the original exposed surface (i.e., the second surface 42) of the piezoelectric wafer substrate 43 before ion implantation of ions into the piezoelectric wafer substrate 43 to form the piezoelectric functional layer 4, and patterning the metal layer to form the patterned electrode layer 3. Therefore, there is no need to perform patterning after the ion implantation, thereby avoiding the need to perform secondary etching of the piezoelectric functional layer 4 or the substrate layer 1 after the ion implantation to achieve patterning. This greatly reduces the complexity of the entire preparation method, simplifies the preparation method, and is also beneficial to improving the overall preparation accuracy and preparation yield. At the same time, it also avoids the strict high temperature conditions during the ion implantation process that lead to excessive stress between the entire metal layer and the piezoelectric functional layer 4, resulting in debonding and other conditions that reduce the overall structural accuracy and overall structural stability.

[0077] Next, in step S2, the dielectric layer 2 is formed after the patterned electrode layer 3 is formed, and is also formed before the piezoelectric wafer substrate 43 is ion-implanted to form the piezoelectric functional layer 4. The dielectric layer 2 fills the gap in the patterned electrode layer 3, and cooperates with the patterned electrode layer 3 to further restrict the patterned electrode layer 3 and the piezoelectric functional layer 4, thereby avoiding the large thermal stress caused by the traditional metal layer distributed on the entire surface during the subsequent first heat treatment. That is, the preparation method can further reduce the stress caused by thermal mismatch between the patterned electrode layer 3 and the piezoelectric functional layer 4, thereby reducing the adverse effects of stress on the overall structure, greatly improving the structural accuracy, structural reliability and structural stability of the obtained piezoelectric heterostructure and the semiconductor device having the piezoelectric heterostructure; in addition, Compared with the situation where the metal layer distributed on the entire surface increases the leakage of the body wave energy of the acoustic wave resonator and introduces strong interference, when the piezoelectric heterostructure prepared by the preparation method is applied to a semiconductor device (such as an acoustic wave resonator), the patterned electrode layer 3 and the dielectric layer 2 can also reduce the leakage of the body wave energy and reduce interference, thereby further improving the acoustic energy confinement capability of the piezoelectric heterostructure; and, in steps S1 to S2, the patterned electrode layer 3 is preferentially formed, which can also improve the convenience of preparing a variety of different types of semiconductor devices. For example, in some embodiments, it is necessary to release part of the dielectric layer 2 under the patterned electrode layer 3 to prepare a body wave device. In this case, compared with the surface metal layer distributed on the entire surface, the release convenience of the dielectric layer 2 under the patterned electrode layer 3 is better, and the preparation accuracy of forming the air gap 5 is higher.

[0078] The dielectric layer 2 can be formed on the piezoelectric wafer substrate 43 with the patterned electrode layer 3 by physical vapor deposition or chemical vapor deposition. The formation temperature of the dielectric layer 2 is less than or equal to a preset temperature, which is 400°C to 750°C. It can be understood that the preset temperature can be any point value between 400°C and 750°C. Exemplarily, the preset temperature can be 400°C, 450°C, 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, etc. In this way, the temperature is relatively low, which can reduce thermal stress. It can also effectively deposit the dielectric layer 2, improve the molding accuracy of the dielectric layer 2, effectively cover the patterned electrode layer 3 and fill the gap in the patterned electrode layer 3, improve the filling sufficiency, and thus help to reduce the adverse effects of stress generated in the subsequent heat treatment process on the overall structure of the piezoelectric heterostructure. In some preferred embodiments, the preset temperature can be selected as 600°C, that is, the formation temperature of the dielectric layer 2 is less than or equal to 600°C.

[0079] Specifically, before ion implantation is performed on the piezoelectric wafer substrate 43 on which the patterned electrode layer 3 and the dielectric layer are formed, and a surface of one side of the piezoelectric wafer substrate 43 having the patterned electrode layer 3 is bonded to the substrate layer to form a bonding structure, that is, between step S2 and step S3, the method further includes:

[0080] The piezoelectric wafer substrate is subjected to a second heat treatment; the temperature of the second heat treatment is greater than the formation temperature of the dielectric layer, and the time of the second heat treatment is greater than the formation time of the dielectric layer.

[0081] The second heat treatment step is used to remove air at the interface between the dielectric layer 2 and the patterned electrode layer 3, prevent the formation of bonding bubbles, and improve the filling density between the dielectric layer 2 and the patterned electrode layer 3, which is beneficial to improving the bonding accuracy and bonding reliability, and further beneficial to improving the overall preparation accuracy and preparation yield.

[0082] In some exemplary embodiments, before and after the second heat treatment, the heating rate and cooling rate of the second heat treatment are 0.2°C / min to 2°C / min; it can be understood that the heating rate and cooling rate of the second heat treatment can be any point value in the range of 0.2°C / min to 2°C / min; illustratively, the heating rate and cooling rate of the second heat treatment can be 0.2°C / min, 0.5°C / min, 1°C / min, 1.2°C / min, 1.5°C / min, 1.8°C / min, 2°C / min, etc.; the slow heating and cooling rates can effectively prevent the piezoelectric wafer substrate from breaking, and are also beneficial to prevent the accumulation of thermal stress, and avoid the adverse effects of rapid temperature changes on the precision and stability of the piezoelectric heterostructure.

[0083] Among them, Fig. 9 As shown, in the process of forming the dielectric layer 2 in step S2, a step layer 21 is formed on the area corresponding to the patterned electrode layer 3, and the step layer 21 covers the patterned electrode layer 3, so that the patterned electrode layer 3 is located as a whole inside the dielectric layer 2. Afterwards, the dielectric layer 2 with the step layer 21 is planarized, and the step layer 21 is removed so that the surface reaches a preset flatness to obtain the dielectric layer 2.

[0084] The preset flatness RMS (root mean square roughness) is less than the preset roughness, and the preset roughness is 0.5nm~2nm; it can be understood that the preset roughness can be any point value between 0.5nm and 2nm; illustratively, the preset roughness can be 0.5nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 1.8nm, 2nm, etc.; the high flatness of the surface of the dielectric layer 2 is beneficial to improve the subsequent bonding accuracy and bonding reliability between the substrate layer 1, and improve the bonding structure and the structural accuracy, structural reliability and structural stability of the piezoelectric heterostructure finally obtained; in some preferred embodiments, the preset roughness is 1nm, that is, the preset flatness of the surface of the dielectric layer 2 is less than 1nm.

[0085] Specifically, in some exemplary embodiments, when the thickness of the step layer 21 is relatively thick, for example, when the thickness of the step layer 21 is greater than or equal to 5 nm, before performing planarization to remove the step layer 21, the step layer 21 can be pre-etched to reduce the thickness of the step layer 21 to less than 5 nm, and then the step layer 2 is planarized. This is beneficial to reduce the performance requirements for the polishing equipment, and the polishing removal amount is also less, which is beneficial to improve the preparation accuracy and preparation yield.

[0086] Next, in step S3, ion implantation is performed on the piezoelectric wafer substrate 43 to form a damaged layer 44 at a preset depth inside the piezoelectric wafer substrate 43, and the piezoelectric wafer substrate 43 is flipped over so that the surface of the piezoelectric wafer substrate 43 having the patterned electrode layer 3 is bonded to the substrate layer 1; thus, through one flip bonding, the crystal axis direction of the original piezoelectric wafer substrate 43 is converted to the opposite direction, that is, the crystal axis direction of the piezoelectric functional layer 4 finally formed is opposite to the crystal axis direction of the original piezoelectric wafer substrate 43, which is convenient for selecting a piezoelectric wafer substrate with a suitable crystal axis. The wafer substrate 43 is prepared, for example, a +X-cut LN film is selected as the piezoelectric functional layer 4, and a -X-cut LN substrate can be used as the piezoelectric wafer substrate 43 for preparation; more importantly, the positive and negative directions of the crystal axis of the piezoelectric functional layer 4 can be suitable for the preparation of subsequent semiconductor devices. On the semiconductor device made based on the piezoelectric functional layer 4, under the condition of having the same in-plane propagation angle, the electromechanical coupling coefficient, spurious response and operating frequency of semiconductor devices such as resonators can be significantly improved to meet the frequency or bandwidth requirements in the 5G and 6G frequency bands.

[0087] In the ion implantation process, the type of implanted ions is at least one of H ions, He ions or Ar ions, the implantation energy is 30 KeV to 300 KeV, and the implantation dose is 1×10 14 ions / cm 2 ~1×10 17 ions / cm 2It can be understood that the implantation energy can be any value between 30KeV and 300KeV, and the implantation dose can be 1×10 14 ions / cm 2 ~1×10 17 ions / cm 2 ; For example, the implantation energy may be 30 KeV, 50 KeV, 100 KeV, 150 KeV, 200 KeV, 300 KeV, etc.; the implantation dose may be 1×10 14 ions / cm 2 , 5×10 14 ions / cm 2 , 1×10 15 ions / cm 2 , 5×10 15 ions / cm 2 , 1×10 16 ions / cm 2 , 1×10 17 ions / cm 2 Etc.; In this way, the thickness and depth of the damaged layer 44 formed in the piezoelectric wafer substrate 43 can be effectively controlled by ion implantation, and the initial thickness range of the piezoelectric functional layer 4 can be preliminarily controlled, so as to facilitate the subsequent steps such as post-annealing and flattening to accurately control the thickness of the piezoelectric functional layer 4, thereby improving the preparation accuracy and convenience.

[0088] Then, if Fig.10 As shown, during the first heat treatment in step S4, the piezoelectric wafer substrate 43 is peeled off along the damaged layer 44, that is, the first heat treatment is used to separate the piezoelectric functional layer 4 of the piezoelectric wafer substrate 43 from the damaged layer 44 and increase the bonding strength between the dielectric layer 2 and the substrate layer 1.

[0089] The temperature of the first heat treatment is 100°C to 450°C, the time is 2h to 24h, and the atmosphere environment includes at least one of nitrogen, oxygen, inert gas and vacuum environment; the heating and cooling rates before and after the first heat treatment are 0.5°C / min to 2.5°C / min, and the heating and cooling rates before and after the first heat treatment are greater than or equal to the heating and cooling rates before and after the second heat treatment; it can be understood that the temperature of the first heat treatment can be any point value in the range of 100°C to 450°C, the time can be any point value in the range of 2h to 24h, and the heating and cooling rates before and after the first heat treatment can be any point value in the range of 0.5°C / min to 2.5°C / min; illustratively, the temperature of the first heat treatment can be 100°C, 150 ℃, 200℃, 250℃, 300℃, 400℃, 450℃, etc.; the time can be 2h, 4h, 6h, 10h, 15h, 20h, 24h, etc.; the heating and cooling speeds before and after the first heat treatment can be 0.5℃ / min, 1℃ / min, 1.5℃ / min, 1.8℃ / min, 2℃ / min, 2.2℃ / min, 2.5℃ / min, etc.; in this way, the piezoelectric functional layer 4 can be separated stably and reliably, and the bonding strength between the dielectric layer 2 and the substrate layer 1 can be improved, which is also beneficial to improving the bonding strength between adjacent layers inside the piezoelectric heterostructure, improving the overall structural strength of the piezoelectric heterostructure, preventing the occurrence of debonding, and greatly improving the stability and durability.

[0090] Moreover, the difference between the bonding temperature of the bonding in step S3 and the temperature of the first heat treatment in step S4 is less than or equal to a preset temperature difference, and the preset temperature is 150°C to 300°C; it can be understood that the preset temperature can be any point value between 150°C and 300°C; illustratively, the preset temperature can be 150°C, 180°C, 200°C, 220°C, 250°C, 280°C, 300°C, etc.; in this way, the temperature difference is small, and thermal stress is not easy to occur, which is beneficial to improving the structural stability of the piezoelectric heterostructure.

[0091] Afterwards, the remaining damaged layer 44 is post-annealed and planarized to form a piezoelectric functional layer 4, thereby obtaining a final piezoelectric heterostructure. The surface after the planarization is the first surface 41, i.e., the peeling surface. The temperature of the post-annealing treatment is 200°C to 600°C, and the heating and cooling rate is 0.5°C / min to 5°C / min. The heating and cooling rate is also greater than or equal to the heating and cooling rate before and after the second heat treatment, thereby accelerating the preparation efficiency. It can be understood that the temperature of the post-annealing treatment can be any point value between 200°C and 600°C, and the heating and cooling rate can be 0.5°C / min to 5°C / min. min; illustratively, the temperature of the post-annealing treatment can be 200°C, 300°C, 400°C, 500°C, 550°C, 600°C, etc.; the heating and cooling speed can be 0.5°C / min, 1°C / min, 1.5°C / min, 2°C / min, 3°C / min, 4°C / min, 5°C / min, etc.; in this way, the piezoelectric wafer substrate 43 can be effectively peeled off along the damaged layer 44, while avoiding adverse effects on the bonding strength of the piezoelectric heterostructure, so that the performance of the piezoelectric heterostructure is effectively maintained, and the accuracy and stability of the piezoelectric heterostructure are improved.

[0092] Specifically, in some exemplary embodiments, the piezoelectric heterostructure further includes an air gap 5; correspondingly, Fig.11 As shown, after step S4, the method further includes:

[0093] The piezoelectric heterostructure is etched to partially remove the dielectric layer between the patterned electrode layer and the substrate layer below the piezoelectric functional layer to form the air gap.

[0094] In this step, the piezoelectric functional layer 4 covers the surface of the entire piezoelectric heterostructure. A target etching area can be defined on the piezoelectric functional layer 4, and the target etching area is etched to form an etching window through the portion of the piezoelectric functional layer 4 that penetrates the target etching area. Afterwards, an etching method such as gas etching is used to remove the underlying dielectric layer 2 through the etching window. The preparation is simple and quick, and the molding accuracy is good.

[0095] On the other hand, the present application also provides a piezoelectric heterogeneous substrate, including the piezoelectric heterogeneous structure as described above, or including a piezoelectric heterogeneous structure prepared by the preparation method of the piezoelectric heterogeneous structure as described above, and the sound velocity, operating frequency and electromechanical coupling coefficient are effectively improved.

[0096] On the other hand, the present application also provides a semiconductor device, comprising the piezoelectric heterostructure and surface electrodes as described above, wherein the surface electrodes are located on the piezoelectric functional layer 4 and at least part of the surface electrodes are arranged on the patterned electrode layer 3 to utilize the acoustic mode excited by the longitudinal electric field to improve the sound velocity and electromechanical coupling coefficient of the semiconductor device; in some exemplary embodiments, the semiconductor device includes at least one of a surface acoustic wave resonator and a bulk acoustic wave resonator.

[0097] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0098] The above description has fully disclosed the specific implementation methods of the present application. It should be pointed out that any changes made by technicians familiar with the field to the specific implementation methods of the present application do not deviate from the scope of the claims of the present application. Accordingly, the scope of the claims of the present application is not limited to the above specific implementation methods.

Claims

1. A piezoelectric heterostructure, characterized in that: The device comprises a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric functional layer, wherein the dielectric layer is located between the substrate layer and the piezoelectric functional layer, the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected to the piezoelectric functional layer; The piezoelectric functional layer has a first surface and a second surface which are opposite to each other. The first surface is a release surface which is located at a side of the piezoelectric functional layer which is opposite to the substrate layer.

2. The piezoelectric heterostructure according to claim 1, characterized in that: The piezoelectric heterostructure further comprises an intermediate adhesion layer, wherein the intermediate adhesion layer is located between the patterned electrode layer and the dielectric layer, and / or The intermediate adhesion layer is located between the patterned electrode layer and the piezoelectric functional layer.

3. The piezoelectric heterostructure according to claim 2, characterized in that: The middle adhesive layer and the patterned electrode layer are arranged in conformity and in alignment.

4. The piezoelectric heterostructure according to claim 2, characterized in that: The intermediate adhesive layer satisfies at least one of the following characteristics: The material of the intermediate adhesion layer includes at least one of titanium, tungsten, titanium tungsten, nickel, chromium and molybdenum; The thickness of the intermediate adhesion layer is 1 nm to 15 nm.

5. The piezoelectric heterostructure according to any one of claims 1 to 4, characterized in that: The piezoelectric heterostructure has an air gap therein, and the air gap is located between the patterned electrode layer and the dielectric layer.

6. The piezoelectric heterostructure according to any one of claims 1 to 4, characterized in that: The thickness of the piezoelectric heterostructure satisfies at least one of the following characteristics: The thickness of the dielectric layer is 10nm to 2000nm; The thickness of the patterned electrode layer is 5nm to 150nm; The thickness of the piezoelectric functional layer is 50nm to 2200nm.

7. The piezoelectric heterostructure according to any one of claims 1 to 4, characterized in that: The material of the piezoelectric heterostructure satisfies at least one of the following characteristics: The material of the substrate layer includes at least one of silicon, silicon oxide, quartz, sapphire, silicon carbide, silicon nitride, gallium nitride and diamond; The material of the dielectric layer includes at least one of silicon oxide, silicon nitride, polysilicon, amorphous silicon, aluminum oxide and aluminum nitride; The material of the patterned electrode layer includes at least one of gold, silver, copper, aluminum, nickel, platinum, titanium, tantalum, tungsten, chromium and molybdenum; The material of the piezoelectric functional layer includes at least one of single crystal lithium niobate, single crystal lithium tantalate, aluminum nitride, scandium-doped aluminum nitride and lead zirconate titanate.

8. A method for preparing a piezoelectric heterostructure, characterized in that: include: forming a patterned electrode layer on a piezoelectric wafer substrate; forming a dielectric layer on the patterned electrode layer; Performing ion implantation on the piezoelectric wafer substrate on which the patterned electrode layer and the dielectric layer are formed, and bonding a surface of one side of the piezoelectric wafer substrate having the patterned electrode layer to the substrate layer to form a bonding structure; The bonding structure is subjected to a first heat treatment so that the piezoelectric wafer substrate is peeled off to form a piezoelectric functional layer, thereby obtaining the piezoelectric heterostructure; the piezoelectric heterostructure comprises a substrate layer, a dielectric layer, a patterned electrode layer and a piezoelectric functional layer, the dielectric layer is located between the substrate layer and the piezoelectric functional layer, the patterned electrode layer is located in the dielectric layer, and one side of the patterned electrode layer is exposed to the dielectric layer and is electrically connected to the piezoelectric functional layer; the piezoelectric functional layer has a first surface and a second surface which are opposite to each other, the first surface is a peeling surface, and the peeling surface is located on the side of the piezoelectric functional layer which is opposite to the substrate layer.

9. The method for preparing a piezoelectric heterostructure according to claim 8, characterized in that: Before ion implantation is performed on the piezoelectric wafer substrate on which the patterned electrode layer and the dielectric layer are formed, and a surface of the piezoelectric wafer substrate having the patterned electrode layer is bonded to the substrate layer to form a bonding structure, the method further comprises: The piezoelectric wafer substrate is subjected to a second heat treatment; the temperature of the second heat treatment is greater than the formation temperature of the dielectric layer, and the time of the second heat treatment is greater than the formation time of the dielectric layer.

10. A semiconductor device, characterized in that: It comprises the piezoelectric heterostructure according to any one of claims 1 to 7 and a surface electrode, wherein the surface electrode is located on the piezoelectric functional layer and at least part of the surface electrode is arranged on the patterned electrode layer.

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