Magnetic memory and array thereof

Abstract

The invention provides a magnetic memory and an array thereof, relates to the technical field of semiconductors, and is used for improving a writing mode of the magnetic memory and realizing a high-density magnetic memory array. According to the magnetic memory structure provided by the invention, the bias region is arranged, and the interior of the bias region is at least filled with the ferromagnetic layer, the antiferromagnetic layer and the seed layer, so that the stability of the magnetic memory can be effectively improved; the stray field generated by the ferromagnetic layer can assist the magnetic direction of the free layer in flipping, so that field-free flipping is realized, the polarity of the ferromagnetic layer can still be stable after the magnetic memory is miniaturized due to the exchange bias effect generated between the ferromagnetic layer and the anti-ferromagnetic layer, the device stability after the size of the magnetic memory is miniaturized is further improved, and the reliability of the magnetic memory is improved. And realization of a high-density magnetic memory array is facilitated.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a magnetic memory and an array thereof. Background Art

[0002] Magnetic Random Access Memory (MRAM) is one of the main candidates for the next generation of memory technology. The basic storage unit of MRAM is the magnetic tunnel junction (MTJ). The core structure of MTJ is a sandwich structure formed by two ferromagnetic layers sandwiching an oxide barrier layer. The magnetization direction of one ferromagnetic layer remains unchanged and is called the fixed layer. The magnetization direction of the other ferromagnetic layer can be changed by external excitation and is called the free layer. When the magnetization direction of the free layer is parallel or antiparallel to the fixed layer, the MTJ is in a low resistance state or a high resistance state, respectively. The two resistance states can represent binary data "0" and "1", respectively.

[0003] According to the different data writing mechanisms, the development of MRAM has undergone three generations of changes. Among them, the third-generation magnetic memory, spin-orbit torque magnetic memory (Spin-orbit Torque MRAM, SOT-MRAM), has the advantages of non-volatility, high-speed and low-power data writing (< 1 ns, < ~0.1 pJ / bit) and high device durability. It is a key technology that is expected to break through the power consumption bottleneck of integrated circuits in the post-Moore era. The basic storage unit structure of SOT-MRAM is to add a heavy metal layer adjacent to the MTJ free layer to form a multilayer film structure of "heavy metal / free layer / barrier layer / fixed layer". The flow of current through the heavy metal can generate a spin current, which can flip the magnetization direction of the free layer, thereby realizing data writing.

[0004] According to the different directions of the write current and the free layer, SOT-MRAM is divided into three types: the write current direction of Type-X devices is parallel to the direction of the free layer magnetic moment, and both are located in the plane; the write current direction of Type-Y devices is perpendicular to the direction of the free layer magnetic moment, and both are located in the plane; the write current direction of Type-Z devices is perpendicular to the direction of the free layer magnetic moment, and the direction of the free layer magnetic moment is located outside the plane (Perpendicular Magnetic Anisotropy, PMA). Among the above three types of MTJ, only Type-Z can be made into a circular device, which is conducive to small-size miniaturization and high-density integration. However, the flipping of the PMA free layer of the Type-Z device requires an external auxiliary magnetic field. The introduction of an external magnetic field will increase the complexity of data writing and is not conducive to process integration.

[0005] The existing technology mainly achieves the magnetic field-free reversal of Type-Z by introducing antiferromagnetic / ferromagnetic exchange bias. In 2019, the Interuniversity Microelectronics Centre (IMEC) of Belgium disclosed that by adding a thicker cobalt magnetic layer on the top of the MTJ to generate a stray magnetic field, the magnetic moment reversal of the free layer can be achieved without introducing an external magnetic field; and in 2022, it was disclosed that by adding a thicker magnetic material at the bottom of the spin-orbit moment layer, a stray field is provided to flip the free layer. However, the above technical means require the addition of a thicker magnetic layer, and the generation of a larger stray magnetic field will also interfere with adjacent devices, which is not conducive to large-scale integration and reduces the device integration density; and when the MTJ continues to shrink, the size of the added magnetic layer will also decrease accordingly, and its magnetic anisotropy will weaken, causing the magnetization direction of the magnetic layer to become unstable, and unable to provide a stable stray magnetic field for deterministic reversal of the free layer. Summary of the invention

[0006] To solve the above problems, the present disclosure provides a magnetic memory and an array thereof. By optimizing the device structure and its array structure, an exchange bias (EB) at the antiferromagnetic / ferromagnetic interface is introduced into the magnetic memory structure to provide a stable stray field, thereby improving the writing method of the magnetic memory and realizing a new high-density storage array.

[0007] According to some embodiments, the present disclosure provides a magnetic memory, including: a substrate, a bias region, a spin-orbit moment layer, and a magnetic tunnel junction arranged above the spin-orbit moment layer; the substrate is located below the spin-orbit moment layer, the upper surface of the bias region is not higher than the upper surface of the spin-orbit moment layer and the lower surface of the bias region is not lower than the lower surface of the substrate, and the interior of the bias region is filled with at least a ferromagnetic layer, an antiferromagnetic layer and a seed layer along the direction away from the magnetic tunnel junction.

[0008] In some possible implementations, a first insertion spacer layer is disposed between the spin-orbit moment layer and the ferromagnetic layer, and / or a second insertion spacer layer is disposed between the ferromagnetic layer and the antiferromagnetic layer.

[0009] In some possible implementations, the initial magnetization direction of the ferromagnetic layer in the magnetic memory is set to have a first polarity, and the initial magnetization direction has a component in a direction parallel to a direction of a write current flowing into the spin-orbit moment layer.

[0010] In some possible implementations, the magnitude of the exchange bias field between the ferromagnetic layer and the antiferromagnetic layer in the magnetic memory is greater than the magnitude of the coercive field of the ferromagnetic layer.

[0011] In some possible implementations, an upper surface of the biasing region is flush with an upper surface of the substrate and a lower surface of the biasing region is not lower than a lower surface of the substrate.

[0012] In some possible implementations, the upper surface of the bias region is higher than the upper surface of the substrate and the lower surface of the bias region is not lower than the lower surface of the substrate, and a first isolation layer is provided around a portion of the bias region that is higher than the upper surface of the substrate.

[0013] The magnetic storage device provided by the embodiments of the present disclosure has at least the following advantages: The magnetic memory provided by the embodiment of the present disclosure includes a substrate, a bias region, a spin-orbit moment layer and a magnetic tunnel junction; the upper surface of the bias region is not higher than the upper surface of the spin-orbit moment layer and the lower surface of the bias region is not lower than the lower surface of the substrate, and the inside of the bias region is filled with at least a ferromagnetic layer, an antiferromagnetic layer and a seed layer in a direction away from the magnetic tunnel junction. The stray field generated by the ferromagnetic layer can assist the magnetic direction of the free layer to flip, thereby realizing field-free flipping. The exchange bias effect generated between the ferromagnetic layer / antiferromagnetic layer enables the stray field of the ferromagnetic layer to remain stable after the magnetic memory is miniaturized, further improving the device stability after the size of the magnetic memory is miniaturized, which is conducive to high-density integration.

[0014] The disclosed embodiment also provides a magnetic memory array, the array comprising one or more magnetic memories as described in all the above implementations distributed in an array, as well as a plurality of write word lines, a plurality of source lines, and a plurality of read word lines; One end of the spin-orbit moment layer of each column of magnetic memory is connected to a write word line; The other end of the spin-orbit moment layer of each row of magnetic memory is connected to a source line; A top electrode is disposed on the top of the magnetic tunnel junction, and the top electrode of each row or column of the magnetic memory is connected to a read word line.

[0015] In some possible implementations, an initial magnetization direction of a ferromagnetic layer in a magnetic memory array is set to have a first polarity; The direction of the write current flowing into the spin-orbit moment layer is controlled by writing a word line and a source line, thereby changing the resistance state of the target magnetic memory.

[0016] The magnetic memory array provided by the present disclosure has at least the following advantages: The magnetic memory array provided by the present disclosure includes one or more array-distributed magnetic memories, a plurality of write word lines, a plurality of source lines and a plurality of read word lines, wherein the bias region of each magnetic memory is filled with at least a ferromagnetic layer, an antiferromagnetic layer and a seed layer, and the stray field generated by the ferromagnetic layer inside the bias region can assist the magnetic direction of the free layer to flip, and no external magnetic field is required, thereby reducing the device volume and facilitating the improvement of the arrangement density of the magnetic memory array; and the exchange bias between the ferromagnetic layer and the antiferromagnetic layer can pin (fix) the polarity of the ferromagnetic layer, provide a stable stray field, and improve the stability of the magnetic memory array.

[0017] An embodiment of the present disclosure also provides a magnetic memory array, which includes a plurality of magnetic memories distributed in an array as described in all the aforementioned implementations, wherein the spin-orbit moment layers of each row of magnetic memories are interconnected to form a spin-orbit moment channel, the bias regions of each column of magnetic memories are interconnected to form a bias channel, and a second isolation layer is arranged between the spin-orbit moment layer and the bias region of each magnetic memory.

[0018] In some possible implementations, the spin-orbit torque channel is formed by connecting the spin-orbit moment layers of each row of magnetic memories through a conductive material, and / or the bias channel is formed by connecting the bias regions of each column of magnetic memories through a conductive material.

[0019] In some possible implementations, the magnetic memory array also includes a number of write word lines, which are configured to allow a write current to flow in a spin-orbit torque channel to change the resistance state of the magnetic memory; a number of control bit lines, which are configured to allow a bias current to flow in a bias channel to change the polarity of a ferromagnetic layer in the bias channel; and the change in the resistance state of the magnetic memory is achieved by controlling the polarity of the ferromagnetic layer and the direction of the write current in the spin-orbit torque channel.

[0020] In some possible implementations, the resistance state of the magnetic memory is changed by controlling the polarity of the ferromagnetic layer and the direction of the write current of the spin-orbit torque channel, including: the ferromagnetic layer in the magnetic memory is a first polarity; the direction of the write current applied by the write word line to the spin-orbit torque channel is controlled to change the resistance state of the magnetic memory.

[0021] In some possible implementations, the resistance state of the magnetic memory is changed by controlling the polarity of the ferromagnetic layer and the direction of the write current of the spin-orbit torque channel, including: the ferromagnetic layer in the magnetic memory is of a first polarity; the resistance state of the magnetic memory is changed by controlling the direction of the write current applied to the spin-orbit torque channel by the write word line; the ferromagnetic layer has a second polarity by controlling the bias current applied to the bias channel by the control bit line; and the magnetic memory has a resistance state opposite to that in the first polarity state by controlling the write word line to apply a write current in the same direction as that in the first polarity state to the spin-orbit torque channel.

[0022] The magnetic memory array provided by the embodiment of the present disclosure has at least the following advantages: The magnetic memory array provided by the embodiment of the present disclosure includes a plurality of magnetic memories distributed in an array, wherein the spin-orbit moment layers of each row of magnetic memories are interconnected to form a spin-orbit moment channel, the bias regions of each column of magnetic memories are interconnected to form a bias channel, an isolation layer is provided between the spin-orbit moment layer and the bias region of each magnetic memory, the stray field generated by the ferromagnetic layer inside the bias channel can assist the magnetic direction of the free layer to flip, and no external magnetic field is required, thereby reducing the volume of the device, which is conducive to improving the arrangement density of the magnetic memory array; and the exchange bias between the ferromagnetic layer and the antiferromagnetic layer can pin (fix) the polarity of the ferromagnetic layer, the magnetization direction is stable and not disturbed by the external magnetic field, the stray field of the device is stable, and miniaturization can be achieved to obtain a high-stability and high-density magnetic memory array. In addition, the magnetic memory array provided by the embodiment of the present disclosure realizes the change of the resistance state of the magnetic memory by controlling the polarity of the ferromagnetic layer and the writing current direction of the spin-orbit moment channel, which can not only refresh the storage states of multiple magnetic memories at the same time, but also realize the writing of a single magnetic memory, and can form a multifunctional gate write magnetic memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the structure of a first magnetic storage device in an embodiment of the present disclosure; Figure 2 It is a schematic structural diagram of a second magnetic memory in an embodiment of the present disclosure; Figure 3 is a schematic diagram of a first magnetic memory array in an embodiment of the present disclosure; Figure 4 is a schematic diagram of a second magnetic memory array in an embodiment of the present disclosure; Figure 5 is a top view of a third magnetic memory array schematic diagram in an embodiment of the present disclosure; Figure 6 It is a top view of a fourth magnetic memory array schematic diagram in an embodiment of the present disclosure.

[0024] Description of reference numerals: M1-magnetic memory; 10-substrate; 20-bias region; 21-ferromagnetic layer; 22-antiferromagnetic layer; 23-seed layer; 30-spin-orbit moment layer; 30A-one end of the spin-orbit moment layer; 30B-the other end of the spin-orbit moment layer; 40-magnetic tunnel junction; 41-free layer; 42-barrier layer; 43-fixed layer; 50-top electrode; 60-first dielectric protection layer; 70-second dielectric protection layer; 80-spin-orbit channel; 90-bias channel; 100-first connection region; 110-second connection region. DETAILED DESCRIPTION

[0025] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described in the present disclosure are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present disclosure.

[0026] The present disclosure provides a magnetic memory M1, whose structure is as follows: Figure 1 As shown, including: A substrate 10, a bias region 20, a spin-orbit moment layer 30, and a magnetic tunnel junction 40 arranged above the spin-orbit moment layer; the substrate 10 is located below the spin-orbit moment layer 30; the upper surface of the bias region 20 is not higher than the upper surface of the spin-orbit moment layer 30 and the lower surface of the bias region 20 is not lower than the lower surface of the substrate 10, and the inside of the bias region 20 is filled with at least a ferromagnetic layer 21, an antiferromagnetic layer 22 and a seed layer 23 along the direction away from the magnetic tunnel junction 40.

[0027] In some possible implementations, the substrate 10 may be an oxide material, a nitride material, or a substrate with a CMOS circuit, etc. The substrate 10 may contain a through hole to achieve electrical connection of the spin-orbit moment layer 30 .

[0028] In some possible implementations, the spin-orbit moment layer 30 may be a single-layer film or a multi-layer composite film layer, and its materials include: heavy metal materials such as platinum, palladium, hafnium, gold, tantalum, tungsten, iridium, and their alloys, oxides, nitrides, borides, etc.; Bi x Se 1-x 、Bi x Sb 1-x , topological insulators such as (Bi,Sb)2Te3; and two-dimensional materials such as MoS2 and WTe2.

[0029] In some possible implementations, the upper surface of the bias region 20 is not higher than the upper surface of the spin-orbit moment layer 30 and the lower surface of the bias region 20 is not lower than the lower surface of the substrate 10, preferably as follows: Figure 1 and Figure 2 The upper surface of the bias region 20 shown is flush with the upper surface of the substrate 10. The bias region 20 located in the substrate 10 can reduce electrical interference and magnetic interference to other units; in some other implementations, the upper surface of the bias region 20 is not higher than the upper surface of the spin-orbit moment layer 30 and the lower surface of the bias region 20 is not lower than the lower surface of the spin-orbit moment layer 30; in some other implementations, the upper surface of the bias region 20 is lower than the upper surface of the substrate 10 and the lower surface of the bias region 20 is not lower than the lower surface of the substrate 10.

[0030] In some possible implementations, the upper surface of the bias region 20 is higher than the upper surface of the substrate 10 and the lower surface of the bias region 20 is not lower than the lower surface of the substrate 10. The periphery of the portion of the bias region 20 that is higher than the upper surface of the substrate 10 is provided with a first isolation layer (not shown), and the material of the first isolation layer is an insulating material such as oxide or nitride.

[0031] In some possible implementations, the shape of the biasing region 20 may be rectangular, cylindrical, or the like.

[0032] In some possible implementations, the material of the ferromagnetic layer 21 can be one or more combinations of Co, Fe, Ni, CoFe, CoFeB, FeB, CoB, NiFe, etc.; the material of the antiferromagnetic layer 22 can be one or more combinations of IrMn, PtMn, FeMn, PdMn, etc.; the material of the seed layer 23 can be one or more alloys of Ta, Ru, Cr, Pt, NiFe, NiFeCr.

[0033] In some possible implementations, a first insertion spacer layer (not shown) is provided between the spin-orbit moment layer 30 and the ferromagnetic layer 21, and / or a second insertion spacer layer (not shown) is provided between the ferromagnetic layer 21 and the antiferromagnetic layer 22. The first insertion spacer layer is used to generate electrical isolation between the spin-orbit moment layer 30 and the ferromagnetic layer 21, and its material may be silicon oxide, silicon nitride or other materials; the second spacer layer is used to adjust the exchange bias field between the ferromagnetic layer 21 and the antiferromagnetic layer 22, and its material may be metal materials such as W, Ta, Mo, Ru and their alloys, or oxide materials such as magnesium oxide and silicon oxide may be used.

[0034] In some possible implementations, the initial magnetization direction of the ferromagnetic layer 21 in the magnetic memory M1 is set to have a first polarity. The initial magnetization direction can be set by annealing, magnetic field induction, or current induction. The initial magnetization direction has a component in a direction parallel to the direction of the write current passed into the spin-orbit moment layer 30. Preferably, the initial magnetization direction is parallel or anti-parallel to the direction of the write current passed into the spin-orbit moment layer 30.

[0035] In some possible implementations, since the ferromagnetic layer 21 in the magnetic memory M1 may have a coercive field, in order to allow a certain exchange bias to occur between the antiferromagnetic layer 22 and the ferromagnetic layer 21, it is preferred that the exchange bias field between the ferromagnetic layer 21 and the antiferromagnetic layer 22 is larger than the coercive field of the ferromagnetic layer 21, so that the exchange bias can pin the polarity of the ferromagnetic layer 21, so that the stray field provided by the ferromagnetic layer 21 in the magnetic memory remains stable. It is known to those skilled in the art that when the exchange bias field between the ferromagnetic layer 21 and the antiferromagnetic layer 22 is equal to or smaller than the coercive field of the ferromagnetic layer 21, an exchange bias may also occur between the antiferromagnetic layer 22 and the ferromagnetic layer 21.

[0036] In some possible implementations, the ferromagnetic layer 21, the antiferromagnetic layer 22 and the seed layer 23 are combined in an embedded manner, the ferromagnetic layer 21 is embedded in the antiferromagnetic layer 22, the antiferromagnetic layer 22 is embedded in the seed layer 23, and the upper surface of the ferromagnetic layer 21 is flush with the upper surface of the bias region 20, such as Figure 1 shown.

[0037] refer to Figure 2 In some possible implementations, the ferromagnetic layer 21, the antiferromagnetic layer 22 and the seed layer 23 are non-embedded, the ferromagnetic layer 21, the antiferromagnetic layer 22 and the seed layer 23 are not embedded with each other, and the upper surface of the ferromagnetic layer 21 is flush with the upper surface of the bias region 20.

[0038] In some possible implementations, the ferromagnetic layer 21, the antiferromagnetic layer 22, the seed layer 23 and other film layers constituting the bias region 20 are combined in any combination of embedded and non-embedded, and the upper surface of the ferromagnetic layer 21 is flush with the upper surface of the bias region 20, such as: the ferromagnetic layer 21 is embedded in the antiferromagnetic layer 22, the antiferromagnetic layer 22 and the seed layer 23 are not embedded in each other, and the upper surface of the ferromagnetic layer 21 is flush with the upper surface of the bias region 20.

[0039] In some possible implementations, the upper and lower surfaces of the ferromagnetic layer 21 , the upper and lower surfaces of the antiferromagnetic layer 22 , and the upper and lower surfaces of the seed layer 23 may be parallel to each other or may not be parallel to each other.

[0040] In some possible implementations, the magnetic tunnel junction 40 structure includes but is not limited to a free layer 41, a barrier layer 42 and a fixed layer 43. The material of the free layer 41 and the fixed layer 43 can be ferromagnetic materials, such as cobalt, iron, boron, nickel, ruthenium, iridium, platinum, etc., and the material of the barrier layer 42 is an insulating material, such as magnesium oxide, aluminum oxide, silicon oxide, etc.

[0041] In some possible implementations, the magnetic direction of the free layer 41 is a vertical magnetic direction perpendicular to the top direction of the magnetic memory M1, or a horizontal magnetic direction parallel to the direction of the current passed into the spin-orbit moment layer 30, or an in-plane magnetic direction parallel to the direction of the current passed into the bias region 20.

[0042] In some possible implementations, the magnetic memory M1 is further provided with a first dielectric protection layer 60 and a second dielectric protection layer 70, and the first dielectric protection layer 60 and the second dielectric protection layer 70 are both made of insulating materials, such as SiO2, SiN, etc.; the materials of the first dielectric protection layer 60 and the second dielectric protection layer 70 can be the same or different.

[0043] In summary, the magnetic memory M1 provided by the embodiment of the present disclosure includes a substrate 10, a bias region 20, a spin-orbit moment layer 30 and a magnetic tunnel junction 40. The upper surface of the bias region 20 is not higher than the upper surface of the spin-orbit moment layer 30 and the lower surface of the bias region 20 is not lower than the lower surface of the substrate 10. The bias region 20 is at least filled with a ferromagnetic layer 21, an antiferromagnetic layer 22 and a seed layer 23. The stray field generated by the ferromagnetic layer 21 can assist the magnetic direction of the free layer 41 to flip, thereby realizing a field-free flip. The exchange bias effect generated between the ferromagnetic layer 21 / antiferromagnetic layer 22 enables the stray field provided by the ferromagnetic layer 21 to remain stable after the device is miniaturized, further improving the device stability of the magnetic memory M1 after size miniaturization, which is conducive to high-density integration.

[0044] The present disclosure also provides a magnetic memory array, such as Figure 3 As shown, the array includes one or more magnetic memories M1 distributed in an array as described in all the above implementations, and a plurality of write word lines WWL q (Write WordLine, q=1,2,3,...,q+2), several source lines SL m (Source Line, m=1,2,3,……, ,m+2) and several read word lines RWL n (Read Word Line, n=1,2,3,..., ,n+2); One end of the spin-track moment layer 30 of each column of the magnetic memory M1 is connected to a write word line WWL q The other end of the spin-track moment layer 30 of each row of magnetic memory M1 is connected to a source line SL m A top electrode 50 is provided on the top of the magnetic tunnel junction M1, and the top electrode of each row or column of the magnetic memory M1 is connected to a read word line RWL n .

[0045] In some possible implementations, one end 30A of the spin-track moment layer 30 of each column of the magnetic memory M1 is connected to a write word line WWL q The other end 30B of the spin-track moment layer 30 of each row of magnetic memory M1 is connected to a source line SL m The other end 30B of the spin-track moment layer 30 of each column of the magnetic memory M1 is connected to a write word line WWL q One end 30A of the spin-track moment layer 30 of each row of magnetic memory M1 is connected to a source line SL m .

[0046] In some possible implementations, the top electrode 50 of each row of magnetic memory M1 is connected to a read word line RWL n , by controlling the read word line RWL nand write word line WWL q The conduction of realizes the reading of the target magnetic memory M1.

[0047] In some possible implementations, the top electrode 50 of each column of magnetic memory M1 is connected to a read word line RWL n ,like Figure 4 As shown, by controlling the read word line RWL n and source line SL m The conduction of realizes the reading of the target magnetic memory M1.

[0048] In some possible implementations, the initial magnetization direction of the ferromagnetic layer 21 in the magnetic memory array is set to have a first polarity, and the initial magnetization direction may be set by annealing, magnetic field induction, or current induction; By writing the word line WWL q and source line SL m Control the direction of the write current flowing into the spin orbit moment layer 30 to change the resistance state of the target magnetic memory M1, specifically: control the write word line WWL of the column where the target magnetic memory M1 is located q and the source line SL m The ferromagnetic layer 21 is turned on, and a write current is passed. The current flowing through the spin-orbit moment layer 30 will generate a spin current. The stray field generated by the ferromagnetic layer 21 can assist the magnetic direction of the free layer 41 to flip, thereby realizing a field-free flip to change the resistance state of the target magnetic memory M1; and the exchange bias between the ferromagnetic layer 21 and the antiferromagnetic layer 22 can pin (fix) the polarity of the ferromagnetic layer 21, so that the polarity of the ferromagnetic layer 21 in the magnetic memory remains stable, providing a stable stray field, and keeping the device stable.

[0049] Combination Figure 3 The array shown and Figure 1 The bias region structure shown in Figure 3 Take device A in the lower left corner of the magnetic memory array as an example: Writing process: setting the initial magnetization direction of the ferromagnetic layer 21 of device A in the magnetic memory array to have a first polarity, and controlling the write word line WWL of the column where device A is located. q and the source line SL of its row m Apply write current I read The conduction of device A can be controlled. The write current I read The spin-orbit moment layer 30 of device A generates a spin current. Since the initial magnetization direction is in the direction of the write current I read There is a component in the direction parallel to the direction, and the stray field generated by the ferromagnetic layer 21 assists the magnetic direction of the free layer 41 to flip, thereby realizing a field-free flip to change the resistance state of the target magnetic memory M1 to the first resistance state, and again controlling the write word line WWL of the column where the device A is located.q and the source line SL of its row m Apply a reverse write current I read , the device A changes from the first resistance state to the second resistance state opposite to the first resistance state; and the exchange bias between the ferromagnetic layer 21 and the antiferromagnetic layer 22 can pin (fix) the polarity of the ferromagnetic layer 21, so that the polarity of the ferromagnetic layer 21 remains stable, providing a stable stray field; Read process: by controlling the read word line RWL n and write word line WWL q The conduction generates a read current I write Realize the reading of the resistance state of device A.

[0050] Figure 4 The resistance state change mode of device A in the magnetic memory array shown is similar to the above Figure 3 The writing method of device A in the magnetic memory array shown is similar and will not be repeated here; the difference is that Figure 4 The magnetic memory array in which the device A is shown is configured to read the word line RWL by controlling the read word line RWL. n and source line SL m The conduction generates a read current I write Realize the reading of the resistance state of device A.

[0051] In some possible implementations, the upper surface of the bias region 20 is not higher than the upper surface of the spin-orbit moment layer 30 and the lower surface of the bias region 20 is not lower than the lower surface of the substrate 10. Preferably, the upper surface of the bias region 20 is flush with the upper surface of the substrate 10. The bias region 20 located in the substrate 10 can reduce electrical interference and magnetic interference to other units; in some other implementations, the upper surface of the bias region 20 is not higher than the upper surface of the spin-orbit moment layer 30 and the lower surface of the bias region 20 is not lower than the lower surface of the spin-orbit moment layer 30; in some other implementations, the upper surface of the bias region 20 is lower than the upper surface of the substrate 10 and the lower surface of the bias region 20 is not lower than the lower surface of the substrate 10.

[0052] In some possible implementations, the upper surface of the bias region 20 is higher than the upper surface of the substrate 10 and the lower surface of the bias region 20 is not lower than the lower surface of the substrate 10. The portion of the bias region 20 that is higher than the upper surface of the substrate 10 has a first isolation layer on the periphery, and the material of the first isolation layer is an insulating material such as oxide or nitride.

[0053] In summary, the magnetic memory array provided by the embodiment of the present disclosure includes: one or more array-distributed magnetic memories M1, a plurality of write word lines WWL q , several source lines SL m and several read word lines RWL n, wherein the bias region 20 of each magnetic memory M1 is filled with at least a ferromagnetic layer 21, an antiferromagnetic layer 22 and a seed layer 23. The stray field generated by the ferromagnetic layer 21 can assist the magnetic direction of the free layer 41 to flip, without the need for an external magnetic field, thereby reducing the device volume and facilitating the increase in the density of the magnetic memory array; and the exchange bias between the ferromagnetic layer 21 and the antiferromagnetic layer 22 can pin (fix) the polarity of the ferromagnetic layer 21, so that the polarity of the ferromagnetic layer 21 in the magnetic memory remains stable, thereby improving the stability of the magnetic memory array.

[0054] The present disclosure also provides a magnetic memory array, such as Figure 5 As shown, the array includes a plurality of magnetic memories M1 distributed in an array as described in all the aforementioned implementations, wherein the spin-orbit moment layers 30 of the magnetic memories M1 in each row are interconnected to form a spin-orbit moment channel 80, the bias regions 20 of the magnetic memories M1 in each column are interconnected to form a bias channel 90, and a second isolation layer (not shown) is arranged between the spin-orbit moment layer and the bias region of each magnetic memory M1.

[0055] Continue to refer Figure 5 The array shown and Figure 1 In the bias region structure shown, in some possible implementations, the spin-orbit moment channel 80 is formed by connecting the spin-orbit moment layer 30 of each row of magnetic memory M1 through a conductive material, or it can be formed by connecting the spin-orbit moment layer 30 of each row of magnetic memory to each other; that is, the first connection region 100 can be a conductive material, or it can be a material constituting the spin-orbit moment layer 30, and its shape can be a bar, a diamond, a trapezoid, a triangle, etc. and their composite shapes.

[0056] In some possible implementations, the bias channel 90 is formed by connecting the bias areas 20 of each column of the magnetic memory M1 through a conductive material, or by connecting the bias areas 20 of each column of the magnetic memory M1 to each other; that is, the second connection area 100 can be a conductive material, or it can be a material that constitutes the bias area 20, and its shape can be a bar, a diamond, a trapezoid, a triangle, etc. and their composite shapes.

[0057] In some possible implementations, the spin-orbit moment channel 80 is not perpendicular to the bias channel 90, and the angle formed by the two is greater than 0 degrees and less than 180 degrees, such as Figure 6 shown.

[0058] In some possible implementations, the spin-track moment layer 30 and the bias region 20 of each magnetic memory M1 in the magnetic memory array have a second isolation layer, and the material of the second isolation layer is an insulating material such as oxide or nitride.

[0059] In some possible implementations, the upper surface of the bias region 20 is not higher than the upper surface of the spin-orbit moment layer 30 and the lower surface of the bias region 20 is not lower than the lower surface of the substrate 10. Preferably, the upper surface of the bias region 20 is flush with the upper surface of the substrate 10. The bias region 20 located in the substrate 10 can reduce electrical interference and magnetic interference to other units; in some other implementations, the upper surface of the bias region 20 is not higher than the upper surface of the spin-orbit moment layer 30 and the lower surface of the bias region 20 is not lower than the lower surface of the spin-orbit moment layer 30; in some other implementations, the upper surface of the bias region 20 is lower than the upper surface of the substrate 10 and the lower surface of the bias region 20 is not lower than the lower surface of the substrate 10.

[0060] In some possible implementations, the upper surface of the bias region 20 is higher than the upper surface of the substrate 10 and the lower surface of the bias region 20 is not lower than the lower surface of the substrate 10. The first isolation layer is provided on the periphery of the portion of the bias region 20 that is higher than the upper surface of the substrate 10. When forming a magnetic memory array, the magnetic memory M1 based on this structure does not need to form a second isolation layer again between the spin-orbit moment layer 30 and the bias region 20. The material of the first isolation layer is an insulating material such as oxide or nitride.

[0061] In some possible implementations, the magnetic memory array further includes: a plurality of write word lines WWL q (WriteWord Line, q=1,2,3,...,q+2), several control bit lines CBL n (Control Bite Line, n=1,2,3,……, ,n+2) and several read word lines (RWL n (Read Word Line, n=1,2,3,…, n+2, not shown in the figure), the write word line is set to allow the write current to flow in the spin-orbit torque channel 80, changing the resistance state of the magnetic memory; the control bit line is set to allow the bias current to flow in the bias channel 90, changing the polarity of the ferromagnetic layer 21 in the bias channel 90; the change of the resistance state of the magnetic memory M1 is achieved by controlling the polarity of the ferromagnetic layer 21 and the direction of the write current of the spin-orbit torque channel 80.

[0062] In some possible implementations, the change of the resistance state of the magnetic memory is achieved by controlling the polarity of the ferromagnetic layer 21 and the direction of the write current of the spin-orbit moment channel 80: setting the initial magnetization direction of the ferromagnetic layer 21 in the magnetic memory array to have a first polarity; controlling the write word line WWL q The direction of the write current applied to the spin-orbit torque channel 80 changes the resistance state of the magnetic memory; Specifically: Control the write word line WWL qWhen a write current is applied to the spin-orbit torque channel 80, the current flowing through the spin-orbit torque layer 30 of the magnetic memory will generate a spin current, and the stray field generated by the ferromagnetic layer 21 can assist the magnetic direction of the free layer 41 to flip, thereby achieving a field-free flip to change the resistance state of the target magnetic memory M1; and, the exchange bias between the ferromagnetic layer 21 and the antiferromagnetic layer 22 can pin (fix) the polarity of the ferromagnetic layer 21, so that the polarity of the ferromagnetic layer 21 in the magnetic memory remains stable, providing a stable stray field, and keeping the device stable.

[0063] by Figure 5 Take device A in the lower left corner of the magnetic memory as an example: Write process: By controlling the bit line CBL n Apply a bias current I to the bias channel of the column where device A is located. 偏置 , the current flows through the seed layer 23, the antiferromagnetic layer 22 and the ferromagnetic layer 21 of the magnetic memory, and the current flowing through the antiferromagnetic layer 22 can generate a spin current flipping exchange bias effect at the interface of the antiferromagnetic layer 22 / ferromagnetic layer 21, that is, the pinning direction is flipped, thereby flipping the magnetic moment direction of the ferromagnetic layer 21, so that the ferromagnetic layer 21 has the first polarity; by writing the word line WWL q Apply a write current I to the spin orbit torque channel 80 SOT , the resistance state of device A is the first resistance state. If a reverse write current I is applied SOT , the resistance state of device A changes from a first resistance state to a second resistance state opposite to the first resistance state; Read process: by controlling the read word line RWL n and write word line WWL q The conduction, or read word line RWL n and control bit line CBL n The conduction generates a read current to realize the reading of the resistance state of device A.

[0064] In some possible implementations, annealing, magnetic field induction, etc. may be used to make the ferromagnetic layer 21 have the first polarity.

[0065] In some possible implementations, the initial magnetization direction of the ferromagnetic layer 21 in the magnetic memory array is set to have a first polarity; by controlling the write word line WWL q The direction of the write current applied to the spin-orbit torque channel 80 can change the resistance state of any one or more rows of magnetic memory, thereby realizing the refresh function of the magnetic memory array.

[0066] Figure 6 The writing and reading methods of device A in the magnetic memory array shown are similar to those described above. Figure 5 The writing and reading methods of device A in the magnetic memory array shown are similar and will not be described in detail here.

[0067] In some possible implementations, the change of the resistance state of the magnetic memory M1 is achieved by controlling the polarity of the ferromagnetic layer 21 in the magnetic memory array and the direction of the write current of the spin-orbit torque channel 80, including: The ferromagnetic layer 21 in the magnetic memory M1 is set to the first polarity; by controlling the write word line WWL q The direction of the write current applied to the spin orbit torque channel 80 changes the resistance state of the magnetic memory M1; by controlling the bit line CBL n Apply a bias current I to the bias channel 90 偏置 , the current flows through the seed layer 23, the antiferromagnetic layer 22 and the ferromagnetic layer 21 of the magnetic memory, and the current flowing through the antiferromagnetic layer 22 will produce a spin current flipping exchange bias effect on the interface of the antiferromagnetic layer 22 / ferromagnetic layer 21, that is, the pinning direction is flipped, thereby flipping the magnetic moment direction of the ferromagnetic layer 21, so that the ferromagnetic layer 21 has a second polarity; by controlling the write word line WWL q A write current having the same direction as that in the first polarity state is applied to the spin-orbit torque channel 80, and the magnetic memory has a resistance state opposite to that in the first polarity state. No external magnetic field is required, thereby reducing the size of the device, which is beneficial to improving the arrangement density of the magnetic memory array and realizing the floating gate transistor array function.

[0068] Continue to refer Figure 5 The array shown and Figure 1 The bias region structure shown in Figure 5 Take device A in the lower left corner of the magnetic memory as an example: The process of device A realizing resistance state change is: S1: By controlling the bit line CBL n Apply a first direction (combined with Figure 5 , the first direction is I in the figure 偏置 The bias current I 偏置 , the current flows through the seed layer 23, the antiferromagnetic layer 22 and the ferromagnetic layer 21 of device A. The current flowing through the antiferromagnetic layer 22 can generate a spin current flipping exchange bias effect at the interface of the antiferromagnetic layer 22 / ferromagnetic layer 21, that is, the pinning direction is flipped, thereby flipping the magnetic moment direction of the ferromagnetic layer 21, so that the ferromagnetic layer 21 of device A has a first polarity.

[0069] S2: Control write word line WWL q Apply a second direction (combined with Figure 5 The second direction is I in the figure SOT The writing current I SOT , write current I SOTThe spin-orbit moment layer 30 in device A generates a spin current, and the stray field generated by the ferromagnetic layer 21 can assist the magnetic direction of the free layer to flip, and device A exhibits a first resistance state; If the control write word line WWL q A write current I in a fourth direction opposite to the second direction is applied to the spin orbit torque channel 80. SOT , device A exhibits a second resistance state opposite to the first resistance state.

[0070] S3: By controlling the bit line CBL n A bias current I in a third direction opposite to the first direction is applied to the bias channel 90. 偏置 , current flowing through the antiferromagnetic layer 22 can generate a spin current flip exchange bias effect at the interface of the antiferromagnetic layer 22 / ferromagnetic layer 21, so that the ferromagnetic layer 21 of device A has a second polarity, and the magnetization direction of the ferromagnetic layer is opposite to the magnetization direction of the ferromagnetic layer with the first magnetism.

[0071] S4: Control write word line WWL q A write current I in a second direction is applied to the spin orbit torque channel 80. SOT , write current I SOT The spin-orbit moment layer 30 in the device A generates a spin current, and the stray field generated by the ferromagnetic layer 21 with the second polarity assists the magnetic direction of the free layer to flip, and the device A exhibits a second resistance state; If the control write word line WWL q A write current I in a fourth direction is applied to the spin-orbit torque channel 80. SOT , device A exhibits a first resistance state.

[0072] Resistive read process: by controlling the read word line RWL n and write word line WWL q The conduction generates a read current to realize the reading of the resistance state of device A.

[0073] In some possible implementations, the read word line RWL may also be controlled n and control bit line CBL n The conduction generates a read current to realize the reading of the resistance state of device A.

[0074] Figure 6 The resistance state changing method and reading method of device A in the magnetic memory array shown are similar to those described above. Figure 5 The resistance state changing method and the reading method of the device A in the magnetic memory array shown are similar and will not be described in detail here.

[0075] In summary, the magnetic memory array provided by the embodiment of the present disclosure includes a plurality of magnetic memories M1 distributed in an array, wherein the spin-orbit moment layers 30 of each row of magnetic memories M1 are interconnected to form a spin-orbit moment channel 80, and the bias regions 20 of each column of magnetic memories M1 are interconnected to form a bias channel 90, and an isolation layer is arranged between the spin-orbit moment layer 30 and the bias region 20 of each magnetic memory M1, and the stray field generated by the ferromagnetic layer 21 inside the bias channel 90 can assist the magnetic direction of the free layer 41 to flip, without the need for an external magnetic field, thereby reducing the device volume, which is beneficial to improving the arrangement density of the magnetic memory array; and the exchange bias between the ferromagnetic layer 21 and the antiferromagnetic layer 22 can pin (fix) the polarity of the ferromagnetic layer 21, the magnetization direction is stable and not disturbed by the external magnetic field, the device stray field is stable, and miniaturization can be achieved to obtain a high-stability and high-density magnetic memory array. In addition, the magnetic memory array provided by the embodiment of the present disclosure realizes the change of the resistance state of the magnetic memory by controlling the polarity of the ferromagnetic layer and the writing current direction of the spin-orbit torque channel. It can not only refresh multiple magnetic memory storage states at the same time, but also realize the writing of a single magnetic memory, and can form a multifunctional gated write magnetic memory array.

[0076] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A magnetic memory, characterized in that: include: A substrate, a bias region, a spin-orbit moment layer, and a magnetic tunnel junction disposed above the spin-orbit moment layer; The substrate is located below the spin-orbit moment layer; The upper surface of the bias region is not higher than the upper surface of the spin-orbit moment layer and the lower surface of the bias region is not lower than the lower surface of the substrate. The bias region is filled with at least a ferromagnetic layer, an antiferromagnetic layer and a seed layer in a direction away from the magnetic tunnel junction.

2. The magnetic memory according to claim 1, characterized in that A first insertion spacer layer is arranged between the spin-orbit moment layer and the ferromagnetic layer, and / or a second insertion spacer layer is arranged between the ferromagnetic layer and the antiferromagnetic layer.

3. The magnetic memory according to claim 1, characterized in that: The initial magnetization direction of the ferromagnetic layer is set to have a first polarity, and the initial magnetization direction has a component in a direction parallel to a direction of a write current flowing into the spin-orbit moment layer.

4. The magnetic memory according to claim 1, characterized in that: The magnitude of the exchange bias field between the ferromagnetic layer and the antiferromagnetic layer is greater than the magnitude of the coercive field of the ferromagnetic layer.

5. The magnetic memory according to claim 1, characterized in that: An upper surface of the biasing region is flush with an upper surface of the substrate.

6. The magnetic memory according to claim 1, characterized in that: The upper surface of the bias region is higher than the upper surface of the substrate, and a first isolation layer is disposed at the periphery of a portion of the bias region that is higher than the upper surface of the substrate.

7. A magnetic memory array, characterized in that: The magnetic memory array comprises one or more magnetic memories according to any one of claims 1 to 6 distributed in an array, as well as a plurality of write word lines, a plurality of source lines and a plurality of read word lines; One end of the spin-orbit moment layer of each column of the magnetic memory is connected to one of the write word lines; The other end of the spin-orbit moment layer of each row of the magnetic memory is connected to one of the source lines; A top electrode is disposed on the top of the magnetic tunnel junction, and the top electrode of each row or column of the magnetic memory is connected to one of the read word lines.

8. The magnetic memory array according to claim 7, characterized in that: The initial magnetization direction of the ferromagnetic layer in the magnetic memory array is a first polarity; The direction of the write current flowing into the spin-track moment layer is controlled by the write word line and the source line to change the resistance state of the target magnetic memory.

9. A magnetic memory array, characterized in that: The magnetic memory array comprises a plurality of magnetic memories according to any one of claims 1 to 6 distributed in an array, wherein the spin-orbit moment layers of the magnetic memories in each row are interconnected to form a spin-orbit moment channel, the bias regions of the magnetic memories in each column are interconnected to form a bias channel, and a second isolation layer is arranged between the spin-orbit moment layer and the bias region of each magnetic memory.

10. The magnetic memory array according to claim 9, characterized in that: The spin-orbit moment channel is formed by connecting the spin-orbit moment layers of each row of the magnetic memory through a conductive material, and / or the bias channel is formed by connecting the bias regions of each column of the magnetic memory through a conductive material.

11. The magnetic memory array according to claim 9, characterized in that: The magnetic memory array further comprises: A plurality of write word lines are arranged to allow a write current to flow in the spin-orbit moment channel to change the resistance state of the magnetic memory; a plurality of control bit lines, configured to allow bias current to flow in the bias channel to change the polarity of the ferromagnetic layer in the bias channel; The change of the resistance state of the magnetic memory is achieved by controlling the polarity of the ferromagnetic layer and the direction of the write current of the spin-orbit torque channel.

12. The magnetic memory array according to claim 11, characterized in that: The change of the resistance state of the magnetic memory is achieved by controlling the polarity of the ferromagnetic layer and the direction of the write current of the spin-orbit moment channel, comprising: The ferromagnetic layer in the magnetic memory is of a first polarity; The resistance state of the magnetic memory is changed by controlling the direction of the write current applied by the write word line to the spin orbit torque channel.

13. The magnetic memory array according to claim 11, characterized in that: The change of the resistance state of the magnetic memory is achieved by controlling the polarity of the ferromagnetic layer and the direction of the write current of the spin-orbit moment channel, and further comprising: The ferromagnetic layer in the magnetic memory is of a first polarity; Applying the bias current to the bias channel through the control bit line so that the ferromagnetic layer has a second polarity; By controlling the write word line to apply a write current in the same direction as that in the first polarity state to the spin-orbit torque channel, the magnetic memory has a resistance state opposite to that in the first polarity state.

Images