Compact array of color adjustable pixels

Abstract

A monolithically integrated red-green-blue (RGB) light emitting diode (LED) array is provided that is fabricated with a reduced number of mesa etching steps and contact terminals. The LED array may have two or three p-n junctions grown sequentially on a wafer. Wherein one p-n junction has an opposite deposition order to the n layer and the p layer. A light emitting active region is embedded between the n layer and the p layer of each p-n junction. Each active region emits light of a different wavelength. The wafer is etched into a multi-stage mesa, creating two independent voltage terminals and one ground contact to control the bias between specific semiconductor layers. All p-n junctions share a common ground contact.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to arrays of light emitting diode (LED) devices and methods of manufacturing the same. More particularly, embodiments are directed to monolithically integrated red, green, blue (RGB) emitter arrays with a reduced number of mesa etching steps and contact terminals. Background Art

[0002] Visualization systems, such as virtual reality systems and augmented reality systems, are becoming increasingly common in fields such as entertainment, education, medicine, and business. There are ongoing efforts to improve visualization systems, such as virtual reality systems and augmented reality systems.

[0003] MicroLEDs (μLEDs) can be small-sized LEDs (typically ~50 μm in diameter or less) that can be used to produce very high-resolution color displays when μLEDs of red, green, and blue wavelengths can be closely spaced. The fabrication of μLED displays typically involves picking singulated μLEDs from separate blue, green, and red WL wafers and arranging them alternately and closely on the display.

[0004] There is interest in high-resolution color LED displays that require microscopic pixel pitches. When the size of the LEDs is in the range of tens of microns or less, it becomes difficult to assemble red, green, and blue LEDs grown on separate wafers. Monolithic RGB integration is an approach that avoids the problem of manipulating the microscopic LEDs into the correct position on the display, but also brings its own set of challenges. Current monolithic RGB arrays require at least three bias terminals plus a ground connection. In high-resolution displays, the space available to make all these mesa etchings and terminals is limited, making it difficult to actually implement the design.

[0005] Other approaches to monolithic RGB use one pn junction containing quantum wells for the three colors. Depending on the bias applied, relatively more or less light is produced in a particular well, allowing some control over the color point. This approach is attractive insofar as they operate using only two terminals per pixel, but excess voltage across the active region is unavoidable and filters are required to obtain acceptable color characteristics for the display. This approach therefore simplifies chip fabrication but is less suitable for making efficient displays with low power consumption.

[0006] Therefore, there is a need for improved μLED devices and improved manufacturing methods. Summary of the invention

[0007] Embodiments of the present disclosure are directed to light emitting diode (LED) arrays and methods for manufacturing LED arrays. In one or more embodiments, the light emitting diode (LED) array includes: a first light emitting stack on a second light emitting stack, a second light emitting stack on a third light emitting stack, and a third light emitting stack on a reflective p-contact electrode bonded to a backplane, wherein the first light emitting stack includes a first electrical contact on a first n-type layer on a first color active region, a first color active region on a first p-type layer, and a first p-type layer on a first tunnel junction, the second light emitting stack includes a second electrical contact on a second n-type layer in contact with the first tunnel junction and on a second tunnel junction, a second tunnel junction on the second p-type layer, and a second p-type layer on the second color active region, and the third light emitting stack includes a third electrical contact on a third n-type layer in contact with the second color active region and on a third p-type layer.

[0008] Another embodiment of the present disclosure is directed to a method for manufacturing an LED array. In one or more embodiments, the method includes: sequentially forming at least three pn junctions on an epitaxial wafer to form an epitaxial stack, the epitaxial stack including at least one n-type layer and at least one p-type layer, and having a color active region embedded between at least one n-type layer and at least one p-type layer; depositing a reflective p-contact electrode on the epitaxial stack; bonding the reflective p-contact electrode to a backplane wafer; dry etching the epitaxial stack to approach at least one n-type layer to form an electrical contact and a mesa; conformally depositing a dielectric layer over the mesa; removing a portion of the dielectric layer to form a dielectric opening on the top surface of the mesa, the dielectric opening exposing at least one n-type layer; depositing an ohmic contact in the dielectric opening to form an electrical contact; depositing a conformal metal layer over a portion of the mesa and forming a gap across the center of the mesa to allow light to exit; and depositing an electrode grid over the top of the LED array.

[0009] Additional embodiments of the present disclosure are directed to visualization or display systems. In one or more embodiments, the visualization system includes: a battery; a radio; a sensor; a video generation processor; a light source including an LED array of one or more embodiments described herein; a modulator; a modulation processor; a beam combiner; a projection optical device; a screen; and a lens. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To facilitate a detailed understanding of the above-listed features of the present disclosure, the present disclosure briefly summarized above may be described in more detail with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the present disclosure and therefore should not be considered to limit its scope, as the present disclosure may allow for other equivalent embodiments. The embodiments as described herein are illustrated in the figures of the accompanying drawings by way of example and not limitation, in which similar reference numerals indicate similar elements.

[0011] Figure 1 A process flow chart showing a method for manufacturing an LED array according to one or more embodiments;

[0012] Figure 2A and Figure 2B is a schematic diagram illustrating how the reverse order of p-layers and n-layers helps control the emission wavelength using an applied voltage;

[0013] Figure 3 is a graph illustrating measured data for LEDs of opposite polarization and same quantum well design according to one or more embodiments;

[0014] Figure 4 is a graph illustrating a measured spectrum of a red-green switchable color LED with p-GaN grown before the quantum wells according to one or more embodiments;

[0015] Figure 5 is a cross-sectional view of an epitaxial structure used in an LED variant before processing according to one or more embodiments;

[0016] Figure 6 According to one or more embodiments, Figure 5 A cross-sectional view of the μLED array after the LED modification shown in FIG.

[0017] Figure 7 yes Figure 6 Schematic top view of the μLED array shown in ;

[0018] Figure 8 is a top view arrangement of a conformal dielectric layer, the conformal dielectric layer being Figure 7 Below the metal lines shown in the μLED array shown in ;

[0019] Fig. 9 is a cross-sectional view of an epitaxial structure used in an alternative LED variation before processing according to one or more embodiments;

[0020] Fig.10 According to one or more embodiments, Fig. 9 A cross-sectional view of a μLED array modified with an alternative LED as shown in ; and

[0021] Fig.11 A block diagram showing an example of a visualization system using a μLED array of one or more embodiments is shown.

[0022] To facilitate understanding, where possible, the same reference numerals have been used to denote common elements in the drawings. The drawings are not drawn to scale. For example, the height and width of the countertops are not drawn to scale. DETAILED DESCRIPTION

[0023] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0024] According to one or more embodiments, the term "substrate" as used herein refers to an intermediate or final structure having a surface or a portion of a surface on which a process is performed. Additionally, in some embodiments, reference to a substrate also refers to only a portion of a substrate, unless the context clearly indicates otherwise. Furthermore, according to some embodiments, reference to depositing on a substrate includes depositing on a bare substrate, or depositing on a substrate having one or more layers, films, features, or materials deposited or formed thereon.

[0025] In one or more embodiments, "substrate" means any substrate or material surface formed on a substrate on which film processing is performed during a fabrication process. In exemplary embodiments, depending on the application, the substrate surface on which processing is performed includes materials such as silicon, silicon oxide, silicon on insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable material (such as metals, metal nitrides, Group III nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials). Substrates include, but are not limited to, light emitting diode (LED) devices. In some embodiments, the substrate is exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps is also performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such an underlying layer as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0026] In this disclosure, the terms "wafer" and "substrate" will be used interchangeably. Thus, as used herein, a wafer is used as a substrate to form the LED devices described herein.

[0027] Examples of different light illumination systems and / or light emitting diode (LED) embodiments will be described more fully below with reference to the accompanying drawings. These examples are not mutually exclusive, and features found in one example can be combined with features found in one or more other examples to achieve additional embodiments. Therefore, it will be understood that the examples shown in the accompanying drawings are provided for illustrative purposes only, and they are not intended to limit the present disclosure in any way. Like numbers always refer to like elements.

[0028] Semiconductor light emitting devices or optical power emitting devices (such as devices that emit ultraviolet (UV) or infrared (IR) optical power) are one of the most efficient light sources currently available. These devices may include light emitting diodes, resonant cavity light emitting diodes, vertical cavity laser diodes, edge emitting lasers, etc. (hereinafter referred to as "LEDs"). For example, due to their compact size and low power requirements, LEDs may be attractive candidates for many different applications. For example, they can be used as light sources (e.g., flashlights and camera flashes) for handheld battery-powered devices (such as cameras and mobile phones). They can also be used for, for example, automotive lighting, head-up display (HUD) lighting, horticultural lighting, street lighting, video flashlights (torch for video), general lighting (e.g., home, store, office and studio lighting, theater / stage lighting, and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, as backlights for displays, and IR spectroscopy. A single LED can provide less bright light than an incandescent light source, and therefore, multi-junction devices or LED arrays (such as monolithic LED arrays, micro-LED arrays, etc.) can be used for applications where higher brightness is desired or required.

[0029] The present disclosure generally relates to the fabrication of micro light emitting diode (μLED) displays and large bandwidth multi-wavelength light emitters for free space visible light communications. Epitaxial tunnel junctions can be used to combine multiple emission wavelengths within a single LED device.

[0030] The fabrication of μLEDs can be simplified if two or more active regions emitting at different wavelengths can be integrated within a single wafer. This approach may be possible within the AlInGaN material system, as it has been demonstrated that blue, green, and red LEDs can all be fabricated in this system. However, the use of multicolor chips in μLED displays requires not only the stacking of multiple layers capable of emitting at different wavelengths within a single epitaxial growth process, but also the ability to vary the respective emission intensity ratios between emitters of different wavelengths.

[0031] In one or more embodiments, bias-based LED color control is used to reduce the number of terminals to a more manageable number than the prior art. However, some independent control of separate junctions is used to avoid the problems of poor color purity and high voltage inherent in other approaches. Additionally, one or more embodiments provide an improved way to control LED wavelength by voltage.

[0032] In one or more embodiments, "reverse polarity" LEDs are advantageously used for display applications. As used herein, the term "reverse polarity" refers to growing the p-GaN layers of the LED before the quantum wells, rather than growing the p-GaN layers of the LED after the quantum wells. It has been generally accepted that high-efficiency p-side down LEDs are not feasible due to unintentional incorporation of acceptor dopants into the quantum wells. However, in one or more embodiments, it has been advantageously discovered that the use of special growth conditions can mitigate the above-mentioned problems. Reverse polarity LEDs are so named because the direction of the pn junction and the InGaN polarization field is opposite to the traditional way.

[0033] As used herein, the term "pn junction" refers to the boundary between two semiconductor layers of opposite conductivity types (p-type and n-type). The "p" side contains an excess of holes, while the "n" side contains an excess of electrons. Excess holes and electrons can be obtained by intentionally doping with acceptor or donor impurities, respectively, and / or can be generated by the presence of natural crystal defects. The boundary is not necessarily steep, planar or smooth. The boundary may include an impurity concentration gradient and / or an intrinsic (neutral) conductivity type layer between the p-type layer and the n-type layer. The boundary may be characterized by a p-type semiconductor protruding into an n-type semiconductor, or vice versa.

[0034] Embodiments of the present disclosure are described by the accompanying drawings, which illustrate devices and processes for forming devices according to one or more embodiments of the present disclosure. The processes shown are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0035] In one or more embodiments, the reverse orientation of polarity helps control the net electric field across the quantum well(s) in a manner that is beneficial for controlling the wavelength. The advantages of this concept are Figure 2A , Figure 2B , Figure 3 The color shift of the LED spectrum is conceptually shown in Figure 4 Shown in.

[0036] Figure 2A and Figure 2B Schematic showing how the reverse order of the p- and n-layers helps control the emission wavelength with an applied voltage. The larger amplitude of the electric field across the indium gallium nitride (InGaN) quantum well increases the wavelength due to the quantum confined Stark effect. Figure 3 The graphs shown in show measured data for LEDs of opposite polarization and identical quantum well design.

[0037] Figure 4is a graph illustrating the measured spectrum of a red-green switchable color LED with p-GaN grown before the quantum wells. The spectrum is characterized by a distinct peak that varies with voltage, rather than having multiple peaks of varying height depending on voltage as in prior art LEDs that use multiple quantum wells of different colors in the same active region. Figure 4 The quantum well ratio Figure 2A and Figure 2B The quantum well shown is wider, allowing for a larger wavelength shift with voltage.

[0038] The μLED array of one or more embodiments advantageously requires fewer contact terminals and mesa etching when compared to known μLED arrays. The μLED array of one or more embodiments requires only two independently biased terminals and a common ground electrode. Additionally, the μLED array of one or more embodiments allows for better control of emission color than known single junction RGB technology. Without intending to be bound by theory, it is believed that the μLED array of one or more embodiments can have lower display power consumption than the disclosed single junction RGB technology.

[0039] In one or more embodiments, two or three light-emitting stacks are sequentially grown on the same epitaxial wafer. One of these junctions has an opposite deposition order of n-layers and p-layers compared to (one or more) other junctions. In one or more embodiments, a light-emitting active region is embedded between the n-layer and p-layer of each junction. Each active region emits light of different wavelengths from (one or more) other active regions. At least one junction has the following properties: when the bias across the junction increases, its emission changes from one of the primary colors to a different (shorter) primary color. For example, the emission can change from red to green, or from green to blue.

[0040] In one or more embodiments, the epitaxy includes at least one tunnel junction to avoid the need for contact etched p-GaN layers. The wafer is etched into multiple layers of mesas, resulting in two separate voltage terminals and a ground contact to control bias between specific semiconductor layers. All junctions share a common ground contact.

[0041] One or more alternative embodiments provide a dual junction device that controls the color emitted by one of the junctions by changing the voltage on one terminal. For example, the color can be changed from red to green by increasing the voltage. The radiance of red and green can be matched by reducing the pulse width modulation period as the bias voltage is increased. Blue emission is controlled by a separate contact terminal to the third (blue) active region. The opposite orientation of the pn junction field relative to the InGaN quantum well polarization field facilitates the color change function with voltage.

[0042] In the detailed example shown in the figures and described below, blue light is generated by a separate drive voltage (applied to Figure 6 and Fig.10 However, alternative embodiments in which the red active region is interchanged with the blue active region are also possible. In these embodiments, red light is emitted using the bias to terminal A, and the magnitude of the bias to terminal B can be used to adjust the emission of another color from green to blue.

[0043] Figure 1 FIG. 5 is a process flow diagram of a method 50 for manufacturing a micro light emitting diode (μLED) array according to one or more embodiments of the present disclosure. Figure 1 In one or more embodiments, the method begins at operation 52: sequentially forming two or three pn junctions on the same epitaxial wafer to form an epitaxial stack, the epitaxial stack including at least one n-type layer and at least one p-type layer, and having a color active region embedded between at least one n-type layer and at least one p-type layer. At operation 54, a reflective p-contact electrode is deposited on the epitaxial stack. At operation 56, the epitaxial stack with the reflective p-contact is bonded to a backplane wafer. At operation 58, the epitaxial stack is dry-etched to access the n-type layer for forming electrical contacts and mesas. At operation 60, a dielectric layer is conformally deposited across the epitaxial wafer above the mesas. At operation 62, a portion of the dielectric layer is removed to form a dielectric opening on the top surface of the mesas, the dielectric opening exposing at least one n-type layer. At operation 64, an ohmic contact is deposited in the dielectric opening to form an electrical contact. At operation 66, a conformal reflective metal layer is deposited over a portion of the mesas, and a gap is formed across the center of the mesas to allow light to exit. At operation 68, an electrode grid is deposited over the top of the LED array.

[0044] refer to Figure 5 , describing the epitaxial growth step of a first variant 100 (Variant A). Figure 5 FIG. 1 is a cross-sectional view of a μLED array 100 according to one or more embodiments. One aspect of the present disclosure relates to a method for manufacturing a μLED array. Figure 5 , the first variation 100 (variation "A") is a triple junction device in which the first and second pn junctions (of opposite pn deposition order) share a common n-type layer connected to one of the electrical terminals. Although the two junctions are driven in parallel (not independently), the aggregate color they emit can be controlled by voltage. For example, when the red and green active regions are connected in parallel, current flows through the red region only at low voltages. The red active region can be designed so that its emission transitions to green at high voltages and is added to the light emitted by the green active region. The blue emission is controlled by a separate contact terminal to the third (blue) active region.

[0045] refer to Figure 5, the μLED array 100 is manufactured by forming a plurality of III-nitride layers on a substrate 102 to form a triple-junction LED (including color active regions) on the substrate. The color active regions include a first color active region 106a, a second color active region 106b, and a third color active region 106c. Any order of stacking different color active regions is within the scope of the present disclosure.

[0046] According to some specific embodiments, the LED array 100 includes three or more pn junctions. In one or more embodiments, the first light emitting stack 105a has a first n-type layer 104a formed on the substrate 102, a first color active region 106a formed on the first n-type layer 104a, a first p-type layer 108a formed on the first color active region 106a, and a first tunnel junction 110a formed on the first p-type layer 108a. The first pn junction includes the first n-type layer 104a and the first p-type layer 108a separated by the first color active region 106a.

[0047] In one or more embodiments, the first color active region 106a is a blue active region. In the illustrated embodiment, there is a first tunnel junction 110a on the first light emitting stack, particularly on the first p-type layer 108a. The tunnel junction is a structure that allows electrons to tunnel from the valence band of the p-type layer to the conduction band of the n-type layer under reverse bias. When electrons tunnel, holes are left in the p-type layer, so that carriers are generated in both regions. Therefore, in a diode-like electronic device, in which only a small leakage current flows in reverse bias, a large current can be transmitted across the tunnel junction in reverse bias. The tunnel junction includes a specific arrangement of the conduction band and the valence band at the pn junction. This can be achieved by using very high doping (for example, in a p++ / n++ junction). In addition, group III nitride materials have inherent polarization, which generates an electric field at the heterogeneous interface between different alloy components. In some cases, this polarization field can also be used to achieve an energy band arrangement for tunneling.

[0048] Still refer to Figure 5, the μLED array 100 further includes a second light-emitting stack 105b on the first light-emitting stack 105a. As recognized by those skilled in the art, the second light-emitting stack 105b may not be an independent light-emitting stack. In one or more embodiments, electrons need to be injected from layer 104c (which is part of the third group 105c) to emit light from the second active area 106b. The second light-emitting stack 105b includes a second n-type layer 104b on the first tunnel junction 110a, a second tunnel junction 110b on the second n-type layer 104b, a second p-type layer 108b on the second tunnel junction 110b, and a second color active area 106b on the second p-type layer 108b. In one or more embodiments, the second color active area 106b is a red active area. In the embodiment shown, there is a second tunnel junction 110b on the second junction 105a, particularly on the second n-type layer 104b. When the second n-type layer 104b is positively biased relative to the second p-type layer 108b, a hole current flows in the second p-type layer 108b through the second tunnel junction 110b. The second tunnel junction 110b itself is a (second) pn junction, which is composed of an n-type layer and a p-type layer not shown separately in the figure. The second p-type layer 108b is used to inject holes required to excite the light emission from the second color active area 106b.

[0049] The third light emitting stack 105c is formed on the second light emitting stack 105b and has a third n-type layer 104c on the second color active region 106b, a third color active region 106c on the third n-type layer 104c, and a third p-type layer 108c on the third color active region 106c. The third n-type layer 104c is used to inject electrons into both the second color active region 106b of the second light emitting stack and the third color active region 106c of the third light emitting stack. The third pn junction includes the third n-type layer 104c and the third p-type layer 108c separated by the third color active region 106c.

[0050] In one or more embodiments, the first n-type layer 104a is formed on a substrate 102. The substrate 102 can be any substrate known to those skilled in the art, which is configured to be used in the formation of an LED device. In one or more embodiments, the substrate 102 includes one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In one or more embodiments, the substrate 102 is a transparent substrate. In a specific embodiment, the substrate 102 includes sapphire. In one or more embodiments, the substrate 102 is not patterned before forming the LED. Therefore, in some embodiments, the substrate 102 is not patterned and can be considered to be flat or substantially flat. In other embodiments, the substrate 102 is a patterned substrate.

[0051] In one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c may include any III-V semiconductor, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also known as III-nitride materials. Therefore, in some embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. In a specific embodiment, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c include gallium nitride (GaN). In one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c are independently doped with n-type dopants, such as silicon (Si) or germanium (Ge). In one or more embodiments, the dopant concentration is from 1e17 to 2e19 cm 3 within the range.

[0052] In one or more embodiments, the group III nitride material layer may be deposited by one or more of sputtering deposition, atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0053] As used herein, "sputter deposition" refers to a physical vapor deposition (PVD) method of thin film deposition by sputtering. In sputter deposition, a material, such as a Group III nitride, is ejected from a target as a source onto a substrate. The technique is based on ion bombardment of the source material (target). The ion bombardment generates vapor due to a purely physical process, i.e., sputtering of the target material.

[0054] As used in accordance with some embodiments herein, "atomic layer deposition" (ALD) or "cyclic deposition" refers to a vapor phase technique for depositing a thin film on a substrate surface. The ALD process involves exposing a substrate surface or a portion of a substrate to alternating precursors, i.e., two or more reactive compounds, to deposit a layer of material on the substrate surface. When the substrate is exposed to alternating precursors, the precursors are introduced sequentially or simultaneously. The precursors are introduced into a reaction zone of a processing chamber, and the substrate or a portion of the substrate is exposed to the precursors separately.

[0055] As used herein in accordance with some embodiments, "chemical vapor deposition" refers to the process of depositing a film of material from a vapor phase by decomposition of a chemical on a substrate surface. In CVD, the substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. A specific subset of CVD processes commonly used in LED manufacturing uses metal organic precursor chemicals and is referred to as MOCVD or metal organic vapor phase epitaxy (MOVPE). As used herein, "substantially simultaneously" means that the majority of the exposures of the precursors co-flow or there is overlap.

[0056] As used herein according to some embodiments, "plasma enhanced atomic layer deposition (PEALD)" refers to a technique for depositing a thin film on a substrate. In some examples of the PEALD process relative to the thermal ALD process, the material can be formed from the same chemical precursors, but at a higher deposition rate and a lower temperature. In the PEALD process, in general, reactant gases and reactant plasmas are sequentially introduced into a processing chamber with a substrate in the chamber. The first reactant gas is pulsed in the processing chamber and adsorbed onto the surface of the substrate. Thereafter, the reactant plasma is pulsed into the processing chamber and reacts with the first reactant gas to form a deposited material, such as a thin film on a substrate. Similar to the thermal ALD process, a purge step can be performed between the delivery of each reactant.

[0057] As used herein in accordance with one or more embodiments, "plasma enhanced chemical vapor deposition (PECVD)" refers to a technique for depositing thin films on substrates. In a PECVD process, a source material in a gas phase or liquid phase, such as a vapor of a gas phase III-nitride material or a liquid phase III-nitride material, is introduced into a PECVD chamber, where the gas phase or liquid phase III-nitride material has been entrained in a carrier gas. A plasma-induced gas is also introduced into the chamber. The generation of a plasma in the chamber generates excited free radicals. The excited free radicals chemically bond to the surface of a substrate located within the chamber, forming a desired film thereon.

[0058] In one or more embodiments, the μLED array 100 is fabricated by placing the substrate 102 in a metal organic vapor phase epitaxy (MOVPE) reactor such that the μLED array layers are epitaxially grown.

[0059] In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c may independently include any III-V semiconductor, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also known as III-nitride materials. Therefore, in some embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc.

[0060] In some embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c independently include a series of doped p-type layers. In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c independently include gallium nitride (GaN) layers. The first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c can be independently doped with any suitable p-type dopant known to those skilled in the art. In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c can be independently doped with magnesium (Mg). In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c independently include a first magnesium-doped p-type aluminum gallium nitride layer, a magnesium-doped p-type gallium nitride layer, and a second magnesium-doped p-type aluminum gallium nitride layer.

[0061] In one or more embodiments, the key difference between the epitaxy used in the μLED array and known μLED arrays is the above-mentioned reverse polarization orientation, and the use of wider than typical quantum wells in applications where large color shifts are intentionally desired. For example, the well width that optimizes internal quantum efficiency (IQE) may be 3nm, while in one or more embodiments it may be preferred to increase the width to 5nm. In one or more embodiments, the well width may range from 2nm to 8nm.

[0062] Figure 6A cross-sectional schematic diagram of the first variant 100 after being processed into a micro LED array is shown. Arrows 126, 128, 130 with different dashed line patterns indicate composite paths that lead to red, green, and blue emissions. In one or more embodiments, when terminal A 122 has a voltage of approximately 3 volts and terminal B 124 has a voltage of approximately 0 volts, blue light 130 is generated. In one or more embodiments, when terminal A 122 has a voltage of approximately 0 volts and terminal B 124 has a voltage greater than 3 volts or higher, red light 128 is generated. In one or more embodiments, when terminal A 122 has a voltage of approximately 0 volts and terminal B has a voltage of approximately 5 volts or higher, green light 126 (or reddish green light) is generated. A method similar to the present invention can be used. Figure 4 The color-shifted red active region shown in FIG. produces red emission with a small bias on terminal B 124 and produces additional green emission with a large bias on terminal B 124. As will be appreciated by those skilled in the art, Figure 6 The first variant 100 presented in FIG. 1 has been modified with respect to its Figure 5 The depiction in is rotated 180 degrees.

[0063] refer to Figure 6 , the first step in making the micro LED wafer 150 is the acceptor activation annealing. Deposit the reflective p contact electrode (p mirror) 118. The reflective p contact electrode (p mirror) 118 may include any suitable material known to those skilled in the art. In one or more embodiments, the reflective p contact electrode (p mirror) 118 includes one or more of aluminum (Al), platinum (Pt), silver (Ag), etc. In other embodiments, the reflective p contact electrode (p mirror) 118 may include a double layer of reflective material (i.e., one or more of aluminum (Al), platinum (Pt), silver (Ag), etc.) and indium tin oxide (ITO), wherein the ITO is a portion of the double layer that is in direct contact with the third p-type layer 108c.

[0064] In one or more embodiments, the reflective p-contact electrode (p-mirror) 118 is then bonded to a backplane wafer 120, which may be pre-coated with a similar metal to facilitate wafer bonding. In one or more embodiments, the backplane wafer 120 includes vias 122 and 124 between the bonding surface and the circuitry in or on opposite sides of the backplane wafer 120.

[0065] Still refer to Figure 6In one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c are etched, for example by dry etching, to form openings for electrical contacts 114, isolation pixels, and vias 124 close to backplane terminals B. In one or more embodiments, there are three etch levels 152, 154, and 156, which is a more manageable number than known μLED arrays.

[0066] In one or more embodiments, the dielectric layer 112 is conformally deposited over the entire wafer 150. As used herein, the term "dielectric" refers to an electrical insulator material that can be polarized by an applied electric field. In one or more embodiments, the dielectric layer includes, but is not limited to: oxides, such as silicon oxide (SiO2), aluminum oxide (Al2O3); nitrides, such as silicon nitride (Si3N4). In one or more embodiments, the dielectric layer includes a multilayer of silicon nitride (Si3N4), silicon oxide (SiO2), or silicon dioxide (SiO2) and silicon nitride (Si3N4). In some embodiments, the dielectric layer composition is non-stoichiometric relative to an ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), carbon oxides (e.g., silicon oxycarbide (SiOC)), and carbon nitride oxides (e.g., silicon oxycarbonitride (SiNCO)).

[0067] In one or more embodiments, the dielectric layer 112 is removed from the electrical contact points using dry etching. An ohmic contact metal layer 114 is deposited and formed in the dielectric opening. Each ohmic contact metal layer 114 reaches the n-type layers 104a, 104b, and 104c and can be the same metal. The ohmic contact metal layer 114 can include any suitable metal known to those skilled in the art. In one or more embodiments, the ohmic contact metal layer 114 includes aluminum (Al).

[0068] Still refer to Figure 6 , a thick partially conformal metal layer 116 is deposited over most of the mesa area. Figure 6 and Figure 7As shown in , a gap 132 is left in the center of the cross-table to allow light to exit and to electrically isolate terminal B from the ground 124. The partially conformal metal layer 116 may include any suitable material known to those skilled in the art. In one or more embodiments, the partially conformal metal layer 116 has high reflectivity and stability. In one or more embodiments, the partially conformal metal layer 116 includes aluminum (Al) or platinum (Pt). Layer 116 can be composed of a stack of multiple different metal films, such as a first metal with high reflectivity properties (such as Al or silver (Ag)) and a second metal with better chemical stability (such as titanium (Ti), chromium (Cr), tungsten (W), gold (Au) or Pt). The partially conformal metal layer 116 uses a through hole 124 to connect the second n-type layer 104b to the backplane terminal B.

[0069] Figure 7 Shows Figure 6 Schematic top view of array 150 shown in cross section in FIG. Figure 7 The portion shown in corresponds to the northwest corner of the much larger display. In one or more embodiments, an electrode grid 172 of ground wires is deposited over the reflective portion of the conformal metal layer 116 on one side of each pixel, such as Figure 7 . The electrode grid 172 is connected to the ground line at the periphery of the display 150. In one or more embodiments, the electrode grid 172 connects the ground terminal ( Figure 6 left side ) is connected to the ground electrode at the periphery of the display.

[0070] refer to Figure 6 and Figure 7 In one or more embodiments, when terminal A 174 is biased above ground potential (i.e., +3V) and terminal B 176 is grounded (i.e., 0V), blue light 130 is emitted. In one or more embodiments, when terminal A 174 is grounded (i.e., 0V), red light 128 or green light 126 can be generated using the bias to terminal B 176, depending on the magnitude of the bias. For example, if the bias to terminal B is in the range from about 3V to less than 5V, red light 128 can be generated, and if the bias to terminal B 176 is greater than 5V, green light 126 can be generated. Although the first color active area 106a and the second color active area 106b are connected in parallel, they can be designed so that for a small bias, current only flows through the second color (red) active area 106b. Therefore, only red light 128 is generated. For a larger bias on terminal B 176, current flows through both the red and green active regions, however, due to the higher IQE of the green active region relative to the red, and the natural tendency of the red emission to shift to shorter wavelengths at higher current densities, the resulting color may be predominantly green. Figure 4Green purity can be further improved by using a "red" active region in the MOSFET, which itself emits green (not red) light at high current density. For the green mode of operation, the pulse width modulation duty cycle can be reduced to make the radiance similar to the red mode with a higher duty cycle.

[0071] Figure 8 184, 186 is shown as a top view arrangement of conformal dielectric layers 182, 184, 186 deposited over the entire surface after the final mesa etch step. In one or more embodiments, conformal dielectric layers 182, 184, 186 are deposited over the entire surface after the final mesa etch step. Figure 7 172 is shown below the electrode grid 172. Figures 6 to 8 , regions 188, 194 indicate where dielectric layers 182, 184, 186 are removed by subsequent etching to access the ohmic contact metal layer 114 on the pixel. Conformal dielectric layers 182, 184, 186 also serve to access vias 192 connected to terminal B in the backplane, and vias 190 connected to terminal A.

[0072] refer to Fig. 9 , describing the epitaxial growth step of a second variant 200 (Variant B). Fig. 9 FIG. 2 shows a cross-sectional view of a μLED array 200 according to one or more embodiments. One aspect of the present disclosure relates to a method for manufacturing a μLED array. Fig. 9 , the second variant 200 (Variant "B") is a dual junction device in which the first and second junctions (of opposite pn deposition order) share a common n-type layer connected to one of the electrical terminals. In one or more embodiments, Variant B 200 has a simpler epitaxial structure and simpler mesa surface morphology than Variant A 100. In Variant B 200, micro-LED fabrication is achieved with one less mesa etch level. In Variant B 200, according to Figure 4 According to the mechanism shown in , the first active region itself provides both red and green light depending on the bias to terminal B.

[0073] refer to Fig. 9 , the μLED array 200 is manufactured by forming a plurality of III-nitride layers on a substrate 202 to form a double-junction LED on a substrate including color active regions. The color active regions include a first color active region 206a and a second color active region 206b. Any order of stacking different color active regions is within the scope of the present disclosure.

[0074] According to some specific embodiments, the LED array 200 includes a first light emitting stack 205a, the first light emitting stack 205a having a first n-type layer 204a formed on a substrate 202, a first tunnel junction 210a formed on the first n-type layer 204a, a first p-type layer 208a formed on the first tunnel junction 210a, a first color active region 206a formed on the first p-type layer 208a, and a second n-type layer 204b formed on the first color active region 206a.

[0075] In one or more embodiments, the first color active region 206a is a red / green active region. In the embodiment shown, there is a tunnel junction 210a between the first n-type layer 204a and the first p-type layer 208a. This arrangement makes it possible to inject holes into the first color active region 206a without requiring the surface of the p-type layer 208a to be in direct contact with the metal. Electrons are injected into the first color active region 206a from the second n-type layer 204b.

[0076] Still refer to Fig. 9 , the μLED array 200 further includes a second light-emitting stack 205b on the first light-emitting stack 205a. The second light-emitting stack 205b includes a second n-type layer 204b, a second color active area 206b on the second n-type layer 204b, and a second p-type layer 208b on the second color active area 206b. It should be noted that the second n-type layer 204b is "shared" between the first and second light-emitting stacks 205a and 205b. In other words, the second n-type layer 204b can be used to inject electrons into both the first active area 206a and the second active area 206b. The second n-type layer 204b can be composed of multiple layers with different n-type doping concentrations. In one or more embodiments, the second color active area 206b is a blue active area. Optionally, a second tunnel junction 210b and a third n-type layer 204c can be formed on the second p-type layer 208b. These optional layers may allow the wafer to be subjected to high temperature processing (eg, high temperature annealing to activate the buried p-type layer) without damaging the p-type layer 208b.

[0077] In one or more embodiments, the first n-type layer 204a is formed on a substrate 202. The substrate 202 can be any substrate known to those skilled in the art, which is configured to be used in the formation of an LED device. In one or more embodiments, the substrate 202 includes one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In one or more embodiments, the substrate 202 is a transparent substrate. In a specific embodiment, the substrate 202 includes sapphire. In one or more embodiments, the substrate 202 is not patterned before forming the LED. Therefore, in some embodiments, the substrate 202 is not patterned and can be considered to be flat or substantially flat. In other embodiments, the substrate 202 is a patterned substrate.

[0078] In one or more embodiments, the first n-type layer 204a, the second n-type layer 204b, and the optional third n-type layer 204c may include any III-V semiconductor, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also known as III-nitride materials. Therefore, in some embodiments, the first n-type layer 204a, the second n-type layer 204b, and the third n-type layer 204c independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. In a specific embodiment, the first n-type layer 204a, the second n-type layer 204b, and the third n-type layer 204c include gallium nitride (GaN). In one or more embodiments, the first n-type layer 204 a , the second n-type layer 204 b , and the third n-type layer 204 c are independently doped with n-type dopants, such as silicon (Si) or germanium (Ge).

[0079] In one or more embodiments, the group III nitride material layer may be deposited by one or more of sputtering deposition, atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD), as described above.

[0080] In one or more embodiments, the μLED array 200 is manufactured by placing the substrate 202 in a metal organic vapor phase epitaxy (MOVPE) reactor so that the μLED array layers are epitaxially grown.

[0081] In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b may independently include any III-V semiconductor, including binary, ternary and quaternary alloys of gallium (Ga), aluminum (Al), indium (In) and nitrogen (N), also known as III-nitride materials. Therefore, in some embodiments, the first p-type layer 208a and the second p-type layer 208b independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc.

[0082] In some embodiments, the first p-type layer 208a and the second p-type layer 208b independently include a series of doped p-type layers. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b independently include gallium nitride (GaN) layers. The first p-type layer 208a and the second p-type layer 208b can be independently doped with any suitable p-type dopant known to those skilled in the art. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b can be independently doped with magnesium (Mg). In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b independently include a first magnesium-doped p-type aluminum gallium nitride layer, a magnesium-doped p-type gallium nitride layer, and a second magnesium-doped p-type aluminum gallium nitride layer.

[0083] In one or more embodiments, the key difference between the epitaxy used in the μLED array 200 and known μLED arrays is the above-mentioned reverse polarization orientation, and the use of wider than typical quantum wells in applications where large color shifts are intentionally desired. For example, the well width that optimizes internal quantum efficiency (IQE) at high current density may be 3nm, while in one or more embodiments it may be preferred to increase the width to 5nm. In one or more embodiments, the well width may range from 2nm to 8nm.

[0084] Fig.10 A schematic cross-sectional view of the second variant 200 after processing into a micro-LED array 250 is shown. Arrows 226, 228 with different dashed line patterns indicate the composite paths that lead to red, green, and blue emission. Figure 4 The color-shifted red active region shown in FIG. produces red emission with a small bias on terminal B and produces green emission with a large bias on terminal B. As will be appreciated by those skilled in the art, Fig. 9 The second variation 200 has been rotated 180 degrees to form a micro LED array 250 .

[0085] refer to Fig.10 , a micro LED wafer 250 is made by first performing an acceptor activation anneal. A reflective p-contact electrode (p-mirror) 218 ​​is deposited. The reflective p-contact electrode (p-mirror) 218 ​​may include any suitable material known to those skilled in the art. In one or more embodiments, the reflective p-contact electrode (p-mirror) 218 ​​includes one or more of aluminum (Al), platinum (Pt), silver (Ag), etc. In other embodiments, the reflective p-contact electrode (p-mirror) 218 ​​may include a double layer of a reflective material (i.e., one or more of aluminum (Al), platinum (Pt), silver (Ag), etc.) and indium tin oxide (ITO), wherein the ITO is a portion of the double layer that is in direct contact with the second p-type layer 208b.

[0086] In one or more embodiments, the reflective p-contact electrode (p-mirror) 218 ​​is then bonded to a backplane wafer 220, which may be pre-coated with a similar metal to facilitate wafer bonding. In one or more embodiments, the backplane wafer 220 includes vias 222 and 224 between the bonding surface and the circuitry in or on opposite sides of the backplane wafer 220.

[0087] Still refer to Fig.10 In one or more embodiments, the first n-type layer 204a and the second n-type layer 204b are etched, for example by dry etching, to form openings for electrical contacts 214, isolation pixels, and vias 224 close to backplane terminals B. In one or more embodiments, there are two etch levels 252 and 254, which is a more manageable number than known RGB μLED arrays.

[0088] In one or more embodiments, the dielectric layer 212 is conformally deposited over the entire wafer 250. In one or more embodiments, the dielectric layer 212 includes, but is not limited to, oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3); nitrides such as silicon nitride (Si3N4). In one or more embodiments, the dielectric layer 212 includes silicon nitride (Si3N4), silicon oxide (SiO2), or a multilayer of silicon dioxide (SiO2) and silicon nitride (Si3N4). In some embodiments, the composition of the dielectric layer 212 is non-stoichiometric relative to an ideal molecular formula. For example, in some embodiments, the dielectric layer 212 includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), carbon oxides (e.g., silicon oxycarbide (SiOC)), and carbon nitride oxides (e.g., silicon oxycarbonitride (SiNCO)).

[0089] In one or more embodiments, the dielectric layer 212 is removed from the electrical contact points using dry etching. Ohmic contact metal 214 is deposited and formed in the dielectric opening. Each ohmic contact metal 214 reaches the n-type layer 204a and 204b and can be the same metal. The ohmic contact metal 214 can include any suitable metal known to those skilled in the art. In one or more embodiments, the ohmic contact metal 214 includes aluminum (Al).

[0090] Still refer to Fig.10 , a thick partial conformal metal layer 216 is deposited over most of the mesa area. A gap 232 is left across the center of the mesa to allow light to exit and to electrically isolate terminal B from ground 224. The partial conformal metal layer 216 may include any suitable material known to those skilled in the art. In one or more embodiments, the partial conformal metal layer 116 has high reflectivity and stability. In one or more embodiments, the partial conformal metal layer 216 includes aluminum (Al) or platinum (Pt). The partial conformal metal layer 216 connects the second n-type layer 204b to the backplane terminal B using a via 224. Layer 216 may be composed of a stack of multiple different metal films, such as a first metal with high reflectivity properties (such as Al or silver (Ag)) and a second metal with better chemical stability (such as titanium (Ti), chromium (Cr), tungsten (W), gold (Au) or Pt). The partial conformal metal layer 216 connects the second n-type layer 204b to the backplane terminal B using a via 224.

[0091] In other non-illustrated embodiments, different implementations of variant B may be produced, with a red active region operated by a fixed current supplied by terminal A, and a green / blue voltage-controlled color switching active region connected to terminal B.

[0092] Figure 5 and Figure 6 The A 100 variant is more complex, but Fig. 9 and Fig.10 Variant B 200 can have higher system efficiency. In one or more embodiments, a green active region designed to emit green at higher currents (Variant A) can be optimized to have a higher internal quantum efficiency than a red active region switched to green emission with a high bias voltage. For InGaN red active regions, quantum efficiency tends to peak at very low current densities. Similar arguments apply to the relative IQE of a green / blue switching active region relative to an active region specifically designed to emit blue at high current densities.

[0093] Visualization systems, such as virtual reality systems and augmented reality systems, are becoming increasingly common in fields such as entertainment, education, medicine, and business.

[0094] In a virtual reality system, a display may present a view of a scene (such as a three-dimensional scene) to a user. The user may move within the scene, such as by repositioning the user's head or by walking. The virtual reality system may detect the user's movement and change the view of the scene to account for the movement. For example, when the user rotates the user's head, the system may present a view of the scene that changes in the view direction to match the user's gaze. In this way, the virtual reality system may simulate the user's presence in the three-dimensional scene. In addition, the virtual reality system may receive tactile sensory input, such as from a wearable position sensor, and may optionally provide tactile feedback to the user.

[0095] In an augmented reality system, a display can incorporate elements from the user's surroundings into the view of a scene. For example, an augmented reality system can add text subtitles and / or visual elements to the view of the user's surroundings. For example, a retailer can use an augmented reality system to show a user what a piece of furniture would look like in a room in the user's home by combining a visualization of the furniture on top of a captured image of the user's surroundings. As the user walks around the user's room, the visualization interprets the user's movements and changes the visualization of the furniture in a manner consistent with the movement. For example, an augmented reality system can place a virtual chair in a room. The user can stand in front of the virtual chair location in the room to view the front of the chair. The user can move to an area behind the virtual chair location in the room to view the back of the chair. In this way, the augmented reality system can add elements to the dynamic view of the user's surroundings.

[0096] Fig.11 A block diagram of an example of a visualization system 10 utilizing a μLED array of one or more embodiments is shown. The visualization system 10 may include a wearable housing 12, such as a headset or goggles. The housing 12 may mechanically support and house the elements detailed below. In some examples, one or more of the elements detailed below may be included in one or more additional housings that may be separate from the wearable housing 12 and may be coupled to the wearable housing 12 wirelessly and / or via a wired connection. For example, a separate housing may reduce the weight of the wearable goggles, such as by including batteries, radios, and other elements. The housing 12 may include one or more batteries 14 that may power any or all of the elements detailed below. The housing 12 may include circuitry that may be electrically coupled to an external power source, such as a wall outlet, to charge the battery 14. The housing 12 may include one or more radios 16 to wirelessly communicate with a server or network via a suitable protocol, such as WiFi.

[0097] The visualization system 10 may include one or more sensors 18, such as optical sensors, audio sensors, tactile sensors, thermal sensors, gyroscope sensors, time-of-flight sensors, triangulation-based sensors, and the like. In some examples, one or more of these sensors may sense the location, position, and / or orientation of the user. In some examples, one or more sensors 18 may generate sensor signals in response to the sensed location, position, and / or orientation. The sensor signals may include sensor data corresponding to the sensed location, position, and / or orientation. For example, the sensor data may include a depth map of the surrounding environment. In some examples, such as for an augmented reality system, one or more sensors 18 may capture real-time video images of the surrounding environment near the user.

[0098] The visualization system 10 may include one or more video generation processors 20. The one or more video generation processors 20 may receive scene data representing a three-dimensional scene from a server and / or a storage medium, such as a set of position coordinates of an object in the scene or a depth map of the scene. The one or more video generation processors 20 may receive one or more sensor signals from one or more sensors 18. In response to the scene data representing the surrounding environment and at least one sensor signal representing the location and / or orientation of the user relative to the surrounding environment, the one or more video generation processors 20 may generate at least one video signal corresponding to a view of the scene. In some examples, the one or more video generation processors 20 may generate two video signals, one for each eye of the user, the two video signals representing views of the scene from the perspective of the left eye and the right eye of the user, respectively. In some examples, the one or more video generation processors 20 may generate more than two video signals and combine the video signals to provide one video signal for both eyes, two video signals for both eyes, or other combinations.

[0099] The visualization system 10 may include one or more light sources 22 that may provide light for a display of the visualization system 10. Suitable light sources 22 may include light emitting diodes, monolithic light emitting diodes, multiple light emitting diodes, arrays of light emitting diodes, arrays of light emitting diodes disposed on a common substrate, segmented light emitting diodes disposed on a single substrate and having individually addressable and controllable (and / or controllable in groups and / or molecular sets) light emitting diode elements, arrays of micro light emitting diodes (microLEDs), and the like.

[0100] The light emitting diode may be a white light emitting diode. For example, the white light emitting diode may emit excitation light, such as blue light or violet light. The white light emitting diode may include one or more phosphors that may absorb some or all of the excitation light and, in response, may emit phosphor light (such as yellow light) having a wavelength greater than the wavelength of the excitation light.

[0101] One or more light sources 22 may include light emitting elements having different colors or wavelengths. For example, the light source may include a red light emitting diode that may emit red light, a green light emitting diode that may emit green light, and a blue light emitting diode that may emit blue light. The red light, green light, and blue light are combined in a specific ratio to produce any suitable color that is visually perceptible in the visible portion of the electromagnetic spectrum.

[0102] The visualization system 10 may include one or more modulators 24. The modulators 24 may be implemented in one of at least two configurations.

[0103] In a first configuration, the modulator 24 may include a circuit that can directly modulate the light source 22. For example, the light source 22 may include an array of light emitting diodes, and the modulator 24 may directly modulate the electrical power, voltage, and / or current directed to each light emitting diode in the array to form modulated light. The modulation may be performed in an analog manner and / or in a digital manner. In some examples, the light source 22 may include an array of red light emitting diodes, an array of green light emitting diodes, and an array of blue light emitting diodes, and the modulator 24 may directly modulate the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes to form modulated light to produce a particular image.

[0104] In a second configuration, the modulator 24 may include a modulation panel, such as a liquid crystal panel. The light source 22 may generate uniform illumination or nearly uniform illumination to illuminate the modulation panel. The modulation panel may include pixels. Each pixel may selectively weaken a corresponding portion of the modulation panel area in response to an electrical modulation signal to form modulated light. In some examples, the modulator 24 may include a plurality of modulation panels that may modulate light of different colors. For example, the modulator 24 may include a red modulation panel that may weaken red light from a red light source (such as a red light emitting diode), a green modulation panel that may weaken green light from a green light source (such as a green light emitting diode), and a blue modulation panel that may weaken blue light from a blue light source (such as a blue light emitting diode).

[0105] In some examples of the second configuration, the modulator 24 may receive uniform white light or nearly uniform white light from a white light source, such as a white light emitting diode. The modulation panel may include a wavelength selective filter on each pixel of the modulation panel. The panel pixels may be arranged in groups, such as three or four groups, where each group may form a pixel of a color image. For example, each group may include a panel pixel with a red filter, a panel pixel with a green filter, and a panel pixel with a blue filter. Other suitable configurations may also be used.

[0106] The visualization system 10 may include one or more modulation processors 26 that may receive a video signal (such as from one or more video generation processors 20) and in response may generate an electrical modulation signal. For configurations in which the modulator 24 directly modulates the light source 22, the electrical modulation signal may drive the light source 24. For configurations in which the modulator 24 includes a modulation panel, the electrical modulation signal may drive the modulation panel.

[0107] The visualization system 10 may include one or more beam combiners 28 (also referred to as beam splitters 28) that may combine light beams of different colors to form a single polychromatic light beam. For configurations in which the light source 22 may include a plurality of light emitting diodes of different colors, the visualization system 10 may include one or more wavelength-sensitive (e.g., dichroic) beam splitters 28 that may combine light of different colors to form a single polychromatic light beam.

[0108] The visualization system 10 can direct the modulated light toward the eyes of the observer in one of at least two configurations. In the first configuration, the visualization system 10 can be used as a projector and can include suitable projection optics 30 that can project the modulated light onto one or more screens 32. The screen 32 can be positioned at a suitable distance from the user's eyes. The visualization system 10 can optionally include one or more lenses 34 that can position a virtual image of the screen 32 at a suitable distance from the eyes, such as a close-focus distance, such as 500mm, 750mm, or another suitable distance. In some examples, the visualization system 10 can include a single screen 32 so that the modulated light can be directed toward both eyes of the user. In some examples, the visualization system 10 can include two screens 32 so that the modulated light from each screen 32 can be directed toward the corresponding eye of the user. In some examples, the visualization system 10 can include more than two screens 32. In a second configuration, the visualization system 10 can direct the modulated light directly into one or both eyes of the observer. For example, projection optics 30 may form an image on the retina of one eye of a user, or may form an image on each retina of both eyes of a user.

[0109] For some configurations of the augmented reality system, the visualization system 10 may include a display that is at least partially transparent so that the user can view the user's surroundings through the display. For such configurations, the augmented reality system may generate modulated light corresponding to an enhancement of the surroundings, rather than the surroundings themselves. For example, in the example of a retailer displaying chairs, the augmented reality system may direct modulated light corresponding to the chairs, rather than the rest of the room, toward the screen or toward the user's eyes.

[0110] Example

[0111] Various embodiments are listed below. It will be understood that the embodiments listed below can be combined with all aspects of the scope of the present invention and other embodiments.

[0112] Embodiment (a). A light emitting diode (LED) array comprises: a first light emitting stack on a second light emitting stack, a second light emitting stack on a third light emitting stack, and a third light emitting stack on a reflective p-contact electrode bonded to a backplane, wherein the first light emitting stack comprises a first electrical contact on a first n-type layer on a first color active region, a first color active region on a first p-type layer, and a first p-type layer on a first tunnel junction, the second light emitting stack comprises a second electrical contact on a second n-type layer in contact with the first tunnel junction and on a second tunnel junction, a second tunnel junction on the second p-type layer, and a second p-type layer on the second color active region, and the third light emitting stack comprises a third electrical contact on a third n-type layer in contact with the second color active region and on a third p-type layer.

[0113] Embodiment (b) The LED array according to embodiment (a), further comprising a dielectric layer surrounding the first light emitting stack, the second light emitting stack and the third light emitting stack.

[0114] Embodiment (c) The LED array according to embodiment (a) to embodiment (b), further comprising a reflective metal layer on the dielectric layer.

[0115] Embodiment (d) The LED array of embodiment (a) to embodiment (c), wherein the first light emitting stack and the second light emitting stack share a second n-type layer connected to the second electrical contact.

[0116] Embodiment (e) The LED array according to embodiment (a) to embodiment (d), wherein when the first light emitting stack and the second light emitting stack are driven in parallel, the aggregate color of the emission is controlled by voltage.

[0117] Embodiment (f) The LED array according to any one of embodiments (a) to (e), further comprising an electrode grid.

[0118] Embodiment (g). According to the LED array described in embodiments (a) to (f), the first n-type layer, the second n-type layer and the third n-type layer independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc.

[0119] Embodiment (h) The LED array according to embodiment (a) to embodiment (g), wherein the first n-type layer, the second n-type layer and the third n-type layer comprise gallium nitride (GaN).

[0120] Embodiment (i) The LED array of embodiments (a) to (h), wherein the first electrical contact, the second electrical contact, and the third electrical contact independently comprise aluminum.

[0121] Embodiment (j) According to the LED array of embodiment (a) to embodiment (i), the reflective p-contact electrode comprises one or more of aluminum (Al), platinum (Pt), and silver (Ag).

[0122] Embodiment (k) The LED array of embodiments (a) to (j), wherein the reflective p-contact electrode comprises a double layer comprising indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt) and silver (Ag).

[0123] Embodiment (l). A method for manufacturing an LED array, the method comprising: sequentially forming at least three pn junctions on an epitaxial wafer to form an epitaxial stack, the epitaxial stack comprising at least one n-type layer and at least one p-type layer, and having a color active region embedded between the at least one n-type layer and the at least one p-type layer; depositing a reflective p-contact electrode on the epitaxial stack; bonding the reflective p-contact electrode to a backplane wafer; dry etching the epitaxial stack to access at least one n-type layer to form an electrical contact and a mesa; conformally depositing a dielectric layer over the mesa; removing a portion of the dielectric layer to form a dielectric opening on the top surface of the mesa, the dielectric opening exposing at least one n-type layer; depositing an ohmic contact in the dielectric opening to form an electrical contact; depositing a conformal metal layer over a portion of the mesa and forming a gap across the center of the mesa to allow light to exit; and depositing an electrode grid over the top of the LED array.

[0124] Embodiment (m) The method according to embodiment (l), further comprising annealing the epitaxial stack before depositing the reflective p-contact electrode.

[0125] Embodiment (n). The method according to embodiments (l) to (m), wherein the epitaxial stack comprises: a first light-emitting stack comprising a first n-type layer on a first color active region, a first color active region on a first p-type layer, and a first p-type layer on a first tunnel junction; a second light-emitting stack comprising a second n-type layer in contact with the first tunnel junction and on a second tunnel junction, a second tunnel junction on the second p-type layer, and a second p-type layer on a second color active region; and a third light-emitting stack comprising a third n-type layer in contact with the second color active region and on a third p-type layer.

[0126] Embodiment (o) The method of embodiment (l) to embodiment (n), wherein when the first light-emitting stack and the second light-emitting stack are driven in parallel, the aggregate color of the emission is controlled by voltage.

[0127] Embodiment (p). The method according to embodiments (l) to (o), wherein the first n-type layer, the second n-type layer and the third n-type layer independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc.

[0128] Embodiment (q) The method of embodiment (l) to embodiment (p), wherein the first n-type layer, the second n-type layer, and the third n-type layer comprise gallium nitride (GaN).

[0129] Embodiment (r) The method of embodiment (l) to embodiment (q), wherein the electrical contact comprises aluminum.

[0130] Embodiment (s). The method according to embodiment (l) to embodiment (r), wherein the reflective p-contact electrode comprises one or more of aluminum (Al), platinum (Pt), and silver (Ag), or wherein the reflective p-contact electrode comprises a double layer comprising indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt), and silver (Ag).

[0131] Embodiment (t). A visualization system comprising: a battery; a radio; a sensor; a video generation processor; a light source comprising an LED array according to any one of embodiments (a) to (r); a modulator; a modulation processor; a beam combiner; a projection optics; a screen; and a lens.

[0132] In the context of describing the materials and methods discussed herein (especially in the context of the following claims), the use of the terms "one" and "an" and "the" and similar references should be interpreted as covering both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the description of the range of values ​​herein is intended only to be used as a shorthand method for individually referring to each individual value falling within the range, and each individual value is incorporated into this specification as if it were individually described herein. Unless otherwise indicated herein or clearly contradicted by the context otherwise, all methods described herein can be performed in any suitable order. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods, and unless otherwise claimed, does not limit the scope. Any language in this specification should not be interpreted as indicating that any unclaimed element is essential for practicing the disclosed materials and methods.

[0133] Throughout the specification, the terms first, second, third, etc. may be used to describe various elements herein, and these elements should not be limited by these terms. These terms may be used to distinguish one element from another.

[0134] Throughout this specification, reference to a layer, region, or substrate being "on" or extending to another element means that it may be directly on or directly extending to another element, or there may be intermediate elements. When an element is referred to as being "directly on" or "directly extending to" another element, there may be no intermediate elements. In addition, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to another element and / or connected or coupled to another element via one or more intermediate elements. When an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element between the element and the other element. It will be understood that these terms are intended to cover different orientations of elements, in addition to any orientation depicted in the figures.

[0135] Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0136] Throughout this specification, reference to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in an embodiment," or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

[0137] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrations of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, it is intended that the present disclosure include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A light emitting diode (LED) array, comprising: a first light emitting stack on a second light emitting stack, a second light emitting stack on a third light emitting stack, a third light emitting stack on a reflective p-contact electrode bonded to a backplane, wherein The first light emitting stack includes a first electrical contact on a first n-type layer on a first color active region, a first color active region on a first p-type layer, and a first p-type layer on a first tunnel junction, The second light emitting stack includes a second electrical contact on a second n-type layer in contact with the first tunnel junction and on the second tunnel junction, a second tunnel junction on the second p-type layer, and a second p-type layer on the second color active area, and The third light emitting stack includes a third electrical contact on the third n-type layer in contact with the second color active region and on the third p-type layer. 2 . The LED array of claim 1 , further comprising a dielectric layer surrounding the first light emitting stack, the second light emitting stack, and the third light emitting stack. 3 . The LED array of claim 2 , further comprising a reflective metal layer on the dielectric layer. 4 . The LED array of claim 1 , wherein the first light emitting stack and the second light emitting stack share a second n-type layer connected to a second electrical contact. 5 . The LED array of claim 4 , wherein when the first light emitting stack and the second light emitting stack are driven in parallel, an aggregate color of emission is controlled by voltage.

6. The LED array of claim 1, further comprising an electrode grid.

7. The LED array according to claim 1, wherein the first n-type layer, the second n-type layer and the third n-type layer independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. 8 . The LED array of claim 7 , wherein the first n-type layer, the second n-type layer, and the third n-type layer comprise gallium nitride (GaN).

9. The LED array of claim 1, wherein the first electrical contact, the second electrical contact, and the third electrical contact independently comprise aluminum.

10. The LED array according to claim 1, wherein the reflective p-contact electrode comprises one or more of aluminum (Al), platinum (Pt), and silver (Ag).

11. The LED array of claim 1, wherein the reflective p-contact electrode comprises a bilayer comprising indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt), and silver (Ag).

12. A method for manufacturing an LED array, the method comprising: sequentially forming at least three pn junctions on the epitaxial wafer to form an epitaxial stack, the epitaxial stack comprising at least one n-type layer and at least one p-type layer, and having a color active region embedded between the at least one n-type layer and the at least one p-type layer; depositing a reflective p-contact electrode on the epitaxial stack; bonding a reflective p-contact electrode to a backplane wafer; dry etching the epitaxial stack to access at least one of the n-type layers to form electrical contacts and mesas; conformally depositing a dielectric layer over the mesa; removing a portion of the dielectric layer to form a dielectric opening on a top surface of the mesa, the dielectric opening exposing the at least one n-type layer; depositing an ohmic contact in the dielectric opening to form an electrical contact; depositing a conformal metal layer over a portion of the mesa and forming a gap across the center of the mesa to allow light to exit; and A grid of electrodes is deposited over top of the LED array.

13. The method of claim 12, further comprising annealing the epitaxial stack prior to depositing the reflective p-contact electrode.

14. The method of claim 12, wherein the epitaxial stack comprises: a first light emitting stack comprising a first n-type layer on a first color active region, a first color active region on a first p-type layer, a first p-type layer on a first tunnel junction; a second light emitting stack including a second n-type layer in contact with the first tunnel junction and on the second tunnel junction, a second tunnel junction on the second p-type layer, and a second p-type layer on the second color active region; and A third light emitting stack includes a third n-type layer in contact with the second color active region and on the third p-type layer.

15. The method of claim 14, wherein when the first light-emitting stack and the second light-emitting stack are driven in parallel, an aggregate color of emission is controlled by a voltage.

16. The method according to claim 14, wherein the first n-type layer, the second n-type layer and the third n-type layer independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. 17 . The method of claim 16 , wherein the first n-type layer, the second n-type layer, and the third n-type layer comprise gallium nitride (GaN).

18. The method of claim 12, wherein the electrical contact comprises aluminum.

19. The method of claim 12, wherein the reflective p-contact electrode comprises one or more of aluminum (Al), platinum (Pt), silver (Ag), or wherein the reflective p-contact electrode comprises a double layer comprising indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt), and silver (Ag).

20. A visualization system comprising: Battery; radio; sensor; Video generation processor; A light source comprising an LED array according to any one of claims 1 to 11; Modulator; Modulation processor; Beam combiner; projection optics; screen; and lens.

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