Oxide semiconductor film, thin film transistor, and electronic device

Abstract

The oxide semiconductor film is provided on the substrate and has a polycrystalline structure, the crystal structure of the oxide semiconductor film is a bixbyite-type structure, and the ratio of the peak intensity of the (222) plane to the peak intensity of the (422) plane of the oxide semiconductor film in an out-of-plane XRD diffraction pattern using Cu-K alpha rays is 3.0 or less. The crystallite diameter calculated from the peak of the (222) plane may be 10 nm or more.

Description

Technical Field

[0001] One embodiment of the present invention relates to an oxide semiconductor (Poly-OS) film having a polycrystalline structure. Another embodiment of the present invention relates to a thin film transistor including the Poly-OS film. Another embodiment of the present invention relates to an electronic device including the thin film transistor. Background Art

[0002] In recent years, the development of thin film transistors using oxide semiconductor films as channels instead of silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon and single crystal silicon has been continuously developed (for example, see Patent Documents 1 to 6). Such thin film transistors including oxide semiconductor films can be formed with a simple structure and by a low-temperature process, just like thin film transistors including amorphous silicon films. In addition, it is known that thin film transistors including oxide semiconductor films have higher field effect mobility than thin film transistors including amorphous silicon films.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] However, the field effect mobility of a thin film transistor including a conventional oxide semiconductor film is not that high even when a crystalline oxide semiconductor film is used. Therefore, it is desirable to improve the crystal structure of an oxide semiconductor film used in a thin film transistor to increase the field effect mobility of the thin film transistor.

[0013] In view of the above problems, one object of one embodiment of the present invention is to provide an oxide semiconductor film having a novel crystal structure. In addition, one object of one embodiment of the present invention is to provide a thin film transistor including an oxide semiconductor film having a novel crystal structure. In addition, one embodiment of the present invention relates to an electronic device including a thin film transistor.

[0014] Means for solving problems

[0015] An oxide semiconductor film involved in one embodiment of the present invention is an oxide semiconductor film having a polycrystalline structure arranged on a substrate, the crystal structure of the oxide semiconductor film is a pyrolusite structure, and in an out-of-plane XRD diffraction pattern using Cu-Kα rays, the ratio of the peak intensity of the (222) plane of the oxide semiconductor film to the peak intensity of the (422) plane is less than 3.0.

[0016] A thin film transistor according to one embodiment of the present invention includes: an oxide semiconductor layer including the above-mentioned oxide semiconductor film; a gate electrode provided on the oxide semiconductor layer; and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode.

[0017] An electronic device according to one embodiment of the present invention includes the above-mentioned thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] [ Figure 1 ] is a schematic cross-sectional view showing the structure of a thin film transistor involved in one embodiment of the present invention.

[0019] [ Figure 2 ] is a schematic top view showing the structure of a thin film transistor involved in one embodiment of the present invention.

[0020] [ Figure 3 ] is a flow chart showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0021] [ Figure 4 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0022] [ Figure 5 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0023] [ Figure 6 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0024] [ Figure 7 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0025] [ Figure 8 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0026] [ Fig. 9 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0027] [ Fig.10 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0028] [ Fig.11 ] is a schematic diagram showing an electronic device involved in one embodiment of the present invention.

[0029] [ Fig.12 ] is the XRD diffraction pattern of the oxide semiconductor film of Example 1.

[0030] [ Fig.13 ] is the XRD diffraction pattern of the oxide semiconductor film of Example 2.

[0031] [ Fig.14 ] is the XRD diffraction pattern of the oxide semiconductor film of Example 3-1.

[0032] [ Fig.15 ] is the XRD diffraction pattern of the oxide semiconductor film of Example 3-2.

[0033] [ Fig.16 ] is the XRD diffraction pattern of the oxide semiconductor film of Comparative Example 1.

[0034] [ Fig.17 ] is the XRD diffraction pattern of the oxide semiconductor film of Comparative Example 2. DETAILED DESCRIPTION

[0035] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically indicated compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and each figure, the same figure mark is marked for the same elements as those described in the accompanying drawings that have appeared, and the detailed description is sometimes appropriately omitted.

[0036] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. As such, for ease of explanation, the phrases such as up or below are used for explanation, but, for example, the up-and-down relationship between the substrate and the oxide semiconductor layer may be configured in a manner opposite to that shown in the figure. In the following description, for example, the expression "oxide semiconductor layer on the substrate" is only used to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. Up or down means the stacking order in a structure having multiple layers stacked, and in the case of a pixel electrode described as above a thin film transistor, it may also be a positional relationship in which the thin film transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of a pixel electrode described as vertically above a thin film transistor, it means a positional relationship in which the thin film transistor and the pixel electrode overlap when viewed from above.

[0037] In the present specification, the term "film" and the term "layer" can be used interchangeably according to circumstances.

[0038] A "display device" refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure that is equipped with other optical components (for example, polarization components, backlight sources, touch panels, etc.) relative to a display unit. As long as no technical contradiction arises, the "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described later, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified for explanation, but the structure in this embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0039] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes multiple combinations of A to C. In addition, the above expressions do not exclude the case where α includes other elements.

[0040] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0041] <First embodiment>

[0042] An oxide semiconductor film according to one embodiment of the present invention is described.

[0043] [1. Composition of Oxide Semiconductor Film]

[0044] The oxide semiconductor film involved in this embodiment includes indium (In) and at least one metal element (M) other than indium. That is, the metal element other than indium contained in the oxide semiconductor film can be one metal element or multiple metal elements. The composition ratio of the oxide semiconductor film preferably satisfies the formula (1) in which the atomic ratio of indium to at least one metal element satisfies the formula (1). In other words, the ratio of indium to all metal elements in the oxide semiconductor film is preferably 50% or more. By increasing the ratio of indium, a crystalline oxide semiconductor film can be formed. In addition, the crystal structure of the oxide semiconductor film preferably has a pyrolusite structure. By increasing the ratio of indium, an oxide semiconductor film having a pyrolusite structure can be formed.

[0045] [Mathematical formula 1]

[0046]

[0047] The detailed manufacturing method of the oxide semiconductor film will be described together with the manufacturing method of the thin film transistor described later, and the oxide semiconductor film can be formed using a sputtering method. The composition of the oxide semiconductor film formed by sputtering depends on the composition of the sputtering target. In the sputtering target having the above composition, an oxide semiconductor film without a composition deviation of the metal elements can be formed by sputtering. Therefore, the composition of the metal elements (indium and other metal elements) of the oxide semiconductor film can also be regarded as the same as the composition of the metal elements of the sputtering target. For example, the composition of the metal elements of the oxide semiconductor film can be determined based on the composition of the metal elements of the sputtering target. It should be noted that since the oxygen contained in the oxide semiconductor film will change according to the process conditions of the sputtering, it is not limited to this.

[0048] In addition, the composition of the metal elements of the oxide semiconductor film can also be determined using fluorescent X-ray analysis or electron probe microanalyzer (EPMA) analysis. In addition, since the oxide semiconductor film has a polycrystalline structure, the composition of the oxide semiconductor film can also be determined using an X-ray diffraction (XRD) method. Specifically, the composition of the metal elements of the oxide semiconductor film can be determined based on the crystal structure and lattice constant of the oxide semiconductor film obtained by the XRD method.

[0049] [2. Crystal structure of oxide semiconductor film]

[0050] The oxide semiconductor film involved in this embodiment has a polycrystalline structure including a plurality of crystal grains. By using the Poly-OS (Poly-crystalline Oxide Semiconductor) technology, an oxide semiconductor film having a novel polycrystalline structure different from the conventional one can be formed, and the details are described later. Therefore, in order to distinguish it from the conventional oxide semiconductor film having a polycrystalline structure, the oxide semiconductor film having a polycrystalline structure involved in this embodiment is sometimes referred to as a Poly-OS film.

[0051] The crystal structure of the Poly-OS film is not particularly limited, but is preferably a bixbyite structure. The crystal structure of the Poly-OS film can be determined using an XRD method or an electron beam diffraction method.

[0052] The crystal structure of the Poly-OS film is different from the crystal structure of the oxide semiconductor film having a polycrystalline structure in the past. Specifically, the inventors of the present application found that although the Poly-OS film has a polycrystalline structure, the polycrystalline structure of the Poly-OS film is different from the polycrystalline structure of the oxide semiconductor film in the past. That is, the inventors of the present application conducted various trials and errors, and as a result, completed an oxide semiconductor film (Poly-OS film) having a novel polycrystalline structure different from the oxide semiconductor film in the past. The characteristics of the crystallinity of the Poly-OS film can be obtained using the XRD method.

[0053] There are two types of XRD methods: out-of-plane measurement and in-plane measurement. Out-of-plane measurement can evaluate the lattice planes parallel to the surface of the film, and in-plane measurement can evaluate the lattice planes perpendicular to the surface of the film. The characteristics of the Poly-OS film can be obtained by out-of-plane measurement.

[0054] Here, the crystal plane (001) of the bixbyite structure in this specification includes (001) and its equivalent (100) and (010). Similarly, the crystal plane (101) includes (101) and its equivalent (110) and (011). In addition, the crystal plane (111) represents (111). In addition, in each plane, "1" can also be "-1", which is regarded as a plane equivalent to each plane.

[0055] It should be noted that, in addition to (001), (101) and (111), there are also (hk0) (h≠k, h and k are natural numbers), (hhl) (h≠l, h and l are natural numbers) and (hkl) (h≠k≠l, h, k and l are natural numbers).

[0056] [2-1. Peak intensity]

[0057] When the oxide semiconductor film is crystalline, a peak appears at a specified diffraction angle in the XRD diffraction pattern measured out of the plane. For example, in the XRD diffraction pattern, a previous crystalline oxide semiconductor film containing more than 50% indium and having a chalcogenide structure has peaks at diffraction angles (2θ) near 31° and near 44°. The peak of the diffraction angle near 31° belongs to the (222) plane of the chalcogenide structure. The peak of the diffraction angle near 44° belongs to the (422) plane of the chalcogenide structure. In addition, the peak intensity of the diffraction angle near 31° is significantly greater than the peak intensity of the diffraction angle near 44°. This means that there are many crystals having a (222) plane in a parallel direction relative to the surface of the oxide semiconductor film.

[0058] It should be noted that the diffraction angle of the XRD diffraction pattern of the oxide semiconductor film may vary depending on the composition of the metal elements contained in the oxide semiconductor film or the production conditions of the oxide semiconductor film. Therefore, in this specification, the vicinity of the diffraction angle peak includes the range of ±2° of the diffraction angle of the peak.

[0059] In the XRD diffraction pattern of the Poly-OS film having the bixbyite structure, there is a peak at a diffraction angle of about 31° corresponding to the (222) plane of the bixbyite structure. However, the peak intensity of the diffraction angle of the Poly-OS film at about 31° is smaller than the peak intensity of the diffraction angle of the conventional crystalline oxide semiconductor film at about 31° under the same film thickness condition. For example, the peak intensity of the diffraction angle of the Poly-OS film at about 31° is less than 1 / 2 of the peak intensity of the diffraction angle of the conventional crystalline oxide semiconductor film at about 31° under the same film thickness condition.

[0060] In the XRD diffraction pattern of the Poly-OS film, a peak sometimes appears at a diffraction angle near 44°. When a peak appears at a diffraction angle near 44°, the ratio of the peak intensity of the diffraction angle near 31° to the peak intensity of the diffraction angle near 44° (hereinafter referred to as the "peak intensity ratio") is 3.0 or less. In addition, in the XRD diffraction pattern of the Poly-OS film, a peak sometimes does not appear at a diffraction angle near 44°. In addition, in the XRD diffraction pattern of the Poly-OS film, a peak sometimes appears at a diffraction angle near 52° corresponding to the (440) plane of the bixbyite structure. The above phenomenon indicates that in the Poly-OS film, there are few crystals having a (222) plane in a parallel direction relative to the surface of the Poly-OS film, and the orientation is relaxed. As a result, there is a state in which there are many crystals having a (440) plane in a parallel direction relative to the surface of the Poly-OS film, and the Poly-OS film has a specific crystal arrangement different from the past.

[0061] As described above, the Poly-OS film shows a characteristic XRD diffraction pattern that is different from that of conventional crystalline oxide semiconductor films. Specifically, when the Poly-OS film has a bixbyite structure, the peak intensity of the (222) plane in the XRD diffraction pattern is small. In the case where the peak of the (422) plane appears, the peak intensity ratio of the (222) plane to the (422) plane is less than 3.0, preferably less than 2.0. In addition, in the Poly-OS film, the peak intensity is small overall, and the peak of the (422) plane sometimes does not appear. In addition, in the Poly-OS film, the peak of the (440) plane sometimes appears, which means that the orientation of the (222) plane relative to the surface of the Poly-OS film is relaxed, and the (440) plane is arranged in a parallel direction relative to the surface of the Poly-OS film. In other words, the crystals contained in the Poly-OS film have a characteristic crystal arrangement that is different from the past.

[0062] [2-2. Crystallite diameter]

[0063] The crystal grains contained in the Poly-OS film may include a plurality of crystallites. The crystallite diameter D can be calculated by the Scherrer formula shown in formula (2) using the peak width of the XRD diffraction pattern. Here, K is the Scherrer constant, λ is the wavelength of the X-ray, β is the half-value width of the peak, and θ is the Bragg angle (equivalent to 1 / 2 of the diffraction angle 2θ).

[0064] [Mathematical formula 2]

[0065] D=Kλ / βcosθ…(2)

[0066] In a Poly-OS film having a pyrolusite structure, the half-value width of the peak corresponding to the (222) plane can be used to calculate the crystallite diameter D of the grains contained in the Poly-OS film. In the out-of-plane XRD diffraction pattern using Cu-Kα rays, the crystallite diameter D is greater than 10 nm, preferably greater than 15 nm, and more preferably greater than 20 nm. In addition, when the film thickness of the Poly-OS film is less than 20 nm, the crystallite diameter D is preferably greater than 0.95 times the film thickness d of the Poly-OS film. That is, the crystallite diameter D is preferably approximately equal to the film thickness of the Poly-OS film. It should be noted that when the film thickness of the Poly-OS film is small, a crystallite diameter D that exceeds the film thickness of the Poly-OS film can sometimes be obtained. In this case, when the crystallite diameter D is a value near the film thickness of the Poly-OS film, it means that the crystallite diameter D is approximately equal to the film thickness of the Poly-OS film, and can be judged to be greater than 0.95 times the film thickness d of the Poly-OS film.

[0067] As described above, in the Poly-OS film, the peak intensity of the (222) plane in the XRD diffraction pattern is small. However, the crystallite diameter of the Poly-OS film is about the same as that of the conventional crystalline oxide semiconductor film. Therefore, the Poly-OS film has a novel crystal structure in which the orientation of the crystal is relaxed compared to the conventional crystalline oxide semiconductor film and the long-range order of the atoms in the film thickness direction (vertical direction relative to the film surface) is maintained.

[0068] As described above, the oxide semiconductor film, i.e., the Poly-OS film, involved in one embodiment of the present invention has a novel crystal structure. Even if the Poly-OS film having such a novel crystal structure is used as a channel of a thin film transistor, the field effect mobility will not decrease but will increase, as described in detail later. Therefore, the electrical characteristics of the thin film transistor including the Poly-OS film are improved.

[0069] <Second embodiment>

[0070] Reference Figures 1 to 10 A thin film transistor 10 according to one embodiment of the present invention will be described. The thin film transistor 10 can be used in, for example, a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a memory circuit.

[0071] [1. Configuration of Thin Film Transistor 10]

[0072] Reference Figure 1 and Figure 2 The structure of the thin film transistor 10 according to one embodiment of the present invention will be described. Figure 1 It is a schematic cross-sectional view showing the structure of a thin film transistor 10 according to one embodiment of the present invention. Figure 2 is a schematic top view showing the structure of a thin film transistor according to one embodiment of the present invention. Specifically, Figure 1 It is along Figure 2 The cross-sectional view is obtained by cutting along the A-A' line.

[0073] like Figure 1As shown, the thin film transistor 10 includes a substrate 100, a light shielding layer 105, a first insulating layer 110, a second insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a fourth insulating layer 180, a source electrode 201, and a drain electrode 203. The light shielding layer 105 is provided on the substrate 100. The first insulating layer 110 covers the upper surface and end surface of the light shielding layer 105 and is provided on the substrate 100. The second insulating layer 120 is provided on the first insulating layer 110. The oxide semiconductor layer 140 is provided on the second insulating layer 120. The gate insulating layer 150 covers the upper surface and end surface of the oxide semiconductor layer 140 and is provided on the second insulating layer 120. The gate electrode 160 overlaps with the oxide semiconductor layer 140 and is provided on the gate insulating layer 150. The third insulating layer 170 covers the upper surface and end surface of the gate electrode 160, and is provided on the gate insulating layer 150. The fourth insulating layer 180 is provided on the third insulating layer 170. The gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 are provided with openings 171 and 173 that expose a portion of the upper surface of the oxide semiconductor layer 140. The source electrode 201 is provided on the fourth insulating layer 180 and inside the opening 171, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is provided on the fourth insulating layer 180 and inside the opening 173, and is in contact with the oxide semiconductor layer 140. It should be noted that, hereinafter, when the source electrode 201 and the drain electrode 203 are not particularly distinguished, they are sometimes collectively referred to as the source / drain electrode 200.

[0074] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH based on the gate electrode 160. That is, the oxide semiconductor layer 140 includes a channel region CH overlapping with the gate electrode 160, and a source region S and a drain region D not overlapping with the gate electrode 160. In the film thickness direction of the oxide semiconductor layer 140, the end of the channel region CH coincides with the end of the gate electrode 160. The channel region CH has the properties of a semiconductor. The source region S and the drain region D each have the properties of a conductor. Therefore, the conductivity of the source region S and the drain region D is greater than the conductivity of the channel region CH. The source electrode 201 and the drain electrode 203 are respectively connected to the source region S and the drain region D, and are electrically connected to the oxide semiconductor layer 140. In addition, the oxide semiconductor layer 140 can be a single-layer structure or a stacked structure.

[0075] like Figure 2As shown, the light shielding layer 105 and the gate electrode 160 each have a certain width in the D1 direction and extend in the D2 direction orthogonal to the D1 direction. In the D1 direction, the width of the light shielding layer 105 is greater than the width of the gate electrode 160. The channel region CH completely overlaps with the light shielding layer 105. In the thin film transistor 10, the D1 direction corresponds to the direction in which the current flows from the source electrode 201 to the drain electrode 203 via the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0076] The substrate 100 can support each layer constituting the thin film transistor 10. As the substrate 100, for example, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate can be used. In addition, as the substrate, a silicon substrate or other non-light-transmitting rigid substrate can be used. In addition, as the substrate, a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate or a fluororesin substrate or other light-transmitting flexible substrate can be used. In order to improve the heat resistance of the substrate 100, impurities can also be introduced into the above-mentioned resin substrate. It should be noted that a substrate having a silicon oxide film or a silicon nitride film formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.

[0077] The light shielding layer 105 can reflect or absorb external light. As described above, since the light shielding layer 105 is arranged in a manner having an area larger than that of the channel region CH of the oxide semiconductor layer 140, it is possible to block external light incident on the channel region CH. As the light shielding layer 105, for example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo) or tungsten (W), or alloys or compounds thereof, etc. can be used. In addition, as the light shielding layer 105, it is not necessary to contain a metal when conductivity is not required. For example, as the light shielding layer 105, a black matrix formed by a black resin can also be used. In addition, the light shielding layer 105 can be a single-layer structure or a stacked structure. For example, the light shielding layer 105 can be a stacked structure of a red filter, a green filter, and a blue filter.

[0078] The first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can prevent impurities from diffusing into the oxide semiconductor layer 140. Specifically, the first insulating layer 110 and the second insulating layer 120 can prevent the diffusion of impurities contained in the substrate 100, and the third insulating layer 170 and the fourth insulating layer 180 can prevent the diffusion of impurities (for example, water, etc.) intruding from the outside. As each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180, for example, silicon oxide (SiO x ), silicon oxide nitride (SiO x Ny ), Silicon Nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) etc. Here, silicon nitride oxide (SiO x N y ) and aluminum oxide nitride (AlO x N y ) are silicon compounds and aluminum compounds containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y ) and aluminum nitride (AlN x O y ) is a silicon compound or an aluminum compound containing oxygen at a ratio less than nitrogen (x>y). In addition, the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may each have a single layer structure or a stacked structure.

[0079] In addition, each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may have a planarization function or a function of releasing oxygen by heat treatment. However, when the second insulating layer 120 includes a silicon oxide film or a silicon nitride oxide film, it is preferable to reduce the hydrogen concentration of the silicon oxide film or the silicon nitride oxide film. For example, the hydrogen concentration of the silicon oxide film used in the second insulating layer 120 is lower than the hydrogen concentration of the silicon oxide film used in the third insulating layer 170.

[0080] The silicon oxide film or silicon nitride oxide film contained in the second insulating layer 120 may or may not be in contact with the oxide semiconductor layer 140. In the case where the silicon oxide film is not in contact with the oxide semiconductor layer 140, it is preferred that other oxide insulating films are provided between the silicon oxide film and the oxide semiconductor layer 140. For example, as an oxide insulating film, a metal oxide containing one or more metal elements selected from aluminum (Al), magnesium (Mg), calcium (Ca), scandium (Sc), gallium (Ga), germanium (Ge), strontium (Sr), nickel (Ni), tantalum (Ta), yttrium (Y), zirconium (Zr), barium (Ba), hafnium (Hf), cobalt (Co) and lanthanide elements can be used. In particular, as a metal oxide, a metal oxide containing aluminum (for example, aluminum oxide, etc.) is preferably used. A metal oxide containing aluminum has high barrier properties to gases such as hydrogen or water.

[0081] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys thereof or compounds thereof can be used as the gate electrode 160, the source electrode 201, and the drain electrode 203. Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a stacked structure.

[0082] The gate insulating layer 150 includes an oxide having insulating properties. Specifically, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x ) or aluminum oxide nitride (AlO x N y ) etc. It is preferred that the gate insulating layer 150 has a composition close to a stoichiometric ratio. In addition, it is preferred that the gate insulating layer 150 has few defects. For example, as the gate insulating layer 150, an oxide in which no defects are observed when evaluated by an electron spin resonance method (ESR) can be used.

[0083] As the oxide semiconductor layer 140 , the Poly-OS film described in the first embodiment can be used.

[0084] The structure of the thin film transistor 10 is described above, but the thin film transistor 10 described above is a so-called top-gate transistor. The thin film transistor 10 can be deformed in various ways. For example, when the light shielding layer 105 is conductive, the thin film transistor 10 can also be a structure in which the light shielding layer 105 functions as a gate electrode and the first insulating layer 110 and the second insulating layer 120 function as gate insulating layers. In this case, the thin film transistor 10 is a so-called dual-gate transistor. In addition, when the light shielding layer 105 is conductive, the light shielding layer 105 can be a floating electrode or can be connected to the source electrode 201. In addition, the thin film transistor 10 can also be a so-called bottom-gate transistor in which the light shielding layer 105 functions as the main gate electrode.

[0085] [2. Method for Manufacturing Thin Film Transistor 10]

[0086] Reference Figures 3 to 10 A method for manufacturing the thin film transistor 10 according to one embodiment of the present invention will be described. Figure 3 1 is a flowchart showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention. Figures 4 to 10Schematic cross-sectional view showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention.

[0087] like Figure 3 As shown, the method for manufacturing the thin film transistor 10 includes steps S1010 to S1110. Steps S1010 to S1110 are described in sequence below, but the order of the steps may be changed in the method for manufacturing the thin film transistor 10. In addition, the method for manufacturing the thin film transistor 10 may include further steps.

[0088] In step S1010, a light shielding layer 105 having a predetermined pattern is formed on the substrate 100. The light shielding layer 105 is patterned using photolithography. In addition, a first insulating layer 110 and a second insulating layer 120 are formed on the light shielding layer 105 (see Figure 4 ). The first insulating layer 110 and the second insulating layer 120 are formed using a CVD method. For example, a silicon nitride film and a silicon oxide film are formed as the first insulating layer 110 and the second insulating layer 120, respectively. When a silicon nitride film is used as the first insulating layer 110, the first insulating layer 110 can block impurities diffused from the substrate 100 side to the oxide semiconductor layer 140. When a silicon oxide film is used as the second insulating layer 120, the second insulating layer 120 can release oxygen by heat treatment.

[0089] In addition, the silicon oxide film used as the second insulating layer 120 is formed by adjusting the gas flow ratio in a manner to reduce the hydrogen concentration. When the silicon oxide film is formed using monosilane (SiH4) gas and nitrous oxide (N2O) gas, for example, the gas flow ratio of monosilane gas to nitrous oxide gas is SiH4:N2O=1:50-200 (50 or more and 200 or less).

[0090] In step S1020, an oxide semiconductor film 145 is formed on the second insulating layer 120 (see Figure 5 The oxide semiconductor film 145 is formed by a sputtering method. The thickness of the oxide semiconductor film 145 is, for example, not less than 10 nm and not more than 100 nm, preferably not less than 15 nm and not more than 70 nm, and more preferably not less than 15 nm and not more than 40 nm.

[0091] The oxide semiconductor film 145 in step S1020 is amorphous. In the Poly-OS technology, in order to make the oxide semiconductor layer 140 have a uniform polycrystalline structure within the substrate surface, the oxide semiconductor film 145 is preferably amorphous after film formation and before heat treatment. Therefore, it is preferred that the film formation conditions of the oxide semiconductor film 145 are conditions under which the oxide semiconductor layer 140 immediately after film formation does not crystallize as much as possible. In the case of forming the oxide semiconductor film 145 by sputtering, the oxide semiconductor film 145 is formed while the temperature of the film-forming object (substrate 100 and the layer formed on the substrate 100) is controlled to be below 100°C, preferably below 80°C, and more preferably below 50°C. In addition, the oxide semiconductor film 145 is formed under conditions of low oxygen partial pressure. The oxygen partial pressure is greater than 2% and less than 20%, preferably greater than 3% and less than 15%, and more preferably greater than 3% and less than 10%.

[0092] In step S1030, the oxide semiconductor film 145 is patterned (see Figure 6 ). The patterning of the oxide semiconductor film 145 is performed using photolithography. As the etching of the oxide semiconductor film 145, wet etching can be used, or dry etching can be used. In wet etching, an acidic etchant can be used for etching. As an etchant, for example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide or hydrofluoric acid can be used.

[0093] In step S1040, the oxide semiconductor film 145 is heat treated. Hereinafter, the heat treatment performed in step S1040 is referred to as "OS annealing". In OS annealing, the oxide semiconductor film 145 is maintained at a specified arrival temperature for a specified time. The specified arrival temperature is greater than 300°C and less than 500°C, preferably greater than 350°C and less than 450°C. In addition, the holding time at the arrival temperature is greater than 15 minutes and less than 120 minutes, preferably greater than 30 minutes and less than 60 minutes. Through OS annealing, the oxide semiconductor film 145 is crystallized to form an oxide semiconductor layer 140 having a polycrystalline structure (i.e., an oxide semiconductor layer 140 including a Poly-OS film).

[0094] In the OS annealing, hydrogen or water contained in the oxide semiconductor layer 140 is removed, but sometimes hydrogen or water contained in the second insulating layer 120 is also removed through the oxide semiconductor layer 140. Hydrogen or water diffused from the second insulating layer 120 to the oxide semiconductor layer 140 may become a factor that hinders crystallization or a factor that promotes crystallization. If crystallization is performed using such a crystallization factor, a conventional crystalline oxide semiconductor layer will be formed. Therefore, in this embodiment, in order to eliminate the above-mentioned crystallization factor, in step S1010, the hydrogen concentration of the silicon oxide film contained in the second insulating layer 120 is reduced. As a result, in the OS annealing, the diffusion of hydrogen or water from the second insulating layer 120 to the oxide semiconductor layer 140 is suppressed, and a Poly-OS film having a new crystal structure different from the conventional one can be formed.

[0095] It should be noted that in step S1010, an aluminum oxide film is preferably formed on the silicon oxide film as the second insulating layer 120. The aluminum oxide film can block hydrogen or water from the silicon oxide film, so that during the OS annealing, the diffusion of hydrogen or water from the second insulating layer 120 to the oxide semiconductor layer 140 can be further suppressed.

[0096] In step S1050, a gate insulating layer 150 is formed on the oxide semiconductor layer 140 (see Figure 7 ). The gate insulating layer 150 is formed by a CVD method. For example, silicon oxide is formed as the gate insulating layer 150. In order to reduce defects in the gate insulating layer 150, the gate insulating layer 150 can be formed at a film forming temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is greater than 50 nm and less than 300 nm, preferably greater than 60 nm and less than 200 nm, and more preferably greater than 70 nm and less than 150 nm. After the gate insulating layer 150 is formed, a process of introducing oxygen into a portion of the gate insulating layer 150 can be performed.

[0097] In step S1060, the oxide semiconductor layer 140 is heat treated. Hereinafter, the heat treatment performed in step S1060 is referred to as "oxidation annealing". When the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer 140. When the oxidation annealing is performed, oxygen is supplied from the second insulating layer 120 and the gate insulating layer 150 to the oxide semiconductor layer 140, and the oxygen defects are repaired.

[0098] In step S1070, a gate electrode 160 having a predetermined pattern is formed on the gate insulating layer 150 (see Figure 8 ). The gate electrode 160 is formed by sputtering or atomic layer deposition, and the gate electrode 160 is patterned using photolithography.

[0099] In step S1080, a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see Figure 8 ). The source region S and the drain region D are formed by ion implantation. Specifically, the gate electrode 160 is used as a mask to implant impurities into the oxide semiconductor layer 140 via the gate insulating layer 150. As the impurities to be implanted, for example, argon (Ar), phosphorus (P) or boron (B) can be used. In the source region S and the drain region D that do not overlap with the gate electrode 160, oxygen defects are generated due to the ion implantation, and hydrogen is captured by the generated oxygen defects. As a result, the resistance of the source region S and the drain region D is reduced. On the other hand, in the channel region overlapping with the gate electrode 160, since no impurities are implanted, no oxygen defects are generated, and the resistance of the channel region CH is not reduced.

[0100] It should be noted that in the thin film transistor 10 , impurities are injected into the oxide semiconductor layer 140 through the gate insulating layer 150 , and thus the gate insulating layer 150 may contain impurities such as argon (Ar), phosphorus (P), or boron (B).

[0101] In step S1090, a third insulating layer 170 and a fourth insulating layer 180 are formed on the gate insulating layer 150 and the gate electrode 160 (see Fig. 9 ). The third insulating layer 170 and the fourth insulating layer 180 are formed by CVD. For example, silicon oxide and silicon nitride are formed as the third insulating layer 170 and the fourth insulating layer 180, respectively. The thickness of the third insulating layer 170 is greater than 50 nm and less than 500 nm. The thickness of the fourth insulating layer 180 is also greater than 50 nm and less than 500 nm.

[0102] In step S1100, openings 171 and 173 are formed in the gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 (see Fig.10 ). By forming the openings 171 and 173 , the source region S and the drain region D of the oxide semiconductor layer 140 are exposed.

[0103] In step S1110, the source electrode 201 is formed on the fourth insulating layer 180 and inside the opening 171, and the drain electrode 203 is formed on the fourth insulating layer 180 and inside the opening 173. The source electrode 201 and the drain electrode 203 are formed as the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning a conductive film after film formation. Through the above steps, a Figure 1 The thin film transistor 10 is shown.

[0104] As mentioned above, the manufacturing method of the thin film transistor 10 is described, but the manufacturing method of the thin film transistor 10 is not limited thereto.

[0105] In the thin film transistor 10 according to the present embodiment, the oxide semiconductor layer 140 includes a Poly-OS film having a novel crystal structure. The thin film transistor 10 including the Poly-OS film having such a novel crystal structure has improved electrical characteristics, as will be described in detail later. For example, the field effect mobility of the thin film transistor 10 is improved.

[0106] <Third embodiment>

[0107] Reference Fig.11 An electronic device according to an embodiment of the present invention will be described.

[0108] Fig.11 1 is a schematic diagram showing an electronic device 1000 according to an embodiment of the present invention. Fig.11 , a smartphone is shown as an example of the electronic device 1000. The electronic device 1000 includes a display device 1100 with curved sides. The display device 1100 includes a plurality of pixels for displaying an image, and the plurality of pixels are controlled by a pixel circuit and a driving circuit. The pixel circuit and the driving circuit include the thin film transistor 10 described in the second embodiment. Since the thin film transistor 10 has a high field effect mobility, the responsiveness of the pixel circuit and the driving circuit can be improved, and as a result, the performance of the electronic device 1000 can be improved.

[0109] It should be noted that the electronic device 1000 involved in this embodiment is not limited to a smartphone. The electronic device 1000 also includes, for example, an electronic device with a display device such as a clock, a tablet computer, a laptop computer, a car navigation system, or a television. In addition, the thin film transistor 10 described in the first embodiment can be applied to all electronic devices, regardless of whether they have a display device or not.

[0110] Example

[0111] Based on the produced samples, the Poly-OS film is described in further detail.

[0112] [1. Sample preparation]

[0113] The samples described below use a sputtering process and an OS annealing process to make an oxide semiconductor film on a substrate. In the sputtering process, both the embodiment and the comparative example use a sputtering target in which the atomic ratio of indium is 70% relative to all the metal elements contained in the sintered body. In any sample, the chemical composition of the oxide semiconductor film after the OS annealing process is the same as the chemical composition of the sputtering target. In addition, in the OS annealing process, both the embodiment and the comparative example control the reaching temperature between 350°C and 450°C.

[0114] [Example 1]

[0115] A silicon oxide film (SiO x ) as a base film. The silicon oxide film is formed by a plasma CVD method using monosilane (SiH4) gas and nitrous oxide (N2O) gas. The flow rate of the monosilane gas is suppressed in a manner that reduces the hydrogen concentration in the silicon oxide film. Specifically, the gas flow ratio of the monosilane gas to the nitrous oxide gas in the formation of the silicon oxide film is SiH4:N2O=1:100.

[0116] An oxide semiconductor film is formed on the base film to a thickness of 30 nm by a sputtering process, and then an OS annealing process is performed on the formed oxide semiconductor film in an air atmosphere.

[0117] [Example 2]

[0118] A laminated film (AlO x / SiO x ) as a base film. The silicon oxide film is formed by a plasma CVD method using monosilane (SiH4) gas and nitrous oxide (N2O) gas. For the monosilane gas, the flow rate of the monosilane gas is suppressed in a manner to reduce the hydrogen concentration in the silicon oxide film. Specifically, the gas flow ratio of the monosilane gas to the nitrous oxide gas in the formation of the silicon oxide film is SiH4:N2O=1:100. Aluminum oxide is formed by a sputtering method using an aluminum (Al) target.

[0119] An oxide semiconductor film is formed on the base film to a thickness of 30 nm by a sputtering process, and then an OS annealing process is performed on the formed oxide semiconductor film in an air atmosphere.

[0120] [Example 3-1], [Example 3-2]

[0121] A laminated film (AlO x / SiO x ) as a base film. The silicon oxide film is formed by a plasma CVD method using monosilane (SiH4) gas and nitrous oxide (N2O) gas. It should be noted that, for the monosilane gas, the flow rate of the monosilane gas is suppressed in a manner to reduce the hydrogen concentration in the silicon oxide film. Specifically, the gas flow ratio of the monosilane gas to the nitrous oxide gas in the formation of the silicon oxide film is SiH4:N2O=1:100. Aluminum oxide is formed by a sputtering method using an aluminum (Al) target.

[0122] An oxide semiconductor film with a thickness of 15 nm is formed on the base film by a sputtering process, and then an OS annealing process is performed on the formed oxide semiconductor film in an air atmosphere.

[0123] [Comparative Example 1]

[0124] A silicon oxide film (SiO x ) as a base film. The silicon oxide film is formed by a plasma CVD method using monosilane (SiH4) gas and nitrous oxide (N2O) gas. It should be noted that the monosilane gas uses a normal gas flow condition. Specifically, the gas flow ratio of monosilane gas to nitrous oxide gas in the formation of the silicon oxide film is SiH4:N2O=1:30.

[0125] An oxide semiconductor film is formed on the base film to a thickness of 30 nm by a sputtering process, and then an OS annealing process is performed on the formed oxide semiconductor film in an air atmosphere.

[0126] [Comparative Example 2]

[0127] A laminated film (AlO x / SiO x ) as a base film. The silicon oxide film is formed by a plasma CVD method using monosilane (SiH4) gas and nitrous oxide (N2O) gas. It should be noted that the monosilane gas uses a normal gas flow condition. Specifically, the gas flow ratio of monosilane gas to nitrous oxide gas in the formation of the silicon oxide film is SiH4:N2O=1:30. Aluminum oxide is formed by a sputtering method using an aluminum (Al) target.

[0128] An oxide semiconductor film is formed on the base film to a thickness of 30 nm by a sputtering process, and then an OS annealing process is performed on the formed oxide semiconductor film in an air atmosphere.

[0129] The differences among the samples produced are summarized in Table 1.

[0130] [Table 1]

[0131]

[0132] [2. Crystal structure analysis based on XRD method]

[0133] The crystal structure of the oxide semiconductor film of each sample was analyzed by XRD. The crystal structure analysis by XRD was performed under the conditions shown in Table 2 using a SmartLab device (manufactured by Rigaku Corporation).

[0134] [Table 2]

[0135]

[0136] In order to confirm the existence of the crystal structure based on the measurement results, the peak was smoothed using an analysis program (JADE6), and the crystal structure file of the bixbyite structure of ICSD (Inorganic Crystal Structure Database: Chemical Information Association) 14388 was used to identify the crystal phase. Then, the broad pattern that could not be assigned an index was judged to be derived from the background of the substrate and removed by three-dimensional approximation.

[0137] Figure 12 to Figure 17 They are respectively the XRD diffraction patterns of Examples 1 to 3-2 and Comparative Examples 1 and 2. Any oxide semiconductor film has a peak at a diffraction angle (2θ) near 31°. The diffraction angle near 31° belongs to the (222) plane of the bixbyite structure, and it can be seen that any oxide semiconductor film has a crystal structure of the bixbyite structure.

[0138] like Fig.12 As shown in FIG. 1 , in the oxide semiconductor film of Example 1, no clear peaks were confirmed except for the diffraction angle near 31°. Fig.13 As shown in FIG. 1 , in the oxide semiconductor film of Example 2, in addition to the diffraction angle near 31°, there is a peak at the diffraction angle near 52°. The diffraction angle near 52° is attributed to the (440) plane of the bixbyite structure. Fig.14 As shown in FIG. 1 , in the oxide semiconductor film of Example 3-1, in addition to the diffraction angle near 31°, there is a peak at the diffraction angle near 44°. The diffraction angle near 44° is attributed to the (422) plane of the bixbyite structure. Fig.15 As shown, in the oxide semiconductor film of Example 3-2, in addition to the diffraction angle near 31°, there is a peak at the diffraction angle near 52°.

[0139] like Fig.16 As shown in FIG. 1 , in the oxide semiconductor film of Comparative Example 1, in addition to the diffraction angle near 31°, there is a peak at the diffraction angle near 44°. Fig.17 As shown, in the oxide semiconductor film of Comparative Example 2, in addition to the diffraction angle near 31°, there is also a peak at the diffraction angle near 44°.

[0140] Will Figure 12 to Figure 17 The results of the XRD diffraction pattern are summarized as shown in Table 3. In Table 2, the peak intensity of the (222) plane relative to the peak intensity of the (422) plane is shown as the peak intensity ratio. In addition, Table 2 also shows the crystallite diameter calculated from the XRD diffraction pattern. The crystallite diameter is calculated based on the half-value width of the peak (corresponding to the (222) plane) at a diffraction angle of about 31.2° that can be confirmed in any oxide semiconductor film.

[0141] [Table 3]

[0142]

[0143] As can be seen from Table 3, the peak intensity of the (222) surface of the oxide semiconductor films of Examples 1 to 3-2 is smaller than that of the oxide semiconductors of Comparative Examples 1 and 2. Example 1 and Comparative Example 1 differ only in the gas flow rate of monosilane gas in the film formation conditions of the silicon oxide film as the base film, but the peak intensity of the (222) surface of Example 1 is less than 1 / 2 of the peak intensity of the (222) surface of Comparative Example 1. Similarly, Example 2 and Comparative Example 2 differ only in the gas flow rate of monosilane gas in the film formation conditions of the silicon oxide film as the base film, but the peak intensity of the (222) surface of Example 2 is less than 1 / 2 of the peak intensity of the (222) surface of Comparative Example 2.

[0144] In addition, in Comparative Examples 1 and 2, the peak of the (422) plane was observed, but in Examples 1, 2, and 3-2, the peak of the (422) plane was not observed. In Example 3-1, the peak of the (422) plane was observed. However, in Example 3-1, the peak intensity ratio was smaller than that in Comparative Examples 1 and 2. The peak intensity ratios of Comparative Examples 1 and 2 were higher than 3.0, while the peak intensity ratio of Example 3-1 was less than 3.0.

[0145] In Examples 1 and 2, where the film thickness of the oxide semiconductor film is 30 nm, the crystallite diameter is 20 nm or more. In addition, in Examples 3-1 and 3-2, where the film thickness of the oxide semiconductor is 15 nm, the crystallite diameter is 1.2 times the film thickness of the oxide semiconductor. That is, the crystallite diameter of the oxide semiconductor film of Examples 3-1 and 3-2 is 0.95 times or more of the oxide semiconductor film, which is approximately the same as the film thickness of the oxide semiconductor film.

[0146] [3. Electrical characteristics]

[0147] Thin film transistors including the oxide semiconductor films of the above-described Examples and Comparative Examples were fabricated using the manufacturing method described in the second embodiment, and their electrical characteristics were measured. Table 4 shows the field effect mobility calculated from the electrical characteristics.

[0148] [Table 4]

[0149] Sample name Field Effect Mobility Example 1 <![CDATA[33.0cm 2 / Vs]]> Example 2 <![CDATA[58.6cm 2 / Vs]]> Example 3-1 <![CDATA[39.1cm 2 / Vs]]> Example 3-2 <![CDATA[41.3cm 2 / Vs]]> Comparative Example 1 <![CDATA[20.7cm 2 / Vs]]> Comparative Example 2 <![CDATA[33.5cm 2 / Vs]]>

[0150] As shown in Table 4, in any of the thin film transistors of the embodiments, a higher than 30 cm 2 / Vs field effect mobility. In addition, Example 1 and Comparative Example 1 differ only in the gas flow rate of monosilane gas in the film forming conditions of the silicon oxide film as the base film, but the field effect mobility of the thin film transistor of Example 1 is greater than the field effect mobility of the thin film transistor of Comparative Example 1. Similarly, Example 2 and Comparative Example 2 differ only in the gas flow rate of monosilane gas in the film forming conditions of the silicon oxide film as the base film, but the field effect mobility of the thin film transistor of Example 2 is greater than the field effect mobility of the thin film transistor of Comparative Example 2.

[0151] From this result, it can be seen that when a Poly-OS film is used as a channel of a thin film transistor, the field effect mobility does not decrease but increases.

[0152] As embodiments of the present invention, the embodiments described above can be appropriately combined for implementation as long as they do not contradict each other. In addition, solutions obtained by adding, deleting or designing components or by adding, omitting or changing conditions of processes based on the embodiments by those skilled in the art are also included in the scope of the present invention as long as they have the gist of the present invention.

[0153] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they are of course understood to be the effects brought about by the present invention.

[0154] Description of Reference Numerals

[0155] 10: thin film transistor, 100: substrate, 105: light shielding layer, 110: first insulating layer, 120: second insulating layer, 140: oxide semiconductor layer, 145: oxide semiconductor film, 150: gate insulating layer, 160: gate electrode, 170: third insulating layer, 171: opening, 173: opening, 180: fourth insulating layer, 200: source / drain electrode, 201: source electrode, 203: drain electrode, 1000: electronic device, 1100: display device

Claims

1. An oxide semiconductor film having a polycrystalline structure and provided on a substrate, The crystal structure of the oxide semiconductor film is a bixbyite structure, In an out-of-plane XRD diffraction pattern using Cu—Kα radiation, a ratio of a peak intensity of a (222) plane of the oxide semiconductor film to a peak intensity of a (422) plane is 3.0 or less.

2. The oxide semiconductor film according to claim 1, wherein The crystallite diameter calculated from the peak of the (222) plane is 10 nm or more.

3. The oxide semiconductor film according to claim 1, wherein The crystallite diameter calculated from the peak of the (222) plane is greater than or equal to 0.95 times the film thickness of the oxide semiconductor film.

4. The oxide semiconductor film according to claim 3, wherein The oxide semiconductor film has a thickness of 20 nm or less.

5. The oxide semiconductor film according to claim 1, wherein The oxide semiconductor film contains indium and at least one metal element. The ratio of the indium to the indium and the at least one metal element is 50% or more.

6. The oxide semiconductor film according to claim 1, wherein The oxide semiconductor film is provided in contact with the oxide insulating film, The oxide insulating film includes one or more metal elements selected from aluminum, magnesium, calcium, scandium, gallium, germanium, strontium, nickel, tantalum, yttrium, zirconium, barium, hafnium, cobalt and lanthanide elements.

7. The oxide semiconductor film according to claim 6, wherein The oxide insulating film includes aluminum oxide.

8. An oxide semiconductor film having a polycrystalline structure and provided on a substrate, The crystal structure of the oxide semiconductor film is a bixbyite structure, In the out-of-plane XRD diffraction pattern using Cu—Kα radiation, the peak intensity of the (422) plane of the oxide semiconductor film was not observed.

9. The oxide semiconductor film according to claim 8, wherein In the XRD diffraction pattern, the crystallite diameter calculated from the peak of the (222) plane is 15 nm or more.

10. The oxide semiconductor film according to claim 8, wherein The oxide semiconductor film contains indium and at least one metal element. The ratio of the indium to the indium and the at least one metal element is 50% or more.

11. The oxide semiconductor film according to claim 8, wherein The oxide semiconductor film is provided in contact with the oxide insulating film, The oxide insulating film includes one or more metal elements selected from aluminum, magnesium, calcium, scandium, gallium, germanium, strontium, nickel, tantalum, yttrium, zirconium, barium, hafnium, cobalt and lanthanide elements.

12. The oxide semiconductor film according to claim 11, wherein The oxide insulating film includes aluminum oxide.

13. A thin film transistor comprising: An oxide semiconductor layer comprising the oxide semiconductor film according to any one of claims 1 to 12; a gate electrode disposed on the oxide semiconductor layer; and A gate insulating layer is provided between the oxide semiconductor layer and the gate electrode.

14. An electronic device comprising the thin film transistor according to claim 13.

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