Chip power-off detection method and device and electronic equipment

Abstract

The invention provides a chip power-off detection method and device and electronic equipment. The method comprises the steps that a power supply voltage corresponding to each target moment of a chip is collected through an analog-to-digital converter detection port of the chip, and the time interval between every two target moments is a preset time interval; calculating an absolute value of a difference value of the power supply voltages corresponding to the two adjacent target moments, and calculating a ratio of the absolute value of the difference value to a preset time interval to obtain a voltage change rate; under the condition that the voltage change rate is larger than a preset threshold value, it is determined that the chip has a power-off risk, chip data are backed up, the power-off risk indicates that the chip has the power-off risk, and the chip data comprise all data in the chip. Through the method and the device, the problem that whether the chip is powered off cannot be detected under the condition that a voltage reduction interruption function is not integrated in the chip in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the technical field of chip power-off detection, and in particular to a chip power-off detection method, device, computer-readable storage medium and electronic device. Background Art

[0002] In the current market, chip power failure detection relies on the integrated voltage reduction interrupt function inside the chip. Since some chips do not integrate the voltage reduction interrupt function internally in order to reduce costs, this results in the product being unable to detect whether there is a power failure after replacing the main control chip to reduce costs, and thus unable to implement the power failure instant storage function. This defect is particularly obvious in certain regions or harsh environments. Large fluctuations in the chip terminal voltage may cause the system to restart or power off, resulting in the loss of important data. Summary of the invention

[0003] The main purpose of the present application is to provide a chip power-off detection method, device, computer-readable storage medium and electronic device, so as to at least solve the problem in the prior art that when the step-down interrupt function is not integrated inside the chip, it is impossible to detect whether the chip is powered off.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a chip power-off detection method is provided, comprising: collecting the power supply voltage corresponding to each target moment of the chip through the chip's analog-to-digital converter detection port, wherein the time interval between each two target moments is a predetermined time interval; calculating the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments, and calculating the ratio of the absolute value of the difference to the predetermined time interval to obtain a voltage change rate; when the voltage change rate is greater than a preset threshold, determining that the chip is at risk of power off and backing up chip data, wherein the power off risk indicates that the chip is at risk of power off, and the chip data includes all data in the chip.

[0005] Optionally, after collecting the power supply voltage corresponding to each target moment of the chip through the chip's analog-to-digital converter detection port, the method further includes: storing each of the target moments and the corresponding power supply voltage in a data storage area of ​​the chip; when the number of the power supply voltages stored in the data storage area is greater than or equal to a predetermined number, predicting a power-off moment based on the power supply voltages stored in the data storage area and the target moments corresponding to the power supply voltages, wherein the power-off moment indicates the moment when the chip is powered off; and backing up the chip data before the power-off moment.

[0006] Optionally, the method also includes: when the number of the power supply voltages stored in the data storage area is less than the predetermined number, determining whether the chip is at risk of power outage based on the current voltage change rate, wherein the current voltage change rate represents the voltage change rate corresponding to the current moment; and backing up the chip data when the chip is at risk of power outage.

[0007] Optionally, predicting the power-off moment based on the power supply voltage stored in the data storage area and the target moment corresponding to the power supply voltage includes: performing regression analysis on the power supply voltage and the target moment corresponding to the power supply voltage using a regression analysis method to obtain a correlation between the power supply voltage and the target moment; and determining, based on the correlation, the target moment when the power supply voltage is disconnected the most times as the power-off moment.

[0008] Optionally, the power supply voltage corresponding to each target moment of the chip is collected through the analog-to-digital converter detection port of the chip, including: obtaining the power pin identifier of the chip, collecting the voltage of the pin corresponding to the power pin identifier, and obtaining the power supply voltage corresponding to each target moment, wherein the power pin identifier is the identifier corresponding to the power pin.

[0009] Optionally, after determining that the chip is at risk of power failure, the method further includes: obtaining the current time, storing the voltage change rate and the current time in a cloud database to predict the power failure time of the chip, wherein the power failure time indicates the time when the chip is powered off.

[0010] Optionally, after determining that the chip is at risk of power outage and backing up the chip data, the method also includes obtaining a standard voltage, a voltage fluctuation range and a write time, wherein the write time indicates the time when the power supply voltage is written to the analog-to-digital converter detection port; determining a multiplication coefficient based on the voltage fluctuation range and the write time, calculating the product of the multiplication coefficient and the standard voltage to obtain a voltage adjustment range, and adjusting the preset threshold based on the voltage adjustment range.

[0011] According to another aspect of the present application, a chip power-off detection device is provided, comprising: an acquisition unit, for acquiring a power pin identifier of a chip, and acquiring the voltage of a pin corresponding to the power pin identifier through an analog-to-digital converter detection port of the chip at a predetermined time interval to obtain a power voltage corresponding to each target moment, wherein the power pin identifier is an identifier corresponding to the power pin, and the time interval between each two target moments is the predetermined time interval; a calculation unit, for calculating the absolute value of the difference between the power voltages corresponding to two adjacent target moments, and calculating the ratio of the absolute value of the difference to the predetermined time interval to obtain a voltage change rate; a determination unit, for determining, when the voltage change rate is greater than a preset threshold, that the chip is at risk of power failure and backing up chip data, wherein the power failure risk indicates that the chip is at risk of power failure, and the chip data includes all data in the chip.

[0012] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute any one of the chip power-off detection methods.

[0013] According to another aspect of the present application, an electronic device is provided, comprising: one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include a method for executing any one of the chip power-off detection methods.

[0014] The technical solution of the present application is applied, and the power supply voltage corresponding to each target moment of the chip is collected through the analog-to-digital converter detection port of the chip, and the time interval between each two target moments is a predetermined time interval; the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments is calculated, and the ratio of the absolute value of the difference to the predetermined time interval is calculated to obtain the voltage change rate; when the voltage change rate is greater than the preset threshold, it is determined that the chip has a power-off risk and the chip data is backed up, and the power-off risk indicates that the chip has a power-off risk, and the chip data includes all the data in the chip. In this way, the power supply voltage of the chip is collected by the analog-to-digital converter to further determine whether the chip will be powered off, and the purpose of predicting chip power off and backing up data is achieved when the interrupt function is not integrated inside the chip. Therefore, it can solve the problem in the prior art that it is impossible to detect whether the chip is powered off when the step-down interrupt function is not integrated inside the chip, and achieve the effect of timely judging the chip power-off risk and saving data. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 A schematic flow chart of a chip power failure detection method provided in an embodiment of the present application is shown;

[0017] Figure 2 A schematic flow chart of a specific chip power failure detection method provided in an embodiment of the present application is shown;

[0018] Figure 3 A structural block diagram of a chip power-off detection device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0020] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0021] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] For the convenience of description, some nouns or terms involved in the embodiments of the present application are explained below:

[0023] AD sampling: The process of converting the collected electrical signal into discrete digital quantities is called AD sampling.

[0024] As introduced in the background technology, some chips in the prior art do not integrate the voltage reduction interrupt function internally in order to reduce costs. This results in the product being unable to detect whether there is a power outage after the main control chip is replaced to reduce costs, and thus being unable to implement the power-off instant storage function. In order to solve the problem of being unable to determine power outages when the voltage reduction interrupt function is not integrated, the embodiments of the present application provide a chip power-off detection method, device, computer-readable storage medium and electronic device.

[0025] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0026] In this embodiment, a method for detecting power failure of a chip running on a mobile terminal, a computer terminal or a similar computing device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0027] Figure 1 FIG. 1 is a flow chart of a method for detecting a power failure of a chip according to an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0028] Step S201, collecting the power supply voltage corresponding to each target moment of the chip through the analog-to-digital converter detection port of the chip, wherein the time interval between each two target moments is a predetermined time interval;

[0029] Specifically, in order to solve the above-mentioned problems existing in the prior art, the present application utilizes the AD sampling function commonly possessed by all chips. AD sampling is the process of converting the collected electrical signals into discrete digital quantities. The chip terminal voltage is monitored in real time through the AD port. Once a power outage is detected, the storage operation can be triggered immediately to ensure the safety and integrity of the data. In this way, without adding additional costs, the chip terminal voltage is monitored in real time through the AD port. The AD port inside the chip is used, and there is no need for an external dedicated monitoring chip, which reduces the system cost; different sampling frequencies and trend thresholds can also be configured through software to adapt to different application scenarios. The Chinese name of AD is the above-mentioned analog-to-digital converter. After the system is powered on, AD continuously collects voltage data in a cycle within a set time period, and collects voltage data at each target moment within the set time period according to a predetermined time interval. The predetermined time interval can be determined according to actual conditions.

[0030] Step S202, calculating the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments, and calculating the ratio of the absolute value of the difference to the predetermined time interval to obtain a voltage change rate;

[0031] Specifically, the ratio of the absolute value of the difference between the power supply voltages at two adjacent target moments to the above-mentioned predetermined time interval is calculated to obtain the voltage change rate. The voltage change rate represents the change in voltage within a predetermined time interval. The voltage change rate can be used to predict whether the voltage may suddenly drop. For example, a sudden drop from normal voltage indicates that there may be a power outage. In this case, the chip data needs to be stored in time to prevent data loss caused by sudden power outage.

[0032] Step S203, when the voltage change rate is greater than a preset threshold, determine that the chip has a power outage risk and back up chip data, wherein the power outage risk indicates that the chip has a power outage risk, and the chip data includes all data in the chip.

[0033] Specifically, it is determined whether the voltage change rate reaches a preset threshold. If it reaches the preset threshold, that is, it is greater than the preset threshold, the power-off storage sequence is immediately started to back up the chip data. If a power-off trend is detected, the voltage trend data is immediately uploaded to the cloud database and the current time is recorded. The power-off trend can be determined by the voltage average calculated at the first moment and the voltage average calculated at the second moment. If there is an obvious voltage drop trend, multiple calculations are required to determine the power-off trend in actual application.

[0034] Through this embodiment, the power supply voltage corresponding to each target moment of the chip is collected through the chip's analog-to-digital converter detection port, and the time interval between each two target moments is a predetermined time interval; the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments is calculated, and the ratio of the absolute value of the difference to the predetermined time interval is calculated to obtain the voltage change rate; when the voltage change rate is greater than the preset threshold, it is determined that the chip has a power-off risk and the chip data is backed up, and the power-off risk indicates that the chip has a power-off risk, and the chip data includes all the data in the chip. In this way, the power supply voltage of the chip is collected by the analog-to-digital converter to further determine whether the chip will be powered off, and the purpose of predicting chip power off and backing up data is achieved when the interrupt function is not integrated inside the chip. Therefore, it can solve the problem in the prior art that it is impossible to detect whether the chip is powered off when the step-down interrupt function is not integrated inside the chip, and achieve the effect of timely judging the chip power-off risk and saving data.

[0035] In the specific implementation process, after the above step S201 collects the power supply voltage corresponding to each target moment of the chip through the chip's analog-to-digital converter detection port, the method further includes the following steps: step S204: storing each target moment and the corresponding power supply voltage in the data storage area of ​​the chip; step S205: when the number of the power supply voltages stored in the data storage area is greater than or equal to a predetermined number, predicting the power-off moment according to the power supply voltages stored in the data storage area and the target moment corresponding to the power supply voltage, wherein the power-off moment indicates the moment when the chip is powered off; step S206: backing up the chip data before the power-off moment. The method performs power-off analysis and prediction on a large amount of historical data through the above steps, so that the power-off trend can be analyzed through historical data and power-off and storage processing can be performed in a timely manner.

[0036] Specifically, the voltage data is continuously collected in a loop within a set time period and the corresponding timestamp is added. At the same time, a timer is set to regularly store the voltage data with the timestamp in the data storage area in the memory. When the amount of data in the data storage area can meet the prediction of future voltage change trends, a data analysis algorithm is used to predict possible power outages, and historical data is analyzed in depth to explore the trend and pattern of voltage drop, that is, the relationship between the power supply voltage and the target time corresponding to the power supply voltage, predict the power outage time, and start the power outage storage program in advance before the power outage time to prevent the data from being completely written when the data volume is large and the power outage speed is too fast. The statistical analysis methods that can be used can be mean, standard deviation, regression analysis, etc. to predict future voltage changes.

[0037] In some optional implementations, the method further includes the following steps: Step S207: when the number of the power supply voltages stored in the data storage area is less than the predetermined number, determining whether the chip has the power outage risk according to the current voltage change rate, wherein the current voltage change rate represents the voltage change rate corresponding to the current moment; Step S208: backing up the chip data when the chip has the power outage risk. In the case where the number of power supply voltages is small, this method directly determines whether there is a power outage risk according to the voltage change rate, so that data can be backed up in a timely manner.

[0038] During the specific implementation process, when the amount of data in the data storage area is insufficient to meet the needs of predicting future voltage changes, it is determined whether the current voltage rate reaches the set threshold. If the threshold is reached, the power-off storage sequence is immediately started to back up the chip data.

[0039] In some optional implementations, the above step S205 predicts the power-off time according to the power supply voltage stored in the data storage area and the target time corresponding to the power supply voltage, which can be achieved by the following steps: Step S2051: Using regression analysis to perform regression analysis on the power supply voltage and the target time corresponding to the power supply voltage, and obtain the correlation between the power supply voltage and the target time; Step S2052: According to the correlation, determine the target time when the power supply voltage is disconnected the most times as the power-off time. The method uses the data analysis method to predict the power-off time through the above steps, so that data backup storage can be performed in time according to historical power-off habits, etc.

[0040] Specifically, the regression analysis method can use a univariate regression analysis method to determine the correlation between the power supply voltage and the corresponding target time, and the correlation can be expressed by a univariate regression equation. The application example is as follows: a product is fixedly maintained every Saturday, and the power needs to be cut off once a month, or a user is used to cutting off the power of a product after 8 pm, then according to the habit, the backup chip data can be saved in advance at a specific time. In other words, from the above correlation, it can be determined that 8 pm is the power-off time, and the data can be backed up in advance at 7:55 pm.

[0041] In some other optional implementations, the above step S201 collects the power supply voltage corresponding to each target moment of the chip through the chip's analog-to-digital converter detection port, which can be implemented by the following steps: obtaining the chip's power pin identifier, collecting the voltage of the pin corresponding to the power pin identifier, and obtaining the power supply voltage corresponding to each target moment, wherein the power pin identifier is the identifier corresponding to the power pin. The method collects the power supply voltage through the above power pin, so that the power supply voltage can be accurately collected.

[0042] In the specific implementation process, after the system is powered on, AD detection initialization and initial time initialization are performed, the power pin identification of the connected chip is clearly identified, and the voltage of the pin corresponding to the power pin identification is collected to obtain the power supply voltage.

[0043] In order to save historical power supply data, after determining that the chip is at risk of power failure, the method further includes the following steps: Step S209: obtaining the current time, storing the voltage change rate and the current time in a cloud database to predict the power failure time of the chip, wherein the power failure time indicates the time when the chip is powered off. The method stores the voltage data and the corresponding current time through the above steps, so that the voltage change trend can be analyzed and predicted based on the stored historical data, so as to perform power failure backup and storage in time.

[0044] In the specific implementation process, the voltage data is continuously collected in a set cycle and a timestamp is added, which is the corresponding current moment. At the same time, a timer is set to regularly store the voltage data with timestamps in the memory or cloud database. In this way, after the amount of stored power supply voltage data reaches a predetermined amount, the power supply voltage change trend can be analyzed based on the stored data to predict the power outage time.

[0045] In some optional implementations, after determining that the chip is at risk of power failure and backing up chip data, the method further includes the following steps: obtaining a standard voltage, a voltage fluctuation range, and a write time, wherein the write time indicates the time when the power supply voltage is written to the detection port of the analog-to-digital converter; determining a multiplication coefficient based on the voltage fluctuation range and the write time, calculating the product of the multiplication coefficient and the standard voltage to obtain a voltage adjustment range, and adjusting the preset threshold value based on the voltage adjustment range. The method adjusts the voltage range through the above steps, so that the preset threshold value can be adjusted to adapt to different application scenarios.

[0046] Specifically, according to the actual operation of the whole machine, the sampling parameters, power-off thresholds, etc. are appropriately adjusted to ensure that the power-off situation can be accurately identified and reported in time. Adjust the parameters and thresholds according to the actual situation. For example, the voltage level is 220V for civil electricity and 380V for industrial electricity. Most fan products are 24V / 12V input electricity. The sampling parameters and power-off thresholds corresponding to different voltages are different. When the standard voltage is 220V, it is necessary to formulate the parameters and accuracy of the same type of sampling according to 220V, and determine the size of the power-off threshold according to the amount of data to be written. The amount of data that needs to be written may be large. According to the previous experimental experience, the writing time needs to account for 60% of the overall power-off time, the voltage fluctuation range is 5%, and the voltage at which the chip cannot work is the lowest voltage of 10%. The product coefficient can be (70%~95%), so the voltage adjustment range can be 220V*(70%~95%), and further select a suitable power-off threshold while ensuring the error.

[0047] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the chip power-off detection method of the present application will be described in detail below in conjunction with specific embodiments.

[0048] This embodiment relates to a specific chip power failure detection method, such as Figure 2 As shown, the following steps are included:

[0049] Step S1: (chip) power on;

[0050] Step S2: AD detection initialization, voltage threshold initialization, and timestamp initialization;

[0051] Step S3: Set a period to collect voltage data and timestamps, and store them in a data buffer in the memory;

[0052] Step S4: Calculate the ratio of the voltage difference between two adjacent time points to the time interval to obtain the voltage drop rate;

[0053] Step S5: Determine whether the amount of data in the cloud database has reached a certain amount. If yes, execute step S6; if no, execute step S9;

[0054] Step S6: predicting future voltage changes using statistical analysis methods;

[0055] Step S7: predict whether power outage is likely, if not, proceed to step S6, if yes, proceed to step S8;

[0056] Step S8: starting the power-off storage module;

[0057] Step S9: Determine whether there is a power outage trend. If yes, execute step S8. If not, upload the current voltage trend data to the cloud.

[0058] The embodiment of the present application also provides a chip power-off detection device. It should be noted that the chip power-off detection device of the embodiment of the present application can be used to execute the chip power-off detection device provided in the embodiment of the present application. The device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0059] The following is an introduction to the chip power failure detection device provided in the embodiment of the present application.

[0060] Figure 3 Schematic diagram of a chip power failure detection device according to an embodiment of the present application. Figure 3 As shown, the device comprises:

[0061] The acquisition unit 10 is used to obtain the power pin identifier of the chip, and collect the voltage of the pin corresponding to the power pin identifier through the analog-to-digital converter detection port of the chip at a predetermined time interval to obtain the power voltage corresponding to each target moment, wherein the power pin identifier is the identifier corresponding to the power pin, and the time interval between each two target moments is the predetermined time interval;

[0062] Specifically, in order to solve the above-mentioned problems existing in the prior art, the present application utilizes the AD sampling function commonly possessed by all chips. AD sampling is the process of converting the collected electrical signals into discrete digital quantities. The chip terminal voltage is monitored in real time through the AD port. Once a power outage is detected, the storage operation can be triggered immediately to ensure the safety and integrity of the data. In this way, without adding additional costs, the chip terminal voltage is monitored in real time through the AD port. The AD port inside the chip is used, and there is no need for an external dedicated monitoring chip, which reduces the system cost; different sampling frequencies and trend thresholds can also be configured through software to adapt to different application scenarios. The Chinese name of AD is the above-mentioned analog-to-digital converter. After the system is powered on, AD continuously collects voltage data in a cycle within a set time period, and collects voltage data at each target moment within the set time period according to a predetermined time interval. The predetermined time interval can be determined according to actual conditions.

[0063] The calculation unit 20 is used to calculate the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments, and calculate the ratio of the absolute value of the difference to the predetermined time interval to obtain a voltage change rate;

[0064] Specifically, the ratio of the absolute value of the difference between the power supply voltages at two adjacent target moments to the above-mentioned predetermined time interval is calculated to obtain the voltage change rate. The voltage change rate represents the change in voltage within a predetermined time interval. The voltage change rate can be used to predict whether the voltage may suddenly drop. For example, a sudden drop from normal voltage indicates that there may be a power outage. In this case, the chip data needs to be stored in time to prevent data loss caused by sudden power outage.

[0065] The determination unit 30 is used to determine that the chip has a power outage risk and back up chip data when the voltage change rate is greater than a preset threshold, wherein the power outage risk indicates that the chip has a power outage risk, and the chip data includes all data in the chip.

[0066] Specifically, it is determined whether the voltage change rate reaches a preset threshold. If it reaches the preset threshold, that is, it is greater than the preset threshold, the power-off storage sequence is immediately started to back up the chip data. If a power-off trend is detected, the voltage trend data is immediately uploaded to the cloud database and the current time is recorded. The power-off trend can be determined by the voltage average calculated at the first moment and the voltage average calculated at the second moment. If there is an obvious voltage drop trend, multiple calculations are required to determine the power-off trend in actual application.

[0067] Through this embodiment, the power supply voltage corresponding to each target moment of the chip is collected through the chip's analog-to-digital converter detection port, and the time interval between each two target moments is a predetermined time interval; the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments is calculated, and the ratio of the absolute value of the difference to the predetermined time interval is calculated to obtain the voltage change rate; when the voltage change rate is greater than the preset threshold, it is determined that the chip has a power-off risk and the chip data is backed up, and the power-off risk indicates that the chip has a power-off risk, and the chip data includes all the data in the chip. In this way, the power supply voltage of the chip is collected by the analog-to-digital converter to further determine whether the chip will be powered off, and the purpose of predicting chip power off and backing up data is achieved when the interrupt function is not integrated inside the chip. Therefore, it can solve the problem in the prior art that it is impossible to detect whether the chip is powered off when the step-down interrupt function is not integrated inside the chip, and achieve the effect of timely judging the chip power-off risk and saving data.

[0068] In the specific implementation process, the device also includes a storage unit, a prediction unit and a first backup unit. The storage unit is used to store each target moment and the corresponding power supply voltage in the data storage area of ​​the chip; the prediction unit is used to predict the power-off moment according to the power supply voltage stored in the data storage area and the target moment corresponding to the power supply voltage when the number of the power supply voltages stored in the data storage area is greater than or equal to a predetermined number, wherein the power-off moment indicates the moment when the chip is powered off; the backup unit is used to back up the chip data before the power-off moment. The device performs power-off analysis and prediction on a large amount of historical data through the above steps, so that the power-off trend can be analyzed through historical data and power-off and storage processing can be performed in time.

[0069] Specifically, the voltage data is continuously collected in a loop within a set time period and a corresponding timestamp is added. At the same time, a timer is set to regularly store the voltage data with a timestamp in the data storage area in the memory. When the amount of data in the data storage area can meet the prediction of future voltage change trends, a data analysis algorithm is used to predict possible power outages, and historical data is analyzed in depth to explore the trend and pattern of voltage drop, that is, the relationship between the power supply voltage and the target time corresponding to the power supply voltage, predict the power outage time, and start the power outage storage program in advance before the power outage time to prevent the data from being completely written when the data volume is large and the power outage speed is too fast. The statistical analysis device that can be used can be the mean, standard deviation, regression analysis, etc. to predict future voltage changes.

[0070] In some optional implementations, the device further includes a determination unit and a second backup unit, the determination unit being used to determine whether the chip has the power-off risk according to the current voltage change rate when the number of the power supply voltages stored in the data storage area is less than the predetermined number, wherein the current voltage change rate represents the voltage change rate corresponding to the current moment; and the second backup unit being used to back up the chip data when the chip has the power-off risk. When the number of power supply voltages is small, the device directly determines whether there is a power-off risk according to the voltage change rate, so that data can be backed up in a timely manner.

[0071] During the specific implementation process, when the amount of data in the data storage area is insufficient to meet the needs of predicting future voltage changes, it is determined whether the current voltage rate reaches the set threshold. If the threshold is reached, the power-off storage sequence is immediately started to back up the chip data.

[0072] In some optional implementations, the prediction unit includes an analysis module and a determination module, the analysis module is used to use a regression analysis method to perform regression analysis on the power supply voltage and the target time corresponding to the power supply voltage to obtain the correlation between the power supply voltage and the target time; the determination module is used to determine the target time when the power supply voltage is disconnected the most times as the power-off time according to the correlation. The device uses a data analysis device to predict the power-off time through the above steps, so that data backup storage can be performed in time according to historical power-off habits.

[0073] Specifically, the regression analysis method can use a univariate regression analysis device to determine the correlation between the power supply voltage and the corresponding target time, and the correlation can be expressed by a univariate regression equation. The application example is as follows: a product is fixedly maintained every Saturday, and the power needs to be cut off once a month, or a user is used to cutting off the power of a product after 8 pm, then according to the habit, the backup chip data can be saved in advance at a specific time. In other words, from the above correlation, it can be determined that 8 pm is the power-off time, and the data can be backed up in advance at 7:55 pm.

[0074] In some other optional implementations, the acquisition unit includes an acquisition module, which is used to obtain the power pin identifier of the chip, collect the voltage of the pin corresponding to the power pin identifier, and obtain the power voltage corresponding to each target moment, wherein the power pin identifier is the identifier corresponding to the power pin. The device collects the power voltage through the power pin, so that the power voltage can be accurately collected.

[0075] In the specific implementation process, after the system is powered on, AD detection initialization and initial time initialization are performed, the power pin identification of the connected chip is clearly identified, and the voltage of the pin corresponding to the power pin identification is collected to obtain the power supply voltage.

[0076] In order to save historical power supply data, the device also includes a storage unit for obtaining the current time, storing the voltage change rate and the current time in a cloud database to predict the power-off time of the chip, wherein the power-off time indicates the time when the chip is powered off. The device stores the voltage data and the corresponding current time through the above steps, so that the voltage change trend can be analyzed and predicted based on the stored historical data, so as to perform power-off backup and storage in time.

[0077] In the specific implementation process, the voltage data is continuously collected in a set cycle and a timestamp is added, which is the corresponding current moment. At the same time, a timer is set to regularly store the voltage data with timestamps in the memory or cloud database. In this way, after the amount of stored power supply voltage data reaches a predetermined amount, the power supply voltage change trend can be analyzed based on the stored data to predict the power outage time.

[0078] In some optional implementations, after determining that the chip is at risk of power failure and backing up chip data, the device further includes an acquisition unit and an adjustment unit, the acquisition unit being used to acquire the standard voltage, voltage fluctuation range, and write time, wherein the write time represents the time when the power supply voltage is written to the detection port of the analog-to-digital converter; the adjustment unit being used to determine a multiplication coefficient according to the voltage fluctuation range and the write time, calculate the product of the multiplication coefficient and the standard voltage, obtain a voltage adjustment range, and adjust the preset threshold according to the voltage adjustment range. The device adjusts the voltage range through the above steps, so that the preset threshold and the like can be adjusted to adapt to different application scenarios.

[0079] Specifically, according to the actual operation of the whole machine, the sampling parameters, power-off thresholds, etc. are appropriately adjusted to ensure that the power-off situation can be accurately identified and reported in time. Adjust the parameters and thresholds according to the actual situation. For example, the voltage level is 220V for civil electricity and 380V for industrial electricity. Most fan products are 24V / 12V input electricity. The sampling parameters and power-off thresholds corresponding to different voltages are different. When the standard voltage is 220V, it is necessary to formulate the parameters and accuracy of the same type of sampling according to 220V, and determine the size of the power-off threshold according to the amount of data to be written. The amount of data that needs to be written may be large. According to the previous experimental experience, the writing time needs to account for 60% of the overall power-off time, the voltage fluctuation range is 5%, and the voltage at which the chip cannot work is the lowest voltage of 10%. The product coefficient can be (70%~95%), so the voltage adjustment range can be 220V*(70%~95%), and further select a suitable power-off threshold while ensuring the error.

[0080] The chip power failure detection device includes a processor and a memory, and the above-mentioned acquisition unit, calculation unit and determination unit are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize corresponding functions. The above-mentioned modules are all located in the same processor; or, the above-mentioned modules are located in different processors in any combination.

[0081] The processor contains a kernel, which calls the corresponding program unit from the memory. One or more kernels can be set to detect whether the chip is powered off by adjusting kernel parameters.

[0082] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0083] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the chip power-off detection method.

[0084] Specifically, the chip power failure detection method includes:

[0085] Step S201, collecting the power supply voltage corresponding to each target moment of the chip through the analog-to-digital converter detection port of the chip, wherein the time interval between each two target moments is a predetermined time interval;

[0086] Specifically, in order to solve the above-mentioned problems existing in the prior art, the present application utilizes the AD sampling function commonly possessed by all chips. AD sampling is the process of converting the collected electrical signals into discrete digital quantities. The chip terminal voltage is monitored in real time through the AD port. Once a power outage is detected, the storage operation can be triggered immediately to ensure the safety and integrity of the data. In this way, without adding additional costs, the chip terminal voltage is monitored in real time through the AD port. The AD port inside the chip is used, and there is no need for an external dedicated monitoring chip, which reduces the system cost; different sampling frequencies and trend thresholds can also be configured through software to adapt to different application scenarios. The Chinese name of AD is the above-mentioned analog-to-digital converter. After the system is powered on, AD continuously collects voltage data in a cycle within a set time period, and collects voltage data at each target moment within the set time period according to a predetermined time interval. The predetermined time interval can be determined according to actual conditions.

[0087] Step S202, calculating the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments, and calculating the ratio of the absolute value of the difference to the predetermined time interval to obtain a voltage change rate;

[0088] Specifically, the ratio of the absolute value of the difference between the power supply voltages at two adjacent target moments to the above-mentioned predetermined time interval is calculated to obtain the voltage change rate. The voltage change rate represents the change in voltage within a predetermined time interval. The voltage change rate can be used to predict whether the voltage may suddenly drop. For example, a sudden drop from normal voltage indicates that there may be a power outage. In this case, the chip data needs to be stored in time to prevent data loss caused by sudden power outage.

[0089] Step S203, when the voltage change rate is greater than a preset threshold, determine that the chip has a power outage risk and back up chip data, wherein the power outage risk indicates that the chip has a power outage risk, and the chip data includes all data in the chip.

[0090] Specifically, it is determined whether the voltage change rate reaches a preset threshold. If it reaches the preset threshold, that is, it is greater than the preset threshold, the power-off storage sequence is immediately started to back up the chip data. If a power-off trend is detected, the voltage trend data is immediately uploaded to the cloud database and the current time is recorded. The power-off trend can be determined by the voltage average calculated at the first moment and the voltage average calculated at the second moment. If there is an obvious voltage drop trend, multiple calculations are required to determine the power-off trend in actual application.

[0091] An embodiment of the present invention provides an electronic device, including a processor, a memory, and a program stored in the memory and executable on the processor, wherein when the processor executes the program, at least the following steps are implemented:

[0092] Step S201, collecting the power supply voltage corresponding to each target moment of the chip through the analog-to-digital converter detection port of the chip, wherein the time interval between each two target moments is a predetermined time interval;

[0093] Specifically, in order to solve the above-mentioned problems existing in the prior art, the present application utilizes the AD sampling function commonly possessed by all chips. AD sampling is the process of converting the collected electrical signals into discrete digital quantities. The chip terminal voltage is monitored in real time through the AD port. Once a power outage is detected, the storage operation can be triggered immediately to ensure the safety and integrity of the data. In this way, without adding additional costs, the chip terminal voltage is monitored in real time through the AD port. The AD port inside the chip is used, and there is no need for an external dedicated monitoring chip, which reduces the system cost; different sampling frequencies and trend thresholds can also be configured through software to adapt to different application scenarios. The Chinese name of AD is the above-mentioned analog-to-digital converter. After the system is powered on, AD continuously collects voltage data in a cycle within a set time period, and collects voltage data at each target moment within the set time period according to a predetermined time interval. The predetermined time interval can be determined according to actual conditions.

[0094] Step S202, calculating the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments, and calculating the ratio of the absolute value of the difference to the predetermined time interval to obtain a voltage change rate;

[0095] Specifically, the ratio of the absolute value of the difference between the power supply voltages at two adjacent target moments to the above-mentioned predetermined time interval is calculated to obtain the voltage change rate. The voltage change rate represents the change in voltage within a predetermined time interval. The voltage change rate can be used to predict whether the voltage may suddenly drop. For example, a sudden drop from normal voltage indicates that there may be a power outage. In this case, the chip data needs to be stored in time to prevent data loss caused by sudden power outage.

[0096] Step S203, when the voltage change rate is greater than a preset threshold, determine that the chip has a power outage risk and back up chip data, wherein the power outage risk indicates that the chip has a power outage risk, and the chip data includes all data in the chip.

[0097] Specifically, it is determined whether the voltage change rate reaches a preset threshold. If it reaches the preset threshold, that is, it is greater than the preset threshold, the power-off storage sequence is immediately started to back up the chip data. If a power-off trend is detected, the voltage trend data is immediately uploaded to the cloud database and the current time is recorded. The power-off trend can be determined by the voltage average calculated at the first moment and the voltage average calculated at the second moment. If there is an obvious voltage drop trend, multiple calculations are required to determine the power-off trend in actual application.

[0098] The devices in this article can be servers, PCs, PADs, mobile phones, etc.

[0099] The present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the method described in each embodiment of the present application:

[0100] Step S201, collecting the power supply voltage corresponding to each target moment of the chip through the analog-to-digital converter detection port of the chip, wherein the time interval between each two target moments is a predetermined time interval;

[0101] Specifically, in order to solve the above-mentioned problems existing in the prior art, the present application utilizes the AD sampling function commonly possessed by all chips. AD sampling is the process of converting the collected electrical signals into discrete digital quantities. The chip terminal voltage is monitored in real time through the AD port. Once a power outage is detected, the storage operation can be triggered immediately to ensure the safety and integrity of the data. In this way, without adding additional costs, the chip terminal voltage is monitored in real time through the AD port. The AD port inside the chip is used, and there is no need for an external dedicated monitoring chip, which reduces the system cost; different sampling frequencies and trend thresholds can also be configured through software to adapt to different application scenarios. The Chinese name of AD is the above-mentioned analog-to-digital converter. After the system is powered on, AD continuously collects voltage data in a cycle within a set time period, and collects voltage data at each target moment within the set time period according to a predetermined time interval. The predetermined time interval can be determined according to actual conditions.

[0102] Step S202, calculating the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments, and calculating the ratio of the absolute value of the difference to the predetermined time interval to obtain a voltage change rate;

[0103] Specifically, the ratio of the absolute value of the difference between the power supply voltages at two adjacent target moments to the above-mentioned predetermined time interval is calculated to obtain the voltage change rate. The voltage change rate represents the change in voltage within a predetermined time interval. The voltage change rate can be used to predict whether the voltage may suddenly drop. For example, a sudden drop from normal voltage indicates that there may be a power outage. In this case, the chip data needs to be stored in time to prevent data loss caused by sudden power outage.

[0104] Step S203, when the voltage change rate is greater than a preset threshold, determine that the chip has a power outage risk and back up chip data, wherein the power outage risk indicates that the chip has a power outage risk, and the chip data includes all data in the chip.

[0105] Specifically, it is determined whether the voltage change rate reaches a preset threshold. If it reaches the preset threshold, that is, it is greater than the preset threshold, the power-off storage sequence is immediately started to back up the chip data. If a power-off trend is detected, the voltage trend data is immediately uploaded to the cloud database and the current time is recorded. The power-off trend can be determined by the voltage average calculated at the first moment and the voltage average calculated at the second moment. If there is an obvious voltage drop trend, multiple calculations are required to determine the power-off trend in actual application.

[0106] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0107] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0108] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0109] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0110] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0111] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0112] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0113] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0114] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0115] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0116] 1) In the chip power-off detection method of the present application, the power supply voltage corresponding to each target moment of the chip is collected through the chip's analog-to-digital converter detection port, and the time interval between each two target moments is a predetermined time interval; the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments is calculated, and the ratio of the absolute value of the difference to the predetermined time interval is calculated to obtain the voltage change rate; when the voltage change rate is greater than a preset threshold, it is determined that the chip has a power-off risk and the chip data is backed up, and the power-off risk indicates that the chip has a power-off risk, and the chip data includes all the data in the chip. In this way, the power supply voltage of the chip is collected by the analog-to-digital converter to further determine whether the chip will be powered off, and the purpose of predicting chip power off and backing up data is achieved when the interrupt function is not integrated inside the chip. Therefore, it can solve the problem in the prior art that it is impossible to detect whether the chip is powered off when the step-down interrupt function is not integrated inside the chip, and achieve the effect of timely judging the chip power-off risk and saving data.

[0117] 2) In the chip power-off detection device of the present application, the power supply voltage corresponding to each target moment of the chip is collected through the chip's analog-to-digital converter detection port, and the time interval between each two target moments is a predetermined time interval; the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments is calculated, and the ratio of the absolute value of the difference to the predetermined time interval is calculated to obtain the voltage change rate; when the voltage change rate is greater than a preset threshold, it is determined that the chip has a power-off risk and the chip data is backed up, and the power-off risk indicates that the chip has a power-off risk, and the chip data includes all the data in the chip. In this way, the power supply voltage of the chip is collected by the analog-to-digital converter to further determine whether the chip will be powered off, and the purpose of predicting chip power off and backing up data is achieved when the interrupt function is not integrated inside the chip. Therefore, it can solve the problem in the prior art that it is impossible to detect whether the chip is powered off when the step-down interrupt function is not integrated inside the chip, and achieve the effect of timely judging the chip power-off risk and saving data.

[0118] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for detecting power failure of a chip, characterized in that: include: The power supply voltage corresponding to each target moment of the chip is collected through the detection port of the analog-to-digital converter of the chip, wherein the time interval between each two target moments is a predetermined time interval; Calculating the absolute value of the difference between the power supply voltages corresponding to two adjacent target moments, and calculating the ratio of the absolute value of the difference to the predetermined time interval to obtain a voltage change rate; When the voltage change rate is greater than a preset threshold, it is determined that the chip has a power outage risk and chip data is backed up, wherein the power outage risk indicates that the chip has a power outage risk, and the chip data includes all data in the chip.

2. The chip power failure detection method according to claim 1, characterized in that: After collecting the power supply voltage corresponding to each target moment of the chip through the analog-to-digital converter detection port of the chip, the method further includes: Storing each of the target moments and the corresponding power supply voltage in a data storage area of ​​the chip; When the number of the power supply voltages stored in the data storage area is greater than or equal to a predetermined number, predicting a power-off time according to the power supply voltages stored in the data storage area and the target time corresponding to the power supply voltages, wherein the power-off time indicates the time when the chip is powered off; The chip data is backed up before the power-off moment.

3. The chip power failure detection method according to claim 2, characterized in that: The method further comprises: In a case where the number of the power supply voltages stored in the data storage area is less than the predetermined number, determining whether the chip has the power-off risk according to a current voltage change rate, wherein the current voltage change rate represents the voltage change rate corresponding to the current moment; Backing up the chip data when the chip is at the risk of power failure.

4. The chip power failure detection method according to claim 2, characterized in that: Predicting a power-off time according to the power supply voltage stored in the data storage area and the target time corresponding to the power supply voltage includes: Using a regression analysis method to perform regression analysis on the power supply voltage and the target time corresponding to the power supply voltage, to obtain a correlation between the power supply voltage and the target time; The target time at which the power supply voltage is disconnected the most times is determined as the power-off time according to the correlation.

5. The chip power failure detection method according to claim 1, characterized in that: The power supply voltage corresponding to each target moment of the chip is collected through the analog-to-digital converter detection port of the chip, including: The power pin identifier of the chip is obtained, and the voltage of the pin corresponding to the power pin identifier is collected to obtain the power voltage corresponding to each target moment, wherein the power pin identifier is an identifier corresponding to the power pin.

6. The chip power failure detection method according to claim 1, characterized in that: After determining that the chip has a power failure risk, the method further includes: The current time is obtained, and the voltage change rate and the current time are stored in a cloud database to predict the power-off time of the chip, wherein the power-off time indicates the time when the chip is powered off.

7. The chip power failure detection method according to claim 1, characterized in that: After determining that the chip has a power failure risk and backing up chip data, the method further includes: Acquire a standard voltage, a voltage fluctuation range, and a write time, wherein the write time indicates the time when the power supply voltage is written into the detection port of the analog-to-digital converter; A multiplication coefficient is determined according to the voltage fluctuation range and the writing time, the product of the multiplication coefficient and the standard voltage is calculated to obtain a voltage adjustment range, and the preset threshold is adjusted according to the voltage adjustment range.

8. A chip power failure detection device, characterized in that: include: A collection unit, used to obtain a power pin identifier of a chip, collect the voltage of a pin corresponding to the power pin identifier through an analog-to-digital converter detection port of the chip at a predetermined time interval, and obtain a power voltage corresponding to each target moment, wherein the power pin identifier is an identifier corresponding to the power pin, and the time interval between each two target moments is the predetermined time interval; a calculation unit, configured to calculate an absolute value of a difference between the power supply voltages corresponding to two adjacent target moments, and calculate a ratio of the absolute value of the difference to the predetermined time interval to obtain a voltage change rate; A determination unit is used to determine that the chip has a power outage risk and back up chip data when the voltage change rate is greater than a preset threshold, wherein the power outage risk indicates that the chip has a power outage risk, and the chip data includes all data in the chip.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the chip power-off detection method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include a method for executing the chip power-off detection method described in any one of claims 1 to 7.

Images