Dynamic bias voltage circuit and integrated circuit

Abstract

A dynamic bias voltage circuit is provided for providing a dynamic bias voltage to at least one specific transistor in an integrated circuit, where the dynamic bias voltage circuit includes a buffer circuit, a voltage divider circuit, and a voltage follower circuit. The buffer circuit is configured to output a second voltage according to the first voltage; a voltage divider circuit coupled to the buffer circuit and configured to implement a voltage dividing function to provide a third voltage according to the second voltage and a pad voltage on a pad of the integrated circuit; and a voltage follower circuit coupled to the voltage divider circuit and configured to generate the bias voltage according to the third voltage. Correspondingly, the invention further provides an integrated circuit comprising the dynamic bias voltage circuit, and the integrated circuit can provide dynamic bias voltage for a specific transistor.

Description

Technical Field

[0001] The present invention relates to a bias voltage circuit, and more particularly, to a dynamic bias voltage circuit and an integrated circuit capable of providing a dynamic bias voltage to a specific transistor in an integrated circuit. Background Art

[0002] In the application of Universal Serial Bus USB 2.0, the voltage variation range on the signal pad of the USB integrated circuit (IC) is relatively wide, for example, the voltage variation range can be -0.4V to 4.03V, that is, the voltage on the pad varies greatly. However, the maximum withstand voltage of the gate-to-drain junction of the metal-oxide-semiconductor (MOS) transistor in some semiconductor manufacturing processes may be very small, for example, the maximum withstand voltage is limited to 1.65V (such as in the 3nm process). Therefore, if the bias voltage of the transistor is still set statically, it will be difficult to meet the reliability requirements in some scenarios. Summary of the invention

[0003] In view of this, one of the objectives of the present invention is to provide a dynamic bias voltage circuit and an integrated circuit, which can provide a dynamic bias voltage to a specific transistor in the integrated circuit.

[0004] In a first aspect, the present invention provides a dynamic bias voltage circuit for providing a dynamic bias voltage to at least one specific transistor in an integrated circuit, wherein the dynamic bias voltage circuit comprises a buffer circuit, a voltage divider circuit and a voltage follower circuit. The buffer circuit is configured to output a second voltage according to a first voltage; the voltage divider circuit is coupled to the buffer circuit and configured to implement a voltage division function to provide a third voltage according to the second voltage and a pad voltage on a pad of the integrated circuit; and the voltage follower circuit is coupled to the voltage divider circuit and configured to generate the bias voltage according to the third voltage.

[0005] In some embodiments, the buffer circuit includes: an amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the first voltage, and the second input terminal is coupled to the output terminal. In some embodiments, the output terminal of the amplifier outputs the second voltage, and the second voltage is equal to the first voltage. In other embodiments, the second voltage is generated according to the output voltage of the amplifier, and the second voltage is less than the first voltage.

[0006] In some embodiments, the dynamic bias voltage circuit further includes: a voltage generating circuit coupled to the buffer circuit and configured to generate the first voltage by dividing the power supply voltage through a resistor network; wherein the resistor network includes a first resistor and a second resistor connected in series.

[0007] In some embodiments, the voltage divider circuit includes: a third resistor and a fourth resistor connected in series, wherein the third voltage is generated at a node between the third resistor and the fourth resistor.

[0008] In some embodiments, a first end of the third resistor is coupled to the pad voltage, a second end of the third resistor is coupled to a first end of the fourth resistor, and a second end of the fourth resistor is coupled to the second voltage.

[0009] In some embodiments, the resistance relationship between the third resistor and the fourth resistor is related to the voltage variation range of the pad voltage and the maximum withstand voltage applied by a specific manufacturing process of the integrated circuit.

[0010] In some embodiments, the voltage follower circuit includes: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is coupled to a first fixed voltage, and the first terminal of the first transistor is coupled to a power supply voltage; a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to the third voltage, the first terminal of the second transistor is coupled to the second terminal of the first transistor, and the node between the first transistor and the second transistor serves as the output terminal of the voltage follower circuit; and a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to the second fixed voltage, the first terminal of the third transistor is coupled to the second terminal of the second transistor, and the second terminal of the third transistor is coupled to ground.

[0011] In some embodiments, the voltage follower circuit includes a source follower, wherein the source follower is implemented by a transistor.

[0012] In some embodiments, the dynamic bias voltage circuit further includes: a current mirror circuit configured to provide an operating current to the voltage follower circuit.

[0013] In some embodiments, the bias voltage is related to the pad voltage and the operating current.

[0014] In some embodiments, the integrated circuit includes a normal operating mode and a power saving mode; wherein, during the normal operating mode, the operating current has a first current value, and during the power saving mode, the operating current has a second current value less than the first current value.

[0015] In some embodiments, the integrated circuit complies with the Universal Serial Bus (USB) standard, and the integrated circuit includes a full-speed transmission FSTX mode and a power saving mode, during which the operating current has a first current value, and during which the operating current has a second current value less than the first current value.

[0016] In some embodiments, the at least one specific transistor is the first transistor seen from the pad of the integrated circuit or at least one transistor directly connected to the pad within the integrated circuit, and the bias voltage is coupled to the control terminal of the at least one specific transistor.

[0017] In a second aspect, the present invention provides an integrated circuit, wherein the integrated circuit comprises the dynamic bias voltage circuit as described above.

[0018] In some embodiments, the integrated circuit also includes an output stage circuit configured to transmit signals to a structure outside the integrated circuit; wherein the bias voltage provided by the dynamic bias voltage circuit is used to control at least one transistor in the output stage circuit directly connected to a pad of the integrated circuit.

[0019] Those skilled in the art will no doubt understand these and other objects of the present invention after reading the following detailed description of the preferred embodiments shown in the accompanying drawings. The detailed description will be given in the following embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention may be more fully understood by reading the following detailed description and by referring to the examples given in the accompanying drawings.

[0021] Figure 1 A simplified schematic diagram of the output stage circuit of a USB IC is shown.

[0022] Figure 2 A simplified schematic diagram of a dynamic bias voltage circuit is shown according to an embodiment of the present invention.

[0023] Figure 3A and Figure 3B According to an embodiment of the present invention, Figure 2 An example implementation of a buffer circuit in .

[0024] Figure 4 A detailed schematic diagram of a dynamic bias voltage circuit is shown according to an embodiment of the present invention.

[0025] In the following detailed description, for the purpose of illustration, many specific details are set forth so that those skilled in the art can more thoroughly understand the embodiments of the present invention. However, it is apparent that one or more embodiments may be implemented without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments listed in the accompanying drawings. DETAILED DESCRIPTION

[0026] The following description is a preferred embodiment of the present invention, which is only used to illustrate the technical features of the present invention, and is not used to limit the scope of the present invention. Certain words are used throughout the specification and claims to refer to specific components. It should be understood by those skilled in the art that manufacturers may use different names to refer to the same components. Therefore, the present specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as a basis for distinction. The terms "component", "system" and "device" used in the present invention can be entities related to computers, wherein the computer can be hardware, software, or a combination of hardware and software. The terms "including" and "comprising" mentioned in the following description and claims are open-ended terms, so they should be interpreted as "including, but not limited to...". In addition, the term "coupled" means an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0027] Corresponding numbers and symbols in the various figures of the drawings generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0028] The term "substantially" or "approximately" as used herein means that within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the technical effect to be achieved. For example, "approximately equal to" means that a certain error from "completely equal to" is acceptable to a person skilled in the art without affecting the correctness of the result.

[0029] The following description is intended to illustrate the general principles of the present invention, and the present invention should not be limited to the example scenarios introduced in this description, and the scope of the present invention should be determined with reference to the appended claims. The present invention provides a dynamic bias voltage circuit that can dynamically track the voltage changes on the IC pad, which is used to provide a dynamic bias voltage to at least one specific transistor in the integrated circuit. For example, the specific transistor can be the first transistor viewed from the pad of the integrated circuit to the integrated circuit (that is, the transistor directly connected to the pad in the integrated circuit, which can also be described as "the first transistor viewed from the pad of the integrated circuit"). The bias voltage generated is related to the voltage on the pad, so that even if the voltage on the pad varies widely, it can ensure that the absolute value of the gate-drain voltage of the specific transistor (that is, the gate-drain junction voltage) will not exceed the maximum withstand voltage applied by its manufacturing process.

[0030] Figure 1 is a simplified schematic diagram of an output stage circuit of an IC (e.g., a USB IC) according to the present invention, wherein the output stage circuit is configured to transmit a signal to a structure outside the integrated circuit (e.g., the signal is transmitted via a signal pad). It should be noted that Figure 1 It is only an example of the present invention, not a limitation of the present invention. For example, the signal pad may be an input / output (I / O) pad, which is used to send and receive signals between the integrated circuit and the external structure coupled to the integrated circuit. For ease of explanation and understanding, the embodiment of the present invention takes the voltage variation range allowed on the pad of the integrated circuit (for example, the signal pad of the IC, which is used to connect to the external structure of the IC) as -0.4V to 4.03V and the maximum withstand voltage of the gate-to-drain junction of the transistor (also interchangeably described as a MOS tube) inside the IC under a specific process (such as a 3nm process) as 1.65V (it can be understood that the gate-to-drain junction voltage difference of the transistor cannot exceed the maximum withstand voltage limited by the manufacturing process of the integrated circuit) as an example for illustration, but the present invention should not be limited to this example. For example, in the case of USB application (but the present invention is not limited thereto), the pad may be a signal pad PAD_DP and / or a signal pad PAD_DM, wherein the signal pad PAD_DP is used for a USB data positive (Data Positive, DP) signal, and the signal pad PAD_DM is used for a USB data negative (Data Minus, DM) signal. Figure 1As shown, when the voltage on the pad PAD of the integrated circuit (not shown in the figure) (also described as "pad voltage") is at 4.03V (i.e., the upper limit of the voltage variation range on the pad), the gate voltages VG_P1 and VG_N1 of transistors P1 and N1 (which are the first transistors viewed from the pad PAD into the integrated circuit or the transistors directly connected to the pad PAD in the integrated circuit) need to be greater than 2.38V, so that the transistors directly connected to the pad PAD (such as Figure 1 The requirement that the absolute value of the gate-to-drain voltage of transistors P1 and N1 in the circuit (i.e., |VGD| is the voltage difference between the gate and the drain, which can also be described as the "gate-drain voltage difference") is less than 1.65V (i.e., the maximum withstand voltage for the gate-drain junction under specific / given / known process conditions) can be met. On the other hand, when the voltage on the pad PAD of the IC is -0.4V (i.e., the lower limit of the voltage variation range on the pad), the gate voltages VG_P1 and VG_N1 of transistors P1 and N1 need to be less than 1.25V, so that the requirement that the absolute value of the gate-to-drain voltage of the transistor directly connected to the pad PAD is less than 1.65V can be met. In view of this, the present invention provides a dynamic bias voltage circuit for generating a dynamic bias voltage as the gate voltage of the first transistor (the transistor directly connected to the pad PAD) viewed from the pad of the IC, so that the gate voltage of these specific transistors (for example, the first transistor viewed from the pad of the IC, that is, the transistor directly connected to the integrated circuit and the pad PAD) can dynamically track the voltage changes on the pad of the IC.

[0031] Figure 2 FIG. 1 is a simplified schematic diagram of a dynamic bias voltage circuit according to an embodiment of the present invention. In this embodiment, an integrated circuit (IC) includes an output stage circuit and a dynamic bias voltage circuit according to the present invention. Figure 2As shown, the dynamic bias voltage circuit 100 includes a buffer circuit 110, a voltage divider circuit 120, and a voltage follower circuit 130. The buffer circuit 110 has the characteristics of high input impedance and low output impedance, and the buffer circuit 110 is configured to output a second voltage V2 according to a first voltage V1 (i.e., a reference voltage), wherein V2=F1*V1 (F1 is a factor less than or equal to 1). By using the buffer circuit 110, the voltage V2 output by the buffer circuit has a high output driving capability and is not easily affected by subsequent circuits / voltages (e.g., V_PAD), so that the dynamic bias voltage circuit provided by the present invention can provide a desired bias voltage as needed.

[0032] Figure 3A and Figure 3B is an example implementation of the buffer circuit 110 shown in accordance with various embodiments of the present invention. In the example implementation shown, the buffer circuit 110 may take the form of a unity gain buffer or a combination of a unity gain buffer and a voltage divider circuit. However, the scope of the present invention is not limited to these designs. In various embodiments of the present invention, the buffer circuit 110 may be any other type of circuit based on a buffer. Preferably, the buffer or unity gain buffer may be implemented using an amplifier (e.g., an error amplifier) ​​in a negative feedback configuration. Figure 3A and Figure 3B As shown, the buffer circuit may include an error amplifier (EA) having a first input terminal (positive input terminal), a second input terminal (negative input terminal) and an output terminal, wherein the first input terminal receives a first voltage V1, and the second input terminal is coupled to the output terminal. Figure 3A In the embodiment shown, the output terminal of the amplifier outputs a second voltage V2, and the second voltage V2 is equal to the first voltage V1. Figure 3B In another embodiment shown, the second voltage V2 is generated based on the output voltage of the amplifier, and the second voltage V2 is less than or lower than the first voltage V1.

[0033] refer to Figure 2, the voltage divider circuit 120 coupled to the output of the buffer circuit 110 is configured to implement a voltage dividing function to provide a third voltage V3 based on the pad voltage V_PAD on the pad PAD and the second voltage V2 output by the buffer circuit 110. In the present embodiment, the voltage divider circuit 120 may be equivalent to including resistors R3 and R4 connected in series. The pad voltage V_PAD is coupled to one end of the resistor R3, the second voltage V2 is coupled to one end of the resistor R4, and the third voltage V3 is generated at a node 125 between the resistors R3 and R4. It should be noted that in various embodiments of the present invention, the voltage divider circuit 120 may include other types of resistor networks, which may have more resistors or elements in addition to the resistors R3 and R4, and the present invention is not limited to this.

[0034] like Figure 2 As shown, the third voltage V3 can be expressed as:

[0035] If V2=V1

[0037] As can be seen from the above, the third voltage is related to the pad voltage V_PAD, so that the third voltage V3 can track the voltage change of the pad voltage V_PAD. It should be noted that the driving capability of the node 125 (which outputs the third voltage V3) of the voltage divider circuit 120 is very weak. Therefore, the dynamic bias voltage circuit 100 further includes a voltage follower circuit 130 to enhance the driving capability, so that the dynamic bias voltage circuit 100 can provide a desired bias voltage as needed.

[0038] Figure 4 FIG. 1 is a detailed schematic diagram of a dynamic bias voltage circuit according to an embodiment of the present invention. Figure 4 As shown, the dynamic bias voltage circuit 100 may further include a voltage generating circuit 105, and the buffer circuit 110 is also coupled to the voltage generating circuit 105. The voltage generating circuit 105 is configured to provide or generate a first voltage V1. For example, the voltage generating circuit 105 may be equivalent to including resistors R1 and R2 connected in series, and the first voltage V1 is generated by dividing the power supply voltage AVDD (e.g., 3.3V) through the resistors R1 and R2. It should be noted that according to various embodiments of the present invention, the voltage generating circuit 105 may include other types of resistor networks, which may have more resistors or elements in addition to the resistors R1 and R2 to meet different design requirements. In addition, in various embodiments of the present invention, the voltage generating circuit 105 may be implemented using a bandgap reference circuit (i.e., a bandgap reference voltage generator), and specifically, the present invention is not limited to this.

[0039] On the other hand, the voltage follower circuit 130 is configured to generate a bias voltage VP according to the third voltage V3 provided by the voltage divider circuit 120. It should be noted that the voltage follower circuit 130 is characterized by a very high input impedance, so that it can be used to isolate the input and output signals, so that the bias voltage VP is not affected by the subsequent circuit / voltage, so that the dynamic bias voltage circuit can provide the desired bias voltage as needed. In particular, the generated bias voltage VP can be applied to / applied to the gate of the first transistor seen from the IC pad or the transistor directly connected to the IC pad. Figure 1 For example, if the example circuit Figure 4 The pad PAD is Figure 1 The generated bias voltage VP can be applied to the gates of transistors P1 and N1.

[0040] In this embodiment, the voltage follower circuit 130 may include a source follower. Figure 4 The transistor M3 shown is implemented. In addition, the voltage follower circuit 130 may also include transistors M2 and M4. The third voltage V3 is coupled to the control terminal (e.g., gate) of the transistor M3, and the bias voltage VP is output from the output terminal of the dynamic bias voltage circuit 100, which is located between the transistors M3 and M4. In addition, the control terminals of the transistors M2 and M4 are coupled to fixed bias voltages V4 and V5, respectively. It should be noted that the present invention does not limit the number of transistors included in the voltage follower circuit 130. In fact, the number of transistors included in the voltage follower circuit 130 is related to the level of the power supply voltage AVDD. For example, if the power supply voltage AVDD is 3.3V and the maximum withstand voltage of the gate-drain junction of the transistor is 1.65V, the arrangement and number of transistors in the voltage follower circuit 130 can be the same as Figure 4 However, in various embodiments of the present invention, more or fewer transistors may be included in the voltage follower circuit 130, and the present invention does not impose any limitation on this. In one embodiment, the transistors M2, M3, and M4 are P-channel Metal Oxide Semiconductor (PMOS) transistors.

[0041] like Figure 4 As shown, the dynamic bias voltage circuit may further include a current mirror circuit 107, which is configured to generate an operating current I1 for the voltage follower circuit 130. For example, the current mirror circuit 107 may include at least one current mirror, which may include Figure 4The transistors M0 and M6 are shown. In particular, the current mirror circuit 107 mirrors the reference current I0 to generate the operating current I1. In addition, in various embodiments of the present invention, the current mirror circuit 107 can have more current mirrors, for example, by mirroring another reference current to generate the reference current I0, so that a large current can be obtained from a small current. It should be noted that the generation of the operating current I1 is not limited to the current mirror circuit.

[0042] exist Figure 4 In the illustrated embodiment, the voltage generating circuit 105 generates a first voltage V1 (i.e., a reference voltage) by dividing the power supply voltage AVDD using resistors R1 and R2. For ease of explanation and understanding, the buffer circuit 110 is taken as a unit gain buffer as an example for illustration. Therefore, the first voltage V1 and the second voltage V2 can be expressed as:

[0043]

[0044] Thus, in Figure 2 and Figure 4 In the illustrated embodiment, the third voltage V3 provided by the voltage divider circuit 120 can be expressed as:

[0045]

[0046] Further, the bias voltage VP generated by the voltage follower circuit 130 can be expressed as:

[0047]

[0048] Among them, the voltage VSG M3 is the source-to-gate voltage of transistor M3, which is equal to VS M3 -VG M3 , where VS M3 is the source voltage of transistor M3, VG M3 is the gate voltage of transistor M3. In addition, the source-gate voltage VSG of transistor M3 M3 The relationship with the operating current I1 can be expressed as follows:

[0049]

[0050] Wherein, K is a constant, for example, under a given / known / specific manufacturing process, it is related to the size of the transistor M3 in the voltage follower circuit 130. Therefore, for a specific value (magnitude, also interchangeably described as "size" or "amplitude") of the operating current I1, the source-gate voltage VSG M3will be known or can be learned. For example, in fact, under a given manufacturing process, the source-gate voltage VSG M3 can be determined according to the value of the operating current I1 and the size of the transistor M3. For the sake of convenience of explanation, the source-gate voltage VSG M3 is usually in the range of several hundred millivolts (for example, 400 - 500 mV).

[0051] From the above expression of the bias voltage VP, it can be learned that the bias voltage VP is equal to the sum of the third voltage V3 (which is related to the pad voltage V_PAD) and a fixed voltage (VSG M3 ). In view of this, the dynamic bias voltage circuit 100 can dynamically track the pad voltage V_PAD.

[0052] In addition, for the sake of convenience of explanation and understanding, assume that the voltage change range of the pad voltage V_PAD is a to b; for the lower limit case of V_PAD = a (which is the lower limit value of the voltage change range), the first preset value of the bias voltage VP is represented as "Va", and for the upper limit case of V_PAD = b (which is the upper limit value of the voltage change range), the second preset value of the bias voltage VP is represented as "Vb". Thus, according to the above expression of the bias voltage VP, the following expression can be rewritten:

[0053]

[0054]

[0055] In summary, through the voltage change range of the pad voltage V_PAD, the values of a and b can be determined. In addition, through the maximum tolerable voltage V_W for the gate-drain junction limit in the manufacturing process, the first preset value Va and the second preset value Vb can be determined according to the requirement that the gate-drain junction voltage difference |VGD| < V_W, where "Va - a - < V_W" and "b - Vb < V_W", that is, "Va < a + V_W" and "Vb > b - V_W". It should be noted that the first preset value Va, the second preset value Vb are related to (or limited by) the voltage change range and the maximum tolerable voltage V_W. Further, the resistance relationship between the resistors R3 and R4 can be further expressed as:

[0056]

[0057] In summary, according to the upper limit value b and the lower limit value a of the voltage variation range of the pad voltage V_PAD, and the maximum tolerance voltage V_W, the resistance relationship between the resistors R3 and R4 can be obtained or determined, wherein the preset value of the bias voltage VP (i.e., Va and Vb) is related to the voltage variation range and the maximum tolerance voltage V_W. In addition, the resistance relationship between the resistors R1 and R2 can also be determined according to the voltage variation range and the maximum tolerance voltage V_W of the pad voltage V_PAD, for example, according to the values ​​of a, b, Va and Vb (which are related to the voltage variation range and the maximum tolerance voltage V_W) and the power supply voltage AVDD and the source-gate voltage VSG of the transistor M3. M3 to be sure.

[0058] As described above, the bias voltage VP provided by the dynamic bias voltage circuit 100 will be applied to the gate of a specific transistor (e.g., the first transistor seen from the pad or a transistor directly connected to the pad). Therefore, when the pad voltage V_PAD is at the lower limit value a, the gate-drain junction voltage |VGD| of the first transistor seen from the pad is "Va-a", which needs to be less than the maximum withstand voltage V_W of the gate-drain junction. In other words, the preset value Va of the bias voltage VP can be any suitable value lower than "a+V_W". On the other hand, when the pad voltage V_PAD is at the upper limit value b, the gate-drain junction voltage |VGD| of the first transistor seen from the pad is "b-vb", which needs to be less than the maximum withstand voltage V_W of the gate-drain junction. In other words, the value Vb of the bias voltage VP can be any suitable value greater than "b-V_W". Assuming that the pad voltage V_PAD varies between -0.4V and 4.03V, and the maximum withstand voltage V_W of the gate-drain junction is 1.65V, the first preset value Va of the bias voltage VP can be any suitable value less than 1.25V, and the second preset value Vb of the bias voltage VP can be any suitable value greater than 2.38. Of course, the second preset value Vb of the bias voltage VP needs to be less than the power supply voltage AVDD (such as 3.3V).

[0059] In one embodiment, the driving capability of the dynamic bias voltage circuit 100 can be adjusted by changing the size of the operating current I1. For example, assuming that the size ratio of transistor M0 and transistor M6 is 1:n, the ratio of the size of the reference current I0 to the size of the operating current I1 is 1:n. Therefore, adjusting the size of the reference current I0 is equivalent to proportionally adjusting the size of the operating current I1. Therefore, increasing the amplitude of the reference current I0 is equivalent to enhancing the driving capability of the voltage follower circuit 130, because the larger the operating current I1, the stronger the driving capability of the voltage follower circuit 130. In addition, since the size of the operating current I1 is related to the source-gate voltage VSG of the transistor M3, M3The relationship is exponential, so the magnitude of the operating current I1 has a relatively small effect on the bias voltage VP. Therefore, when setting the first preset value Va and the second preset value Vb, a certain voltage margin can be reserved.

[0060] In one embodiment, an integrated circuit (IC) may include a normal operating mode and a power-saving mode. In the normal operating mode, the operating current I1 has a first current value; in the power-saving mode, the operating current I1 has a second current value less than the first current value. In particular, in USB applications (e.g., USB2.0), the normal operating mode refers to the full-speed transmission (FSTX) mode. When the USB IC operates in the FSTX mode, the operating current I1 of the voltage follower circuit 130 is set to be higher to enhance the driving capability, thereby avoiding interference from the signal on the pad PAD (the interference will affect the performance of the dynamic bias voltage circuit 100) and having a higher driving capability. However, when the USB IC operates in the power-saving mode, almost all circuits in the USB IC may stop working, but the dynamic bias voltage circuit 100 still needs to work. Therefore, the operating current I1 is reduced to reduce power consumption. Thus, in some embodiments, different values ​​of the operating current I1 can be pre-set for different operating modes. For example, the FSTX mode may set a first current value, and the power saving mode may set a second current value, wherein the first current value is greater than the second current value.

[0061] It should be noted that, although the voltage variation range related to USB 2.0 (e.g., -0.4V to 4.03V) and the maximum withstand voltage limited by a specific manufacturing process (e.g., 1.65V as limited by the 3nm process) are used as examples in the present invention to explain the concept / concept of the present invention, the present invention is not limited to the specific values ​​in this example. The dynamic bias voltage circuit of the present invention can be used for ICs other than USB ICs, thereby ensuring that the gate-drain junction voltage |VGD| of the first transistor (i.e., at least one transistor directly connected to the pad in the integrated circuit) seen from the IC pad (e.g., I / O pad) does not exceed the maximum withstand voltage limited by the specific manufacturing process of the IC. Therefore, for integrated circuits under specific manufacturing processes, the present invention can effectively ensure the reliability requirements of transistors, thereby making the performance of the integrated circuit more stable.

[0062] Although the present invention has been described by way of example and in terms of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. Instead, it is intended to cover various modifications and similar structures (as will be apparent to those skilled in the art), for example, combinations or replacements of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar structures.

Claims

1. A dynamic bias voltage circuit for providing a dynamic bias voltage to at least one specific transistor in an integrated circuit, comprising: a buffer circuit configured to output a second voltage according to the first voltage; A voltage divider circuit coupled to the buffer circuit and configured to implement a voltage dividing function to provide a third voltage according to the second voltage and a pad voltage on a pad of the integrated circuit; as well as The voltage follower circuit is coupled to the voltage divider circuit and is configured to generate the bias voltage according to the third voltage.

2. The dynamic bias voltage circuit according to claim 1, characterized in that: The buffer circuit includes: an amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the first voltage, and the second input terminal is coupled to the output terminal; Wherein, the output terminal of the amplifier outputs the second voltage, and the second voltage is equal to the first voltage; or The second voltage is generated according to the output voltage of the amplifier, and the second voltage is smaller than the first voltage.

3. The dynamic bias voltage circuit according to claim 1, characterized in that: The dynamic bias voltage circuit also includes: A voltage generating circuit is coupled to the buffer circuit and is configured to generate the first voltage by dividing the power supply voltage through a resistor network; The resistor network includes a first resistor and a second resistor connected in series.

4. The dynamic bias voltage circuit according to claim 1, characterized in that: The voltage divider circuit includes: A third resistor and a fourth resistor are connected in series, wherein the third voltage is generated at a node between the third resistor and the fourth resistor.

5. The dynamic bias voltage circuit according to claim 4, characterized in that: A first end of the third resistor is coupled to the pad voltage, a second end of the third resistor is coupled to a first end of the fourth resistor, and a second end of the fourth resistor is coupled to the second voltage.

6. The dynamic bias voltage circuit according to claim 5, characterized in that: The resistance relationship between the third resistor and the fourth resistor is related to the voltage variation range of the pad voltage and the maximum withstand voltage applied by the specific manufacturing process of the integrated circuit.

7. The dynamic bias voltage circuit according to claim 1, characterized in that: The voltage follower circuit comprises: A first transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the first transistor is coupled to a first fixed voltage, and the first terminal of the first transistor is coupled to a power supply voltage; a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to the third voltage, the first terminal of the second transistor is coupled to the second terminal of the first transistor, and a node between the first transistor and the second transistor serves as an output terminal of the voltage follower circuit; and The third transistor has a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor is coupled to a second fixed voltage, the first terminal of the third transistor is coupled to the second terminal of the second transistor, and the second terminal of the third transistor is coupled to ground.

8. The dynamic bias voltage circuit according to claim 1, characterized in that: The voltage follower circuit includes a source follower, wherein the source follower is implemented by a transistor.

9. The dynamic bias voltage circuit according to claim 1, characterized in that: The dynamic bias voltage circuit also includes: The current mirror circuit is configured to provide an operating current to the voltage follower circuit.

10. The dynamic bias voltage according to claim 9, characterized in that: The bias voltage is related to the pad voltage and the operating current.

11. The dynamic bias voltage circuit according to claim 1, characterized in that: The integrated circuit includes a normal operating mode and a power saving mode; wherein, during the normal operating mode, the operating current has a first current value, and during the power saving mode, the operating current has a second current value less than the first current value.

12. The dynamic bias voltage circuit according to claim 1, characterized in that: The integrated circuit complies with the Universal Serial Bus (USB) standard, and the integrated circuit includes a full-speed transmission FSTX mode and a power saving mode. During the FSTX mode, the operating current has a first current value, and during the power saving mode, the operating current has a second current value that is smaller than the first current value.

13. The dynamic bias voltage circuit according to claim 1, characterized in that: The at least one specific transistor is the first transistor seen from the pad of the integrated circuit or at least one transistor in the integrated circuit directly connected to the pad, and the bias voltage is coupled to the control terminal of the at least one specific transistor.

14. An integrated circuit, characterized in that: The integrated circuit comprises a dynamic bias voltage circuit as claimed in any one of claims 1 to 13.

15. The integrated circuit according to claim 14, characterized in that The integrated circuit also includes: an output stage circuit configured to transmit a signal to a structure external to the integrated circuit; The bias voltage provided by the dynamic bias voltage circuit is used to control at least one transistor in the output stage circuit that is directly connected to the pad of the integrated circuit.

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