Controllable output voltage circuit

Abstract

The invention relates to the technical field of voltage circuits, in particular to a controllable output voltage circuit which comprises a controllable voltage stabilization source U1, an NPN transistor Q1, a PWM signal and a resistance-capacitance device, the controllable voltage stabilization source U1, the NPN transistor Q1 and the resistance-capacitance device jointly form a series voltage stabilization regulator circuit, PWM-duty is a duty ratio, and PWM-duty is a duty ratio. A PWM signal is connected to a voltage reference pin of the controllable voltage-stabilizing source U1 through the RC integrating circuit, the PWM signal controllably adjusts the reference voltage of the controllable voltage-stabilizing source U1 through the RC integrating circuit, so that the base potential of an NPN transistor Q1 is controllable, and the purpose of controlling the output voltage is achieved. The requirement for controllable adjustment of the output voltage in a specific application scene is met, the circuit can work normally in the PWM no-signal state and the PWM signal state, and the circuit has different output characteristics in different states, so that the circuit can adapt to various working scenes, and the universality and flexibility of the circuit are improved.

Description

Technical Field

[0001] The present invention relates to the field of voltage circuits, and in particular to a controllable output voltage circuit. Background Art

[0002] With the continuous development and widespread application of electronic products, the demand for diversified DC power supply technology is growing. In many application scenarios, it is necessary to achieve controllable adjustment of the output voltage to meet the working requirements of different equipment. At present, the voltage of the commonly used controllable adjustment circuit is mostly proportional to the PWM-duty (duty cycle), that is, when the PWM-duty is large, the output voltage is large, and vice versa.

[0003] In the prior art, it may be difficult to achieve precise voltage control when the voltage of the controllable regulating circuit is in direct proportion to the PWM-duty (duty cycle), because within different duty cycle ranges, the voltage change may not be linear, resulting in difficulty in accurately predicting and controlling the output voltage. Under a direct proportional relationship, a change in the duty cycle will directly lead to a change in the output voltage, which may affect the stability of the circuit. For example, when the power supply fluctuates or the load changes, the adjustment of the duty cycle may cause a large fluctuation in the output voltage, affecting the normal operation of the circuit. For some systems with high requirements on stability, such as precision instruments, communication equipment, etc., this instability may be unacceptable.

[0004] In view of this demand, the existing circuit technology has limitations and cannot meet the requirements of actual application scenarios. Therefore, the present invention proposes a controllable output voltage circuit to solve the problem that the reference voltage is inversely proportional to the PWM-duty to meet diverse application needs. Summary of the invention

[0005] The purpose of the present invention is to provide a controllable output voltage circuit to solve the problem that the voltage of the controllable regulating circuit is in direct proportion to the PWM duty (duty cycle), and it may be difficult to achieve precise voltage control, so as to meet diverse application requirements.

[0006] The inventors have found that because the voltage change may not be linear within different duty cycle ranges, it is difficult to accurately predict and control the output voltage. Under a positive proportional relationship, the change in duty cycle will directly lead to a change in output voltage, which may affect the stability of the circuit. For example, when the power supply fluctuates or the load changes, the adjustment of the duty cycle may cause a large fluctuation in the output voltage, affecting the normal operation of the circuit. For some systems with high requirements for stability, such as precision instruments, communication equipment, etc., this instability may be an unacceptable problem. To overcome the above problems, the present invention achieves the following technical effects:

[0007] A controllable output voltage circuit includes a controllable voltage regulator U1, an NPN transistor Q1, a PWM signal and a resistor-capacitor device. The controllable voltage regulator U1, the NPN transistor Q1 and the resistor-capacitor device together form a series voltage regulator circuit. PWM-duty is a duty cycle. The PWM signal is connected to the voltage reference pin of the controllable voltage regulator U1 through an RC integration circuit. The PWM signal is controllably regulated through the RC integration circuit to adjust the reference voltage of the controllable voltage regulator U1, thereby realizing the controllability of the base potential of the NPN transistor Q1, and further achieving the purpose of controllable output voltage:

[0008] The output voltage is inversely proportional to the PWM-duty signal, that is, when the PWM-duty signal accounts for a small proportion of the space, the output voltage is high; when the PWM-duty signal accounts for a large proportion of the space, the output voltage is low;

[0009] In this circuit, the PWM-duty signal has two states, one is the state of PWM without signal, and the other is the state of PWM with signal;

[0010] The output voltage of the circuit can be connected to the positive phase pin of the operational amplifier as a reference potential. The series voltage regulator can be controlled by PWM-duty to output different voltages, thereby achieving the purpose of controlling the output current and realizing an inverse proportional linear relationship between the output current and PWM-duty.

[0011] Preferably, there are multiple resistor and capacitor components, and the RC integration circuit is composed of a resistor R8, a capacitor C3 and a resistor R7, which mainly acts as a buffer and smoothes the voltage waveform during PWM operation, while changing the magnitude of the current flowing into and out of the Vref node of the controllable voltage regulator U1.

[0012] Preferably, when the PWM is in a state of no signal, the resistors R7 and R8 in the RC integration circuit are in a state of not being connected to the circuit, and the circuit is a typical application of a series voltage regulator. Under the circuit usage premise of an input voltage of 3.5V-35V, an output voltage of 3.0V-35V, and a high potential of a PWM rectangular wave >2.5V, that is, in the PWM rectangular wave, "high potential" refers to the voltage value when the rectangular wave is in a high level state, the output voltage is jointly set by the upper bias resistor R3 and the lower bias resistor R5.

[0013] Preferably, when the PWM is in a state without a signal, the output voltage is set by the upper bias resistor R3 and the lower bias resistor R5. In this process, since the PWM signal is not connected, it is equivalent to that the resistor R8 is in a suspended state in the circuit. At this time, the circuit is a series voltage stabilization circuit, and the voltage expression of its output voltage Vo is:

[0014] Vo = Vref × (R3 + R5) / R5;

[0015] Among them, Vref is the reference voltage of the controllable voltage regulator U1, which is 2.5V. In this actual application circuit, the input Vin is a 12V DC source, and the output Vo is equal to 5.12V. The resistor R12 and the resistor R11 form a voltage divider circuit. The voltage divider on the resistor R11 provides a reference potential for the non-phase pin of the U2A comparator. This reference potential has a fixed proportional relationship with Vo.

[0016] Preferably, when the PWM has a signal state, the series voltage stabilizing circuit is transformed into a controllable output voltage circuit, and the output voltage is determined by the PWM-duty. Kirchhoff's law is used to analyze the circuit state at this time, and it can be divided into two states for analysis, one is when the PWM signal is set to the high part, and the other is when the PWM signal is set to the low part.

[0017] Preferably, when the PWM signal is set to the high part, the direction of the PWM signal current flows from the resistor R8 to the resistor R7, and then flows to the lower bias resistor R5. At this time, the current on the lower bias resistor R5 consists of two parts, one part flows from the PWM signal, and the other part flows from the upper bias resistor R3, which can be expressed by the following expression: IR5=IR3+I resistor R7.

[0018] Preferably, when the PWM signal is set to the low part, the direction of the PWM signal current flows from the Vref of the controllable voltage-stabilizing source U1 to the resistors R7 and R8 to the signal ground of the PWM. At this time, the Vref of the controllable voltage-stabilizing source U1 flows to the ground through the lower bias resistor R5, and also flows to the ground through the resistors R7+resistor R8, which can be expressed by the following expression: IR3=IR5+Iresistor R7.

[0019] Preferably, by calculating IR3 in different states, and then calculating the voltage on the bias resistor R3 by Ohm's law, and then multiplying it by the PWM-duty value of the corresponding state and adding the reference voltage Vref of the controllable voltage regulator U1, the output voltage can be expressed by the following expression:

[0020] Vo=(D×R3×IR3+(1-D)×R3×IR3)+Vref;

[0021] Wherein, D is the duty value, D×R3×IR3 is the output voltage on the upper bias resistor R3 when the PWM signal is set to the high part, and (1-D)×R3×IR3 is the output voltage on the upper bias resistor R3 when the PWM signal is set to the low part.

[0022] Preferably, by analyzing the expression, it can be known that when there is no PWM signal, the output voltage is determined by the resistance ratio of the upper resistor R3 and the lower resistor R5; when there is a PWM signal, the output voltage is determined by the PWM-duty, and the slope k value of the output voltage composition of different duty values ​​is determined by the resistor R7+resistor R8. Under the same conditions, the smaller the resistance value of the resistor R7+resistor R8, the greater the slope, and vice versa, the smaller the slope.

[0023] Preferably, the controllable output voltage circuit described in claim 1 is applied to the following circuit: the DC input voltage Vin is connected to the circuit, the Vin end is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, the Vin end is also connected to one end of the resistor R3, the other end of the resistor R3 is connected to the base of the NPN transistor Q1, the emitter of the transistor Q1 is grounded, the cathode of U1 is connected to the collector of the NPN transistor Q1, the anode of U1 is grounded, the resistor R1 is connected to U1, the reference electrode of U1 is grounded through the lower bias resistor R5, and is connected to the base of the NPN tube Q1 through the upper bias resistor R3, the capacitor C2 is connected between U1 and the lower bias resistor R5, the PWM signal passes through the RC integration circuit composed of the resistor R8 and the resistor R7, the resistor R7 is connected to the upper bias resistor R3 and the lower bias resistor R5, the resistor R7 and the resistor R8 are connected in series between the PWM signal input end and the ground, the capacitor C3 is connected between the resistor R7 and the resistor R8, one end of the capacitor C3 is grounded, the upper bias resistor R3 is connected to the capacitor C4, and one end of the capacitor C4 is grounded.

[0024] Technical effects and advantages of the present invention:

[0025] 1. The circuit can achieve an inverse proportional relationship between the output voltage and the PWM-duty signal, meeting the demand for controllable output voltage adjustment in specific application scenarios and providing support for precise control of related equipment;

[0026] 2. The circuit can work normally in both PWM signal-free and signal-enabled states, and has different output characteristics in different states, making it adaptable to a variety of working scenarios and improving the versatility and flexibility of the circuit;

[0027] 3. By connecting the output voltage as the reference potential to the positive phase pin of the op amp, and using PWM-duty to control the series voltage regulator to output different voltages, the output current is controlled, and the output current and PWM-duty are inversely proportional linear relations, which helps to optimize the performance and efficiency of the circuit;

[0028] 4. The circuit is mainly composed of a controllable voltage regulator, an NPN transistor and common resistors and capacitors. The structure is relatively simple and the components are all common components, which reduces the cost and complexity of the circuit and facilitates production and maintenance.

[0029] 5. Within the specific range of input voltage and output voltage, the circuit can work stably, the output voltage can be calculated by a clear formula, and by reasonably setting the resistance value, the slope of the output voltage can be controlled, thereby improving the stability and reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The present invention is a schematic diagram of a controllable output voltage circuit.

[0031] Figure 2 This is a schematic diagram of the current flow principle when the PWM signal is set to the high part of the present invention.

[0032] Figure 3 This is a schematic diagram of the current flow principle when the PWM signal is set to the low part of the present invention.

[0033] Figure 4 This is a schematic diagram of a specific application circuit of the present invention.

[0034] Figure 5 It is a schematic diagram of controllable output voltage characteristics of a specific application case of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] The present invention provides Figure 1-Figure 5 A controllable output voltage circuit shown in the figure includes a controllable voltage regulator U1, an NPN transistor Q1, a PWM signal and a resistor-capacitor device. The controllable voltage regulator U1, the NPN transistor Q1 and the resistor-capacitor device together constitute a series voltage regulator circuit. PWM-duty is a duty cycle. The PWM signal is connected to the voltage reference pin of the controllable voltage regulator U1 through an RC integration circuit. The PWM signal is controllably regulated through the RC integration circuit to adjust the reference voltage of the controllable voltage regulator U1, thereby realizing the controllability of the base potential of the NPN transistor Q1, and further achieving the purpose of controllable output voltage:

[0037] The output voltage is inversely proportional to the PWM-duty signal, that is, when the PWM-duty signal accounts for a small proportion of the space, the output voltage is high; when the PWM-duty signal accounts for a large proportion of the space, the output voltage is low;

[0038] In this circuit, the PWM-duty signal has two states, one is the state of PWM without signal, and the other is the state of PWM with signal;

[0039] The output voltage of the circuit can be connected to the positive phase pin of the operational amplifier as a reference potential, and the series voltage regulator can be controlled by PWM-duty to output different voltages, thereby achieving the purpose of controlling the output current and realizing the inverse proportional linear relationship between the output current and PWM-duty;

[0040] The controllable output voltage circuit described in claim 1 is applied to the following circuit: a DC input voltage Vin is connected to the circuit, a Vin terminal is connected to one end of a capacitor C1, the other end of the capacitor C1 is grounded, a Vin terminal is also connected to one end of an upper bias resistor R3, the other end of the upper bias resistor R3 is connected to the base of an NPN transistor Q1, the emitter of the transistor Q1 is grounded, a cathode of U1 is connected to the collector of the NPN transistor Q1, an anode of U1 is grounded, a resistor R1 is connected to U1, a reference electrode of U1 is grounded through a resistor R5, and connected to the base of the NPN tube Q1 through the upper bias resistor R3, a capacitor C2 is connected between U1 and the lower bias resistor R5, a PWM signal passes through an RC integration circuit composed of a resistor R8 and a resistor R7, a resistor R7 is connected to the upper bias resistor R3 and the lower bias resistor R5, a resistor R7 and a resistor R8 are connected in series between the PWM signal input terminal and the ground, a capacitor C3 is connected between the resistor R7 and the resistor R8, one end of the capacitor C3 is grounded, a capacitor C4 is connected to the upper bias resistor R3, and one end of the capacitor C4 is grounded;

[0041] See also Figure 1 , the circuit describes a series voltage regulator based on a controllable voltage regulator U1 and an NPN transistor, which is characterized in that the output voltage is controlled by a PWM (pulse width modulation) signal. When there is no PWM signal, the resistors R7 and R8 in the RC integration circuit are not connected to the circuit, and the output voltage is set by the upper bias resistor R3 and the lower bias resistor R5. When there is a PWM signal, the series voltage regulator circuit is transformed into a controllable output voltage circuit, and the output voltage is determined by the PWM-duty. Since the duty cycle of the PWM signal is converted into a reference voltage of the controllable voltage regulator U1 through the RC integration circuit, and then the base potential and collector current of the NPN transistor are controlled, the output voltage is inversely proportional to the duty cycle of the PWM signal. When the duty cycle is low, the average voltage is low, the output of U1 is also low, the conduction degree of the NPN transistor is small, and the output voltage is high; when the duty cycle is high, the opposite is true.

[0042] There are multiple resistors and capacitors. The RC integration circuit is composed of a resistor R8, a capacitor C3 and a resistor R7. It is mainly used for buffering and smoothing voltage waveforms during PWM operation, and at the same time changes the magnitude of the current flowing into and out of the Vref (reference voltage, used to set the stable value of the output voltage) node of the controllable voltage regulator U1. When the PWM has no signal, the resistors R7 and R8 in the RC integration circuit are not connected to the circuit. The circuit is a typical application of a series voltage regulator. When the input voltage is 3.5V-35V and the output voltage is 3.0V- Under the circuit use premise of 35V and PWM rectangular wave high potential>2.5V (in PWM rectangular wave, "high potential" refers to the voltage value when the rectangular wave is in a high level state), the output voltage is set by the upper bias resistor R3 and the lower bias resistor R5. When the PWM has no signal, the output voltage is set by the upper bias resistor R3 and the lower bias resistor R5. In this process, since the PWM signal is not connected, it is equivalent to that the resistor R8 is in a suspended state in the circuit. At this time, the circuit is a series voltage stabilization circuit, and the voltage expression of its output voltage Vo is:

[0043] Vo = Vref × (R3 + R5) / R5;

[0044] Among them, Vref is the reference voltage of the controllable voltage regulator U1, which is 2.5V. In this practical application circuit, the input Vin is a 12V DC source, and the output Vo is equal to 5.12V. Then, the resistor R12 and the resistor R11 form a voltage divider circuit. The voltage divided on the resistor R11 provides a reference potential for the non-phase pin of the U2A comparator. This reference potential is in a fixed proportional relationship with Vo.

[0045] See also Figure 1 , through the duty cycle adjustment of the PWM signal, the output voltage can be precisely controlled, making the circuit more flexible and adaptable in different application scenarios. When the PWM signal does not exist, the circuit can automatically degenerate into a stable series voltage regulator circuit to ensure the stability and reliability of the output voltage; among them, the input voltage is determined by the VCEO of Q1, and this voltage cannot exceed the VCEO of device Q1; it is also affected by the VKA of U1, and the VKA of U1 cannot exceed this value in actual application. The minimum output voltage is the reference potential Vref+VBE of U1, and the maximum output voltage is Vin-Vbe.

[0046] When the PWM has a signal, the series voltage regulator circuit is transformed into a controllable output voltage circuit, and the output voltage is determined by the PWM-duty. Kirchhoff's law is used to analyze the circuit state at this time. At this time, it can be analyzed in two states. One is when the PWM signal is set to the high part (PWM set high potential>2.5), and the other is when the PWM signal is set to the low part. When the PWM signal is set to the high part (PWM set high potential>2.5), the PWM signal current direction flows from the resistor R8 to the resistor R7, and then flows to the lower bias resistor R5. At this time, the current on the lower bias resistor R5 consists of two parts, one part is from the PWM signal, and the other part is from the upper bias resistor R3, which can be used as shown in the following table The expression is: IR5 = IR3 + I resistor R7. When the PWM signal is set to low, the PWM signal current flows from the Vref (internal 2.5V reference source) of the controllable voltage regulator U1 to the resistor R7, the resistor R8 to the PWM signal ground (zero potential point). At this time, the Vref of the controllable voltage regulator U1 flows to the ground through R5, and also flows to the ground through the resistor R7 + resistor R8. It can be expressed by the following expression: IR3 = IR5 + I resistor R7. By calculating IR3 in different states, and then calculating the voltage on the bias resistor R3 by Ohm's law, and then multiplying it by the PWM-duty value of the corresponding state and adding the reference voltage Vref of the controllable voltage regulator U1, the output voltage can be expressed by the following expression:

[0047] Vo=(D×R3×IR3+(1-D)×R3×IR3)+Vref;

[0048] Where D is the PWM-duty value, D×R3×IR3 is the output voltage on the upper bias resistor R3 when the PWM signal is set to the high part, and (1-D)×R3×IR3 is the output voltage on the upper bias resistor R3 when the PWM signal is set to the low part;

[0049] By analyzing the expression, it can be known that when there is no PWM signal, the output voltage is determined by the resistance ratio of the upper bias resistor R3 and the lower bias resistor R5; when there is a PWM signal, the output voltage is determined by the PWM-duty, and the slope k value of the output voltage composition with different PWM-duty values ​​is determined by the resistor R7+resistor R8. Under the same conditions, the smaller the resistance value of the resistor R7+resistor R8, the greater the slope, and vice versa.

[0050] See also Figure 2-3When the PWM signal is in the high part, the PWM signal charges the capacitor C3 through the resistor R8 and the resistor R7, generating an average voltage related to the PWM duty cycle (duty value). This average voltage is used as the reference voltage (Vref_PWM) of U1. U1 adjusts its output voltage according to this reference voltage, thereby controlling the base current of the NPN transistor Q1, thereby adjusting the output voltage Vo. The upper bias resistor R3 and the lower bias resistor R5 are used as voltage divider resistors, but they do not directly determine the specific value of the output voltage Vo, but work together with the feedback mechanism of U1 to ensure the stability of the output voltage. When the PWM signal is in the low part, the capacitor C3 discharges through the resistor R7, but the discharge speed is relatively slow to maintain a certain voltage level. The reference voltage of U1 decreases, causing the output voltage of U1 to also decrease, thereby reducing the base current of the NPN transistor Q1 and the output voltage Vo rising. Therefore, during the PWM low period, the output voltage Vo is not directly determined by the upper bias resistor R3 and the lower bias resistor R5, but is jointly determined by the feedback mechanism of U1 and PWM-duty.

[0051] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions only describe the principles of the present invention. The present invention may be subject to various changes and improvements without departing from the spirit and scope of the present invention. These changes and improvements fall within the scope of the present invention. The scope of protection claimed by the present invention is defined by the attached claims and their equivalents.

Claims

1. A controllable output voltage circuit, comprising a controllable voltage regulator U1, an NPN transistor Q1, a PWM signal and a resistor and capacitor device, characterized in that: The controllable voltage regulator U1, NPN transistor Q1 and resistor-capacitor device together form a series voltage regulator circuit, PWM-duty is the duty cycle, the PWM signal is connected to the voltage reference pin of the controllable voltage regulator U1 through the RC integration circuit, and the PWM signal is controllably adjusted through the RC integration circuit to adjust the reference voltage of the controllable voltage regulator U1, thereby realizing the controllability of the base potential of the NPN transistor Q1, and further achieving the purpose of controllable output voltage; The output voltage is inversely proportional to the PWM-duty signal, that is, when the PWM-duty signal accounts for a small proportion of the space, the output voltage is high; When the PWM-duty signal has a large share, the output voltage is low; In this circuit, the PWM-duty signal has two states, one is the state of PWM without signal, and the other is the state of PWM with signal; The output voltage of the circuit can be connected to the positive phase pin of the operational amplifier as a reference potential. The series voltage regulator can be controlled by PWM-duty to output different voltages, thereby achieving the purpose of controlling the output current and realizing an inverse proportional linear relationship between the output current and PWM-duty.

2. The controllable output voltage circuit according to claim 1, characterized in that: There are multiple resistor and capacitor components. The RC integration circuit is composed of a resistor R8, a capacitor C3 and a resistor R7. It mainly plays the role of buffering and smoothing the voltage waveform during PWM operation, and at the same time changes the size of the current flowing into and out of the Vref node of the controllable voltage regulator U1.

3. A controllable output voltage circuit according to claim 2, characterized in that: When the PWM is in a state of no signal, the resistors R7 and R8 in the RC integration circuit are not connected to the circuit. The circuit is a typical application of a series voltage regulator. Under the premise of input voltage 3.5V-35V, output voltage 3.0V-35V and high potential of the PWM rectangular wave>2.5V, that is, in the PWM rectangular wave, "high potential" refers to the voltage value when the rectangular wave is in a high level state, the output voltage is jointly set by the upper bias resistor R3 and the lower bias resistor R5.

4. The controllable output voltage circuit according to claim 3, characterized in that: When the PWM has no signal, the output voltage is set by the upper bias resistor R3 and the lower bias resistor R5. In this process, since the PWM signal is not connected, it is equivalent to that the resistor R8 is in a suspended state in the circuit. At this time, the circuit is a series voltage stabilization circuit, and the voltage expression of its output voltage Vo is: Vo = Vref × (R3 + R5) / R5; Among them, Vref is the reference voltage of the controllable voltage regulator U1, which is 2.5V. In this actual application circuit, the input Vin is a 12V DC source, and the output Vo is equal to 5.12V. The resistor R12 and the resistor R11 form a voltage divider circuit. The voltage divider on the resistor R11 provides a reference potential for the non-phase pin of the U2A comparator. This reference potential has a fixed proportional relationship with Vo.

5. The controllable output voltage circuit according to claim 1, characterized in that: When the PWM has a signal state, this series voltage regulator circuit is transformed into a controllable output voltage circuit. The output voltage is determined by the PWM-duty. Kirchhoff's law is used to analyze the circuit state at this time. At this time, it can be divided into two states for analysis, one is when the PWM signal is set to the high part, and the other is when the PWM signal is set to the low part.

6. The controllable output voltage circuit according to claim 5, characterized in that: When the PWM signal is set to the high part, the PWM signal current flows from resistor R8 to resistor R7, and then flows to the lower resistor R5. At this time, the current on the lower resistor R5 is composed of two parts, one part is from the PWM signal, and the other part is from the upper resistor R3, which can be expressed by the following expression: IR5=IR3+I resistor R7.

7. The controllable output voltage circuit according to claim 5, characterized in that: When the PWM signal is set to the low part, the direction of the PWM signal current flows from the Vref of the controllable voltage regulator U1 to the resistors R7 and R8 to the signal ground of the PWM. At this time, the Vref of the controllable voltage regulator U1 flows to the ground through the lower bias resistor R5, and also flows to the ground through the resistors R7 + R8, which can be expressed as the following expression: IR3 = IR5 + I resistor R7.

8. A controllable output voltage circuit according to claims 6-7, characterized in that: By calculating IR3 in different states, and then using Ohm's law to calculate the voltage on the bias resistor R3, and then multiplying it by the PWM-duty value of the corresponding state and adding the reference voltage Vref of the controllable voltage regulator U1, the output voltage can be expressed by the following expression: Vo=(D×R3×IR3+(1-D)×R3×IR3)+Vref; Wherein, D is the duty value, D×R3×IR3 is the output voltage on the upper bias resistor R3 when the PWM signal is set to the high part, and (1-D)×R3×IR3 is the output voltage on the upper bias resistor R3 when the PWM signal is set to the low part.

9. A controllable output voltage circuit according to claims 4-7, characterized in that: By analyzing the expression, it can be seen that when there is no PWM signal, the output voltage is determined by the resistance ratio of the upper resistor R3 and the lower resistor R5; when there is a PWM signal, the output voltage is determined by the PWM-duty, and the slope k value of the output voltage composition with different PWM-duty values ​​is determined by the resistor R7 + resistor R8. Under the same conditions, the smaller the resistance value of the resistor R7 + resistor R8, the greater the slope, and vice versa.

10. The controllable output voltage circuit according to claim 1, characterized in that: The controllable output voltage circuit described in claim 1 is applied to the following circuit: a DC input voltage Vin is connected to the circuit, a Vin end is connected to one end of a capacitor C1, the other end of the capacitor C1 is grounded, and a Vin end is also connected to one end of an upper bias resistor R3, the other end of the upper bias resistor R3 is connected to the base of an NPN transistor Q1, the emitter of the transistor Q1 is grounded, a cathode of U1 is connected to the collector of the NPN transistor Q1, an anode of U1 is grounded, a resistor R1 is connected to U1, a reference electrode of U1 is grounded through a lower bias resistor R5, and connected to the base of the NPN tube Q1 through the upper bias resistor R3, a capacitor C2 is connected between U1 and the lower bias resistor R5, a PWM signal passes through an RC integration circuit composed of a resistor R8 and a resistor R7, a resistor R7 is connected to the upper bias resistor R3 and the lower bias resistor R5, a resistor R7 and a resistor R8 are connected in series between the PWM signal input end and the ground, a capacitor C3 is connected between the resistor R7 and the resistor R8, one end of the capacitor C3 is grounded, a capacitor C4 is connected to the upper bias resistor R3, and one end of the capacitor C4 is grounded.

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