Server backboard, communication system and control method of communication system

Abstract

The invention relates to the technical field of communication, and discloses a server backboard, a communication system and a control method of the communication system, the server backboard is applied to a bus communication system, the server backboard comprises a first interface unit, a switch unit and an editable logic device, the first interface unit is used for transmitting information between the programmable logic device and external equipment; the programmable logic device is used for outputting a control signal based on the power-on state of the first power supply and the external equipment; the switch unit is used for switching the switch state based on the control signal, so that when the external equipment is not powered on or the first power supply is not powered on, the first power supply and the external equipment are disconnected. According to the invention, the power supply of the backboard can be isolated from the power supply of the external equipment, the situation that the backboard of the server is damaged due to electric leakage through the bus when the backboard and the external equipment are not electrified synchronously is avoided, and the safety of the backboard of the server is improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a server backplane, a communication system and a control method for the communication system. Background Art

[0002] The SGPIO protocol is a protocol for serial communication, mainly used for input and output control between the system motherboard and the external device backplane. The SGPIO protocol uses serial communication to transmit data, and it completes communication by using clock, data and control signals. The CLK signal is used to synchronize data transmission, the DATA signal is used to transmit actual data, and the CTRL signal is used to transmit control information, such as the start and end flags of transmission.

[0003] In the communication system, the controller and the hard disk are respectively arranged on the mainboard and the backplane, and the mainboard and the backplane communicate via the SGPIO protocol through cables. Since the mainboard and the backplane each have a pull-up power supply, when the two pull-up power supplies POWER_1 and POWER_2 are turned on asynchronously, the pull-up power supply that is turned on first will leak electricity to the other pull-up power supply side through the SGPIO bus between the mainboard and the backplane, damaging the device connected to the power-on side. Summary of the invention

[0004] In view of this, the present invention provides a server backplane, a communication system and a control method of the communication system to solve the problem that when the backplane and the external device are powered on asynchronously, the power supplies of the two will leak electricity to each other.

[0005] In a first aspect, the present invention provides a server backplane, which is applied to a bus communication system. The server backplane includes: a first interface unit, a switch unit and an editable logic device, wherein a first end of the first interface unit is connected to a communication end of the editable logic device and a first end of the switch unit, a second end of the first interface unit is connected to an external device through a bus, a third end of the first interface unit is grounded, and the first interface unit is used to transmit information between the editable logic device and the external device; a power supply end of the editable logic device is connected to a second end of the switch unit and a first power supply, an output end of the editable logic device is connected to a control end of the switch unit, and the editable logic device is used to output a control signal based on the first power supply and the power-on status of the external device; the switch unit is used to switch the switch state based on the control signal, so that when the external device is not powered on, or the first power supply is not powered on, the circuit between the first power supply and the external device is disconnected.

[0006] The server backplane provided by the present invention is provided with a switch unit between the bus and the first power supply. When the editable logic device determines that one of the first power supply and the external device is not powered on, the switch unit is controlled to be disconnected, thereby cutting off the path between the first power supply and the power supply of the external device. This avoids the situation in which the power supply of the device powered on first leaks through the bus to the power supply of the device powered on later when the first power supply and the external device are powered on asynchronously, thereby improving the reliability of the backplane server.

[0007] In an optional embodiment, the server backplane also includes: a first pull-up circuit, wherein a first end of the first pull-up circuit is connected to a first end of the switch unit, a second end of the first pull-up circuit is connected to a communication end of the editable logic device, and the first pull-up circuit is used to improve the driving capability of the editable logic device.

[0008] The server backplane provided by the present invention adds a first pull-up circuit at the communication end of the editable logic device to ensure signal quality. On the one hand, it is used to limit current and prevent the large current of the first power supply from damaging the editable logic device. On the other hand, it is used to clamp the level of the communication end under the action of the first power supply, provide current when the bus driving capacity is insufficient, and improve the driving capacity of the editable logic device.

[0009] In an optional embodiment, the communication end of the editable logic device includes: a clock interface, a reset interface, an output interface and an input interface; the clock interface is used to receive a clock signal, the reset interface is used to receive a clock reset signal, the output interface is used to output configuration data, and the input interface is used to receive configuration data; the first pull-up circuit includes: a first pull-up resistor, a second pull-up resistor, a third pull-up resistor and a fourth pull-up resistor, wherein the first end of the first pull-up resistor is connected to the first end of the switch unit, and the second end of the first pull-up resistor is connected to the clock interface of the editable logic device; the first end of the second pull-up resistor is connected to the first end of the switch unit, and the second end of the second pull-up resistor is connected to the reset interface of the editable logic device; the first end of the third pull-up resistor is connected to the first end of the switch unit, and the second end of the third pull-up resistor is connected to the output interface of the editable logic device; the first end of the fourth pull-up resistor is connected to the first end of the switch unit, and the second end of the fourth pull-up resistor is connected to the input interface of the editable logic device.

[0010] In an optional embodiment, the switch unit includes: a MOS switch, wherein a control end of the MOS switch is connected to an output end of the editable logic device, a first end of the MOS switch is connected to a first end of the first interface unit, and a second end of the MOS switch is connected to a power supply end of the editable logic device; the MOS switch is used to switch a switch state based on a control signal, so that when the external device is not powered on, or the first power supply is not powered on, the circuit between the first power supply and the external device is disconnected.

[0011] In an optional implementation, the server backplane further includes: a grounding resistor connected to the control end of the switch unit.

[0012] The server backplane provided by the present invention has a grounding resistor which is used to keep the MOS switch in an off state when the first power supply is not powered on, that is, when the editable logic device is not working, so as to prevent the control end level of the MOS switch from floating and thus being turned on, causing the power supply of the external device to leak to the first power supply.

[0013] In a second aspect, the present invention provides a communication system, comprising: a server mainboard and a server backplane of the first aspect, wherein a power supply end of the server mainboard is connected to a second power supply, a communication end of the server mainboard is connected to a second end of a first interface unit via a bus, and the server mainboard is used to control the operation of an editable logic device after power-on; when the second power supply is not powered on, or the first power supply is not powered on, the switch unit switches the switch state based on a control signal, so that the first power supply is disconnected from the external device.

[0014] In the communication system provided by the present invention, a server mainboard is connected to a server backplane through a bus, the server mainboard and the server backplane are powered by a second power supply and a first power supply respectively, a switch unit is arranged between the second power supply and the first power supply, and when the editable logic device determines that one of the first power supply and the second power supply is not powered on, the switch unit is controlled to be disconnected, and the path between the first power supply and the second power supply is cut off, thereby avoiding the situation that when the first power supply and the second power supply are powered on asynchronously, the power supply of the device powered on first leaks to the power supply of the device powered on later through the bus, thereby avoiding the device powered on later from having a malfunction due to leakage, and improving the reliability of the backplane server.

[0015] In an optional embodiment, the server motherboard includes: a controller, a second interface unit and a second pull-up circuit, wherein the power supply end of the controller is connected to the second power supply, the communication end of the controller is connected to the first end of the second interface unit and the first end of the second pull-up circuit, and the controller is used to control the operation of the editable logic device after power-on; the second end of the second pull-up circuit is connected to the second power supply, and the second pull-up circuit is used to improve the driving capability of the controller; the second end of the second interface unit is connected to the second end of the first interface unit through a bus, the third end of the second interface unit is grounded, and the second interface unit is used to transmit information between the controller and the editable logic device.

[0016] In an optional embodiment, the communication end of the controller includes: a clock interface, a reset interface, an output interface and an input interface; the second pull-up circuit includes: a fifth pull-up resistor, a sixth pull-up resistor, a seventh pull-up resistor and an eighth pull-up resistor, wherein the first end of the fifth pull-up resistor is connected to the second power supply, and the second end of the fifth pull-up resistor is connected to the clock interface of the controller; the first end of the sixth pull-up resistor is connected to the second power supply, and the second end of the sixth pull-up resistor is connected to the reset interface of the controller; the first end of the seventh pull-up resistor is connected to the second power supply, and the second end of the seventh pull-up resistor is connected to the output interface of the controller; the first end of the eighth pull-up resistor is connected to the second power supply, and the second end of the eighth pull-up resistor is connected to the input interface of the controller.

[0017] In a third aspect, the present invention provides a control method for a communication system, which is applied to the editable logic device of the first aspect, and the method comprises: detecting whether there is a voltage of a first power supply; when the voltage of the first power supply is not detected, controlling the switch unit to be disconnected, so that the circuit between the first power supply and the second power supply is broken; when the voltage of the first power supply is detected and there is no voltage signal at the communication end, controlling the switch unit to be disconnected; when a voltage signal is detected at the communication end, indicating that the voltage of the second power supply has been detected, controlling the switch unit to be turned on.

[0018] The control method of the communication system provided by the present invention detects that after the first power supply is powered on, the switch unit is disconnected to prevent the first power supply from leaking to the second power supply through the bus; the switch unit is turned on only when the second power supply is also powered on, avoiding the situation that when the first power supply and the second power supply are powered on asynchronously, the power supply of the device powered on first leaks to the power supply of the device powered on later through the bus, avoiding the malfunction of the device powered on later due to leakage, and improving the reliability of the backplane server.

[0019] In an optional embodiment, when the voltage of the first power supply is detected and there is no voltage signal at the communication end, the process of controlling the switch unit to disconnect includes: controlling the switch unit to disconnect so that the bus discharges, and setting the communication end to a floating state, and then detecting in real time whether there is a voltage signal at the communication end. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1It is a schematic diagram of an SGPIO communication line in the related art;

[0022] Figure 2 It is a schematic diagram of voltage waveform during power supply timing synchronization in the related art;

[0023] Figure 3 It is a schematic diagram of voltage waveform when the power supply timing is not synchronized in the related art;

[0024] Figure 4 is a composition diagram of a server backplane according to an embodiment of the present invention;

[0025] Figure 5 is another composition diagram of a server backplane according to an embodiment of the present invention;

[0026] Figure 6 is a specific circuit structure diagram of a server backplane according to an embodiment of the present invention;

[0027] Figure 7 is a composition diagram of a communication system according to an embodiment of the present invention;

[0028] Figure 8 is a specific circuit structure diagram of a communication system according to an embodiment of the present invention;

[0029] Fig. 9 It is a flowchart of a control method of a communication system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0031] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0032] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0034] In the server bus communication system, such as Figure 1 As shown, IC1 is the server mainboard, and IC4 is the server backplane. The two transmit SGPIO signals through two connectors and bus CABLE. Since IC1 and IC4 are distributed on different boards, in order to ensure signal quality, pull-up resistors are set at the position of IC1 close to the connector and the position of IC4 close to the connector, and the pull-up power supply is respectively selected from the power supply POWER_1 and POWER_2 on the respective boards.

[0035] Ideally, if Figure 2 As shown, the timing of the two pull-up power supplies POWER_1 and POWER_2 are synchronized, and no leakage problem will occur between the server mainboard and the server backplane through the bus.

[0036] But usually, if Figure 3 As shown in the figure, the two pull-up power supplies POWER_1 and POWER_2 are turned on asynchronously. When one power supply is output and the other power supply is not output, one end of the power supply will leak to the other end through the SGPIO bus. When POWER_2 is later than POWER_1, power will leak from POWER_1 to POWER_2 through R1 / R2 / R3 / R4, bus, R5 / R6 / R7 / R8. This leakage causes a section of the power-on waveform on the backplane, such as Figure 3 The "step" of POWER_2' is shown. Although POWER_1 and POWER_2 cannot be completely synchronized, as long as the time from t2 to t3 can be ignored (ms level or less), leakage will not have any impact. However, if the time from t2 to t3 is several seconds or longer, leakage will cause functional impact on the equipment on the server motherboard and server backplane.

[0037] In order to solve the above problems, this embodiment provides a server backplane, which is applied to a bus communication system, such as Figure 4As shown, the server backplane 1 includes: a first interface unit 11 , a switch unit 12 and an editable logic device 13 .

[0038] like Figure 4 As shown, the first end of the first interface unit 11 is connected to the communication end of the editable logic device 13 and the first end of the switch unit 12, the second end of the first interface unit 11 is connected to the external device through a bus, and the third end of the first interface unit 11 is grounded. The first interface unit 11 is used to transmit information between the editable logic device 13 and the external device.

[0039] Optionally, the switch unit 12 and the editable logic device 13 may also be directly connected to an external device without being connected to the external device through the first interface unit 11 .

[0040] Optionally, the external device may be a controller.

[0041] Optionally, the editable logic device 13 is integrated on the hard disk, which also includes multiple functional chips such as Flash, EEPROM, sensor, etc. Each chip exchanges information with an external device through the first interface unit 11, transmits control signals through the SGPIO bus, and reads and writes hard disk data.

[0042] like Figure 4 As shown, the power supply end of the editable logic device 13 is connected to the second end of the switch unit 12 and the first power supply, the output end of the editable logic device 13 is connected to the control end of the switch unit 12, and the editable logic device 13 is used to output a control signal based on the first power supply and the power-on status of the external device.

[0043] Figure 4 In the embodiment, the switch unit 12 is used to switch the switch state based on the control signal, so that when the external device is not powered on, or the first power supply is not powered on, the circuit between the first power supply and the external device is disconnected.

[0044] Specifically, Figure 4 In the example, the editable logic device 13 applies the following control method to realize power-on detection and server backplane control:

[0045] (1) Detecting whether there is a voltage of the first power supply; (2) When the voltage of the first power supply is not detected, controlling the switch unit to be disconnected, thereby disconnecting the circuit between the first power supply and the external device; (3) When the voltage of the first power supply is detected and there is no voltage signal at the communication end, controlling the switch unit to be disconnected; when a voltage signal is detected at the communication end, indicating that the voltage of the external device has been detected, controlling the switch unit to be turned on.

[0046] Specifically, Figure 4In the example, when the first power supply is powered on first and the external device is powered on later, the editable logic device 13 detects the voltage of the first power supply and disconnects the switch unit 12 first, so that the voltage of the first power supply will not be input into the external device through the first interface unit 11 and the bus, and the voltage on the bus is discharged through the first interface unit 11; since the external device is not powered on at this time, the external device will not output a voltage signal, and there is no voltage signal at the first end of the first interface unit 11. When the external device is powered on, the voltage of the external device is transmitted to the communication end of the editable logic device 13 through the bus and the first interface unit in sequence. After reading the voltage signal, the editable logic device 13 determines that the external device is powered on and controls the switch unit 12 to be turned on, and the external device and the editable logic device 13 perform data transmission normally.

[0047] Specifically, Figure 4 In the embodiment, when the external device is powered on first and the first power supply is powered on later, since the editable logic device 13 has no power supply voltage and does not output a control signal, the switch unit 12 is disconnected, and the leakage current of the external device cannot be transmitted to the first power supply through the bus; when the first power supply is powered on, the editable logic device 13 is powered on and controls the switch unit 12 to turn on based on the voltage signal of the communication end, and the external device and the editable logic device 13 perform data transmission normally.

[0048] Optionally, the switch unit 12 may be a controllable switch such as a MOS switch, a transistor, or an integrated switch.

[0049] The server backplane provided in this embodiment is provided with a switch unit between the bus and the first power supply. When the editable logic device determines that the first power supply and one of the external devices are not powered on, the switch unit is controlled to disconnect, thereby cutting off the path between the first power supply and the power supply of the external device. This avoids the situation in which the power supply of the device that is powered on first leaks through the bus to the power supply of the device that is powered on later when the first power supply and the external device are powered on asynchronously, thereby improving the reliability of the backplane server.

[0050] In some optional embodiments, such as Figure 5 As shown, the server backplane further includes: a first pull-up circuit 14 , wherein a first end of the first pull-up circuit 14 is connected to a first end of the switch unit 12 , and a second end of the first pull-up circuit 14 is connected to a communication end of the editable logic device 13 .

[0051] Specifically, Figure 5In the figure, the first pull-up circuit 14 is used to limit the current of the communication end of the editable logic device 13 on the one hand, and on the other hand, since the circuit of the SGPIO signal sends a low level in an open-drain manner and sends a high level in a high-impedance manner, the first pull-up circuit 14 is also used to pull up the communication end level to the first power supply voltage when the switch unit 12 is turned on, thereby improving the driving capability of the editable logic device 13 and ensuring the quality of signal transmission.

[0052] Optionally, the first pull-up circuit may be a plurality of resistors connected in series or in parallel or in series and parallel.

[0053] In some optional embodiments, such as Figure 6 As shown, the communication end of the editable logic device 13 includes: a clock interface SGPIO_DEVICE_SCLK, a reset interface SGPIO_DEVICE_SLOAD, an output interface SGPIO_DEVICE_SDOUT and an input interface SGPIO_DEVICE_SDIN; the clock interface SGPIO_DEVICE_SCLK is used to receive a clock signal, the reset interface SGPIO_DEVICE_SLOAD is used to receive a clock reset signal, the output interface SGPIO_DEVICE_SDOUT is used to output configuration data, and the input interface SGPIO_DEVICE_SDIN is used to receive configuration data.

[0054] Optionally, the communication terminal of the editable logic device 13 is connected to the switch unit 12 through the first pull-up circuit 14, illustratively, as Figure 6 As shown, the first pull-up circuit 14 includes: a first pull-up resistor R1, a second pull-up resistor R2, a third pull-up resistor R3 and a fourth pull-up resistor R4, wherein a first end of the first pull-up resistor R1 is connected to a first end of the switch unit 12, and a second end of the first pull-up resistor R1 is connected to a clock interface SGPIO_DEVICE_SCLK of the editable logic device 13; a first end of the second pull-up resistor R2 is connected to a first end of the switch unit 12, and a second end of the second pull-up resistor R2 is connected to a reset interface SGPIO_DEVICE_SLOAD of the editable logic device 13; a first end of the third pull-up resistor R3 is connected to a first end of the switch unit 12, and a second end of the third pull-up resistor R3 is connected to an output interface SGPIO_DEVICE_SDOUT of the editable logic device 13; a first end of the fourth pull-up resistor R4 is connected to a first end of the switch unit 12, and a second end of the fourth pull-up resistor R4 is connected to an input interface SGPIO_DEVICE_SDIN of the editable logic device 13.

[0055] Specifically, Figure 6In the embodiment, when the switch unit 12 is turned on, the first pull-up resistor R1, the second pull-up resistor R2, the third pull-up resistor R3 and the fourth pull-up resistor R4 are respectively used to pull up the clock interface SGPIO_DEVICE_SCLK, the reset interface SGPIO_DEVICE_SLOAD, the output interface SGPIO_DEVICE_SDOUT and the input interface SGPIO_DEVICE_SDIN of the editable logic device 13 to a high level, thereby improving the driving capability of the editable logic device 13, ensuring the stability of the signal line, preventing the signal line from being suspended, and limiting the current size of each interface to protect the editable logic device 13 from being damaged by a large current shock.

[0056] Optionally, Figure 6 In the embodiment, the switch unit 12 includes: a MOS switch, wherein the control end of the MOS switch is connected to the output end of the editable logic device 13, the first end of the MOS switch is connected to the first end of the first interface unit 11, and the second end of the MOS switch is connected to the power supply end of the editable logic device 13; the control end of the MOS switch is also connected to the grounding resistor R5, and the grounding resistor R5 is to ensure that when POWER_1 is not powered on, that is, when the editable logic device 13 is not working, the control end of the MOS switch is maintained at a low level, so that the MOS switch remains in a disconnected state. If there is no grounding resistor R5, the control end level of the MOS switch is floating, and the MOS switch may be turned on, causing the power supply of the external device to leak to POWER_1.

[0057] Optionally, Figure 6 In the embodiment, the MOS switch is used to switch the switch state based on the control signal. When the MOS switch is turned on, the voltages of the first power supply POWER_1 and POWER_1' are equal. When the MOS switch is turned off, POWER_1' has no voltage. Therefore, when the external device is not powered on, or the first power supply POWER_1 is not powered on, the MOS switch is turned off, and the circuit between POWER_1' and the external device is disconnected, and no leakage current flows between the first power supply POWER_1 and the external device.

[0058] It should be noted that those skilled in the art can set the resistance value and number of the pull-up resistors in the first pull-up circuit as required.

[0059] This embodiment provides a communication system, such as Figure 7As shown, it includes: a server mainboard 2 and a server backplane 1 of the above embodiments and any optional implementation manner thereof, wherein the power supply end of the server mainboard 2 is connected to the second power supply, the communication end of the server mainboard 2 is connected to the second end of the first interface unit 11 through a bus, and the server mainboard 2 is used to control the operation of the editable logic device 13 after power-on; when the second power supply is not powered on, or the first power supply is not powered on, the switch unit 12 switches the switch state based on the control signal, so that the first power supply is disconnected from the external device.

[0060] Specifically, Figure 7 In the embodiment, the editable logic device 13 applies the following control method to realize power-on detection and communication system control:

[0061] (1) Detecting whether there is a voltage of the first power supply; (2) When the voltage of the first power supply is not detected, controlling the switch unit to be disconnected, so that the circuit between the first power supply and the second power supply is disconnected; (3) When the voltage of the first power supply is detected and there is no voltage signal at the communication end, controlling the switch unit to be disconnected; when a voltage signal is detected at the communication end, indicating that the voltage of the second power supply is detected, controlling the switch unit to be turned on.

[0062] Specifically, Figure 7 In the example, when the first power supply is powered on first and the second power supply is powered on later, the editable logic device 13 detects the voltage of the first power supply and disconnects the switch unit 12 first, so that the voltage of the first power supply will not leak to the second power supply through the first interface unit 11 and the bus, and the voltage on the bus is discharged through the first interface unit 11; since the second power supply has not been powered on at this time, the server mainboard 2 will not output a voltage signal, and there is no voltage signal at the first end of the first interface unit 11. When the second power supply is powered on, the voltage of the second power supply is transmitted to the communication end of the editable logic device 13 through the bus and the first interface unit 11 in sequence. After reading the voltage signal, the editable logic device 13 determines that the second power supply is powered on and controls the switch unit 12 to be turned on, and the second power supply and the editable logic device 13 perform data transmission normally.

[0063] Specifically, Figure 7 In the embodiment, when the second power supply is powered on first and the first power supply is powered on later, since the editable logic device 13 has no power supply voltage and does not output a control signal, the switch unit 12 is disconnected, and the leakage of the second power supply cannot be transmitted to the first power supply through the bus; when the first power supply is powered on, the editable logic device 13 is powered on and controls the switch unit 12 to turn on based on the voltage signal of the communication end, and the server motherboard 2 and the editable logic device 13 perform data transmission normally.

[0064] In the communication system provided by the present embodiment, the server mainboard is connected to the server backplane through a bus, the server mainboard and the server backplane are powered by the second power supply and the first power supply respectively, a switch unit is arranged between the second power supply and the first power supply, and when the editable logic device determines that one of the first power supply and the second power supply is not powered on, the switch unit is controlled to be disconnected, and the path between the first power supply and the second power supply is cut off, thereby avoiding the situation that when the first power supply and the second power supply are powered on asynchronously, the power supply of the device powered on first will leak to the power supply of the device powered on later through the bus, thereby avoiding the malfunction of the device powered on later due to leakage, and improving the reliability of the backplane server.

[0065] In some optional embodiments, such as Figure 8 As shown, the server motherboard 2 includes: a controller 21, a second interface unit 23 and a second pull-up circuit 22, wherein the power supply end of the controller 21 is connected to the second power supply POWER_2, the communication end of the controller 21 is connected to the first end of the second interface unit 23 and the first end of the second pull-up circuit 22; the second end of the second pull-up circuit 22 is connected to the second power supply POWER_2; the second end of the second interface unit 23 is connected to the second end of the first interface unit 11 through the bus CABLE, and the third end of the second interface unit 23 is grounded.

[0066] Specifically, Figure 8 In the embodiment, the controller 21 is used to control the editable logic device 13 to work after power-on, the second pull-up circuit 22 is used to improve the driving capability of the controller 21 , and the second interface unit 23 is used to transmit information between the controller 21 and the editable logic device 13 .

[0067] Optionally, the second pull-up circuit may be a plurality of resistors connected in series or in parallel or in series and parallel.

[0068] Optionally, the server motherboard may also include a controllable switch, the output end of the controller is connected to the control end of the controllable switch, the first end and the second end of the controllable switch are respectively connected to the second power supply and the second end of the second pull-up circuit, and the controller can control the controllable switch to be turned on by monitoring the power-on sequence of the first power supply and the second power supply: when the first power supply is powered on first and the second power supply is powered on later, the controller controls the controllable switch to be turned off until the second power supply is powered on; when the second power supply is powered on first and the first power supply is powered on later, the controller detects the voltage of the second power supply and then turns off the controllable switch until the first power supply is powered on, and then the controller reads the voltage signal of the communication end and controls the controllable switch to be turned on, so that the mainboard and the backplane can transmit data normally.

[0069] In some optional embodiments, such as Figure 8As shown, the communication end of the controller 21 includes: a clock interface SGPIO_HOST_SCLK, a reset interface SGPIO_HOST_SLOAD, an output interface SGPIO_HOST_SDOUT and an input interface SGPIO_HOST_SDIN.

[0070] Optionally, the communication end of the controller 21 is connected to the second power supply POWER_2 through a second pull-up circuit 22. Exemplarily, the second pull-up circuit 22 includes: a fifth pull-up resistor R6, a sixth pull-up resistor R7, a seventh pull-up resistor R8 and an eighth pull-up resistor R9. Figure 8 In the embodiment, a first end of the fifth pull-up resistor R6 is connected to the second power supply POWER_2, and a second end of the fifth pull-up resistor R6 is connected to the clock interface SGPIO_HOST_SCLK of the controller 21; a first end of the sixth pull-up resistor R7 is connected to the second power supply POWER_2, and a second end of the sixth pull-up resistor R7 is connected to the reset interface SGPIO_HOST_SLOAD of the controller 21; a first end of the seventh pull-up resistor R8 is connected to the second power supply POWER_2, and a second end of the seventh pull-up resistor R8 is connected to the output interface SGPIO_HOST_SDOUT of the controller 21; a first end of the eighth pull-up resistor R9 is connected to the second power supply POWER_2, and a second end of the eighth pull-up resistor R9 is connected to the input interface SGPIO_HOST_SDIN of the controller 21.

[0071] Specifically, Figure 8 In the embodiment, when the second power supply POWER_2 is powered on, the fifth pull-up resistor R6, the sixth pull-up resistor R7, the seventh pull-up resistor R8 and the eighth pull-up resistor R9 are respectively used to pull up the clock interface SGPIO_HOST_SCLK, the reset interface SGPIO_HOST_SLOAD, the output interface SGPIO_HOST_SDOUT and the input interface SGPIO_HOST_SDIN of the controller 21 to a high level to ensure the stability of the signal line and prevent the signal line from being suspended, while limiting the current size of each interface to protect the controller 21 from being damaged by large current shock.

[0072] It should be noted that those skilled in the art can set the type and number of interfaces of the controller communication terminal as needed, and there is no limitation on the number and connection method of the corresponding pull-up resistors. The functions of the controller include but are not limited to the contents described in the above embodiments.

[0073] This embodiment provides a control method for a communication system, which is applied to the editable logic device of the above embodiment and any optional implementation manner thereof, such as Fig. 9 As shown, the method includes:

[0074] Step S1: Detect whether there is a voltage of a first power supply.

[0075] Specifically, refer to Figure 8 The editable logic device 13 determines the power-on sequence of the first power supply POWER_1 and the second power supply POWER_2 by detecting whether there is a voltage of the first power supply POWER_1.

[0076] Step S2: when the voltage of the first power supply is not detected, the switch unit is controlled to be disconnected, so that the circuit between the first power supply and the second power supply is disconnected.

[0077] Specifically, refer to Figure 8 When there is no voltage of the first power supply POWER_1, it indicates that the editable logic device 13 has no power supply, so the output terminal control_pin of the editable logic device 13 will not output a control signal to maintain a low level, so that the switch unit 12 maintains a disconnected state by default. At this time, even if the second power supply POWER_2 is powered on, the current of the second power supply POWER_2 will not leak into the first power supply POWER_1 through the bus.

[0078] Step S3: When the voltage of the first power supply is detected and there is no voltage signal at the communication end, the switch unit is controlled to be disconnected; when a voltage signal is detected at the communication end, indicating that the voltage of the second power supply is detected, the switch unit is controlled to be turned on.

[0079] Among them, when the voltage of the first power supply is detected and there is no voltage signal at the communication end, the process of controlling the switch unit to disconnect includes: controlling the switch unit to disconnect so that the bus discharges, and setting the communication end to a floating state, and then detecting in real time whether there is a voltage signal at the communication end.

[0080] Specifically, refer to Figure 8 , when the voltage of the first power supply POWER_1 is detected and there is no voltage signal at the communication end, it indicates that at this time, the first power supply POWER_1 is powered on, but the second power supply POWER_2 is not powered on, so the controller 21 has no output voltage, and each interface of the communication end of the editable logic device 13 will not detect the output voltage signal of the controller 21, that is, the first power supply POWER_1 is powered on before the second power supply POWER_2. At this time, the output end control_pin of the editable logic device 13 will not output a control signal to maintain a low level, so that the switch unit 12 continues to maintain the disconnected state, and there is no voltage at POWER_1'. The editable logic device 13 first sets the interface of each communication end to a low level, so that the residual charge on the bus is released to the ground, and then sets the interface of the communication end to a floating input, and reads the value of each communication end interface in real time to detect whether the communication end has a voltage signal sent by the controller 21.

[0081] Specifically, refer to Figure 8 When the editable logic device 13 detects that there is a voltage signal at the communication end, indicating that the second power supply POWER_2 is powered on, the controller 21 starts to work and outputs voltage, and the output voltage is sequentially input to the communication end of the editable logic device 13 through the second interface unit 23, the bus CABLE, and the first interface unit 11, so that after the communication end interface is converted to a high level, the editable logic device 13 sets the level of the output end control_pin to a high level and outputs a control signal, so that the switch unit 12 is turned on, and a path is formed between the first power supply POWER_1 and the second power supply POWER_2 and the bus, thereby restoring the normal SGPIO function of the communication system.

[0082] The control method of the communication system provided in the present embodiment detects that after the first power supply is powered on, the switch unit is disconnected to prevent the first power supply from leaking to the second power supply through the bus; the switch unit is turned on only when the second power supply is also powered on, thereby preventing the power supply of the device powered on first from leaking to the power supply of the device powered on later through the bus when the first power supply and the second power supply are powered on asynchronously, thereby preventing the device powered on later from having functional abnormalities due to leakage, thereby improving the reliability of the backplane server.

[0083] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A server backplane, characterized in that: Applied to a bus communication system, the server backplane comprises: a first interface unit, a switch unit and an editable logic device, wherein: The first end of the first interface unit is connected to the communication end of the editable logic device and the first end of the switch unit, the second end of the first interface unit is connected to the external device through a bus, the third end of the first interface unit is grounded, and the first interface unit is used to transmit information between the editable logic device and the external device; The power supply end of the editable logic device is connected to the second end of the switch unit and the first power supply, the output end of the editable logic device is connected to the control end of the switch unit, and the editable logic device is used to output a control signal based on the first power supply and the power-on state of the external device; The switch unit is used to switch the switch state based on the control signal, so that when the external device is not powered on, or the first power supply is not powered on, the circuit between the first power supply and the external device is disconnected.

2. The server backplane according to claim 1, characterized in that: Also includes: The first pull-up circuit, wherein The first end of the first pull-up circuit is connected to the first end of the switch unit, the second end of the first pull-up circuit is connected to the communication end of the editable logic device, and the first pull-up circuit is used to improve the driving capability of the editable logic device.

3. The server backplane according to claim 2, characterized in that: The communication end of the editable logic device includes: a clock interface, a reset interface, an output interface and an input interface; The clock interface is used to receive a clock signal, the reset interface is used to receive a clock reset signal, the output interface is used to output configuration data, and the input interface is used to receive configuration data; The first pull-up circuit includes: a first pull-up resistor, a second pull-up resistor, a third pull-up resistor and a fourth pull-up resistor, wherein: A first end of the first pull-up resistor is connected to a first end of the switch unit, and a second end of the first pull-up resistor is connected to a clock interface of the editable logic device; A first end of the second pull-up resistor is connected to a first end of the switch unit, and a second end of the second pull-up resistor is connected to a reset interface of the editable logic device; The first end of the third pull-up resistor is connected to the first end of the switch unit, and the second end of the third pull-up resistor is connected to the output interface of the editable logic device; A first end of the fourth pull-up resistor is connected to a first end of the switch unit, and a second end of the fourth pull-up resistor is connected to an input interface of the editable logic device.

4. The server backplane according to claim 1, characterized in that: The switch unit comprises: a MOS switch, wherein: The control end of the MOS switch is connected to the output end of the editable logic device, the first end of the MOS switch is connected to the first end of the first interface unit, and the second end of the MOS switch is connected to the power supply end of the editable logic device; The MOS switch is used to switch the switch state based on the control signal, so that when the external device is not powered on or the first power supply is not powered on, the first power supply and the external device are disconnected.

5. The server backplane according to any one of claims 1 to 4, characterized in that: Also includes: A grounding resistor connected to the control terminal of the switch unit.

6. A communication system, characterized in that: include: A server motherboard and a server backplane according to any one of claims 1 to 5, wherein: The power supply end of the server mainboard is connected to the second power supply, the communication end of the server mainboard is connected to the second end of the first interface unit through a bus, and the server mainboard is used to control the operation of the editable logic device after power-on; When the second power supply is not powered on, or the first power supply is not powered on, the switch unit switches the switch state based on the control signal, so that the circuit between the first power supply and the external device is disconnected.

7. The communication system according to claim 6, characterized in that: The server mainboard includes: a controller, a second interface unit and a second pull-up circuit, wherein: The power supply end of the controller is connected to the second power supply, the communication end of the controller is connected to the first end of the second interface unit and the first end of the second pull-up circuit, and the controller is used to control the editable logic device to work after power-on; The second end of the second pull-up circuit is connected to the second power supply, and the second pull-up circuit is used to improve the driving capability of the controller; The second end of the second interface unit is connected to the second end of the first interface unit through a bus, the third end of the second interface unit is grounded, and the second interface unit is used for transmitting information between the controller and the editable logic device.

8. The communication system according to claim 7, characterized in that The communication end of the controller includes: a clock interface, a reset interface, an output interface and an input interface; The second pull-up circuit includes: a fifth pull-up resistor, a sixth pull-up resistor, a seventh pull-up resistor and an eighth pull-up resistor, wherein: A first end of the fifth pull-up resistor is connected to the second power supply, and a second end of the fifth pull-up resistor is connected to the clock interface of the controller; A first end of the sixth pull-up resistor is connected to the second power supply, and a second end of the sixth pull-up resistor is connected to a reset interface of the controller; A first end of the seventh pull-up resistor is connected to the second power supply, and a second end of the seventh pull-up resistor is connected to the output interface of the controller; A first end of the eighth pull-up resistor is connected to the second power supply, and a second end of the eighth pull-up resistor is connected to an input interface of the controller.

9. A method for controlling a communication system, characterized in that: Applied to the editable logic device according to any one of claims 6 to 8, the method comprising: Detecting whether there is a voltage of the first power supply; When the voltage of the first power supply is not detected, the switch unit is controlled to be disconnected, so that the first power supply and the second power supply are disconnected; When the voltage of the first power supply is detected and there is no voltage signal at the communication end, the control switch unit is disconnected; when a voltage signal is detected at the communication end, indicating that the voltage of the second power supply is detected, the control switch unit is turned on.

10. The method according to claim 9, characterized in that The process of controlling the switch unit to disconnect when the voltage of the first power supply is detected and there is no voltage signal at the communication end includes: The switch unit is controlled to be disconnected to discharge the bus, and after the communication terminal is set to a floating state, it is detected in real time whether there is a voltage signal at the communication terminal.

Images