In-memory logical operation circuit and system based on DRAM (Dynamic Random Access Memory)

Abstract

The invention belongs to the technical field of integrated circuits, and discloses an in-memory logical operation circuit and system based on a DRAM (Dynamic Random Access Memory). And the in-memory logic operation circuit comprises two DRAM (Dynamic Random Access Memory) units and a sensitive amplifier for generating a logic operation result. The in-memory logic operation circuit defines one group of logic input signals as storage content of the DRAM unit, the other group of logic input signals as read-out control signals of the circuit, and double-phase output signals of the sensitive amplifier are defined as positive and negative phase output results of logic operation. On the basis, the in-memory logic operation system provided by the invention comprises at least one in-memory logic operation circuit, a writing word line, a writing bit line, a reading word line decoding and driving circuit, a logic configuration circuit and a control circuit. According to the invention, while the storage function of the in-memory logic operation circuit is not damaged, the in-memory logic operation circuit scheme is provided, and the compatibility of the in-memory logic operation and the memory array is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and more specifically, relates to an in-memory logic operation circuit and system based on dynamic random access memory (DRAM). Background Art

[0002] In edge computing application scenarios such as face recognition, target detection, and wearable health monitoring, the storage wall bottleneck problem of the traditional von Neumann architecture is very prominent due to the limited resources of mobile edge devices. Computing In Memory (CIM) is a new architecture suitable for data-centric deep neural network (DNN) operations. By embedding some matrix-based operation logic into the memory architecture, high-latency and high-power data communication between the memory and the processor is avoided, reducing energy consumption and computing delays. Computing In Memory is a targeted method to solve the above-mentioned storage wall problem, which greatly improves the hardware processing performance of deep neural network applications.

[0003] In the in-memory computing implementation of deep neural networks, the DRAM-based computing architecture is a widely-watched technology route. DRAM uses the amount of charge stored in the capacitor at the storage node as a physical state variable. Generally, a high charge is used as a logical "1" and a low charge is used as a logical "0". In the current DRAM-based computing scheme, one set of input data is generally configured as a set of input signals of the storage and computing unit, and the input value is represented by the pulse width or pulse amplitude of the voltage pulse. Another set of input data is generally configured as the storage content of the storage and computing unit, and the calculation results are represented by the values ​​of basic electrical parameters such as voltage, current, and charge within the storage and computing unit and between the storage units, mainly including logical operations, multiplication and addition operations, etc.

[0004] Focusing on the computing strategy within DRAM, many papers in recent years have provided DRAM-based storage and computing circuit solutions. The 1T1C-based DRISA system realizes the in-memory deployment of logical operations such as addition and shift; the system composed of 3T1C DARAM units realizes the in-memory deployment of multiplication and addition with analog voltage values ​​representing the calculation results. However, most of the existing DRAM-based in-memory logic operation circuits are based on the principle of analog charge sharing, which greatly reduces the read margin compared to the read operation of conventional storage DRAM chips during the calculation process. Although the existing DRAM-based complex operation circuits have improved the computing density and parallelism, they still have the problems of low computing accuracy and complex peripheral circuits. In order to realize the computing function, most of the existing DRAM-based operation circuits have made adjustments to the unit and array structure, so that the DRAM storage and computing system no longer supports conventional storage functions.

[0005] In summary, how to provide programmable in-memory logic computing functions while ensuring the compatibility of logic computing and storage array storage functions, improve the computing accuracy of hardware accelerators used in applications such as deep neural networks, and reduce the complexity of peripheral circuits are still key issues in the field of in-memory computing. Summary of the invention

[0006] In view of the above defects or improvement needs of the prior art, the present invention provides an in-memory logic operation circuit and system based on DRAM, which aims to ensure the compatibility of logical calculation and storage functions while providing programmable in-memory logic calculation functions and improving calculation accuracy.

[0007] To achieve the above object, according to a first aspect of the present invention, there is provided an in-memory logic operation circuit based on DRAM, comprising: an in-memory logic calculation unit based on DRAM and a sense amplifier; wherein the in-memory logic calculation unit comprises a first storage unit and a second storage unit;

[0008] The first storage unit and the second storage unit both include a write transistor TW and N connected read transistors TR, N≥1; the gate of the write transistor TW is connected to the write word line, the source is connected to the write bit line, and the drain is connected to the first end of the N connected read transistors TR, and the connected node is a storage node; the second end of the N connected read transistors TR is connected to the read word line, and the third end is connected to the read bit line;

[0009] After the read bit lines of the first storage unit and the second storage unit are connected together, they are connected to the positive input terminal of the sense amplifier; the signal received by the positive input terminal is compared with the reference signal received by the inverting input terminal of the sense amplifier to generate a logic operation result;

[0010] Wherein, the first group of logic input signals (Din 1 , Din 1 ′) corresponds to the storage node voltage of the first storage unit and the second storage unit. The storage node voltage indicates logic "1" when the readout tube TR is turned on, and indicates logic "0" when the readout tube TR is turned off. The second group of logic input signals (Din 2 , Din 2 ′) corresponds to a read word line signal connected to the first storage unit and the second storage unit, and the read word line signal represents a logic "1" when read enabled and a logic "0" when on standby.

[0011] Further, when N=1, the first end of the readout tube TR is a gate, the second end is a drain, and the third end is a source;

[0012] When N=2, the connection method of the two readout tubes TR is: the drain of one readout tube is grounded, the gate is connected to the drain of the write tube TW, and the source is connected to the drain of the other readout tube; the gate of the other readout tube is connected to the read word line, and the source is connected to the read bit line.

[0013] According to a second aspect of the present invention, a logic operation method based on the in-memory logic operation circuit of the first aspect is provided, including a read operation and a logic "not" operation, specifically: a first logic input signal Din 1 (A) Stored to the storage node of the first storage unit, Din 1 (A) The inverted signal input to a storage node of a second storage unit;

[0014] Using the read word line signal connected to the first storage unit as the first storage unit read control signal, and using the read word line signal connected to the second storage unit as the second storage unit read control signal;

[0015] When the first storage unit read control signal is read enable and the second storage unit read control signal is standby, the positive phase output signal of the sense amplifier is the first storage unit read signal Dout (A), and the negative phase output signal is the "not" operation result of the first storage unit.

[0016] When the first storage unit read control signal is standby and the second storage unit read control signal is read enable, the positive phase output signal of the sense amplifier is the second storage unit read signal The inverted output signal is the "not" operation result of the second storage unit.

[0017] Furthermore, it also includes logical "AND / NOT" operation, specifically:

[0018] The first logic input signal Din 1 (A) Stored to the storage node of the first storage unit, Din 1 (A) The inverted signal input to a storage node of a second storage unit;

[0019] The read word line signal connected to the first storage unit is the second logic input signal Din 2 (B), the read word line signal connected to the second storage unit is a standby signal representing a logic "0";

[0020] The sensitive amplifier outputs the logical output potential signal Dout (A·B) with the "AND" and "NAND" being mutually inverted.

[0021] Furthermore, it also includes logical "or / or not" operation, specifically:

[0022] The first logic input signal Din 1 (A) Stored to the storage node of the first storage unit, Din 1 (A) The inverted signal input to a storage node of a second storage unit;

[0023] The read word line signal connected to the first storage unit is a read enable signal representing logic "1", and the read word line signal connected to the second storage unit is a second logic input signal Din 2 ′(B);

[0024] The sense amplifier outputs the logic output potential signal Dout (A+B) which is inverted by "OR" and "NOR".

[0025] Furthermore, it also includes logical "XOR / XOR" operation, specifically:

[0026] The first logic input signal Din 1 (A) Stored to the storage node of the first storage unit, Din 1 (A) The inverted signal input to a storage node of a second storage unit;

[0027] The read word line signal connected to the first storage unit is the second logic input signal Din 2 (B), the read word line signal connected to the second storage unit is Din 2 (B) The inverted signal

[0028] The sensitive amplifier outputs the logical output potential signal Dout (A⊙B) of "XOR" and "XOR" which are mutually inverted.

[0029] According to a third aspect of the present invention, there is provided an in-memory computing system based on DRAM, comprising: at least one in-memory logic computing unit, at least one sense amplifier, a write word line decoding and driving circuit, a write bit line decoding and driving circuit, a read word line decoding and driving circuit, a logic configuration circuit, and a control circuit; wherein the in-memory logic computing unit and the sense amplifier correspond to the in-memory logic computing unit and the sense amplifier described in the first aspect;

[0030] The in-memory logic calculation units are connected to form an array structure, the first storage unit and the second storage unit in the same in-memory logic calculation unit are located in the same column, and the in-memory logic calculation units in each column share the same sense amplifier through a common read bit line, so that each in-memory logic calculation unit in the same column and the sense amplifier in the column can form the in-memory logic operation circuit described in the first aspect, and the in-memory logic calculation units in each column share the same write bit line;

[0031] The first storage unit and the second storage unit in each row of the in-memory logic computing unit use the corresponding read word lines RWL1 and RWL2, and the corresponding write word lines; the in-memory logic computing units in the same row that share the same RWL1 and RWL2 perform logic operations in parallel;

[0032] The write word line decoding and driving circuit is used to convert the external address signal into each write word line signal of the array under the control of the control circuit;

[0033] The write bit line decoding and driving circuit is used to convert the external data signal into each write bit line signal of the array under the control of the control circuit;

[0034] The read word line decoding and driving circuit is used to convert the external address signal into each read word line signal of the array under the control of the control circuit;

[0035] The logic configuration circuit is used to switch the configured logic input signal under the control of the control circuit so that the in-memory logic operation circuit can implement logic operation.

[0036] Further, the logic input signal configuration is performed on the in-memory logic operation circuit, including configuring the first group of logic input signals (Din 1 , Din 1 ′) to configure and the second set of logic input signals (Din 2 , Din 2 ′) is configured to implement any one or more logical operations of reading and logical “NOT” operation, logical “AND / NOT” operation, logical “OR / NOT” operation, and logical “EXCLUSIVE OR / EXCLUSIVE OR” operation;

[0037] Among them, the first group of logic input signals (Din 1 , Din 1 ') is configured to: convert the first logic input signal Din 1 (A) Stored to the storage node of the first storage unit, Din 1 (A) The inverted signal input to a storage node of a second storage unit;

[0038] The second set of logic input signals (Din 2 , Din 2 ′) is configured by connecting the read word lines RWL1 and RWL2 to the first storage unit and the second storage unit to realize the reading and logical “not” operation. The second set of logic input signals (Din 2 , Din 2 ′) is configured as logic "1" and logic "0"; when implementing the logic "AND / NOT" operation, the second group of logic input signals (Din 2 , Din 2 ') is configured as Din 2 (B) and logic "0"; when implementing the logic "OR / NOT" operation, the second group of logic input signals (Din 2 , Din 2 ') is configured as logic "1" and Din 2 '(B); When implementing logical "XOR / XOR", the second set of logic input signals (Din 2 , Din 2 ') is configured as Din 2 (B) and Din 2 (B) The inverted signal

[0039] According to a fourth aspect of the present invention, an in-memory computing hardware accelerator is provided, on which the in-memory computing system based on DRAM according to the third aspect is deployed.

[0040] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0041] (1) The in-memory logic operation circuit based on DRAM in the present invention directly uses DRAM units (first storage units and second storage units) to construct in-memory logic operation units, which will not destroy the conventional access function of DRAM, and realizes in-memory logic operation without modifying the storage unit structure and the read-write circuit. The structure is simple, and the terminal of the write tube TW is directly connected to the write word line and the write bit line, and the terminal of the read tube TR is directly connected to the read word line and the read bit line, so that when it is formed into an array and applied to the in-memory logic operation system, there is no need to change the peripheral circuit structure. In addition, the input of the in-memory logic operation circuit of the present invention is pure digital logic, and there will be no loss of truncation accuracy when performing complex logic operations. Compared with the existing in-memory logic circuit that represents the input value by the pulse width or pulse amplitude of the voltage pulse, it has higher accuracy.

[0042] (2) Furthermore, based on the in-memory logic operation circuit of the present invention, by configuring two groups of logic input signals, one or more of conventional access, "not", "AND / NOT", "OR / NOT" and "XOR / XOR" logic calculations can be implemented.

[0043] (3) Furthermore, the in-memory computing system formed by the in-memory logic operation circuit of the present invention fully utilizes the parallel readout characteristics of the array and realizes parallel computing of logic operations without changing the peripheral circuit structure.

[0044] (4) Furthermore, the in-memory computing system of the present invention is deployed on an in-memory computing hardware accelerator. During the multiplication and accumulation calculation of input data and weight data, the weight data in the DRAM storage array is not destroyed and can be reused in multiple calculation processes, thereby improving the calculation accuracy.

[0045] In summary, the present invention provides an in-memory logic operation circuit solution while maintaining the storage function of the in-memory logic operation circuit, thereby improving the compatibility of the in-memory logic operation and the memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Schematic diagram of the structure of a DRAM-based in-memory logic operation circuit in an embodiment of the present invention;

[0047] Figure 2 A schematic diagram of an in-memory logic operation circuit and an input signal setting scheme based on a 2T DRAM provided in an embodiment of the present invention; wherein: Figure 2 (a) is the in-memory logic operation circuit, and (b) is a schematic diagram of the input signal setting scheme;

[0048] Figure 3 A circuit schematic diagram and truth table for implementing a logic normal read and "not" operation of a DRAM memory logic operation circuit provided by an embodiment of the present invention; wherein, Figure 3 (a) is a schematic diagram of a circuit for realizing conventional logic reading and "not" operation, and (b) is a corresponding truth table;

[0049] Figure 4 A circuit schematic diagram and truth table for implementing logical "AND / NOT" operations in a DRAM memory logic operation circuit provided by an embodiment of the present invention; wherein, Figure 4 (a) is a schematic diagram of a circuit for implementing a logical "AND / NOT" operation, and (b) is a corresponding truth table;

[0050] Figure 5 A circuit diagram and truth table for implementing a logic "OR / NOT" operation of a DRAM in-memory logic operation circuit provided by an embodiment of the present invention; wherein: Figure 5(a) is a schematic diagram of a circuit for implementing a logical "OR / NOT" operation, and (b) is a corresponding truth table;

[0051] Figure 6 A circuit schematic diagram and truth table for implementing a logical "XOR / XOR" operation of a DRAM in-memory logic operation circuit provided by an embodiment of the present invention; wherein, Figure 6 (a) is a schematic diagram of a circuit for implementing a logical "XOR / XOR" operation, and (b) is the corresponding truth table;

[0052] Figure 7 A schematic diagram of a DRAM-based in-memory computing system structure provided in an embodiment of the present invention.

[0053] Figure 8 A schematic diagram of a configuration method for implementing conventional read and logical "NOT", "AND / NOT", "OR / NOT", and "XOR / XOR" operations in a DRAM in-memory computing system provided by an embodiment of the present invention;

[0054] Fig. 9 A schematic diagram of parallel operations using the DRAM in-memory computing system provided by an embodiment of the present invention, taking the multiplication and addition operations of input vectors and weight vectors in a neural network convolution computing application as an example.

[0055] Throughout the drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0056] 1 is a logic calculation unit in memory, 2 is a sense amplifier, 3 is a logic configuration circuit, 4 is a write word line decoding and driving circuit, 5 is a write bit line decoding and driving circuit, 6 is a read word line decoding and driving circuit, 7 is a control circuit; 11 is a first storage unit, 12 is a second storage unit, 111 and 121 are first MOS tubes, and 112 and 122 are second MOS tubes. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0058] In the present invention, the terms "first", "second", etc. in the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0059] Example 1

[0060] like Figure 1As shown, an embodiment of the present invention provides an in-memory logic operation circuit based on DRAM, which mainly includes: an in-memory logic calculation unit 1 based on DRAM, and a sensitive amplifier 2 for generating a logic operation result; the in-memory logic calculation unit 1 includes a first storage unit and a second storage unit connected to a read bit line; wherein the first storage unit and the second storage unit are DRAM units.

[0061] The first storage unit includes a write tube TW and N read tubes TR, and the second storage unit includes a write tube TW and N read tubes TR, N ≥ 1;

[0062] When N=1, the gate of the write transistor TW in the first storage unit or the second storage unit is connected to the write word line, the source is connected to the write bit line, and the drain is connected to the gate of the read transistor TR. The node where the write transistor TW and the read transistor TR are connected is called the storage node; the drain of the read transistor TR is connected to the read word line, and the source is connected to the read bit line;

[0063] When N>1, the gate of the write transistor TW in the first storage unit or the second storage unit is connected to the write word line, the source is connected to the write bit line, and the drain is connected to the first end of the N connected read transistors TR. The connected node is called a storage node; the second end of the N connected read transistors TR is connected to the read word line, and the third end of the N connected read transistors TR is connected to the read bit line;

[0064] After the read bit lines of the first storage unit and the second storage unit are connected together, they are connected to the positive input terminal of the sense amplifier 2; the signal received by the positive input terminal is compared with the reference signal amplitude of the negative input terminal of the sense amplifier 2 to generate a logic operation result; wherein the positive and negative two-phase output signals of the sense amplifier are defined as the positive and negative output results of the logic operation; the signal received by the positive input terminal of the sense amplifier 2 is the current or voltage signal after the logic operation of the first storage unit and the second storage unit.

[0065] It should be noted that, when N>1, the embodiment of the present invention does not limit the connection mode between the N readout tubes TR, as long as the N readout tubes TR can be connected to have the same function as the readout tube TR when N=1. As one implementation mode, when N=2, the connection mode between the two readout tubes TR (denoted as TR1 and TR2) is:

[0066] The drain of the first readout tube TR1 is grounded, the gate is connected to the drain of the write tube TW, the source is connected to the drain of the second readout tube TR2, the gate of the second readout tube TR2 is connected to the read word line, and the source of the second readout tube TR2 is connected to the read bit line.

[0067] As a specific implementation method, the above-mentioned in-memory logic operation circuit defines a group of logic input signals as the voltage level of the storage node, and assumes that the storage node represents logic "1" when the read tube TR is turned on, and represents logic "0" when the read tube TR is turned off; another group of logic input signals is defined as the potential signal input to the read tube TR through the read word line connected to the first storage unit and the second storage unit (that is, the read word line signal connecting the two storage units), and assumes that any potential signal represents logic "1" when it is read enabled, otherwise (that is, when not reading, or in standby) it represents logic "0".

[0068] In each embodiment of the present invention, the gate of the write tube TW is connected to the write word line (Write Word Line, abbreviated as WWL), the source is connected to the write bit line (Write Bit Line, abbreviated as WBL), and the drain is connected to the gate of the read tube TR. The node where the write tube TW is connected to the read tube TR is called a storage node. The drain of the read tube TR is connected to the read word line (Read Word Line, abbreviated as RWL), and the source is connected to the read bit line (Read Bit Line, abbreviated as RBL).

[0069] Let's take N=1 as an example. Figure 2 (a) in FIG. 1 illustrates an example of a DRAM-based in-memory logic operation circuit. Figure 2 The example shown in (b) illustrates the correspondence between physical signals and logical information in a DRAM-based in-memory logic operation circuit.

[0070] like Figure 2As shown in (a), the in-memory logic operation circuit based on DRAM includes an in-memory logic calculation unit 1 based on DRAM, and a sensitive amplifier 2 for generating a logic operation result. The in-memory logic calculation unit 1 includes a first storage unit 11 and a second storage unit 12. The first storage unit is composed of a first MOS transistor 111 (a write transistor of the first storage unit) and a second MOS transistor 112 (a read transistor of the first storage unit), and the drain of the first MOS transistor 111 is connected to the gate of the second MOS transistor 112. The second storage unit is composed of a first MOS transistor 121 (a write transistor of the second storage unit) and a second MOS transistor 122 (a read transistor of the second storage unit), and the drain of the first MOS transistor 121 is connected to the gate of the second MOS transistor 122. The gate terminals of the write tubes of the two groups of storage cells (the first storage cell 11 and the second storage cell 12) are connected to WWL, the source terminals of the write tubes of the two groups of storage cells are connected to WBLL and WBLR respectively, the drain terminals of the read tubes of the two groups of storage cells are connected to RWL1 and RWL2 respectively, the source terminals of the two groups of storage cells are connected and connected to the positive input terminal of the sensitive amplifier 2 through RBL, the signal received at the input terminal is compared with the reference signal received at the inverting input terminal of the sensitive amplifier 2, and the positive and negative two-phase output potential signals of the sensitive amplifier 2 are the current logic output operation results.

[0071] The first set of logic input signals (Din 1 , Din 1 ′) represents the storage node voltage of the first storage unit 11 and the second storage unit 12, a high voltage represents a logic "1", and a low voltage represents a logic "0"; in other embodiments, a high voltage may represent a logic "0", and a low voltage may represent a logic "1", which is related to the transmission characteristics of the MOS tube. The second group of logic input signals (Din 2 , Din 2 ′) respectively represent the signal input from the drain terminal of the first storage unit 11 through the read word line RWL1 and the signal input from the drain terminal of the second storage unit 12 through the read word line RWL2, with the read enable signal representing logic "1" and the standby signal representing logic "0".

[0072] Example 2

[0073] The embodiment of the present invention provides a logic operation method based on the in-memory logic operation circuit in Embodiment 1, involving four logic operations and their corresponding embodiments, namely a "not" operation, an "and / not" operation, an "or / not" operation, and an "exclusive or / exclusive or" operation. Figure 2 , combined with Figure 3-5 , the in-memory logic computing unit based on DRAM in this embodiment is explained.

[0074] By configuring the logic input signal, the in-memory logic operation circuit in the embodiment of the present invention can realize conventional reading and "not" operation at the same time, such as Figure 3 As shown, specifically:

[0075] The first logic input signal Din 1 (A) Stored to the storage node of the first storage unit 11, when N=1, the storage node is the node where the drain of the first MOS tube 111 as a write tube and the gate of the second MOS tube 112 as a read tube in the first storage unit 11 are connected; the first logic input signal ( For Din 1 (A) is stored in the storage node of the second storage unit 12. When N=1, the storage node is the node where the drain of the first MOS transistor 121 as a write transistor and the gate of the second MOS transistor 122 as a read transistor in the second storage unit 12 are connected. 1 (A) and the first logic input signal The signal value corresponds to the conduction level of each readout tube. In the embodiment of the present invention, the signal value of 0 corresponds to the turn-off level of the readout tube, and the signal value of 1 corresponds to the conduction level of the readout tube.

[0076] The read word line signal connected to the first storage unit is used as the first storage unit read control signal, and the read word line signal connected to the second storage unit is used as the second storage unit read control signal. When the first storage unit read control signal is read enable and the second storage unit read control signal is standby, the positive phase output signal of the sense amplifier is the first storage unit read signal, and the negative phase output signal of the sense amplifier is the "not" operation result of the first storage unit. When the first storage unit read control signal is standby and the second storage unit read control signal is read enable, the positive phase output signal of the sense amplifier is the second storage unit read signal, and the negative phase output signal of the sense amplifier is the "not" operation result of the second storage unit. Among them, when read enable, it indicates that the signal value is 1, and when standby, it indicates that the signal value is 0.

[0077] like Figure 3 As shown, the read word line signal connected to the first storage unit is used as the second logic input signal Din 2 (1) The read word line signal connected to the second storage unit is the second logic input signal Din 2 ′(0) as an example, the second logic input signal Din with a signal value of 1 2 (1) Input the drain terminal of the first storage unit 11 through the read word line RWL1; input the second logic input signal Din with a signal value of 0 2'(0) is input to the drain terminal of the second storage unit 12 through the read word line RWL2. The signal value of 1 corresponds to the RWL level being the read enable level, thereby generating a read current corresponding to the storage node level; the signal value of 0 corresponds to the RWL level being the standby level.

[0078] The source terminals of the first storage unit 11 and the second storage unit 12 are connected to the positive input terminal of the sense amplifier 2 through RBL, and the reference signal is connected to the negative input terminal of the sense amplifier 2. The reference signal is configured as a voltage or current signal that can distinguish between 1 and 0 results. The sense amplifier 2 compares the electrical signals at the positive input terminal and the negative input terminal, and generates a logic output potential signal in which the conventional reading result and the "not" operation result are mutually inverted, Dout (A) and

[0079] The present invention provides a DRAM-based in-memory logic operation circuit that can be used to implement logic "AND / NOT" operations. Figure 4 As shown, the specific method is as follows:

[0080] The first logic input signal Din 1 (A) Stored to the storage node of the first storage unit 11, when N=1, the storage node is the node where the drain of the first MOS transistor 111 as a write transistor and the gate of the second MOS transistor 112 as a read transistor in the first storage unit 11 are connected; the first logic input signal Din 1 (A) The inverted signal The storage node of the second storage unit 12 is stored. When N=1, the storage node is a node where the drain of the first MOS transistor 121 as a write transistor and the gate of the second MOS transistor 122 as a read transistor in the first storage unit 12 are connected. The signal value corresponds to the on-level of the read transistor; in the embodiment of the present invention, the signal value of 0 corresponds to the off-level of the read transistor.

[0081] The read word line signal connected to the first storage unit is the second logic input signal Din 2 (B), that is, the second logic input signal Din 2 (B) The drain terminal of the first storage unit 11 is input through RWL1; the read word line signal connected to the second storage unit is a standby signal representing a logic "0", that is, a second logic input signal Din with a signal value of 0 2 '(0) is input to the drain terminal of the second storage unit 12 through RWL2. The signal value of 1 corresponds to the RWL level being the read enable level, thereby generating a read current corresponding to the storage node level; the signal value of 0 corresponds to the RWL level being the standby level.

[0082] The source terminals of the first storage unit 11 and the second storage unit 12 are connected to the positive input terminal of the sense amplifier 2 through RBL. The reference signal is connected to the negative input terminal of the sense amplifier 2. The reference signal is configured as a voltage or current signal that can distinguish between 1 and 0 results. The sense amplifier 2 compares the electrical signals at the positive input terminal and the negative input terminal to generate "AND" and "NAND" mutually inverted logic output potential signals, Dout (A·B) and

[0083] The embodiment of the present invention provides a DRAM-based in-memory logic operation circuit that can be used to implement a logic "OR / NOT" operation. Figure 5 As shown, the specific method is as follows:

[0084] The first logic input signal Din 1 (A) Stored to the storage node of the first storage unit 11, when N=1, the storage node is the node where the drain of the first MOS transistor 111 as a write transistor and the gate of the second MOS transistor 112 as a read transistor in the first storage unit 11 are connected; the first logic input signal Din 1 (A) The inverted signal The storage node of the second storage unit 12 is stored. When N=1, the storage node is a node where the drain of the first MOS transistor 121 as a write transistor and the gate of the second MOS transistor 122 as a read transistor in the first storage unit 12 are connected. The signal value corresponds to the on-level of the read transistor; the signal value of 0 corresponds to the off-level of the read transistor.

[0085] The read word line signal connected to the first storage unit is a read enable signal representing a logic "1", that is, the second logic input signal Din with a signal value of 1 2 (1) The drain terminal of the first storage unit 11 is input through RWL1; the read word line signal connected to the second storage unit is the second logic input signal Din 2 '(B), that is, the second logic input signal Din 2 '(B) is input to the drain terminal of the second storage unit 12 through RWL2. The signal value of 1 corresponds to the RWL level being the read enable level, thereby generating a read current corresponding to the storage node level; in the embodiment of the present invention, the signal value of 0 corresponds to the RWL level being the standby level.

[0086] The source terminals of the first storage unit 11 and the second storage unit 12 are connected to the positive input terminal of the sense amplifier 2 through RBL, and the reference signal is connected to the negative input terminal of the sense amplifier 2. The reference signal is configured as a voltage or current signal that can distinguish between 1 and 0 results. The sense amplifier 2 compares the electrical signals at the positive input terminal and the negative input terminal to generate "OR" and "NOR" mutually inverted logic output potential signals, Dout (A+B) and

[0087] The present invention provides a DRAM-based in-memory logic operation circuit that can be used to implement a logic "XOR / XOR" operation. Figure 6 As shown, the specific method is as follows:

[0088] The first logic input signal Din 1 (A) Stored to the storage node of the first storage unit 11, when N=1, the storage node is the node where the drain of the first MOS transistor 111 as a write transistor and the gate of the second MOS transistor 112 as a read transistor in the first storage unit 11 are connected; the first logic input signal Din 1 (A) The inverted signal The storage node of the second storage unit 12 is stored. When N=1, the storage node is a node where the drain of the first MOS transistor 121 as a write transistor and the gate of the second MOS transistor 122 as a read transistor in the first storage unit 12 are connected. The signal value corresponds to the on-level of the read transistor; in the embodiment of the present invention, the signal value of 0 corresponds to the off-level of the read transistor.

[0089] The read word line signal connected to the first storage unit is the second logic input signal Din 2 (B), that is, the second logic input signal Din 2 (B) The drain terminal of the first storage unit 11 is input through RWL1; the read word line signal connected to the second storage unit is the second logic input signal Din 2 (B) The inverted signal The second logic input signal Din 2 (B) The inverted signal The drain terminal of the second storage unit 12 is input through RWL2. The signal value of 1 corresponds to the RWL level being the read enable level, thereby generating a read current corresponding to the storage node level; the signal value of 0 corresponds to the RWL level being the standby level.

[0090] The source terminals of the first storage unit 11 and the second storage unit 12 are connected to the positive input terminal of the sense amplifier 2 through RBL, and the reference signal is connected to the negative input terminal of the sense amplifier 2. The reference signal is configured as a voltage or current signal that can distinguish between 1 and 0 results. The sense amplifier 2 compares the electrical signals at the positive input terminal and the negative input terminal to generate "XOR" and "XOR" logic output potential signals that are inverted from each other, Dout (A⊙B) and

[0091] Example 3

[0092] like Figure 7As shown, an embodiment of the present invention provides an in-memory computing system based on DRAM, comprising at least one in-memory logic computing unit 1 ( Figure 7 The DRAM CIM cell in the embodiment 1 includes a sense amplifier 2 (SA) in the in-memory logic operation circuit in at least one of the above-mentioned embodiments 1, a write word line decoding and driving circuit 4, a write bit line decoding and driving circuit 5, a read word line decoding and driving circuit 6, a logic configuration circuit 3, and a control circuit 7.

[0093] The in-memory logic calculation units 1 are connected to form an array structure, and two storage units (the first and second storage units) of the same in-memory logic calculation unit 1 are located in the same column. The in-memory logic calculation units of each column share the same sense amplifier through a shared read bit line, so that each in-memory logic calculation unit 1 of the same column and the sense amplifier 2 of the column can form the in-memory logic operation circuit in the above-mentioned embodiment 1, and the in-memory logic calculation units 1 of each column share the same write bit line; the first storage unit and the second storage unit in the in-memory logic calculation unit 1 of each row use a corresponding read word line respectively, and the two read word lines are respectively called RWL1 and RWL2; the first storage unit and the second storage unit in the in-memory logic calculation unit 1 of each row use a corresponding write word line respectively, and the two write word lines are respectively called WWL1 and WWL2; the in-memory logic operation units 1 of the same row that share the same RWL1 and RWL2 can perform logical operations in parallel;

[0094] The write word line decoding and driving circuit is used to convert the external address signal into each write word line signal of the array under the control of the control circuit;

[0095] The write bit line decoding and driving circuit is used to convert the external data signal into each write bit line signal of the array under the control of the control circuit;

[0096] The read word line decoding and driving circuit is used to convert the external address signal into each read word line signal of the array under the control of the control circuit;

[0097] The logic configuration circuit is used to switch the conventional reading and logic calculation tasks of the in-memory logic operation circuit under the control of the control circuit; specifically, by configuring the logic input signal of the in-memory logic operation circuit to realize any one or more logic operations of conventional access and NOT, AND / NAND, OR / NOT, XOR / XOR.

[0098] The control circuit is used to control the various circuit parts of the in-memory computing system.

[0099] See also Figure 2The in-memory computing system shows an in-memory logic operation circuit based on two groups of two-transistor DRAMs and sense amplifiers. It can be understood that the in-memory computing system in this embodiment can also include other forms of in-memory logic operation circuits, such as two groups of three-transistor DRAMs and sense amplifiers.

[0100] like Figure 8 As shown, as a preferred implementation, the logic configuration circuit configures the logic input signal of the in-memory logic operation circuit, including:

[0101] For the first set of logic input signals, the charge level stored in the storage unit is configured during writing through the corresponding write bit line connected to the internal logic operation unit (the first storage unit and the second storage unit). 1 (A) is stored in the storage node of the first storage unit 11, and the first logic input signal ( For Din 1 (A) is stored in the storage node of the second storage unit 12.

[0102] For the second set of logic input signals, the read bit lines connected through the first and second storage cells are configured during readout. Specifically:

[0103] Access and NOT operation: symbol m1 indicates that the DRAM cells (first storage cell 11 or second storage cell 12) directly form an array to perform a normal access operation or a "NOT" operation. The control circuit 7 controls the logic configuration circuit 3 to select the signal value of logic 1 and the signal value of logic 0 to RWL1 and RWL2 respectively, and directly applies the single column selection read enable signal generated by address decoding required for normal reading to the drain terminal of the readout tube, which is used to enable the reading of data in the normal access operation.

[0104] XOR operation: symbol m2 indicates that every two DRAM cells (first storage cell 11 and second storage cell 12) form a group, and together with the sense amplifier 2, form an in-memory logic operation circuit. The two DRAM storage cells are respectively based on the first storage cell 11 and the second storage cell 12 in the in-memory logic operation circuit, and the control circuit 7 controls the logic configuration circuit 3 to select the second logic input signal Din 2 (B) To RWL1, select the inverted signal of the second logic input signal To RWL2, RWL1 and RWL2 apply input signals to the two DRAM cells through the readout tube drain terminal.

[0105] AND operation: symbol m3 indicates that every two DRAM cells (first storage cell 11 and second storage cell 12) form a group, and together with the sense amplifier 2, form an in-memory logic operation circuit. The two DRAM storage cells are respectively based on the first storage cell 11 and the second storage cell 12 in the in-memory logic operation circuit, and the control circuit 7 controls the logic configuration circuit 3 to select the second logic input signal Din 2 (B) To RWL1, a signal with a logic 0 is selected to RWL2, and RWL1 and RWL2 apply input signals to the two DRAM cells through the drain terminal of the sense tube.

[0106] OR operation: symbol m4 indicates that every two DRAM cells (first storage cell 11 and second storage cell 12) form a group, and together with the sense amplifier 2, form an in-memory logic operation circuit. The two DRAM storage cells are respectively based on the first storage cell 11 and the second storage cell 12 in the in-memory logic operation circuit, and the control circuit 7 controls the logic configuration circuit 3 to select the signal with a logic value of 1 to RWL1, and selects the second logic input signal Din 2 '(B) To RWL2, RWL1 and RWL2 apply input signals to the two DRAM cells through the sense tube drain terminals.

[0107] Example 4

[0108] An embodiment of the present invention provides an in-memory computing hardware accelerator, on which the DRAM-based in-memory computing system in Example 3 is deployed, and can implement various algorithm calculations taking neural networks as an example.

[0109] Specifically, the multiplication and accumulation calculation is decomposed into step-by-step logical calculation to realize the multiplication and accumulation calculation of input data and weight data in the neural network. During each calculation process, the weight data in the DRAM storage array is not destroyed and can be reused in multiple calculation processes.

[0110] like Fig. 9 As shown, the multiplication and addition operation of input vector and weight vector w is performed in the neural network convolution calculation application. 1 ·in 1 +w 2 ·in 1 As an example, it is explained that the DRAM-based in-memory computing system provided in the embodiment of the present invention can realize DRAM-based weight non-destructive parallel computing. The specific steps are as follows: split the multiplication and addition operations and first complete w in the first and second in-memory computing circuits. 1 ·in 1 and w 2 ·in 1The two parts are "AND" operated, and then the results of the "AND" operation are added, and the "AND" result operation is completed in the third memory calculation circuit. The fourth in-memory calculation circuit completes the "carry" result operation C = (w 1 ·in 1 )·(w 2 ·in 1 ).

[0111] In the first and second in-memory logic operation circuits, the positive and negative two-phase weight combination is represented as a potential signal stored in the DRAM unit, and the controller controls the positive and negative two-phase values ​​of different weights of the neural network to be written into the DRAM unit at the corresponding position through the WBL, such as Fig. 9 middle As shown; the positive and negative two-phase input combination is represented as the potential signal of the array RWL, and the controller controls the positive input and logic 0 to pass through the RWL input array, such as Fig. 9 in 1 ,0) as shown; share the same set of RWL, that is, share the same set (in i ,0) The data storage logic operation circuit can perform "AND / NOT" operations in parallel, and generate logic operation output potential signals in parallel through different RBLs connected to different sensitive amplifiers, such as Fig. 9 Medium 1 ·in 1 and w 2 ·in 1 As shown. It can also be seen that during the calculation process, the weights stored in the DRAM unit Will not be destroyed and can be repeated with different groups (in i ,in i ′ ) data for calculation.

[0112] In the third in-memory logic operation circuit, the positive and negative phases are ANDed together. 1 ·in 1 It is represented as the potential signal stored in the DRAM unit. The controller controls the positive and negative phase "AND" operation results to be written into the DRAM unit at the corresponding position through WBL, such as Fig. 9 middle As shown; the result of the positive and negative phase "AND" operation Represented as the potential signal of the array RWL, it is input into the array through RWL, such as Fig. 9 As shown in; connected to the sense amplifier through RBL to generate "XOR / XOR" logic operation output potential signal, such as Fig. 9 middle shown.

[0113] In the fourth in-memory logic operation circuit, the positive and negative phases of the "AND" operation result w 1 ·in1 It is represented as the potential signal stored in the DRAM unit. The controller controls the positive and negative phase "AND" operation results to be written into the DRAM unit at the corresponding position through WBL, such as Fig. 9 middle As shown; the positive phase "AND" operation result and logic 0, that is, (w 2 ·in 1 ,0) is represented as the potential signal of the array RWL, which is input into the array through RWL, such as Fig. 9 As shown in; connected to the sense amplifier through RBL to generate "AND / NOT" logic operation output potential signal, such as Fig. 9 C=(w 1 ·in 1 )·(w 2 ·in 1 ) as shown.

[0114] In summary, the in-memory logic operation circuit provided by the present invention includes two DRAM units and a sensitive amplifier for generating a logic operation result. The in-memory logic operation circuit defines a set of logic input signals as the storage content of the DRAM unit, another set of logic input signals as the read control signal of the circuit, and the bi-phase output signal of the sensitive amplifier as the positive and negative output results of the logic operation. The present invention provides an in-memory logic calculation compatible with the DRAM storage array, which realizes the in-memory logic calculation without destroying the conventional access function, without modifying the storage unit and the array structure and the read-write circuit, and does not need to introduce additional computing elements and complex computing circuits in the array, and has a simple structure and low computing overhead. The in-memory logic operation circuit and in-memory computing system compatible with the storage function of the present invention are a differential DRAM in-memory logic (DRAM-based Differential Logic in Memory, DRAM-DLIM), which can improve the reliability of the DRAM storage computing system.

[0115] The provided DRAM-based logic operation circuit has logic operation functions, and can realize "not", "and / not", "or / not" and "exclusive or / exclusive or" logic calculations, and on this basis, a complex logic operation system can be constructed.

[0116] The in-memory computing system of the present invention fully utilizes the parallel readout characteristics of the array to realize parallel computing of logical operations.

[0117] Different from the existing method of representing input values ​​by pulse width or pulse amplitude of voltage pulses, the logic operation input provided by the present invention is pure digital logic, which can complete operations such as bit-by-bit multiplication and bit-by-bit search of fixed-point numbers without loss of precision, and has higher precision than complex operations.

[0118] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A DRAM-based in-memory logic operation circuit, characterized in that: include: An in-memory logic computing unit and a sense amplifier based on DRAM; wherein the in-memory logic computing unit comprises a first storage unit and a second storage unit; The first storage unit and the second storage unit both include a write transistor TW and N connected read transistors TR, N≥1; the gate of the write transistor TW is connected to the write word line, the source is connected to the write bit line, and the drain is connected to the first end of the N connected read transistors TR, and the connected node is a storage node; the second end of the N connected read transistors TR is connected to the read word line, and the third end is connected to the read bit line; After the read bit lines of the first storage unit and the second storage unit are connected together, they are connected to the positive input terminal of the sense amplifier; the signal received by the positive input terminal is compared with the reference signal received by the inverting input terminal of the sense amplifier to generate a logic operation result; Among them, the first group of logic input signals (Din1, Din1′) of the in-memory logic operation circuit corresponds to the storage node voltages of the first storage unit and the second storage unit, and the storage node voltages represent logic "1" when the read tube TR is turned on, and represent logic "0" when the read tube TR is turned off; the second group of logic input signals (Din2, Din2′) correspond to the read word line signals connected to the first storage unit and the second storage unit, and the read word line signals represent logic "1" when read enable, and represent logic "0" when on standby.

2. The in-memory logic operation circuit according to claim 1, characterized in that: When N=1, the first end of the readout tube TR is the gate, the second end is the drain, and the third end is the source; When N=2, the connection method of the two readout tubes TR is: the drain of one readout tube is grounded, the gate is connected to the drain of the write tube TW, and the source is connected to the drain of the other readout tube; the gate of the other readout tube is connected to the read word line, and the source is connected to the read bit line.

3. A logic operation method based on the in-memory logic operation circuit according to claim 1 or 2, characterized in that: It includes a read operation and a logic "not" operation, specifically: storing the first logic input signal Din1(A) to the storage node of the first storage unit, and inputting the inverted signal Din1'(A) of Din1(A) to the storage node of the second storage unit; Using the read word line signal connected to the first storage unit as the first storage unit read control signal, and using the read word line signal connected to the second storage unit as the second storage unit read control signal; When the first storage unit read control signal is read enable and the second storage unit read control signal is standby, the positive phase output signal of the sense amplifier is the first storage unit read signal Dout (A), and the negative phase output signal is the "not" operation result of the first storage unit. When the first storage unit read control signal is standby and the second storage unit read control signal is read enable, the positive phase output signal of the sense amplifier is the second storage unit read signal The inverted output signal is the "not" operation result of the second storage unit.

4. The logic operation method according to claim 3, characterized in that: It also includes logical "AND / NOT" operations, specifically: The first logic input signal Din1(A) is stored in the storage node of the first storage unit, and the inverted signal of Din1(A) is stored in the storage node of the first storage unit. input to a storage node of a second storage unit; The read word line signal connected to the first storage unit is the second logic input signal Din2 (B), and the read word line signal connected to the second storage unit is a standby signal representing logic "0"; The sensitive amplifier outputs the logical output potential signal Dout (A·B) with "AND" and "NAND" being mutually inverted.

5. The logic operation method according to claim 3 or 4, characterized in that: It also includes logical "or / or not" operations, specifically: The first logic input signal Din1(A) is stored in the storage node of the first storage unit, and the inverted signal of Din1(A) is stored in the storage node of the first storage unit. input to a storage node of a second storage unit; The read word line signal connected to the first storage unit is a read enable signal representing a logic "1", and the read word line signal connected to the second storage unit is a second logic input signal Din2'(B); The sense amplifier outputs the logic output potential signal Dout (A+B) which is inverted by "OR" and "NOR".

6. The logic operation method according to claim 5, characterized in that: It also includes logical "XOR / XOR" operations, specifically: The first logic input signal Din1(A) is stored in the storage node of the first storage unit, and the inverted signal of Din1(A) is stored in the storage node of the first storage unit. input to a storage node of a second storage unit; The read word line signal connected to the first storage unit is the second logic input signal Din2(B), and the read word line signal connected to the second storage unit is the inverted signal of Din2(B). The sensitive amplifier outputs the logical output potential signal Dout (A⊙B) of "XOR" and "XOR" which are mutually inverted.

7. A DRAM-based in-memory computing system, characterized in that: include: At least one in-memory logic calculation unit, at least one sense amplifier, a write word line decoding and driving circuit, a write bit line decoding and driving circuit, a read word line decoding and driving circuit, a logic configuration circuit, and a control circuit; wherein the in-memory logic calculation unit and the sense amplifier correspond to the in-memory logic calculation unit and the sense amplifier according to claim 1 or 2; The in-memory logic calculation units are connected to form an array structure, the first storage unit and the second storage unit in the same in-memory logic calculation unit are located in the same column, and the in-memory logic calculation units in each column share the same sensitive amplifier through a shared read bit line, so that each in-memory logic calculation unit in the same column and the sensitive amplifier in the column can form the in-memory logic operation circuit according to claim 1 or 2, and the in-memory logic calculation units in each column share the same write bit line; The first storage unit and the second storage unit in each row of the in-memory logic computing unit use the corresponding read word lines RWL1 and RWL2, and the corresponding write word lines; the in-memory logic computing units in the same row that share the same RWL1 and RWL2 perform logic operations in parallel; The write word line decoding and driving circuit is used to convert the external address signal into each write word line signal of the array under the control of the control circuit; The write bit line decoding and driving circuit is used to convert the external data signal into each write bit line signal of the array under the control of the control circuit; The read word line decoding and driving circuit is used to convert the external address signal into each read word line signal of the array under the control of the control circuit; The logic configuration circuit is used to switch the configured logic input signal under the control of the control circuit so that the in-memory logic operation circuit can implement logic operation.

8. The DRAM-based in-memory computing system according to claim 7, characterized in that: Configuring the logic input signal of the in-memory logic operation circuit includes configuring the first group of logic input signals (Din1, Din1′) and configuring the second group of logic input signals (Din2, Din2′) to implement any one or more logic operations of reading and logic "not" operation, logic "and / not" operation, logic "or / not" operation, and logic "exclusive or / exclusive or" operation; The first group of logic input signals (Din1, Din1′) is configured as follows: the first logic input signal Din1(A) is stored in the storage node of the first storage unit, and the inverted signal of Din1(A) is stored in the storage node of the first storage unit. input to a storage node of a second storage unit; The second group of logic input signals (Din2, Din2′) are configured through the read word lines RWL1 and RWL2 connected to the first storage unit and the second storage unit. When reading and logic "not" operations are implemented, the second group of logic input signals (Din2, Din2′) are configured as logic "1" and logic "0"; when implementing logic "and / and-not" operations, the second group of logic input signals (Din2, Din2′) are configured as Din2(B) and logic "0"; when implementing logic "or / or-not" operations, the second group of logic input signals (Din2, Din2′) are configured as logic "1" and Din2′(B); when implementing logic "exclusive or / exclusive or", the second group of logic input signals (Din2, Din2′) are configured as Din2(B) and the inverted signals of Din2(B) 9. An in-memory computing hardware accelerator, characterized in that: The in-memory computing hardware accelerator is deployed with the DRAM-based in-memory computing system described in claim 7 or 8.

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