Verilog-A Model Optimization Method, Device, Probability Calculation Unit, and Method for Simulating Neuron Characteristics

Abstract

The present invention provides a Verilog-A model optimization method, device, probability calculation unit and method for simulating neuron characteristics, including: establishing an equivalent model of a neuron based on a volatile memristor; simulating the dynamic characteristics of the volatile memristor, the first correspondence between the conduction probability and the input pulse amplitude, the second correspondence between the conduction speed and the input pulse frequency, and the third correspondence between the conduction frequency, the conduction current and the gate voltage; based on the dynamic characteristics, the first correspondence, the second correspondence and the third correspondence of the volatile memristor, debugging the parameters of the Verilog-A model of the neuron based on the volatile memristor, so that the dynamic characteristics, the first correspondence, the second correspondence and the third correspondence of the volatile memristor are consistent with the experimental characteristics of the neuron based on the volatile memristor. The present invention can enhance the high-order neuron performance of the volatile memristor model and contribute to the simulation implementation of large-scale memristor neural network circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of new circuit element models, and particularly to a Verilog-A model optimization method, device, probability calculation unit and method for simulating neuron characteristics. Background Art

[0002] With the rapid development of computationally intensive technologies such as neural networks, scientists are attempting to implement neural networks in circuits. Traditional CMOS circuits are difficult to meet the requirements of large-scale neural networks due to their high complexity and high power consumption when simulating neuron behavior.

[0003] Currently, researchers are exploring new computing elements in order to achieve dynamic characteristics and efficiency closer to biological nervous systems. Volatile memristors, due to their unique memory-computation integrated characteristics and the ability to simulate dynamic behaviors of neurons such as adjustable threshold voltages and signal processing capabilities, have become important research objects in this field.

[0004] However, although previous studies have attempted to simulate the basic behavior of memristors through various methods, these models often fail to fully consider the dynamics and adjustability of volatile memristors in practical applications, as well as the accuracy and flexibility when simulating complex neural network behaviors. Therefore, before applying volatile memristors to actual neural networks, their high-order neural characteristics cannot be accurately captured. Summary of the Invention

[0005] The present invention provides a Verilog-A model optimization method, device, probability calculation unit and method for simulating neuron characteristics, to solve the defect that the high-order neural characteristics of volatile memristors cannot be accurately captured before applying them to actual neural networks in the prior art, and to meet the requirements of constructing efficient and low-power artificial neural networks by realizing more accurate simulation and high adjustability of the adjustable neuron model based on volatile memristors.

[0006] The present invention provides a Verilog-A model optimization method for simulating neuron characteristics, including:

[0007] Establish an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model includes the top electrode port, bottom electrode port and gate electrode port of the volatile memristor, and the top electrode port and bottom electrode port control the process of filament growth or fracture inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of filament growth or fracture inside the volatile memristor by applying different voltages;

[0008] Simulate the dynamic characteristics of the volatile memristor, wherein the dynamic characteristics include the processes of filament growth, conduction, retention and fracture inside the volatile memristor;

[0009] Simulate the first correspondence between the conduction probability of the volatile memristor and the input pulse amplitude;

[0010] Simulate the second correspondence between the conduction speed of the volatile memristor and the input pulse frequency;

[0011] Simulate the third correspondence between the conduction frequency, conduction current of the volatile memristor and the gate voltage;

[0012] Based on the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence, perform parameter debugging on the Verilog-A model of the neuron based on the volatile memristor, so that the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0013] According to the Verilog-A model optimization method for simulating neuron characteristics provided by the present invention, the steps of simulating the dynamic characteristics of the volatile memristor specifically include:

[0014] Preset a threshold voltage V hold , apply a varying voltage difference V tb between the top electrode port and the bottom electrode port to simulate the dynamic characteristics of the volatile memristor;

[0015] When V tb is higher than V hold , and V tb gradually increases, the filaments inside the volatile memristor start to grow until conduction occurs, the current surges, and more filaments are conducted;

[0016] When V tb gradually decreases, the filaments inside the volatile memristor start to break, and when the last conducting filament breaks, the current suddenly decreases.

[0017] According to the Verilog-A model optimization method for simulating neuron characteristics provided by the present invention, the steps of simulating the first correspondence between the conduction probability of the volatile memristor and the input pulse amplitude specifically include:

[0018] With the gate voltage maintained at 0V, apply multiple voltage pulses with different preset amplitudes to the top electrode port of the volatile memristor to obtain the first correspondence between the conduction probability of the volatile memristor and the voltage pulse amplitude.

[0019] According to the Verilog-A model optimization method for simulating neuron characteristics provided by the present invention, the steps of simulating the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency specifically include:

[0020] Under the conditions of the same gate voltage, input pulse width, and input pulse amplitude, voltage pulses with different frequencies are applied to the top electrode port to simulate the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency.

[0021] According to the Verilog-A model optimization method for simulating neuron characteristics provided by the present invention, the steps of simulating the third corresponding relationship between the conduction frequency, conduction current of the volatile memristor, and the gate voltage specifically include:

[0022] Under the condition of applying the same input voltage to the top electrode port, different gate voltages are applied to the gate electrode port to simulate the third corresponding relationship between the conduction frequency, conduction current of the volatile memristor, and the gate voltage.

[0023] According to the Verilog-A model optimization method for simulating neuron characteristics provided by the present invention, the steps of parameter debugging for the Verilog-A model of the neuron based on the volatile memristor specifically include:

[0024] S61. Debug the parameters in the growth formula of the conductive filament so that the influence of the growth of the conductive filament by the top electrode and gate electrode voltages is consistent with the actual experimental results;

[0025] S62. Debug the parameters in the fracture formula of the conductive filament so that the degree and probability of fracture of the conductive filament when the top electrode voltage drops back are consistent with the actual experimental results under the influence of the top electrode and gate electrode voltages;

[0026] S63. Debug the parameters of the conduction current formula when the conductive filament conducts so that the influence of the conduction current by the top electrode and gate electrode voltages at different stages is consistent with the actual experimental results.

[0027] The present invention also provides a probability calculation unit, including: a volatile memristor, a voltage comparator, a load resistor, and a reference voltage terminal;

[0028] Wherein, the volatile memristor includes a top electrode port, a bottom electrode port, and a gate electrode port. The top electrode port and the bottom electrode port control the process of the growth or fracture of the internal filament of the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of the growth or fracture of the internal filament of the volatile memristor by applying different voltages;

[0029] The volatile memristor is debugged for parameters by the Verilog-A model optimization method for simulating neuron characteristics as described in any one of the above.

[0030] The bottom electrode of the volatile memristor is connected to the positive electrode of the voltage comparator, and the negative electrode of the voltage comparator is connected to the reference voltage terminal.

[0031] According to the probability calculation unit provided by the present invention, in the simulation of the probability calculation algorithm, the probability calculation unit is used as a true random number generator with controllable probability.

[0032] The present invention also provides a probability calculation method, which is implemented by the probability calculation unit as described in any one of the above. The method includes:

[0033] Adjust the input voltage of the top electrode of the volatile memristor to simulate the fourth corresponding relationship between the output voltage of the probability calculation unit and the input voltage of the top electrode.

[0034] According to the fourth corresponding relationship, fit to obtain the relationship curve between the output voltage of the probability calculation unit and the input voltage of the top electrode of the volatile memristor.

[0035] The present invention also provides a Verilog-A model optimization device for simulating neuron characteristics, including:

[0036] An equivalent model establishment module for establishing an equivalent model of a neuron based on a volatile memristor. The equivalent model includes a top electrode port, a bottom electrode port, and a gate electrode port of the volatile memristor. The top electrode port and the bottom electrode port control the process of filament growth or breakage inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of filament growth or breakage inside the volatile memristor by applying different voltages.

[0037] A first simulation module for simulating the dynamic characteristics of the volatile memristor. The dynamic characteristics include the processes of filament growth, conduction, retention, and breakage inside the volatile memristor.

[0038] A second simulation module for simulating the first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude.

[0039] A third simulation module for simulating the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency.

[0040] A fourth simulation module for simulating the third corresponding relationship between the conduction frequency, conduction current of the volatile memristor and the gate voltage.

[0041] A parameter debugging module, configured to perform parameter debugging on a Verilog-A model of a neuron based on a volatile memristor according to the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence, and the third correspondence, so that the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence, and the third correspondence are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0042] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the Verilog-A model optimization method for simulating neuron characteristics or the probability calculation method as described above is implemented.

[0043] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the Verilog-A model optimization method for simulating neuron characteristics or the probability calculation method as described above is implemented.

[0044] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, the Verilog-A model optimization method for simulating neuron characteristics or the probability calculation method as described above is implemented.

[0045] The Verilog-A model optimization method, device, probability calculation unit, and method for simulating neuron characteristics provided by the present invention comprehensively consider factors such as the design of the Verilog-A model for simulating neuron characteristics, the dynamic characteristics of the volatile memristor, and the regulation of the gate voltage, can accurately capture the growth and fracture process of the memristor filament, and thus accurately represent neuron characteristics consistent with experimental data; compared with other volatile memristor calculation models, the present invention reduces the complexity of volatile memristor state calculation, considers the regulation properties of the gate electrode, enhances the performance of higher-order neurons of the volatile memristor model, and helps the simulation implementation of large-scale memristor neural network circuits. Description of the Drawings

[0046] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0047] Figure 1 It is a schematic flowchart of the Verilog-A model optimization method for simulating neuron characteristics provided by an embodiment of the present invention.

[0048] Figure 2 The I-V curve diagram of the volatile memristor provided by the embodiment of the present invention and the particle growth states in each stage.

[0049] Figure 3 The simplified growth and fracture logic of the filaments provided by the embodiment of the present invention.

[0050] Figure 4 The conduction characteristics of the volatile memristor provided by the embodiment of the present invention under different input pulse amplitudes.

[0051] Figure 5 The conduction characteristics of the volatile memristor provided by the embodiment of the present invention under different input intervals.

[0052] Figure 6 The conduction characteristics of the volatile memristor provided by the embodiment of the present invention under different gate voltages.

[0053] Figure 7 The structural schematic diagram of the probability calculation unit provided by the embodiment of the present invention.

[0054] Figure 8 The output voltage V in the probability calculation unit provided by the embodiment of the present invention out varies with the input voltage V in trend diagram.

[0055] Figure 9 The schematic diagram of the two-dimensional Metropolis-Hastings algorithm simulation performed using the Verilog-A model for simulating neuron characteristics provided by the embodiment of the present invention.

[0056] Figure 10 The structural schematic diagram of the Verilog-A model optimization device for simulating neuron characteristics provided by the embodiment of the present invention.

[0057] Figure 11 The structural schematic diagram of the electronic device provided by the present invention. Detailed implementation manners

[0058] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts fall within the scope of protection of the present invention.

[0059] The present invention will be specifically described below in conjunction with the accompanying drawings of the specification. The specific operation methods in the method embodiments can also be applied to the apparatus embodiments or system embodiments. In the description of the present invention, unless otherwise specified, "at least one" includes one or more. "Plurality" means two or more. For example, at least one of A, B, and C includes: A alone, B alone, A and B present simultaneously, A and C present simultaneously, B and C present simultaneously, and A, B, and C present simultaneously. In the present invention, " / " means "or". For example, A / B can represent A or B; "and / or" herein is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B present simultaneously, and B alone.

[0060] The present invention will be specifically described below in conjunction with the specific implementation manners.

[0061] In some specific implementation manners of the present invention, as Figure 1 shown, the present solution provides a method for optimizing a Verilog-A model simulating neuron characteristics, including the following steps:

[0062] Step 100: Establish an equivalent model of a neuron based on a volatile memristor. Wherein, the equivalent model includes a top electrode port, a bottom electrode port, and a gate electrode port of the volatile memristor. The top electrode port and the bottom electrode port control the process of filament growth or fracture inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of filament growth or fracture inside the volatile memristor by applying different voltages;

[0063] Step 200: Simulate the dynamic characteristics of the volatile memristor. Wherein, the dynamic characteristics include the processes of filament growth, conduction, retention, and fracture inside the volatile memristor;

[0064] Step 300: Simulate the first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude;

[0065] Step 400: Simulate the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency;

[0066] Step 500: Simulate the third corresponding relationship between the conduction frequency, conduction current of the volatile memristor and the gate voltage;

[0067] Step 600: Based on the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence, and the third correspondence, perform parameter debugging on the Verilog-A model of the neuron based on the volatile memristor, so that the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence, and the third correspondence are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0068] It should be noted that the existing basic behavior simulation schemes of memristors cannot achieve real-time adjustment, and it is difficult to accurately simulate the dynamics and adjustability of volatile memristors in practical applications. The simulation efficiency is low, and it is difficult to meet the requirements of accuracy and flexibility when simulating the behavior of complex neural networks.

[0069] Therefore, the present invention constructs a new adjustable neuron model based on a volatile memristor, that is, the Verilog-A model of the neuron based on the volatile memristor as described above, to meet the needs of constructing an efficient and low-power artificial neural network through more accurate simulation and high adjustability.

[0070] In some possible embodiments of the present invention, the step of simulating the dynamic characteristics of the volatile memristor specifically includes:

[0071] Preset a threshold voltage V hold , apply a varying voltage difference V tb between the top electrode port and the bottom electrode port to simulate the dynamic characteristics of the volatile memristor;

[0072] When V tb is higher than V hold , and V tb is gradually increasing, the filaments inside the volatile memristor start to grow until they conduct, the current surges, and more filaments are conducted;

[0073] When V tb is gradually decreasing, the filaments inside the volatile memristor start to break, and when the last conducting filament breaks, the current suddenly decreases.

[0074] Specifically, this embodiment provides an implementation manner for simulating the dynamic characteristics of the volatile memristor. By applying a varying voltage difference V tb between the top electrode port and the bottom electrode port, and simulating the dynamic characteristics of the volatile memristor according to the comparison result between V tb and the preset threshold voltage V hold .

[0075] In possible embodiments, as Figure 2 shown, Figure 2I-V curve of the volatile memristor provided by the embodiment of the present invention and the particle growth states in each stage Figure 2 shows the implementation logic of the Verilog-A model that uses a volatile memristor to simulate neuron characteristics, including processes such as the growth, conduction, retention, and rupture of filaments. When the voltage difference (V tb ) between the top electrode and the bottom electrode is higher than V hold , filaments start to grow until conduction causes a sudden increase in current. Subsequently, more filaments are conducted, as shown in Figure 1 (e), (c), (d), corresponding to the filament growth process; as V tb decreases, the filaments start to rupture. When the last conducting filament ruptures, the current suddenly decreases, as shown in Figure 1 (c), (b), (a), corresponding to the filament rupture process.

[0076] Furthermore, during the processes of filament growth, conduction, retention, and rupture, the implementation of the gate voltage will affect memristor properties such as the conduction speed, rupture speed, and rupture degree of the filaments, thereby changing the excitability or inhibitory property of the neurons.

[0077] It can be clearly seen from (b) in Figure 2 that the parameter "gjump" decreases. The parameter "gjump" is used to characterize the influence of different numbers of connected conductive filaments on the current increment. The decrease of this parameter represents a certain degree of weakening effect on the current due to the decrease in the number of conductive filaments conducted before the rupture of the last conductive filament.

[0078] It can be clearly seen from (c) in Figure 2 that as the voltage difference between the top electrode and the bottom electrode increases, more conductive filaments appear in this volatile memristor.

[0079] It can be clearly seen from (d) in Figure 2 that when the voltage difference between the top electrode and the bottom electrode reaches a preset voltage threshold, this volatile memristor is in a low-resistance state and a conductive current flows through.

[0080] It can be clearly seen from (e) in Figure 2 that during the process of gradually increasing the voltage between the top electrode and the bottom electrode, the filaments in this memristor start to grow and the current is weak. At this time, the memristor is in a high-resistance state.

[0081] In a possible embodiment, at a higher gate voltage, the rupture of the filaments is more severe.

[0082] The above process can also be illustrated by the simplified growth and rupture logic of the filaments. Figure 3 The simplified growth and rupture logic of the filaments provided by the embodiment of the present invention is as shown in Figure 3As shown, first, determine the voltage difference (V tb ) between the top electrode and the bottom electrode of the volatile memristor to see if it is higher than the preset holding voltage threshold V hold . When it is determined that V tb is higher than V hold , it is determined that the filaments of the volatile memristor start to grow; otherwise, it is determined that the filaments in the volatile memristor start to dissolve. When it is determined that V tb is higher than V hold , determine whether the conductive gap in the volatile memristor is the minimum gap. If so, determine to pass the conductive current; otherwise, pass the weak current.

[0083] With the above settings in the embodiments of the present invention, the growth and breakage of filaments can be directly estimated without solving equations, reducing the computational amount and showing neuron-like properties.

[0084] In some possible embodiments of the present invention, the step of simulating the first correspondence between the conduction probability of the volatile memristor and the input pulse amplitude specifically includes:

[0085] With the gate voltage maintained at 0V, apply a plurality of voltage pulses with different preset amplitudes to the top electrode port of the volatile memristor to obtain the first correspondence between the conduction probability of the volatile memristor and the voltage pulse amplitude.

[0086] Specifically, this embodiment provides an implementation manner of simulating the relationship between the conduction probability of the volatile memristor and the input pulse amplitude. By applying a plurality of voltage pulses with different preset amplitudes to the top electrode port, the correspondence between the conduction probability of the volatile memristor and the input pulse amplitude is simulated.

[0087] In a possible embodiment, as Figure 4 shown, Figure 4 is the conduction characteristic of the volatile memristor provided in the embodiments of the present invention under different input pulse amplitudes. Figure 4 shows the memristor current under different input pulse amplitudes. By applying pulses with a period of 10 ms and a duty cycle of 40% of 2.6V, 2.4V, 2.2V, and 2.0V to the top electrode of the memristor and keeping the gate voltage at 0V, the result that the conduction probability of the memristor decreases as the input amplitude decreases is finally obtained.

[0088] In some possible embodiments of the present invention, the step of simulating the second correspondence between the conduction speed of the volatile memristor and the input pulse frequency specifically includes:

[0089] With the same gate voltage, input pulse width, and input pulse amplitude, apply voltage pulses with different frequencies to the top electrode port to simulate the second correspondence between the conduction speed of the volatile memristor and the input pulse frequency.

[0090] Specifically, this embodiment provides an implementation manner for simulating the relationship between the conduction speed of a volatile memristor and the input pulse frequency. By applying voltage pulses with different frequencies to the top electrode port, the corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency is simulated.

[0091] In a possible embodiment, as Figure 5 shown, Figure 5 are the conduction characteristics of the volatile memristor provided by the embodiment of the present invention at different input intervals, Figure 5 showing the memristor current at different input intervals. By changing the input frequencies to 150 Hz, 100 Hz, and 50 Hz at the same gate voltage, input pulse width, and input amplitude, the result that the smaller the input interval, the faster the memristor conducts is finally obtained.

[0092] In some possible implementation manners of the present invention, the step of simulating the third corresponding relationship between the conduction frequency, conduction current of the volatile memristor and the gate voltage specifically includes:

[0093] When applying the same input voltage to the top electrode port, different gate voltages are applied to the gate electrode port to simulate the third corresponding relationship between the conduction frequency, conduction current of the volatile memristor and the gate voltage.

[0094] Specifically, this embodiment provides an implementation manner for simulating the relationship between the conduction frequency, conduction current of a volatile memristor and the gate voltage. By applying different gate voltages to the gate electrode port, the corresponding relationship between the conduction frequency, conduction current of the volatile memristor and the gate voltage is simulated.

[0095] In a possible embodiment, as Figure 6 shown, Figure 6 are the conduction characteristics of the volatile memristor provided by the embodiment of the present invention at different gate voltages, Figure 6 showing the conduction characteristics at the same gate voltage. By changing the gate voltage from 0 to -4V at the same input (amplitude 3V, period 10 ms, duty cycle 50%), the result that the higher the gate voltage, the higher the conduction frequency and conduction current is finally obtained.

[0096] In some possible implementation manners of the present invention, the step of parameter debugging for the Verilog-A model of the neuron based on the volatile memristor specifically includes:

[0097] Step 61, debugging the parameters in the growth formula of the conductive filament so that the influence of the growth of the conductive filament by the voltages of the top electrode and the gate electrode is consistent with the actual experimental results;

[0098] Step 62: Debug the parameters in the breaking formula of the conductive filament so that the degree of breakage and the probability of breakage of the conductive filament when the top electrode voltage drops back are affected by the voltages of the top electrode and the gate electrode in a manner consistent with the actual experimental results;

[0099] Step 63: Debug the parameters in the conduction current formula when the conductive filament is conducting so that the influence of the conduction current on the voltages of the top electrode and the gate electrode at different stages is consistent with the actual experimental results.

[0100] Specifically, this embodiment provides an implementation method for parameter debugging of the Verilog-A model of a neuron based on a volatile memristor. By finely adjusting the key parameters such as the growth, breakage, and conduction current of the conductive filament in the volatile memristor of the Verilog-A model, the behavior of the simulation model can accurately reproduce the memristor conduction characteristics observed in actual experiments under different electrode voltage conditions, thereby ensuring the reliability of the simulation results and a high degree of consistency with physical devices. With the above settings in the embodiments of the present invention, the neuron characteristics are consistent with the experimental data after parameter debugging and can be applied to large-scale circuit simulations.

[0101] The Verilog-A model optimization method for simulating neuron characteristics provided by the embodiments of the present invention takes into account the growth and breakage of the filaments of the volatile memristor, the dynamic characteristics of the device, and the regulation of the gate voltage; it takes into account the regulation process of the neuron by the gate voltage. A lower gate voltage results in a smaller conduction current, a greater probability of filament breakage, and a stronger degree of breakage. It takes into account the dynamic characteristics of the device. The filament growth process and the degree of breakage both exhibit a certain degree of randomness, and the probability is regulated by the voltages of the three ports. It reduces the computational complexity of the volatile memristor calculation, enhances the performance of the high-order neurons of the volatile memristor model, and helps the simulation implementation of large-scale memristor neural network circuits.

[0102] In some specific implementation schemes of the present invention, this solution provides an equivalent model of a neuron based on a volatile memristor, including: a top electrode port, a bottom electrode port, and a gate electrode port;

[0103] Among them, the top electrode port and the bottom electrode port are used to control the growth or breakage of the filaments of the volatile memristor;

[0104] The gate electrode port is used to control the speed and degree of growth or breakage of the filaments of the volatile memristor.

[0105] Specifically, this embodiment provides an implementation manner of an equivalent model of a neuron based on a volatile memristor. By setting top electrode and bottom electrode ports for controlling the growth or breakage of the memristor filament, and a gate electrode for controlling the degree of neuron inhibition or excitation, the growth and breakage of the volatile memristor filament, the dynamic characteristics of the device, and the regulation of the gate voltage are considered in the model. By applying different gate voltages through the gate electrode port, the corresponding relationship between the conduction frequency, conduction current of the volatile memristor and the gate voltage is simulated, and the real-time tunability of the volatile memristor is realized.

[0106] Furthermore, by directly estimating the growth and breakage of the filament, without solving equations, the computational amount is reduced, and the volatile memristor exhibits neuron-like properties. Therefore, the complexity of the volatile memristor calculation is reduced, the high-order neuron performance of the volatile memristor model is enhanced, which is helpful for the simulation implementation of large-scale memristor neural network circuits.

[0107] The Verilog-A model optimization method for simulating neuron characteristics provided by the embodiments of the present invention considers factors such as the design of the cation-based volatile memristor model, the dynamic characteristics of the device, and the regulation of the gate voltage. By simulating the growth and breakage process of the cation-based memristor filament, the high-order characteristics of neurons can be accurately realized, so as to achieve the purpose of large-scale neural network circuit simulation.

[0108] In some specific implementation manners of the present invention, such as Figure 7 shown, this solution provides a probability calculation unit, including: a volatile memristor, a voltage comparator, a load resistor, and a reference voltage terminal;

[0109] Among them, the volatile memristor includes a top electrode port, a bottom electrode port, and a gate electrode port. The top electrode port and the bottom electrode port control the process of the growth or breakage of the filament inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of the growth or breakage of the filament inside the volatile memristor by applying different voltages;

[0110] The parameters of the volatile memristor are debugged by the Verilog-A model optimization method for simulating neuron characteristics in any of the above embodiments;

[0111] The bottom electrode of the volatile memristor is connected to the positive electrode of the voltage comparator, and the negative electrode of the voltage comparator is connected to the reference voltage terminal.

[0112] In some specific implementation manners of the present invention, a probability calculation method is also provided. This method is implemented by the probability calculation unit described in the above embodiments. The method includes:

[0113] Adjust the input voltage of the top electrode of the volatile memristor to simulate the fourth corresponding relationship between the output voltage of the probability calculation unit and the input voltage of the top electrode;

[0114] According to the fourth corresponding relationship, fit to obtain the relationship curve between the output voltage of the probability calculation unit and the input voltage of the top electrode of the volatile memristor.

[0115] Specifically, this embodiment provides an implementation manner of a probability calculation method. By using a volatile memristor in a probability calculation unit, a relationship curve between the output voltage and the input voltage of the probability calculation unit is fitted.

[0116] In a possible embodiment, as Figure 8 shown, Figure 8 is the trend chart of the output voltage V out changing with the input voltage V in provided by the probability calculation unit of the embodiment of the present invention, which shows the change trend of Vout with Vin in the probability calculation unit. By applying different input voltage amplitudes in the Figure 8 probability calculation unit, different V Figure 7 average values are obtained, and an S curve can be obtained after fitting. out

[0117] In some possible implementation manners of the present invention, the probability calculation unit is used as a true random number generator with controllable probability in the probability calculation algorithm simulation.

[0118] Figure 9 In a possible embodiment, as Figure 9 shown, Figure 9 is a schematic diagram of the two-dimensional Metropolis-Hastings algorithm simulation using the Verilog-A model provided by the embodiment of the present invention. It can be seen from Figure 9 that in the two-dimensional Metropolis-Hastings algorithm simulation using this Verilog-A model, the probability calculation unit composed of this Verilog-A model can be used as a true random number generator with controllable probability for probability calculation algorithm simulation.

[0119] The embodiment of the present invention provides a new and efficient method for the simulation and parameter debugging of large-scale memristor neural network circuits by introducing a Verilog-A model of an adjustable neuron based on a volatile memristor, which not only greatly improves the calculation efficiency, but also can accurately express the high-order characteristics of neurons, shows simulation results highly consistent with experimental data, and reveals its wide application potential in probability calculation circuit simulation.

[0120] In some implementation manners of the present invention, as Figure 10As shown, there is also provided an optimization device for a Verilog-A model simulating neuron characteristics, including:

[0121] An equivalent model establishment module 1001, configured to establish an equivalent model of a neuron based on a volatile memristor. Among them, the equivalent model includes a top electrode port, a bottom electrode port, and a gate electrode port of the volatile memristor. The top electrode port and the bottom electrode port control the process of filament growth or fracture inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of filament growth or fracture inside the volatile memristor by applying different voltages.

[0122] A first simulation module 1002, configured to simulate the dynamic characteristics of the volatile memristor. Among them, the dynamic characteristics include the processes of filament growth, conduction, retention, and fracture inside the volatile memristor.

[0123] A second simulation module 1003, configured to simulate a first correspondence between the conduction probability of the volatile memristor and the input pulse amplitude.

[0124] A third simulation module 1004, configured to simulate a second correspondence between the conduction speed of the volatile memristor and the input pulse frequency.

[0125] A fourth simulation module 1005, configured to simulate a third correspondence between the conduction frequency, conduction current of the volatile memristor, and the gate voltage.

[0126] A parameter debugging module 1006, configured to perform parameter debugging on the Verilog-A model of the neuron based on the volatile memristor according to the dynamic characteristics, the first correspondence, the second correspondence, and the third correspondence of the volatile memristor, so that the dynamic characteristics, the first correspondence, the second correspondence, and the third correspondence of the volatile memristor are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0127] Figure 11 The schematic diagram of the physical structure of an electronic device is exemplified, as Figure 11As shown in the figure, the electronic device may include: a processor 1110, a communications interface 1120, a memory 1130, and a communication bus 1140. Among them, the processor 1110, the communications interface 1120, and the memory 1130 complete communication with each other through the communication bus 1140. The processor 1010 can call the logical instructions in the memory 1130 to execute a Verilog-A model optimization method for simulating the characteristics of neurons. The method includes: establishing an equivalent model of a neuron based on a volatile memristor, where the equivalent model includes the top electrode port, the bottom electrode port, and the gate electrode port of the volatile memristor, and the top electrode port and the bottom electrode port control the process of filament growth or fracture inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of filament growth or fracture inside the volatile memristor by applying different voltages; simulating the dynamic characteristics of the volatile memristor, where the dynamic characteristics include the processes of filament growth, conduction, retention, and fracture inside the volatile memristor; simulating the first correspondence between the conduction probability of the volatile memristor and the input pulse amplitude; simulating the second correspondence between the conduction speed of the volatile memristor and the input pulse frequency; simulating the third correspondence between the conduction frequency, conduction current of the volatile memristor, and the gate voltage; based on the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence, and the third correspondence, debugging the parameters of the Verilog-A model of the neuron based on the volatile memristor, so that the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence, and the third correspondence are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0128] In addition, when the logical instructions in the above-mentioned memory 1130 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0129] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the Verilog-A model optimization method for simulating neuron characteristics provided by the above various methods. The method includes: establishing an equivalent model of a neuron based on a volatile memristor, where the equivalent model includes a top electrode port, a bottom electrode port, and a gate electrode port of the volatile memristor, and the top electrode port and the bottom electrode port control the process of filament growth or breakage inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of filament growth or breakage inside the volatile memristor by applying different voltages; simulating the dynamic characteristics of the volatile memristor, where the dynamic characteristics include the processes of filament growth, conduction, retention, and breakage inside the volatile memristor; simulating a first correspondence between the conduction probability of the volatile memristor and the input pulse amplitude; simulating a second correspondence between the conduction speed of the volatile memristor and the input pulse frequency; simulating a third correspondence between the conduction frequency, conduction current of the volatile memristor, and the gate voltage; based on the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence, and the third correspondence, performing parameter debugging on the Verilog-A model of the neuron based on the volatile memristor, so that the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence, and the third correspondence are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0130] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the Verilog-A model optimization method for simulating neuron characteristics provided by the above-mentioned various methods. The method includes: establishing an equivalent model of a neuron based on a volatile memristor, where the equivalent model includes a top electrode port, a bottom electrode port, and a gate electrode port of the volatile memristor, and the top electrode port and the bottom electrode port control the process of filament growth or fracture inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of filament growth or fracture inside the volatile memristor by applying different voltages; simulating the dynamic characteristics of the volatile memristor, where the dynamic characteristics include the processes of filament growth, conduction, retention, and fracture inside the volatile memristor; simulating a first correspondence relationship between the conduction probability of the volatile memristor and the input pulse amplitude; simulating a second correspondence relationship between the conduction speed of the volatile memristor and the input pulse frequency; simulating a third correspondence relationship between the conduction frequency, conduction current of the volatile memristor and the gate voltage; based on the dynamic characteristics of the volatile memristor, the first correspondence relationship, the second correspondence relationship, and the third correspondence relationship, performing parameter debugging on the Verilog-A model of the neuron based on the volatile memristor, so that the dynamic characteristics of the volatile memristor, the first correspondence relationship, the second correspondence relationship, and the third correspondence relationship are consistent with the experimental characteristics of the neuron based on the volatile memristor.

[0131] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0132] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Verilog-A model optimization method for simulating neuron characteristics, characterized in that: include: Establish an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model includes a top electrode port, a bottom electrode port and a gate electrode port of the volatile memristor, and the top electrode port and the bottom electrode port control the process of growth or breakage of the filaments inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of growth or breakage of the filaments inside the volatile memristor by applying different voltages; Simulating dynamic characteristics of the volatile memristor, wherein the dynamic characteristics include the growth, conduction, retention and breaking process of the filaments inside the volatile memristor; Simulating a first corresponding relationship between a turn-on probability of the volatile memristor and an input pulse amplitude; Simulating a second corresponding relationship between a conduction speed of the volatile memristor and an input pulse frequency; Simulating a third corresponding relationship among the conduction frequency, conduction current and gate voltage of the volatile memristor; Based on the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence, parameters of the Verilog-A model of the neuron based on the volatile memristor are debugged to make the dynamic characteristics of the volatile memristor, the first correspondence, the second correspondence and the third correspondence consistent with the experimental characteristics of the neuron based on the volatile memristor.

2. The Verilog-A model optimization method for simulating neuron characteristics according to claim 1, characterized in that: The step of simulating the dynamic characteristics of the volatile memristor specifically comprises: Preset threshold voltage V hold , a varying voltage difference V is applied between the top electrode port and the bottom electrode port tb , to simulate the dynamic characteristics of the volatile memristor; When V tb Higher than V hold , and V tb When the current gradually increases, the filaments inside the volatile memristor begin to grow until they are turned on, the current increases suddenly, and more filaments are turned on; When V tb As the current gradually decreases, the filaments inside the volatile memristor begin to break, and when the last conductive filament breaks, the current drops sharply.

3. The Verilog-A model optimization method for simulating neuron characteristics according to claim 2, characterized in that: The step of simulating a first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude specifically includes: When the gate voltage is kept at 0V, a plurality of voltage pulses with different preset amplitudes are applied to the top electrode port of the volatile memristor to obtain a first corresponding relationship between the conduction probability of the volatile memristor and the voltage pulse amplitude.

4. The Verilog-A model optimization method for simulating neuron characteristics according to claim 3, characterized in that: The step of simulating the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency specifically includes: Under the condition of the same gate voltage, input pulse width and input pulse amplitude, voltage pulses of different frequencies are applied to the top electrode port to simulate the second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency.

5. The Verilog-A model optimization method for simulating neuron characteristics according to claim 1, characterized in that: The step of simulating a third corresponding relationship between the on-frequency, on-current and the gate voltage of the volatile memristor specifically includes: When the same input voltage is applied to the top electrode port, different gate voltages are applied to the gate electrode port to simulate a third corresponding relationship among the conduction frequency, conduction current and the gate voltage of the volatile memristor.

6. The Verilog-A model optimization method for simulating neuron characteristics according to any one of claims 1 to 5, characterized in that: The step of performing parameter debugging on the Verilog-A model of the neuron based on the volatile memristor specifically includes: S61, adjusting the parameters in the growth formula of the conductive filaments so that the growth of the conductive filaments is affected by the voltage of the top electrode and the gate electrode in accordance with the actual experimental results; S62, adjusting the parameters in the fracture formula of the conductive filament so that the fracture degree and fracture probability of the conductive filament are affected by the voltage between the top electrode and the gate electrode when the top electrode voltage drops, which are consistent with the actual experimental results; S63. Adjust the parameters of the on-current formula when the conductive filament is turned on, so that the influence of the top electrode and gate electrode voltages on the on-current at different stages is consistent with the actual experimental results.

7. A probability calculation unit, characterized in that: include: A volatile memristor, a voltage comparator, a load resistor and a reference voltage terminal; wherein the volatile memristor comprises a top electrode port, a bottom electrode port and a gate electrode port, and the top electrode port and the bottom electrode port control the process of the growth or breaking of the filaments inside the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of the growth or breaking of the filaments inside the volatile memristor by applying different voltages; The volatile memristor is parameter-adjusted by the Verilog-A model optimization method for simulating neuron characteristics according to any one of claims 1 to 6; The bottom electrode of the volatile memristor is connected to the positive electrode of the voltage comparator, and the negative electrode of the voltage comparator is connected to the reference voltage terminal.

8. The probability calculation unit according to claim 7, characterized in that: The probability calculation unit is used as a true random number generator with controllable probability in the probability calculation algorithm simulation.

9. A probability calculation method, characterized in that: The method is implemented by the probability calculation unit according to claim 7 or 8, and comprises: adjusting the input voltage of the top electrode of the volatile memristor to simulate a fourth corresponding relationship between the output voltage of the probability calculation unit and the input voltage of the top electrode; According to the fourth corresponding relationship, a relationship curve between the output voltage of the probability calculation unit and the input voltage of the top electrode of the volatile memristor is obtained by fitting.

10. A Verilog-A model optimization device for simulating neuron characteristics, characterized in that: include: An equivalent model establishment module, used to establish an equivalent model of a neuron based on a volatile memristor, wherein the equivalent model includes a top electrode port, a bottom electrode port and a gate electrode port of the volatile memristor, the top electrode port and the bottom electrode port control the process of growth or breakage of the internal filaments of the volatile memristor by applying different voltages; the gate electrode port controls the speed and degree of growth or breakage of the internal filaments of the volatile memristor by applying different voltages; A first simulation module, used to simulate the dynamic characteristics of the volatile memristor, wherein the dynamic characteristics include the growth, conduction, retention and breaking process of the filament inside the volatile memristor; A second simulation module, used for simulating a first corresponding relationship between the conduction probability of the volatile memristor and the input pulse amplitude; A third simulation module, used to simulate a second corresponding relationship between the conduction speed of the volatile memristor and the input pulse frequency; A fourth simulation module, used to simulate a third corresponding relationship between the conduction frequency, the conduction current and the gate voltage of the volatile memristor; A parameter debugging module is used to perform parameter debugging on the Verilog-A model of the neuron based on the volatile memristor based on the dynamic characteristics of the volatile memristor, the first corresponding relationship, the second corresponding relationship and the third corresponding relationship, so that the dynamic characteristics of the volatile memristor, the first corresponding relationship, the second corresponding relationship and the third corresponding relationship are consistent with the experimental characteristics of the neuron based on the volatile memristor.

Images