Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, the display panel comprises a gate drive circuit, a pull-down capacitor is arranged in the gate drive circuit, at least one of a first node and a second node is electrically connected with a first pole plate of the pull-down capacitor, and a second pole plate of the pull-down capacitor is electrically connected with a low-potential power supply end. By arranging the pull-down capacitor between at least one of the first node and the second node and the low-potential power supply end, the capability of maintaining the first node and / or the second node at a low potential can be improved through the pull-down capacitor, the capability of maintaining other nodes and the signal output end at a low potential is improved, the pull-down speed is improved, and the power consumption is reduced. The low potential maintaining capability is improved, and the pull-down maintaining capability is increased by the pull-down capacitor, so that the channel width of transistors in the pull-down maintaining module and the anti-phase module can be properly reduced, the electric leakage is reduced, and the low electric leakage and low potential maintaining capability of the gate driving circuit are considered.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] GOA (Gate On Array, array substrate row drive) technology refers to a driving method for realizing row-by-row scanning of the gate by making the gate row scanning drive signal on the array substrate. Since the GOA technology can omit the gate drive chip and the circuit board, save the space of the gate drive chip and the circuit board, and can realize a narrow frame, the GOA technology is widely used in display panels. In the existing gate drive circuit, a pull-down maintenance module is used to maintain the pull-down state of the output end and the node of the gate drive circuit, and in order to increase the pull-down speed of the pull-down maintenance module, the channel width of the transistor in the pull-down maintenance module is increased, but in actual use, it is found that due to the large channel width of the transistor of the pull-down maintenance module, the leakage of the transistor of the pull-down maintenance module is more serious. When the node in the gate drive circuit outputs a high potential, due to the influence of leakage, the node of the gate drive circuit cannot maintain a high potential, resulting in the gate drive circuit being unable to output the scan signal normally, thereby causing display abnormality. Reducing the channel width of the transistor of the pull-down maintenance module will result in a poor pull-down maintenance effect of the pull-down maintenance module.

[0003] Therefore, the existing gate driving circuit has a technical problem that the pull-down maintenance module cannot take into account both low leakage and low potential maintenance capabilities. Summary of the invention

[0004] The embodiments of the present application provide a suspension motor, which improves the safety of the suspension motor and at least partially solves the above technical problems.

[0005] In order to achieve the above object, according to a first aspect of the present application, a display panel is provided, the display panel comprising: a plurality of cascaded gate drive circuits, each of the gate drive circuits comprising:

[0006] a pull-up module, electrically connected to the first node, the pull-up module being configured to connect the clock signal line with the signal output end of the gate driving circuit of this stage, or disconnect the electrical connection between the clock signal line and the signal output end according to the potential of the first node;

[0007] A pull-down maintaining module, electrically connected to the first node and the low potential power supply terminal;

[0008] an inverting module, one end of which is electrically connected to the first node, and the other end of which is electrically connected to the pull-down maintaining module at a second node, and the inverting module is configured to control the pull-down maintaining module to connect the low potential power supply end with the first node, or disconnect the electrical connection between the low potential power supply end and the first node according to the potential of the first node;

[0009] The gate drive circuit further includes a pull-down capacitor, at least one of the first node and the second node is electrically connected to a first plate of the pull-down capacitor, and a second plate of the pull-down capacitor is electrically connected to the low potential power supply terminal.

[0010] According to a second aspect of the present application, a display device is provided, comprising a display panel as described in any one of the above embodiments.

[0011] The embodiments of the present application provide a display panel and a display device, wherein the display panel includes a gate driving circuit, and a pull-down capacitor is provided in the gate driving circuit so that at least one of the first node and the second node is electrically connected to the first electrode plate of the pull-down capacitor, and the second electrode plate of the pull-down capacitor is electrically connected to the low potential power supply terminal. By providing a pull-down capacitor between at least one of the first node and the second node and the low potential power supply terminal, the ability to maintain the first node and / or the second node at a low potential can be improved through the pull-down capacitor, and the ability to maintain other nodes and the signal output terminal at a low potential is improved, the pull-down speed is improved, and the ability to maintain a low potential is improved. Moreover, since the pull-down capacitor increases the pull-down maintenance capability, the channel width of the transistors in the pull-down maintenance module and the inversion module can be appropriately reduced, thereby reducing leakage, thereby taking into account both the low leakage and low potential maintenance capabilities of the gate driving circuit.

[0012] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0014] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0015] Figure 1 A circuit diagram of a gate driving circuit of a comparative display device provided in an embodiment of the present application.

[0016] Figure 2 A schematic diagram of dividing a frame time under different touch modes provided in an embodiment of the present application.

[0017] Figure 3 The comparative display device provided in the embodiment of the present application adopts Figure 2 When one of the touch modes is used, a timing diagram showing abnormal display appears.

[0018] Figure 4 A schematic plan view of a display panel provided in an embodiment of the present application.

[0019] Figure 5 A first circuit diagram of a gate drive circuit provided in an embodiment of the present application.

[0020] Figure 6 A second circuit diagram of the gate drive circuit provided in an embodiment of the present application.

[0021] Figure 7 A third circuit diagram of the gate drive circuit provided in an embodiment of the present application.

[0022] Figure 8 A first cross-sectional schematic diagram of a display panel provided in an embodiment of the present application.

[0023] Fig. 9 A schematic diagram of a first stacking method of a display panel provided in an embodiment of the present application.

[0024] Fig.10 for Fig. 9 An exploded view of the gate layer and active layer of the display panel in FIG.

[0025] Fig.11 for Fig. 9 Exploded view of the source / drain layer and pixel conductive layer of the display panel.

[0026] Fig.12 A second cross-sectional schematic diagram of a display panel provided in an embodiment of the present application.

[0027] Fig.13 A schematic diagram of a second stacking method of a display panel provided in an embodiment of the present application.

[0028] Fig.14 for Fig.13 An exploded view of the gate layer and active layer of the display panel in FIG.

[0029] Fig.15 for Fig.13 Exploded view of the source / drain layer and pixel conductive layer of the display panel. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0031] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "electrically connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0032] In order to illustrate the principle of the technical problem of the present application, a comparative display device is provided. It is understandable that the comparative display device cannot be used as the prior art in the embodiments of the present application. Figure 1 As shown, a gate driving circuit in a comparative display device includes a first transistor T11a, a second transistor T21a, a third transistor T32a, a fourth transistor T42a and a capacitor Cba, the gate of the first transistor T11a and the first electrode of the first transistor T11a are connected to the output terminal G(N-1)a of the previous stage gate driving circuit, the second electrode of the first transistor T11a, the gate of the second transistor T21a, one plate of the capacitor Cba and the second electrode of the fourth transistor T42a are connected to the first point Qa, the first electrode of the second transistor T21a is connected to the clock line CKa, the second electrode of the second transistor T21a, the other plate of the capacitor Cba and the second electrode of the third transistor T32a are connected to the output terminal G(N)a of the current stage gate driving circuit, the gate of the third transistor T32a and the gate of the fourth transistor T42a are connected to the second point Ka or the third point Pa, and the first electrode of the third transistor T32a and the first electrode of the fourth transistor T42a are connected to the low potential line VSSa. The third transistor T32a is used to maintain the output terminal G(N)a at a low potential, and the fourth transistor T42a is used to maintain the first point Qa at a low potential. By testing the gate drive circuit, it is found that the larger the channel width of the third transistor T32a and the fourth transistor T42a, the better their ability to maintain a low potential.

[0033] At the same time, in order to realize the touch function, the comparative display device divides a frame into a display time period D and a touch time period T, such as Figure 2 As shown, Figure 2(a) is a schematic diagram of the time division of a frame when there is no touch. Figure 2 As can be seen from (a) in the figure, a frame can be divided into a display time period D and a blank time period B. Figure 2 (b) is a schematic diagram of time division of a frame when there is touch control. Figure 2 As can be seen from (b) in the figure, touch control is performed during the blank time period B of a frame. This solution is relatively Figure 2 (a) in the above equation can be considered as simply extending the blank time period B. Figure 2 (c) in FIG. 1 is another time division diagram of a frame when there is touch control. Figure 2 As can be seen in (c), a frame is divided into multiple display time periods D and multiple touch time periods T, and different touch electrodes are scanned in different time periods, so as to realize multiple reporting points in one frame and realize high-frequency touch.

[0034] In comparison, the display device uses Figure 2 In the touch mode (c) in FIG. 1 , it can be seen that there is a long touch time period between adjacent display time periods. At this time, the gate drive circuit needs to be suspended. During this time, the potential of the first point Qa needs to be maintained at a high potential. However, in actual use, it is found that the first point Qa cannot maintain a high potential in a high temperature environment. Figure 3 As shown, it can be seen that in the touch time period T, the potential of the first point Qa should be maintained at a high potential, but in fact it cannot be maintained at a high potential, resulting in an abnormal signal output to the scan line Gate, resulting in abnormal display. By testing the gate drive circuit, it was found that this was due to the large channel width of the second transistor T21a, the third transistor T32a and the fourth transistor T42a, resulting in serious leakage. Therefore, the existing gate drive circuit has a technical problem that the pull-down maintenance module cannot take into account both low leakage and low potential maintenance capabilities.

[0035] The embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0036] Figure 4 A schematic plan view of a display panel provided in an embodiment of the present application. Figure 5 A first circuit diagram of a gate drive circuit provided in an embodiment of the present application. Figure 6 A second circuit diagram of the gate drive circuit provided in an embodiment of the present application. Figure 7 A third circuit diagram of the gate drive circuit provided in an embodiment of the present application. Figure 8 A first cross-sectional schematic diagram of a display panel provided in an embodiment of the present application. Fig. 9 A schematic diagram of a first stacking method of a display panel provided in an embodiment of the present application. Fig.10 for Fig. 9 An exploded view of the gate layer and active layer of the display panel in FIG. Fig.10 (a) in Fig. 9 An exploded view of a gate layer of a display panel; Fig.10 (b) in Fig. 9 An exploded view of the active layer of a display panel. Fig.11 for Fig. 9 An exploded view of the source / drain electrode layer and the pixel conductive layer of the display panel; Fig.11 (a) in Fig. 9 An exploded view of the source and drain layers of the display panel; Fig.11 (b) in Fig. 9 An exploded view of the pixel conductive layer of the display panel in FIG. Fig.12 A second cross-sectional schematic diagram of a display panel provided in an embodiment of the present application. Fig.13 A schematic diagram of a second stacking method of a display panel provided in an embodiment of the present application. Fig.14 for Fig.13 An exploded view of the gate layer and active layer of the display panel in FIG. Fig.14 (a) in Fig.13 An exploded view of a gate layer of a display panel; Fig.14 (b) in Fig.13 An exploded view of the active layer of a display panel. Fig.15 for Fig.13 An exploded view of the source / drain electrode layer and the pixel conductive layer of the display panel; Fig.15 (a) in Fig.13 An exploded view of the source and drain layers of the display panel; Fig.15 (b) in Fig.13 An exploded view of the pixel conductive layer of the display panel in FIG.

[0037] like Figures 4 to 15As shown, the embodiment of the present application provides a display panel, the display panel 1 includes a plurality of cascaded gate drive circuits 21, each of the gate drive circuits 21 includes a pull-up module 211, a pull-down maintenance module 212 and an inversion module 213, the pull-up module 211 is electrically connected to a first node Q, and the pull-up module 211 is configured to connect a clock signal line CK with a signal output terminal G(N) of the gate drive circuit 21 at this stage according to the potential of the first node Q, or disconnect the clock signal line CK from the signal output terminal G(N). The pull-down maintaining module 212 is electrically connected to the first node Q and the low potential power supply terminal VSS; one end of the inverting module 213 is electrically connected to the first node Q, and the other end of the inverting module 213 is connected to the pull-down maintaining module 212 at a second node K, and the inverting module 213 is configured to control the pull-down maintaining module 212 to connect the low potential power supply terminal VSS and the first node Q, or disconnect the electrical connection between the low potential power supply terminal VSS and the first node Q according to the potential of the first node Q;

[0038] The gate drive circuit 21 further includes a pull-down capacitor 214, at least one of the first node Q and the second node K is electrically connected to a first plate of the pull-down capacitor 214, and a second plate of the pull-down capacitor 214 is electrically connected to the low potential power supply terminal VSS.

[0039] An embodiment of the present application provides a display panel, which includes a gate driving circuit. By setting a pull-down capacitor in the gate driving circuit, at least one of the first node Q and the second node K is electrically connected to the first plate of the pull-down capacitor, and the second plate of the pull-down capacitor is electrically connected to the low potential power supply terminal. By setting a pull-down capacitor between at least one of the first node Q and the second node K and the low potential power supply terminal, the ability to maintain the first node Q and / or the second node K at a low potential can be improved by the pull-down capacitor, and the ability to maintain other nodes and the signal output terminal at a low potential is improved, the pull-down speed is improved, and the ability to maintain a low potential is improved. Since the pull-down capacitor increases the pull-down maintenance capability, the channel width of the transistors in the pull-down maintenance module and the inversion module can be appropriately reduced, thereby reducing leakage, thereby taking into account the low leakage and low potential maintenance capabilities of the gate driving circuit.

[0040] Specifically, it can be understood that, due to the overlap between the gate and the source (or drain) in each transistor, a capacitor will be formed between the two. The embodiment of the present application has been found through testing that when the channel width of the transistor in the pull-down maintenance module is larger, the leakage in a high temperature environment is more serious, and when the capacitance formed by the gate and the source (or drain) of the transistor in the pull-down maintenance module is smaller, the leakage in a high temperature environment is more serious, and it is found that the smaller the proportion of the capacitance formed by the gate and the source of the transistor in the pull-up module to the total capacitance (the sum of the capacitances in the circuit), the smaller the leakage. Therefore, it can be known that increasing the channel width of the transistor in the pull-down maintenance module can improve the ability to resist positive bias and speed up the pull-down speed, but it will cause serious leakage, increasing the capacitance formed by the gate and the source of the transistor in the pull-down maintenance module can reduce leakage, and reducing the proportion of the capacitance formed by the gate and the source of the transistor in the pull-up module to the total capacitance (the sum of the capacitances in the circuit) can reduce leakage. However, in the related art, since each transistor is independently provided, reducing the channel width of each transistor will cause the capacitance between its gate and source to decrease. Therefore, in the embodiment of the present application, at least one pull-down capacitor is provided to separate the pull-down capacitor from the capacitance formed by the gate and source of the transistor, so that the capacitance of the pull-down capacitor and the channel width of the transistor can be designed independently, so that the pull-down speed can be accelerated and the low potential performance can be maintained through the pull-down capacitor, and the leakage can be reduced by regulating the channel width of the transistor, thereby taking into account the low leakage and low potential maintenance capabilities of the gate drive circuit.

[0041] Specifically, it can be understood that the pull-down capacitor added in the embodiment of the present application and the capacitance formed by the gate and source of each transistor can be regarded as connected in series. When the two are regarded as a whole, it is equivalent to increasing the capacitance formed by the gate and source of the transistor. Moreover, since the size of the pull-down capacitor can be adjusted, it is equivalent to realizing the separation design of the capacitance formed by the gate and source of the transistor and the channel width of the transistor. The two can be designed independently, thereby taking into account a relatively small channel width and a relatively large capacitance, thereby taking into account the low leakage and low potential maintenance capabilities of the gate drive circuit.

[0042] Specifically, Figure 4 As shown, the non-display area 102 can be arranged around the display area 101, but the embodiments of the present application are not limited to this. The non-display area 102 can be arranged on two sides or three sides of the display area 101, and the non-display area 102 can be bent to the back side of the display panel. The non-display area 102 may include a gate drive circuit area 102a located on both sides of the display area 101, and the gate drive circuit can be arranged in the gate drive circuit setting area, but the embodiments of the present application are not limited to this, and the gate drive circuit area can be arranged on one side of the display area. Accordingly, the gate drive circuit is arranged on one side of the display area.

[0043] Specifically, the non-display area 102 may further include a binding area (not shown).

[0044] In some embodiments, Figure 5 As shown, the first plate of the pull-down capacitor 214 is electrically connected to the second node K, and the second plate of the pull-down capacitor 214 is electrically connected to the low potential power supply terminal VSS. By electrically connecting the first plate of the pull-down capacitor to the second node K, and the second plate of the pull-down capacitor to the low potential power supply terminal, the pull-down speed of the first node Q and the signal output terminal can be accelerated through the pull-down capacitor, and the channel width of the transistor in the pull-down maintenance module can be reduced accordingly, reducing the risk of leakage, and improving the high potential stability of the first node Q and the signal output terminal.

[0045] In some embodiments, Figure 6 As shown, the first plate of the pull-down capacitor 214 is electrically connected to the first node Q, and the second plate of the pull-down capacitor 214 is electrically connected to the low potential power supply terminal VSS. By electrically connecting the first plate of the pull-down capacitor to the first node Q, and the second plate of the pull-down capacitor to the low potential power supply terminal, the pull-down speed of the second node K and the third node can be accelerated through the pull-down capacitor, and the channel width of the transistor in the inverting module can be reduced accordingly, thereby improving the high potential stability of the second node K and the third node.

[0046] Specifically, considering that the inverting module will be connected to the pull-down maintaining module, the stability of the inverting module will directly affect the stability of the pull-down maintaining module, thereby indirectly affecting the display effect. Therefore, the embodiment of the present application electrically connects the first plate of the pull-down capacitor to the first node Q, and the second plate of the pull-down capacitor to the low potential power supply terminal, so that the pull-down speed of the second node K and the third node can be accelerated through the pull-down capacitor, thereby improving the ability of the inverting module to maintain a low potential, and correspondingly can reduce the channel width of the transistor in the inverting module, reduce leakage, and avoid display abnormalities.

[0047] In some embodiments, Figure 7As shown, the pull-down capacitor 214 includes a first sub-capacitor Cqt and a second sub-capacitor Ckt, the first plate of the first sub-capacitor Cqt is electrically connected to the first node Q, the second plate of the first sub-capacitor Cqt is electrically connected to the low potential power supply terminal VSS, the first plate of the second sub-capacitor Ckt is electrically connected to the second node K, and the second plate of the second sub-capacitor Ckt is electrically connected to the low potential power supply terminal VSS. By making the first plate of the first sub-capacitor Cqt electrically connected to the first node Q and the second plate of the first sub-capacitor Cqt electrically connected to the low potential power supply terminal, the pull-down speed of the second node K and the third node can be accelerated through the first sub-capacitor Cqt, and the channel width of the transistor in the inverting module can be reduced accordingly, thereby improving the high potential stability of the second node K and the third node. By electrically connecting the first plate of the second sub-capacitor Ckt to the second node K and the second plate of the second sub-capacitor Ckt to the low potential power supply terminal, the pull-down speed of the first node Q and the signal output terminal can be accelerated through the second sub-capacitor Ckt, and the channel width of the transistor in the pull-down maintenance module can be reduced accordingly, reducing the leakage risk and improving the high potential stability of the first node Q and the signal output terminal.

[0048] In some embodiments, Figures 5 to 7 As shown, the pull-down maintenance module 212 includes a first pull-down maintenance transistor T32 and a second pull-down maintenance transistor T42, the gate of the first pull-down maintenance transistor T32 is electrically connected to the second node K, the first electrode of the first pull-down maintenance transistor T32 is electrically connected to the low potential power supply terminal VSS, and the second electrode of the first pull-down maintenance transistor T32 is electrically connected to the signal output terminal G(N); the gate of the second pull-down maintenance transistor T42 is electrically connected to the second node K, the first electrode of the second pull-down maintenance transistor T42 is electrically connected to the low potential power supply terminal VSS, and the second electrode of the second pull-down maintenance transistor T42 is electrically connected to the first node Q;

[0049] Among them, the first electrode plate of the second sub-capacitor Ckt is electrically connected to the gate of the first pull-down maintenance transistor T32 and the gate of the second pull-down maintenance transistor T42. By setting the first pull-down maintenance transistor T32 and the second pull-down maintenance transistor T42, the second electrode of the first pull-down maintenance transistor T32 is connected to the signal output end, and the second electrode of the second pull-down maintenance transistor T42 is connected to the first node Q, so that the signal output end and the first node Q can be controlled to be maintained at a low potential by the first pull-down maintenance transistor T32 and the second pull-down maintenance transistor T42, so that the gate drive circuit works normally. And the first electrode plate of the second sub-capacitor Ckt is electrically connected to the gate of the first pull-down maintenance transistor T32 and the gate of the second pull-down maintenance transistor T42, which can speed up the pull-down speed of the first node Q and the signal output end, and correspondingly reduce the channel width of the first pull-down maintenance transistor T32 and the second pull-down maintenance transistor T42, thereby reducing leakage, taking into account the low leakage and low potential maintenance capabilities of the gate drive circuit.

[0050] In some embodiments, Figures 5 to 7 As shown, the inverting module 213 includes a first inverting transistor T51, a second inverting transistor T52, a third inverting transistor T53 and a fourth inverting transistor T54, the gate of the first inverting transistor T51 is electrically connected to the high potential power supply terminal VGH, and the first electrode of the first inverting transistor T51 is electrically connected to the high potential power supply terminal VGH; the gate of the second inverting transistor T52 is electrically connected to the first node Q, the first electrode of the second inverting transistor T52 is electrically connected to the low potential power supply terminal VSS, and the second electrode of the second inverting transistor T52 is electrically connected to the second electrode of the first inverting transistor T51. connected to a third node P; a gate of the third inverting transistor T53 and a second electrode of the first inverting transistor T51 are electrically connected to the third node P, a first electrode of the third inverting transistor T53 is electrically connected to the high potential power supply terminal VGH, and a second electrode of the third inverting transistor T53 and the pull-down maintaining module 212 are electrically connected to the second node K; a gate of the fourth inverting transistor T54 is electrically connected to the first node Q, a first electrode of the fourth inverting transistor T54 is electrically connected to the low potential power supply terminal VSS, and a second electrode of the fourth inverting transistor T54 is electrically connected to the second node K;

[0051] The first plate of the first sub-capacitor Cqt is electrically connected to the gate of the second inverting transistor T52 and the gate of the fourth inverting transistor T54. By electrically connecting the first plate of the first sub-capacitor Cqt to the gate of the second inverting transistor T52 and the gate of the fourth inverting transistor T54, the pull-down speed of the second node K and the third node can be accelerated, and the channel width of the second inverting transistor T52 and the fourth inverting transistor T54 can be reduced accordingly, thereby reducing leakage, and taking into account the low leakage and low potential maintenance capabilities of the gate drive circuit.

[0052] In some embodiments, Figures 7 to 15 As shown, the display panel 1 includes a substrate 311, a gate layer 312 and a source-drain layer 315; the gate layer 312 is arranged on one side of the substrate 311, and the gate layer 312 includes a gate T32G of the first pull-down sustaining transistor T32, a gate T42G of the second pull-down sustaining transistor T42, a gate T52G of the second inverting transistor T52, a gate T54G of the fourth inverting transistor T54, a first electrode Cqt1 of the first sub-capacitor Cqt and a first electrode Ckt of the second sub-capacitor Ckt. Plate Ckt1; a source-drain layer 315 is disposed on a side of the gate layer 312 away from the substrate 311, the source-drain layer 315 includes a first electrode T32S of the first pull-down sustaining transistor T32, a first electrode T42S of the second pull-down sustaining transistor T42, a first electrode T52S of the second inverting transistor T52, a first electrode T54S of the fourth inverting transistor T54, a second plate Cqt2 of the first sub-capacitor Cqt, and a second plate Ckt2 of the second sub-capacitor Ckt;

[0053] The gate T32G of the first pull-down sustaining transistor T32, the gate T42G of the second pull-down sustaining transistor T42 and the first plate Ckt1 of the second sub-capacitor Ckt are connected, and the first electrode T32S of the first pull-down sustaining transistor T32, the first electrode T42S of the second pull-down sustaining transistor T42 and the second plate Ckt2 of the second sub-capacitor Ckt are connected;

[0054] And / or, the gate T52G of the second inverting transistor T52, the gate T54G of the fourth inverting transistor T54 and the first plate Cqt1 of the first sub-capacitor Cqt are connected, and the first electrode T52S of the second inverting transistor T52, the first electrode T54S of the fourth inverting transistor T54 and the second plate Ckt2 of the first sub-capacitor CqtCkt are connected.

[0055] Specifically, only the gate T32G of the first pull-down maintaining transistor T32, the gate T42G of the second pull-down maintaining transistor T42 and the first plate Ckt1 of the second sub-capacitor Ckt can be connected, and the first electrode T32S of the first pull-down maintaining transistor T32, the first electrode T42S of the second pull-down maintaining transistor T42 and the second plate Ckt2 of the second sub-capacitor Ckt can be connected, so that when the second sub-capacitor Ckt is added, the gate of the first pull-down maintaining transistor T32, the gate of the second pull-down maintaining transistor T42 and the first plate of the second sub-capacitor Ckt can be combined and set, and the first electrode of the first pull-down maintaining transistor T32, the first electrode of the second pull-down maintaining transistor T42 and the second plate of the second sub-capacitor Ckt can be combined and set, so as to reduce the frame, improve the space utilization while increasing the second sub-capacitor Ckt, and reduce the frame. There is no limitation on the design of the second inverting transistor T52, the fourth inverting transistor T54 and the first sub-capacitor Cqt.

[0056] Specifically, only the gate T52G of the second inverting transistor T52, the gate T54G of the fourth inverting transistor T54 and the first plate Cqt1 of the first sub-capacitor Cqt can be connected, and the first electrode T52S of the second inverting transistor T52, the first electrode T54S of the fourth inverting transistor T54 and the second plate Ckt2 of the first sub-capacitor CqtCkt can be connected, so that when the first sub-capacitor Cqt is increased, the gate of the second inverting transistor T52, the gate of the fourth inverting transistor T54 and the first plate of the first sub-capacitor Cqt can be combined and set, and the first electrode of the second inverting transistor T52, the first electrode of the fourth inverting transistor T54 and the second plate of the first sub-capacitor Cqt can be combined and set, so as to reduce the frame, increase the space utilization while increasing the first sub-capacitor Cqt, and reduce the frame. There is no limitation on the design of the first pull-down maintenance transistor T32, the second pull-down maintenance transistor T42 and the second sub-capacitor Ckt.

[0057] Specifically, the gate T32G of the first pull-down maintaining transistor T32, the gate T42G of the second pull-down maintaining transistor T42 and the first plate Ckt1 of the second sub-capacitor Ckt can be connected, and the first electrode T32S of the first pull-down maintaining transistor T32, the first electrode T42S of the second pull-down maintaining transistor T42 and the second plate Ckt2 of the second sub-capacitor Ckt are connected; and the gate T52G of the second inverting transistor T52, the gate T54G of the fourth inverting transistor T54 and the first plate Cqt1 of the first sub-capacitor Cqt are connected, and the first electrode T52S of the second inverting transistor T52, the first electrode T54S of the fourth inverting transistor T54 and the second plate Ckt2 of the first sub-capacitor CqtCkt are connected. Therefore, when adding the first sub-capacitor Cqt and the second sub-capacitor Ckt, the gate of the first pull-down maintaining transistor T32, the gate of the second pull-down maintaining transistor T42 and the first plate of the second sub-capacitor Ckt can be combined, the gate of the second inverting transistor T52, the gate of the fourth inverting transistor T54 and the first plate of the first sub-capacitor Cqt can be combined, the first electrode of the first pull-down maintaining transistor T32, the first electrode of the second pull-down maintaining transistor T42 and the second plate of the second sub-capacitor Ckt can be combined, and the first electrode of the second inverting transistor T52, the first electrode of the fourth inverting transistor T54 and the second plate of the first sub-capacitor Cqt can be combined, thereby reducing the border, improving space utilization while increasing the first sub-capacitor Cqt and the second sub-capacitor Ckt, and reducing the border.

[0058] Specifically, Figure 8 , Fig.12 As shown, the display panel 1 also includes a gate insulating layer 313, an active layer 314, an interlayer insulating layer 316 and a pixel conductive layer 317. The gate insulating layer 313 can be arranged on the side of the gate layer 312 away from the substrate 311, the active layer 314 is arranged between the gate insulating layer 313 and the source and drain layer 315, the interlayer insulating layer 316 is arranged on the side of the source and drain layer 315 away from the active layer, and the pixel conductive layer 317 is arranged on the side of the interlayer insulating layer 316 away from the source and drain layer 315.

[0059] In some embodiments, Figures 8 to 15As shown, the first electrode T32S of the first pull-down sustain transistor T32 includes a first branch electrode 411 and a second branch electrode 412, the first branch electrode 411 and the second branch electrode 412 are arranged along the first direction X, the length L1 of the first branch electrode 411 in the second direction Y is greater than the length L2 of the second branch electrode 412 in the second direction Y, and the second electrode plate Ckt2 of the second sub-capacitor Ckt and the portion of the first branch electrode 411 exceeding the second branch electrode 412 are arranged along the first direction X;

[0060] Among them, in the second direction Y, the second plate Ckt2 of the second sub-capacitor Ckt is located between the second branch electrode 412 and the first electrode T42S of the second pull-down maintenance transistor T42. The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. By making the first electrode of the first pull-down maintenance transistor T32 include a first branch electrode and a second branch electrode, the length of the first branch electrode is greater than the length of the second branch electrode, the second plate of the second sub-capacitor Ckt and the part of the first branch electrode exceeding the second branch electrode are arranged along the first direction, and the second plate of the second sub-capacitor Ckt is located between the second branch electrode and the first electrode of the second pull-down maintenance transistor T42, then by shortening the part of the second branch electrode in the first electrode of the first pull-down maintenance transistor T32, the part is used as the second plate of the second sub-capacitor Ckt, thereby reducing the channel width of the transistor while increasing the second sub-capacitor Ckt, that is, while improving the electrical properties of the display panel, improving the space utilization and reducing the frame.

[0061] Specifically, it can be seen that the connection between the gate of the fourth inverting transistor T54 and the second electrode of the second pull-down maintaining transistor T42 (i.e., the first node Q) is arranged corresponding to the first branch electrode, the first electrode of the second pull-down maintaining transistor T42 is arranged corresponding to the second branch electrode, and the connection between the gate of the fourth inverting transistor T54 and the second electrode of the second pull-down maintaining transistor T42 is arranged along the first direction with the first electrode of the second pull-down maintaining transistor T42, thereby improving space utilization and appropriately reducing the channel width of the second pull-down maintaining transistor T42, thereby improving the electrical properties of the display panel while improving space utilization and reducing the border.

[0062] In some embodiments, Figures 8 to 15As shown, the second electrode plate Cqt2 of the first sub-capacitor Cqt is located between the first electrode T52S of the second inverting transistor T52 and the first electrode T54S of the fourth inverting transistor T54. By making the second electrode plate of the first sub-capacitor Cqt located between the first electrode of the second inverting transistor T52 and the first electrode of the fourth inverting transistor T54, the second electrode plate of the first sub-capacitor Cqt can be formed by utilizing the gap between the first electrode of the second inverting transistor T52 and the first electrode of the fourth inverting transistor T54, thereby improving the electrical properties of the display panel, improving the space utilization rate, and reducing the frame.

[0063] Specifically, it can be seen that in the second direction, the length of the first electrode of the fourth inverting transistor T54 is greater than the length of the first electrode of the second inverting transistor T52, and the connection between the second electrode of the second inverting transistor T52 and the gate of the third inverting transistor (i.e., the third node P) and the part of the first electrode of the fourth inverting transistor T54 that exceeds the first electrode of the second inverting transistor T52 are arranged correspondingly, thereby improving space utilization and reducing the border.

[0064] Specifically, it can be understood that compared with independently setting each transistor, when adding a pull-down capacitor, the embodiment of the present application can improve the electrical properties of the display panel while improving space utilization and reducing the border by adjusting the connection relationship and position of each transistor.

[0065] Specifically, Figure 8 , Fig. 9 , Fig.10 As shown, in Fig.10 As can be seen in (a), the gate layer 312 includes the gate T32G of the first pull-down maintaining transistor T32, the gate T42G of the second pull-down maintaining transistor T42, the gate T52G of the second inverting transistor T52, the gate T53G of the third inverting transistor T53, the gate T54G of the fourth inverting transistor T54, the first plate Cqt1 of the first sub-capacitor Cqt and the first plate Ckt1 of the second sub-capacitor Ckt. It can be understood that the gate layer also includes the gates of other transistors. Fig.10 Not shown in (a).

[0066] Specifically, Figure 8 , Fig. 9 , Fig.10 As shown, in Fig.10As can be seen in (b), the active layer 314 includes the active portion T32A of the first pull-down sustaining transistor T32, the active portion T42A of the second pull-down sustaining transistor T42, the active portion T52A of the second inverting transistor T52, the active portion T53A of the third inverting transistor T53 and the active portion T54A of the fourth inverting transistor T54. It can be understood that the active layer also includes the active portions of other transistors. Fig.10 Not shown in (b).

[0067] Specifically, it can be understood that the gate of each transistor is arranged corresponding to the active portion of each transistor.

[0068] Specifically, Figure 8 , Fig. 9 , Fig.11 As shown, in Fig.11 As can be seen in (a), the source-drain layer 315 includes the first electrode T32S of the first pull-down sustaining transistor T32, the second electrode T32D of the first pull-down sustaining transistor T32, the first electrode T42S of the second pull-down sustaining transistor T42, the second electrode T42D of the second pull-down sustaining transistor T42, the first electrode T52S of the second inverting transistor T52, the second electrode T52D of the second inverting transistor T52, the first electrode T53S of the third inverting transistor T53, the second electrode T53D of the third inverting transistor T53, the first electrode T54S of the fourth inverting transistor T54, the second electrode T54D of the fourth inverting transistor T54, the second plate Cqt2 of the first sub-capacitor Cqt, and the second plate Ckt2 of the second sub-capacitor Ckt. It can be understood that the source-drain layer also includes the first and second electrodes of other transistors. Fig.11 Not shown in (a).

[0069] Specifically, Figure 8 , Fig. 9 , Fig.11 As shown, in Fig.11As can be seen in (b), the pixel conductive layer 317 may include a first connection portion K1, a second connection portion K2, a third connection portion K3 and a fourth connection portion K4. The first connection portion K1 passes through the via hole 301 to connect the gate T32G of the first pull-down sustaining transistor T32 and the second electrode T53D of the third inverting transistor T53. The second connection portion K2 passes through the via hole 301 to connect the second electrode T42D of the second pull-down sustaining transistor T42 and the gate T54G of the fourth inverting transistor T54. The third connection portion K3 passes through the via hole 301 to connect the second electrode T52D of the second inverting transistor T52 and the gate T53G of the third inverting transistor T53. The fourth connection portion K4 passes through the via hole 301 to connect the first electrode T53S of the third inverting transistor T53. It can be understood that the pixel conductive layer also includes other connection portions. Fig.11 Not shown in (b).

[0070] Specifically, in the embodiment of the present application, there is no limitation on the film layer in which the vias are set, and it can be understood that the positions of the vias through which different connecting parts pass can be different, and the same connecting part can pass through multiple vias. The vias can be vias that connect the pixel conductive layer to the gate layer, or vias that connect the pixel conductive layer to the source and drain layers.

[0071] In some embodiments, Figures 12 to 15 As shown, the display panel 1 further includes a pixel conductive layer 317, and the pixel conductive layer 317 is disposed on a side of the source and drain electrode layer 315 away from the gate layer 312;

[0072] The pixel conductive layer 317 is electrically connected to at least one of the gate of the first pull-down sustaining transistor T32, the gate of the second pull-down sustaining transistor T42, the gate of the second inverting transistor T52, and the gate of the fourth inverting transistor T54. By electrically connecting the pixel conductive layer to at least one of the gate of the first pull-down sustaining transistor T32, the gate of the second pull-down sustaining transistor T42, the gate of the second inverting transistor T52, and the gate of the fourth inverting transistor T54, the control capability of each transistor can be increased, and the capacitance of the pull-down capacitor can be increased, thereby increasing the pull-down sustaining capability.

[0073] Specifically, the pixel conductive layer can be electrically connected to at least one of the first node Q and the second node K, so that the pixel conductive layer is equivalent to another capacitor connected in series with the pull-down capacitor, thereby increasing the pull-down maintenance capability, improving the control capability of the transistor, and reducing leakage.

[0074] Specifically, the pixel conductive layer may be connected to the first node Q, or connected to the second node K, or the pixel conductive layer may include two parts, one part connected to the first node Q, and the other part connected to the second node K.

[0075] Specifically, the pixel conductive layer can be connected to one, two, three or four of the gate of the first pull-down sustaining transistor T32, the gate of the second pull-down sustaining transistor T42, the gate of the second inverting transistor T52 and the gate of the fourth inverting transistor T54. When the pixel conductive layer is connected to the gates of multiple transistors, multiple transparent conductive parts can be provided to prevent signal crosstalk.

[0076] In some embodiments, Figures 12 to 15 As shown, the pixel conductive layer 317 includes a first transparent conductive portion 317a and a second transparent conductive portion 317b, the first transparent conductive portion 317a is connected to the gate of the first pull-down sustaining transistor T32 and the gate of the second pull-down sustaining transistor T42, and the second transparent conductive portion 317b is connected to the gate of the second inverting transistor T52 and the gate of the fourth inverting transistor T54. By making the pixel conductive layer include the first transparent conductive portion and the second transparent conductive portion, the first transparent conductive portion is connected to the gate of the first pull-down sustaining transistor T32 and the gate of the second pull-down sustaining transistor T42, and the second transparent conductive portion is connected to the gate of the second inverting transistor T52 and the gate of the fourth inverting transistor T54, so that the first sub-capacitor Cqt and the second sub-capacitor Ckt can be increased, so that the pull-down sustaining capability can be further improved, and the gate control capability of each transistor is increased, and leakage is reduced.

[0077] Specifically, Fig.12 , Fig.13 , Fig.14 As shown, in Fig.14 As can be seen in (a), the gate layer 312 includes the gate T32G of the first pull-down maintaining transistor T32, the gate T42G of the second pull-down maintaining transistor T42, the gate T52G of the second inverting transistor T52, the gate T53G of the third inverting transistor T53, the gate T54G of the fourth inverting transistor T54, the first plate Cqt1 of the first sub-capacitor Cqt and the first plate Ckt1 of the second sub-capacitor Ckt. It can be understood that the gate layer also includes the gates of other transistors. Fig.14 Not shown in (a).

[0078] Specifically, Fig.12 , Fig.13 , Fig.14 As shown, in Fig.14As can be seen in (b), the active layer 314 includes the active portion T32A of the first pull-down sustaining transistor T32, the active portion T42A of the second pull-down sustaining transistor T42, the active portion T52A of the second inverting transistor T52, the active portion T53A of the third inverting transistor T53 and the active portion T54A of the fourth inverting transistor T54. It can be understood that the active layer also includes the active portions of other transistors. Fig.14 Not shown in (b).

[0079] Specifically, it can be understood that the gate of each transistor is arranged corresponding to the active portion of each transistor.

[0080] Specifically, Fig.12 , Fig.13 , Fig.15 As shown, in Fig.15 As can be seen in (a), the source-drain layer 315 includes the first electrode T32S of the first pull-down sustaining transistor T32, the second electrode T32D of the first pull-down sustaining transistor T32, the first electrode T42S of the second pull-down sustaining transistor T42, the second electrode T42D of the second pull-down sustaining transistor T42, the first electrode T52S of the second inverting transistor T52, the second electrode T52D of the second inverting transistor T52, the first electrode T53S of the third inverting transistor T53, the second electrode T53D of the third inverting transistor T53, the first electrode T54S of the fourth inverting transistor T54, the second electrode T54D of the fourth inverting transistor T54, the second plate Cqt2 of the first sub-capacitor Cqt, and the second plate Ckt2 of the second sub-capacitor Ckt. It can be understood that the source-drain layer also includes the first and second electrodes of other transistors. Fig.11 Not shown in (a).

[0081] Specifically, Fig.12 , Fig.13 , Fig.15 As shown, in Fig.15As can be seen in (b), the pixel conductive layer 317 may include a first transparent conductive portion 317a, a second transparent conductive portion 317b, a third connecting portion K3 and a fourth connecting portion K4. The first transparent conductive portion 317a passes through the via 301 to connect the gate T32G of the first pull-down sustaining transistor T32 and the second electrode T53D of the third inverting transistor T53, and the projection of the first transparent conductive portion on the substrate may overlap with the projection of the gate of the first pull-down sustaining transistor T32, the gate of the second pull-down sustaining transistor T42 and the second sub-capacitor Ckt on the substrate. 317b connects the second electrode T42D of the second pull-down maintaining transistor T42 and the gate T54G of the fourth inverting transistor T54 through the via hole 301, and the second transparent conductive portion can overlap with the gate of the second inverting transistor T52, the gate of the fourth inverting transistor T54 and the first sub-capacitor Cqt on the substrate, the third connecting portion K3 connects the second electrode T52D of the second inverting transistor T52 and the gate T53G of the third inverting transistor T53 through the via hole 301, and the fourth connecting portion K4 connects the first electrode T53S of the third inverting transistor T53 through the via hole 301. It can be understood that the pixel conductive layer also includes other connecting portions. Fig.15 Not shown in (b).

[0082] Specifically, it can be understood that, according to different film layer designs of the display panel, the pixel conductive layer can be arranged in the same layer as the pixel electrode, can be arranged in the same layer as the common electrode, or can be arranged independently.

[0083] In some embodiments, Figures 5 to 7 As shown, the gate drive circuit 21 further includes:

[0084] The pull-up control module 215 includes a pull-up control transistor T11, a gate of the pull-up control transistor T11 and a first electrode of the pull-up control transistor T11 are configured to receive a pull-up control signal, and a second electrode of the pull-up control transistor T11 is electrically connected to the first node Q;

[0085] The pull-down module 216 includes a first pull-down transistor T31 and a second pull-down transistor T41, wherein the gate of the first pull-down transistor T31 is configured to receive a first pull-down control signal, the first electrode of the first pull-down transistor T31 is electrically connected to the low potential power supply terminal VSS, and the second electrode of the first pull-down transistor T31 is electrically connected to the signal output terminal G(N); the gate of the second pull-down transistor T41 is configured to receive a second pull-down control signal, the first electrode of the second pull-down transistor T41 is electrically connected to the low potential power supply terminal VSS, and the second electrode of the second pull-down transistor T41 is electrically connected to the first node Q;

[0086] The reset module 217 includes a first reset transistor TrG and a second reset transistor TrQ, wherein the gate of the first reset transistor TrG is connected to the reset signal line Rst, the first electrode of the first reset transistor TrG is electrically connected to the low potential power supply terminal VSS, and the second electrode of the first reset transistor TrG is electrically connected to the signal output terminal G(N); the gate of the second reset transistor TrQ is connected to the reset signal line Rst, the first electrode of the second reset transistor TrQ is electrically connected to the low potential power supply terminal VSS, and the second electrode of the second reset transistor TrQ is electrically connected to the first node Q;

[0087] A storage capacitor Cbt, one plate of the storage capacitor Cbt is electrically connected to the first node Q, and the other plate of the storage capacitor Cbt is electrically connected to the signal output terminal G(N).

[0088] Specifically, Figures 5 to 7 As shown, the pull-up module 211 includes a pull-up transistor T21, a gate of the pull-up transistor T21 is electrically connected to the first node Q, a first electrode of the pull-up transistor T21 is connected to the clock signal line CK, and a second electrode of the pull-up transistor T21 is connected to the signal output terminal G(N).

[0089] Specifically, the display panel 1 includes a plurality of cascaded gate drive circuits 21, the gate of the pull-up control transistor T11 in the first-stage gate drive circuit 21 can be connected to the start signal line STV, and the gates of the pull-up control transistors T11 in the other-stage gate drive circuits 21 can be connected to the signal output terminals G(N-3) of the first three-stage gate drive circuits 21. N is greater than or equal to 4, and N is an integer.

[0090] Specifically, the gate of the first pull-down transistor T31 in the gate drive circuit of this level can be connected to the signal output terminal G(N+4) in the next four-level gate drive circuit, and the gate of the second pull-down transistor T41 in the gate drive circuit of this level can be connected to the signal output terminal G(N+6) in the next six-level gate drive circuit.

[0091] Specifically, in the embodiments of the present application, examples are given of signal lines or signal terminals to which the gates of various transistors are connected. It will be understood that the embodiments of the present application are not limited thereto. For example, the gate of the first pull-down transistor T31 in the gate drive circuit of this level may be connected to the signal output terminal G(N+2) in the next two levels of gate drive circuits. Different connection methods may be used without affecting the display, which will not be described in detail herein.

[0092] Specifically, each transistor in the embodiment of the present application can be a silicon semiconductor transistor (for example, a low-temperature polycrystalline silicon thin film transistor) to reduce power consumption, but the embodiment of the present application is not limited to this. Each transistor can be an oxide semiconductor transistor (for example, an indium gallium zinc oxide thin film transistor), or some transistors can be silicon semiconductor transistors (for example, low-temperature polycrystalline silicon thin film transistors) and some transistors can be oxide semiconductor transistors (for example, indium gallium zinc oxide thin film transistors).

[0093] Specifically, each transistor in the embodiment of the present application may be an N-type transistor.

[0094] Specifically, the first electrode may be a source electrode and the second electrode may be a drain electrode; or the first electrode may be a drain electrode and the second electrode may be a source electrode.

[0095] Specifically, it can be understood that since the gate drive circuit in the embodiment of the present application adds a pull-down capacitor, even if the various dimensions of the pull-down transistor (including the length and width of its gate, the length and width of its source, the length and width of its drain, etc.) remain unchanged, the ratio of the capacitance formed by the gate and source of the pull-down transistor to the total capacitance will inevitably become smaller, thereby reducing leakage.

[0096] Specifically, it can be understood that in order to illustrate the specific design of each structure, the above embodiment divides a structure. It can be understood that when the influence of factors such as impedance is not considered, multiple structures with different labels are actually multiple parts of a structure. The signals on the structure are the same and can be named with one label. For example, the first electrode of the first pull-down maintenance transistor T32, the second electrode of the second pull-down maintenance transistor T42, and the second plate of the second sub-capacitor Ckt are actually three parts of a structure. The first branch electrode and the second branch electrode are divided from the part corresponding to the first pull-down maintenance transistor T32 in the structure. In other words, the above structures transmit the same signal and can be labeled with the same label. Similarly, other similar designs can refer to the above description.

[0097] Specifically, the above embodiments illustrate some embodiments of the display panel from aspects of circuits, film layers, etc. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined, split, or split and then combined. For example, the first electrode plate of the pull-down capacitor 214 is electrically connected to the second node K, the second electrode plate of the pull-down capacitor 214 is electrically connected to the low potential power supply terminal VSS, the pull-down maintenance module 212 includes a first pull-down maintenance transistor T32 and a second pull-down maintenance transistor T42, the gate of the first pull-down maintenance transistor T32 is electrically connected to the second node K, and the first pull-down maintenance transistor The first electrode of T32 is electrically connected to the low potential power supply terminal VSS, and the second electrode of the first pull-down maintaining transistor T32 is electrically connected to the signal output terminal G(N); the gate of the second pull-down maintaining transistor T42 is electrically connected to the second node K, the first electrode of the second pull-down maintaining transistor T42 is electrically connected to the low potential power supply terminal VSS, and the second electrode of the second pull-down maintaining transistor T42 is electrically connected to the first node Q; wherein the first electrode plate of the pull-down capacitor 214 is electrically connected to the gate of the first pull-down maintaining transistor T32 and the gate of the second pull-down maintaining transistor T42. Alternatively, the first electrode plate of the pull-down capacitor 214 is electrically connected to the second node K, the second electrode plate of the pull-down capacitor 214 is electrically connected to the low potential power supply terminal VSS, the display panel 1 includes a substrate 311, a gate layer 312 and a source-drain layer 315; the gate layer 312 is arranged on one side of the substrate 311, and the gate layer 312 includes the gate of the first pull-down maintenance transistor T32, the gate of the second pull-down maintenance transistor T42, and the first electrode plate of the pull-down capacitor; the source-drain layer 315 is arranged on the gate layer 312 away from the gate On one side of the substrate 311, the source-drain layer 315 includes a first electrode of the first pull-down maintaining transistor T32, a first electrode of the second pull-down maintaining transistor T42 and a second plate of the pull-down capacitor 214; wherein the gate of the first pull-down maintaining transistor T32, the gate of the second pull-down maintaining transistor T42 and the first plate of the pull-down capacitor are connected, and the first electrode of the first pull-down maintaining transistor T32, the first electrode of the second pull-down maintaining transistor T42 and the second plate of the pull-down capacitor 214 are connected.

[0098] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0099] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0100] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0101] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0102] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: A plurality of cascaded gate drive circuits are included, each of the gate drive circuits comprising: a pull-up module, electrically connected to the first node, the pull-up module being configured to connect the clock signal line with the signal output end of the gate driving circuit of this stage, or disconnect the electrical connection between the clock signal line and the signal output end according to the potential of the first node; A pull-down maintaining module, electrically connected to the first node and the low potential power supply terminal; an inverting module, one end of which is electrically connected to the first node, and the other end of which is electrically connected to the pull-down maintaining module at a second node, and the inverting module is configured to control the pull-down maintaining module to connect the low potential power supply end with the first node, or to disconnect the electrical connection between the low potential power supply end and the first node according to the potential of the first node; The gate drive circuit further includes a pull-down capacitor, at least one of the first node and the second node is electrically connected to a first plate of the pull-down capacitor, and a second plate of the pull-down capacitor is electrically connected to the low potential power supply terminal.

2. The display panel according to claim 1, characterized in that: The first electrode plate of the pull-down capacitor is electrically connected to the second node, and the second electrode plate of the pull-down capacitor is electrically connected to the low potential power supply terminal.

3. The display panel according to claim 1, characterized in that: The first electrode plate of the pull-down capacitor is electrically connected to the first node, and the second electrode plate of the pull-down capacitor is electrically connected to the low potential power supply terminal.

4. The display panel according to claim 1, characterized in that: The pull-down capacitor includes a first sub-capacitor and a second sub-capacitor, the first plate of the first sub-capacitor is electrically connected to the first node, the second plate of the first sub-capacitor is electrically connected to the low potential power supply terminal, the first plate of the second sub-capacitor is electrically connected to the second node, and the second plate of the second sub-capacitor is electrically connected to the low potential power supply terminal.

5. The display panel according to claim 4, characterized in that: The pull-down maintaining module comprises: a first pull-down sustaining transistor, wherein a gate of the first pull-down sustaining transistor is electrically connected to the second node, a first electrode of the first pull-down sustaining transistor is electrically connected to the low potential power supply terminal, and a second electrode of the first pull-down sustaining transistor is electrically connected to the signal output terminal; a second pull-down sustaining transistor, wherein a gate of the second pull-down sustaining transistor is electrically connected to the second node, a first electrode of the second pull-down sustaining transistor is electrically connected to the low potential power supply terminal, and a second electrode of the second pull-down sustaining transistor is electrically connected to the first node; The first electrode plate of the second sub-capacitor is electrically connected to the gate of the first pull-down sustaining transistor and the gate of the second pull-down sustaining transistor.

6. The display panel according to claim 5, characterized in that: The inverting module comprises: a first inverting transistor, wherein a gate of the first inverting transistor is electrically connected to a high potential power supply terminal, and a first electrode of the first inverting transistor is electrically connected to the high potential power supply terminal; a second inverting transistor, wherein a gate of the second inverting transistor is electrically connected to the first node, a first electrode of the second inverting transistor is electrically connected to the low potential power supply terminal, and a second electrode of the second inverting transistor and a second electrode of the first inverting transistor are electrically connected to a third node; a third inverting transistor, wherein the gate of the third inverting transistor and the second electrode of the first inverting transistor are electrically connected to the third node, the first electrode of the third inverting transistor is electrically connected to the high potential power supply terminal, and the second electrode of the third inverting transistor and the pull-down maintaining module are electrically connected to the second node; a fourth inverting transistor, wherein a gate of the fourth inverting transistor is electrically connected to the first node, a first electrode of the fourth inverting transistor is electrically connected to the low potential power supply terminal, and a second electrode of the fourth inverting transistor is electrically connected to the second node; The first electrode plate of the first sub-capacitor is electrically connected to the gate of the second inverter transistor and the gate of the fourth inverter transistor.

7. The display panel according to claim 6, characterized in that: The display panel comprises: substrate; a gate layer, disposed on one side of the substrate, comprising a gate of the first pull-down sustaining transistor, a gate of the second pull-down sustaining transistor, a gate of the second inverter transistor, a gate of the fourth inverter transistor, a first plate of the first sub-capacitor, and a first plate of the second sub-capacitor; a source-drain layer, arranged on a side of the gate layer away from the substrate, comprising a first electrode of the first pull-down sustaining transistor, a first electrode of the second pull-down sustaining transistor, a first electrode of the second inverting transistor, a first electrode of the fourth inverting transistor, a second plate of the first sub-capacitor, and a second plate of the second sub-capacitor; The gate of the first pull-down sustaining transistor, the gate of the second pull-down sustaining transistor and the first plate of the second sub-capacitor are connected, and the first electrode of the first pull-down sustaining transistor, the first electrode of the second pull-down sustaining transistor and the second plate of the second sub-capacitor are connected; And / or, the gate of the second inverter transistor, the gate of the fourth inverter transistor and the first plate of the first sub-capacitor are connected, and the first electrode of the second inverter transistor, the first electrode of the fourth inverter transistor and the second plate of the first sub-capacitor are connected.

8. The display panel according to claim 7, characterized in that: The first electrode of the first pull-down sustain transistor includes a first branch electrode and a second branch electrode, the first branch electrode and the second branch electrode are arranged along a first direction, the length of the first branch electrode in the second direction is greater than the length of the second branch electrode in the second direction, and the second electrode plate of the second sub-capacitor and the portion of the first branch electrode exceeding the second branch electrode are arranged along the first direction; Wherein, in the second direction, the second plate of the second sub-capacitor is located between the second branch electrode and the first electrode of the second pull-down sustain transistor; and the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

9. The display panel according to claim 7, characterized in that: The second electrode plate of the first sub-capacitor is located between the first electrode of the second inverter transistor and the first electrode of the fourth inverter transistor.

10. The display panel according to claim 7, characterized in that: The display panel further comprises a pixel conductive layer, wherein the pixel conductive layer is arranged on a side of the source and drain electrode layer away from the gate layer; The pixel conductive layer is electrically connected to at least one of the gate of the first pull-down sustaining transistor, the gate of the second pull-down sustaining transistor, the gate of the second inverter transistor, and the gate of the fourth inverter transistor.

11. The display panel according to claim 10, characterized in that: The pixel conductive layer includes a first transparent conductive portion connected to the gate of the first pull-down sustaining transistor and the gate of the second pull-down sustaining transistor, and a second transparent conductive portion connected to the gate of the second inversion transistor and the gate of the fourth inversion transistor.

12. The display panel according to any one of claims 1 to 11, characterized in that: The gate drive circuit further includes: A pull-up control module, comprising a pull-up control transistor, a gate of the pull-up control transistor and a first electrode of the pull-up control transistor being configured to receive a pull-up control signal, and a second electrode of the pull-up control transistor being electrically connected to the first node; A pull-down module, comprising a first pull-down transistor and a second pull-down transistor, wherein a gate of the first pull-down transistor is configured to receive a first pull-down control signal, a first electrode of the first pull-down transistor is electrically connected to the low potential power supply terminal, and a second electrode of the first pull-down transistor is electrically connected to the signal output terminal; a gate of the second pull-down transistor is configured to receive a second pull-down control signal, a first electrode of the second pull-down transistor is electrically connected to the low potential power supply terminal, and a second electrode of the second pull-down transistor is electrically connected to the first node; A reset module, comprising a first reset transistor and a second reset transistor, wherein the gate of the first reset transistor is connected to a reset signal line, the first electrode of the first reset transistor is electrically connected to the low potential power supply terminal, and the second electrode of the first reset transistor is electrically connected to the signal output terminal; the gate of the second reset transistor is connected to the reset signal line, the first electrode of the second reset transistor is electrically connected to the low potential power supply terminal, and the second electrode of the second reset transistor is electrically connected to the first node; A storage capacitor, wherein one plate of the storage capacitor is electrically connected to the first node, and the other plate of the storage capacitor is electrically connected to the signal output end.

13. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 12.

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