Data alignment for memory

Abstract

The invention relates to data alignment for memory. The memory device can implement individual time adjustments to align portions of a multi-level signal modulated by a modulation scheme having three levels. In some cases, signal paths for generating and transmitting the portions of the multi-level signal can refer to a clock signal, and an adjustable delay circuit can apply individual delays to the clock signal received at each signal path. For example, a first adjustable delay circuit can apply a first time adjustment to the clock signal received at a first signal path for generating a first portion. And, a second adjustable delay circuit can apply a second time adjustment to the clock signal received at a second signal path for generating a second portion. Application of the time adjustment to the signal path can temporally align the portion of the multi-level signal compared to the clock signal.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 771,448, filed by Bach et al. on July 12, 2024, entitled “DATA ALIGNMENT FOR MEMORY,” and U.S. patent application No. 63 / 534,512, filed by Bach et al. on August 24, 2023, entitled “DATA ALIGNMENT FOR MEMORY,” each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to data alignment of memories. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) a state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic DRAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells may be described according to either a volatile configuration or a non-volatile configuration. A non-volatile configured memory cell may maintain a stored logic state for an extended period of time even in the absence of an external power source. A volatile configured memory cell may lose the stored state when disconnected from the external power source. Summary of the invention

[0006] An apparatus is described. The apparatus may include: at least one memory device; and at least one controller coupled to the at least one memory device and configured to cause the apparatus to: identify data for transmission as a multi-level signal on a conductive path, the data comprising first data processed by a first signaling component for transmission on the conductive path and second data processed by a second signaling component for transmission on the conductive path; apply a first time adjustment to a clock signal received at the first signaling component; apply a second time adjustment to the clock signal received at the second signaling component; and generate the multi-level signal based at least in part on the first signaling component generating a first portion of the multi-level signal including the first data and the second signaling component generating a second portion of the multi-level signal including the second data, wherein applying the first time adjustment and the second time adjustment to the clock signal is associated with aligning a timing of the first portion of the multi-level signal transmitted on the conductive path with a timing of the second portion of the multi-level signal transmitted on the conductive path.

[0007] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to: identify data for transmission as a multi-level signal on a conductive path, the data including first data processed by a first signaling component for transmission on the conductive path and second data processed by a second signaling component for transmission on the conductive path; apply a first time adjustment to a clock signal received at the first signaling component; apply a second time adjustment to the clock signal received at the second signaling component; and generate the multi-level signal based at least in part on the first signaling component generating a first portion of the multi-level signal including the first data and the second signaling component generating a second portion of the multi-level signal including the second data, wherein applying the first time adjustment and the second time adjustment to the clock signal is associated with aligning the timing of the first portion of the multi-level signal transmitted on the conductive path with the timing of the second portion of the multi-level signal transmitted on the conductive path.

[0008] A method is described. The method may include: identifying data for transmission as a multi-level signal on a conductive path, the data comprising first data processed by a first signaling component for transmission on the conductive path and second data processed by a second signaling component for transmission on the conductive path; applying a first time adjustment to a clock signal received at the first signaling component; applying a second time adjustment to the clock signal received at the second signaling component; and generating the multi-level signal based at least in part on the first signaling component generating a first portion of the multi-level signal including the first data and the second signaling component generating a second portion of the multi-level signal including the second data, wherein applying the first time adjustment and the second time adjustment to the clock signal is associated with aligning a timing of the first portion of the multi-level signal transmitted on the conductive path with a timing of the second portion of the multi-level signal transmitted on the conductive path. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting data alignment of memory according to examples disclosed herein is presented.

[0010] Figure 2 An example of a signaling circuit supporting data alignment of a memory according to examples disclosed herein is shown.

[0011] Figure 3A and Figure 3B An example of a multi-level signaling diagram is shown to support data alignment of memories according to examples disclosed herein.

[0012] Figure 4 A block diagram is shown of a memory device supporting data alignment of memory according to examples disclosed herein.

[0013] Figure 5 A flow chart is shown illustrating a method or methods of supporting data alignment of memory according to examples disclosed herein. DETAILED DESCRIPTION

[0014] In some cases, a memory device (e.g., or a host device) may generate a multi-level signal (e.g., a signal modulated using a modulation scheme having three or more different amplitude levels) for transmitting information (e.g., one or more information bits). However, in some such cases, during the generation of the multi-level signal, a portion of the multi-level signal (e.g., a sub-eye between two levels of the multi-level signal) may become misaligned with other portions (e.g., sub-eyes). For example, some multi-level signal paths may include two or more signaling components (e.g., each including a serialization component and a driver), each signaling component being associated with a corresponding portion of generating and transmitting (e.g., driving) the multi-level signal (e.g., each signaling component being associated with a signal transition between two levels). However, the timing of the two or more signaling components may become misaligned, resulting in misaligned portions of the multi-level signal. This may occur during serialization of data to generate portions of the multi-level signal or during assembly of portions of the multi-level signal for transmission, such that serialization (e.g., the time difference of serialization at each signaling component) or assembly may cause the portion to become misaligned in time (e.g., when compared to a clock signal). In some embodiments, misalignment between portions of a multilevel signal may reduce the signal-to-noise ratio (SNR) of the multilevel signal or increase the bit error rate (BER) or both, which may limit the transmission speed of the multilevel signal. In addition, misalignment between portions of a multilevel signal may cause difficulties (e.g., due to misaligned sampling points of the portions) and other disadvantages during reading the signal.

[0015] According to examples as described herein, memory devices may implement individual time adjustments (e.g., delays) to align portions of multilevel signals generated using different signal paths (e.g., signal chains). In some cases, the signal paths associated with the portions generating and transmitting the multilevel signals may reference a clock signal, and the memory devices may apply individual time adjustments to the clock signals received at each signal path. For example, a memory device (e.g., a first adjustable delay circuit) may apply a first time adjustment to a clock signal received at a first signal path associated with generating a first portion of the multilevel signal. And, a memory device (e.g., a second adjustable delay circuit) may apply a second time adjustment to a clock signal received at a second signal path associated with generating a second portion of the multilevel signal. In some cases, applying the first time adjustment and the second time adjustment may align the generation and assembly of the first and second portions of the multilevel signal, so that the first and second portions of the multilevel signal may be aligned in time (e.g., compared to the clock signal). Aligning portions of the multilevel signal may increase the SNR of the multilevel signal and reduce the BER of the multilevel signal, thereby supporting a relatively high transmission speed of the multilevel signal (e.g., compared to the previous implementation). Additionally, aligning portions of a multi-level signal may prevent difficulties during reading of the signal (eg, due to aligning sampling points of the portions), among other advantages.

[0016] Features of the present disclosure are illustrated and described in the context of systems, signaling circuits, and multi-level signaling diagrams. Features of the present disclosure are further illustrated and described in the context of block diagrams and flow charts.

[0017] Figure 1 An example of a system 100 that supports data alignment of memory according to examples disclosed herein is shown. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0018] System 100 may include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. Memory device 110 may be a component of system 100 that is operable to store data for one or more other components of system 100.

[0019] Portions of system 100 may be instances of host device 105. Host device 105 may be an instance of a processor (e.g., circuitry, processing circuitry, processing component) that uses memory within the device to perform processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or any combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host (e.g., host device 105).

[0020] Memory device 110 may be a stand-alone device or component that is operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: a modulation scheme to modulate a signal, various pin configurations for communicating a signal, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other functions.

[0021] Memory device 110 is operable to store data for components of host device 105. In some examples, memory device 110 (e.g., operating as an auxiliary type device of host device 105, operating as an independent type device of host device 105) may respond to and execute commands provided by host device 105 through external memory controller 120. Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0022] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (such as one or more peripheral components or one or more input / output controllers). The components of host device 105 may be coupled to each other using a bus 135.

[0023] The processor 125 is operable to provide functionality (e.g., control functionality) for the system 100 or the host device 105. The processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, the processor 125 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, the external memory controller 120 may be implemented by the processor 125 or may be part of the processor 125.

[0024] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include instructions (e.g., programs, software) stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0025] In some examples, system 100 or host device 105 may include various peripheral components. A peripheral component may be any input device or output device, or an interface to such a device, that may be integrated into or with system 100 or host device 105. Examples may include one or more of a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a universal serial bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a peripheral component interconnect (PCI) or a dedicated graphics port. The peripheral component(s) may be other components that are understood by one of ordinary skill in the art to be peripherals.

[0026] In some examples, system 100 or host device 105 may include input components, output components, or both. An input component may represent a device or signal external to system 100 that can provide information (e.g., signals, data) to system 100 or its components. In some examples, an input component may include an interface (e.g., a user interface or an interface between other devices). In some examples, an input component may be a peripheral device that interfaces with system 100 via one or more peripheral components or may be managed by an I / O controller. An output component may represent a device or signal external to system 100 that is operable to receive an output from any of system 100 or its components. Examples of output components may include a display, an audio speaker, a printing device, another processor on a printed circuit board, and others. In some examples, an output may be a peripheral device that interfaces with system 100 via one or more peripheral components or may be managed by an I / O controller.

[0027] The memory device 110 may include a memory device controller 155 and one or more memory dies 160 (e.g., memory chips) to support capacity (e.g., expected capacity, specified capacity) for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more storage bodies, one or more tiles, one or more sectors), each of which is operable to store one or more data bits. A memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0028] The memory device controller 155 may include components (e.g., circuitry, logic) operable to control the operation of the memory device 110. The memory device controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The memory device controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the memory device controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0029] In some examples, memory device 110 may communicate information (e.g., data, commands, or both) with host device 105. For example, memory device 110 may receive a write command indicating that memory device 110 is to store data received from host device 105, or receive a read command indicating that memory device 110 is to provide data stored in memory die 160 to host device 105, among other types of information communications.

[0030] A local memory controller 165 (e.g., local to the memory die 160) may include components (e.g., circuitry, logic) operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate (e.g., receive or transmit data or commands or both) with the memory device controller 155. In some examples, the memory device 110 may not include a memory device controller 155 and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the memory device controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or any combination thereof. Examples of components that may be included in the memory device controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other components operable to support the described operations of the memory device controller 155 or the local memory controller 165, or both.

[0031] The external memory controller 120 is operable to enable communication of information (e.g., data, commands, or both) between components of the system 100 (e.g., between components of the host device 105 (e.g., the processor 125) and the memory device 110). The external memory controller 120 may process (e.g., convert, translate) communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120, or other components of the system 100 or the host device 105, or the functions thereof described herein may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host device 105. Although the external memory controller 120 is described as being external to the memory device 110, in some examples, the external memory controller 120 or the functions thereof described herein may be implemented by one or more components of the memory device 110 (e.g., the memory device controller 155, the local memory controller 165), or vice versa.

[0032] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium that carries information between host device 105 and memory device 110. Each channel 115 may include one or more signal paths (e.g., transmission media, conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path that is operable to carry a signal. For example, a channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at host device 105 and a second terminal at memory device 110. A terminal may be an example of a conductive input or output point of a device of system 100, and a terminal may be operable to serve as part of a channel.

[0033] The channels 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, the channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or any combination thereof. In some examples, signaling may be conveyed through the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be aligned for each clock cycle (e.g., on either a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be aligned for each clock cycle (e.g., on both a rising and falling edge of a clock signal).

[0034] In some examples, CA channel 186 is operable to transmit commands between host device 105 and memory device 110, the commands including control information (e.g., address information) associated with the commands. For example, the commands carried by CA channel 186 may include a read command with an address of desired data. In some examples, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) for communicating control information (e.g., commands or addresses).

[0035] In some examples, the clock signal channel 188 is operable to transmit one or more clock signals between the host device 105 and the memory device 110. The clock signal is operable to oscillate between a high state and a low state, and can support coordination (e.g., in time) between the actions of the host device 105 and the actions of the memory device 110. In some examples, the clock signal can be a single-ended signal. In some examples, the clock signal can provide a timing reference for command and addressing operations of the memory device 110 or other system-wide operations of the memory device 110. The clock signal can be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal can be generated by a system clock, which can include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors).

[0036] In some examples, data channel 190 is operable to transfer information (e.g., data, control information) between host device 105 and memory device 110. For example, data channel 190 may transfer information to be written to memory device 110 (e.g., bidirectionally) or information to be read from memory device 110.

[0037] Channel 115 may include any number of signal paths (including a single signal path). In some examples, channel 115 may include multiple individual signal paths. For example, a channel may be x4 (e.g., including 4 signal paths), x8 (e.g., including 8 signal paths), x16 (e.g., including 16 signal paths), etc.

[0038] Signals communicated via channel 115 may be modulated using one or more different modulation schemes. In some examples, a binary symbol (or binary level) modulation scheme may be used to modulate signals communicated between host device 105 and memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to 2. The symbols of the binary symbol modulation scheme may be operable to represent one digital data bit (e.g., the symbol may represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and others.

[0039] In some examples, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals transmitted between the host device 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to 3. The symbols of the multi-symbol modulation scheme may be operable to represent more than one digital data bit (e.g., the symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM5, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and others. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one information bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols.

[0040] According to an example as described herein, the memory device 110 may implement individual time adjustments (e.g., delays) to align portions (e.g., sub-eyes between two levels) of a multilevel signal (e.g., a signal modulated by a modulation scheme having three or more different amplitude levels). In some cases, two or more signal paths may be used to generate (e.g., serialize) and transmit two or more portions of a multilevel signal. Each signal path may be referenced to a clock signal, and the memory device 110 may apply individual time adjustments to the clock signal received at each signal path. For example, the memory device 110 may apply a first time adjustment to a clock signal received at a first signal path associated with generating a first portion of the multilevel signal. And, the memory device 110 may apply a second time adjustment to a clock signal received at a second signal path associated with generating a second portion of the multilevel signal. In some cases, applying the first time adjustment and the second time adjustment may align the generation and assembly of the first and second portions of the multilevel signal so that the first and second portions of the multilevel signal may be aligned in time (e.g., compared to the clock signal). Aligning portions of a multilevel signal can increase the SNR of the multilevel signal and reduce the BER of the multilevel signal, thereby supporting a relatively high transmission speed of the multilevel signal (e.g., compared to previous implementations). In addition, aligning portions of a multilevel signal can prevent difficulties during reading the signal (e.g., due to aligned sampling points of the portions) and other advantages.

[0041] In addition to applicability in memory devices as described herein, techniques for data alignment of memories may be generally implemented to support increased connectivity of electronic systems. As the use of systems that rely on interconnected electronic devices increases, the connectivity of these electronic devices becomes an increasingly relevant factor in the operation of the systems. For example, as critical systems become more dependent on connectivity, as systems use a larger number of interconnected devices, or as the number and complexity of signals transmitted between devices increases, delays associated with signals transmitted between devices may become increasingly relevant. Implementation of the techniques described herein may support techniques for increased connectivity in electronic systems by aligning portions of multi-level signals, which may improve data transmission between devices and enable increased communication between devices, among other benefits.

[0042] Figure 2 An example of a signaling circuit 200 supporting data alignment of a memory according to examples disclosed herein is shown. The signaling circuit 200 may implement reference Figure 1 For example, the signaling circuit 200 may be implemented at a memory device or a host device, which may be an example of the memory device 110 or the host device 105, respectively, as described in reference to FIG. Figure 1 The signaling circuit 200 may be configured to generate, align, and transmit a multi-level signal 205 based on applying individual time adjustments to a clock signal received at a signaling path of the signaling circuit 200 .

[0043] The signaling circuit 200 may be configured to generate and transmit a multilevel signal 205, which may be modulated according to a modulation scheme (e.g., PAM3) that includes three or more different amplitude levels (e.g., level -1, level 0, level 1), each amplitude level associated with a respective value (e.g., -1, 0, 1) indicating information on the multilevel signal 205. In some cases, the multilevel signal 205 may include two or more portions 206, wherein each portion 206 (e.g., a sub-eye) is associated with a transition between two of the three or more different amplitude levels. The signaling circuit 200 may include, for example, two (e.g., more) signaling paths, each signaling path associated with generating and transmitting (e.g., driving) a respective portion 206 (e.g., a sub-eye) of the multilevel signal 205. For example, a first signaling path may be configured to generate and transmit a portion 206-a of a multilevel signal 205, such that the first signaling path may be associated with generating and transmitting the multilevel signal 205 at two of three or more different amplitude levels (e.g., level 1, level 0) or transitioning between the two. In some such examples, a second signaling path may be configured to generate and transmit a portion 206-b of the multilevel signal 205, such that the second signaling path may be associated with generating and transmitting the multilevel signal 205 at two of three or more different amplitude levels (e.g., level 0, level-1) or transitioning between the two. Each of the first signaling path and the second signaling path may include similar components configured to perform similar operations for generating, aligning, and transmitting a corresponding portion 206 of the multilevel signal 205. For clarity and brevity, a first signaling path is described herein, which may be exemplary of a second signaling path and include similar components.

[0044] The first signaling path may include a signaling component 210-a (e.g., a first signaling component) configured to generate and transmit a portion 206-a of the multi-level signal 205. The signaling component 210-a may include a serialization component 215-a (e.g., a first serialization component) and a transmission component 220-a (e.g., a first driver). The serialization component 215-a may be configured to serialize data 225-a received at the serialization component 215-a via one or more signals. In some examples, the data 225-a may be transmitted to the serialization component 215-a via one or more data lines 226-a, which may be examples of data channels 190, as described with reference to FIG. Figure 1As described. In some cases, serialized data 225-a may include converting data 225-a from parallel input to serial output. In some cases, serialized data 225-a may be associated with a portion 206-a that generates a multi-level signal 205, so that the portion 206-a of the multi-level signal 205 includes serialized data 225-a. For example, the serialization component 215-a may be configured to generate a portion 206-a (e.g., including serialized data 225-a) and transmit the portion 206-a to the transmission component 220-a. However, in other cases, after the serialization data 225-a, the serialization component 215-a may transmit the serialized data 225-a to the transmission component 220-a. The transmission component 220-a may be configured to transmit (e.g., drive) the portion 206-a to the pad 245 of the signaling circuit 200. In some cases, the transmission component 220-a can be configured to assemble the serialized data 225-a received from the serialization component 215-a into the portion 206-a and then transmit the portion 206-a to the pad 245. The pad 245 can be a contact (e.g., an electrode) coupled to a conductive path 250 configured to carry the multi-level signal 205 (e.g., to a receiver).

[0045] The first signaling path may also include an adjustable delay circuit 235-a coupled to the signaling component 210-a. The adjustable delay circuit 235-a may be configured to apply a time adjustment (e.g., a first time adjustment) to the clock signal 230. The clock signal 230 may provide a time reference for the operation of the signaling component 210-a, such that the serialization component 215-a and the transmission component 220-a may each perform operations described herein based on the clock signal 230. In some examples, the clock signal may be received at the adjustable delay circuit 235-b via one or more clock signal lines, which may be examples of the clock signal channel 188, such as reference 188. Figure 1 described. In some cases, applying the time adjustment to the clock signal 230 may delay one or more operations performed by the signaling component 210-a, such as generating and transmitting the portion 206-a. In some such cases, applying the time adjustment to the clock signal 230 may delay the timing of the portion 206-a within the resulting multi-level signal 205. For example, the signaling component 210-a may be associated with an inherent delay for performing operations associated with generating and transmitting the portion 206-a, and the time adjustment may provide additional delay for aligning the timing of the portion 206-a and the portion 206-b. In some examples, the time adjustment may be applied to the signaling component 210-a before the serialization component 215-a, at the serialization component 215-a, after the serialization component 215-a but before the transmission component 220-a, at the transmission component 220-a, or after the transmission component 220-a, or any combination thereof.

[0046] In some cases, the time adjustment may be associated with an indication (e.g., a value) stored in the read-only memory 240. In some such cases, the indication may be stored in one or more one-time programmable memory elements (e.g., fuses, antifuses) of the read-only memory 240. In some examples, applying the time adjustment may include accessing the read-only memory 240 to identify the indication and transmitting the indication to the adjustable delay circuit 235-a so that the adjustable delay circuit 235-a can apply the time adjustment associated with the indication. In some cases, the indication may be determined before the indication is stored in the read-only memory 240. In some such cases, determining the indication may include measuring a misalignment (e.g., a difference) in timing between the portion 206-a and the portion 206-b of the multi-level signal. The indication may be generated based on determining a delay (e.g., based on measuring the misalignment) that may be applied to the signaling component 210-a to align the timing of the portions 206-a and 206-b.

[0047] Similarly, the second signaling path may include a signaling component 210-b (e.g., a second signaling component) configured to generate and transmit a portion 206-b of the multilevel signal 205. The signaling component 210-b may include a serialization component 215-b (e.g., a second serialization component) and a transmission component 220-b (e.g., a second driver). The serialization component 215-b may be configured to serialize data 225-b received via one or more data lines 226-b. In some cases, the serialization component 215-b may be configured to generate the portion 206-b and transmit the portion 206-b or the serialized data 225-b to the transmission component 220-b. The transmission component 220-b may be configured to transmit (e.g., drive) the portion 206-b to the pad 245, or assemble the serialized data 225-b into the portion 206-b and then transmit the portion 206-b to the pad 245. The second signaling path may also include an adjustable delay circuit 235-b configured to apply a time adjustment (e.g., a second time adjustment) to the clock signal 230. In some such cases, applying the time adjustment may delay the timing of the portion 206-b within the resulting multi-level signal 205. The time adjustment may be associated with an indication (e.g., a value) stored in one or more one-time programmable memory elements of the read-only memory 240, and applying the time adjustment may include accessing, by the adjustable delay circuit 235-b, the indication in the read-only memory 240. The indication may be generated based on determining a delay that may be applied to the signaling component 210-b to align the timing of the portions 206-a and 206-b (e.g., based on measuring misalignment).

[0048] A process for operating the signaling circuit 200 may be described herein. The process may include identifying (e.g., receiving) data 225-a and data 225-b at the serialization component 215-a and the serialization component 215-b, respectively. The process may include concurrently receiving the clock signal 230 at both the adjustable delay circuit 235-a and the adjustable delay circuit 235-b. In some cases, the adjustable delay circuit 235-a may apply a first time adjustment to the clock signal 230 (e.g., generating a first time adjusted clock signal 230), and / or the adjustable delay circuit 235-b may apply a second time adjustment to the clock signal 230 (e.g., generating a second time adjusted clock signal 230). In some such cases, the adjustable delay circuit 235-a may transmit the first time adjusted clock signal 230 to the signaling component 210-a, and the adjustable delay circuit 235-b may transmit the second time adjusted clock signal 230 to the signaling component 210-b. Then, the serialization component 215-a can serialize the data 225-a based on the first time adjusted clock signal 230 to generate the portion 206-a. Similarly, the serialization component 215-b can serialize the data 225-a based on the second time adjusted clock signal 230 to generate the portion 206-b. After generating the portions 206-a and 206-b, the transmission component 220-a and the transmission component 220-b can transmit the corresponding portion 206 to the pad 245 based on the corresponding time adjustment. Finally, the pad 245 can transmit the multi-level signal 205 to the receiver along the conductive path 250, where the receiver can read the multi-level signal 205.

[0049] According to the examples described herein, applying individual time adjustments to each signal path can (e.g., in time) align the portion 206-a and portion 206-b of the multilevel signal 205. For example, each signaling component 210 can be associated with an inherent delay of the corresponding portion 206 for generating and transmitting the multilevel signal 205. However, applying the time adjustment can align the timing of the portion 206-a and portion 206-b so that the inherent delay of each signaling component 210 may not misalign the multilevel signal 205. In some cases, aligning the portion 206 of the multilevel signal 205 can support an increased SNR and a reduced BER, which can support an increased transmission speed of the multilevel signal 205 (e.g., compared to the previous implementation). In addition, due to the alignment read window of the portion 206 of the multilevel signal 205, aligning the portion 206 of the multilevel signal 205 can improve the reading of the multilevel signal 205 at the receiver of the multilevel signal 205.

[0050] Figure 3A and 3B1 shows examples of multi-level signaling diagrams 300-a and 300-b that support data alignment of memory according to examples disclosed herein. The multi-level signaling diagrams 300-a and 300-b can each be implemented as described in reference to Figure 2 Aspects of the signaling circuit 200 are described or their operation is shown. For example, multi-level signaling diagrams 300-a and 300-b illustrate read windows (e.g., sometimes referred to as eyes or sub-eyes) for a multi-level signal and a portion of a multi-level signal, which may be examples of a multi-level signal 205 and portions 206-a and 206-b, respectively, as shown in reference to Figure 2 Specifically, the multi-level signaling diagram 300-a illustrates a read window of a multi-level signal generated without applying individual time adjustments to portions of the multi-level signal (e.g., as in previous embodiments). However, the multi-level signaling diagram 300-b illustrates a read window of a multi-level signal 205 generated based on applying individual time adjustments to portions 206 of the multi-level signal 205.

[0051] Multilevel signaling diagrams 300-a and 300-b each depict a multilevel signal modulated using a modulation scheme (e.g., PAM3) including three levels 305, which may be different amplitude levels of a voltage. For example, the three levels 305 may include a level 305-a (e.g., level 1), a level 305-b (e.g., level 0), and a level 305-c (e.g., level -1), wherein each level 305 may be associated with a symbol (e.g., 1, 0, -1) representing the multilevel signal. For example, if the multilevel signal is sampled (e.g., read) when the multilevel signal is at level 305-a, the value of the multilevel signal may correspond to a value (e.g., 1) corresponding to level 305-a.

[0052] The multi-level signaling diagrams 300-a and 300-b also depict read windows for multi-level signals. For example, read window 310 (e.g., read window 310-a, read window 310-b) may be a read window for a portion of a multi-level signal associated with a transition between level 305-a and level 305-b (e.g., portion 206-a). Similarly, read window 315 (e.g., read window 315-a, read window 315-b) may be a read window for a portion of a multi-level signal associated with a transition between level 305-b and level 305-c (e.g., portion 206-b). Each read window 310 and each read window 315 may be associated with an ideal sampling point such that at the ideal sampling point, the corresponding portion of the multi-level signal may have a relatively strong SNR. For example, read window 310-a may have an ideal sampling point 311-a, and read window 315-a may have an ideal sampling point 316-a. In some cases, the multi-level signal may be sampled at the sampling point 320 , such that one or more values ​​of the multi-level signal may be sampled (eg, read) at the sampling point 320 .

[0053] However, in the multi-level signaling diagram 300-a, portions of the multi-level signal may be misaligned in time. For example, during the generation and / or transmission of portions of the multi-level signal, portions of the multi-level signal may become misaligned due to timing delays in the generation and / or transmission of the portions at the corresponding signal paths (e.g., the signaling components 210-a and 210-b). For example, if multiple signal paths are used to generate different portions of the multi-level signal (e.g., as shown in FIG. 2 ), the portions of the multi-level signal may become misaligned. Figure 2 316-a). In the example shown and described above, the read window may become misaligned in time. That is, without an adjustable delay circuit coupled to the signal path and configured to align the timing of a portion of the multilevel signal, the portion may be misaligned, resulting in misaligned read windows 310-a and 315-a. In addition, the misaligned read windows 310-a and 315-a may cause the sampling points 311-a and 316-a to be misaligned in time. However, because the multilevel signal is sampled at the sampling point 320-a, if any of the sampling points 311-a and 316-a is misaligned with the sampling point 320-a, the misaligned sampling points 311-a and / or 316-a may result in an increased probability of sampling error of the multilevel signal.

[0054] For example, if sampling point 311-a and sampling point 320-a are aligned, but sampling point 316-a and sampling point 320-a are misaligned, then sampling of the multilevel signal at sampling point 320-a may produce a value of a portion (e.g., portion 206-a) associated with read window 310-a. However, if both sampling points 311-a and 316-a are misaligned with sampling point 320-a, then sampling of the multilevel signal at sampling point 320-a may not produce, may be erroneously produced (e.g., misread), or may produce one of the values ​​associated with read windows 310-a and / or 315-a. Furthermore, as the misalignment between sampling points 311-a and 316-a increases, the BER of the multilevel signal may increase and the SNR of the multilevel signal may decrease, among other disadvantages.

[0055] However, in the multi-level signaling diagram 300-b, portions of the multi-level signal may be aligned in time. For example, during the generation and / or transmission of a portion of the multi-level signal, the portion of the multi-level signal may be aligned based on applying a time adjustment to a corresponding signal path associated with the generation and transmission of the portion of the multi-level signal. That is, an adjustable delay circuit coupled to the signal path may be configured to align the timing of the portion of the multi-level signal, thereby generating aligned read windows 310-b and 315-b. In addition, the aligned read windows 310-b and 315-b may cause the sampling points 311-b and 316-b to be aligned in time, or more closely aligned in time. Therefore, if the sampling points 311-b and 316-b are aligned in time, the multi-level signal may be sampled at the sampling point 320-b, where the sampling occurs where the sampling points 311-b and 316-b are aligned. In addition, increasing the alignment of the read windows 310-b and 315-b can increase the read window margin (e.g., sampling margin) for sampling the multi-level signal. Because the multi-level signal is sampled at a time when the read windows 310-b and 315-b have a relatively strong SNR, the multi-level signal can be sampled at a relatively low BER.

[0056] According to the examples described herein, applying individual time adjustments to portions of a multilevel signal to align the portions can achieve read window alignment of the portions. In some cases, aligning the read windows 310 and 315 of the multilevel signal can support increased SNR and reduced BER, which can support increased transmission speeds of the multilevel signal (e.g., compared to previous implementations). In addition, aligning the read windows 310 and 315 of the multilevel signal can improve reading of the multilevel signal at a receiver of the multilevel signal and other advantages.

[0057] Figure 4 A block diagram 400 is shown of a memory device 420 that supports data alignment of memory according to examples disclosed herein. The memory device 420 may be a reference Figure 1 3. Memory device 420 or its various components may be examples of means for performing various aspects of data alignment of memory described herein. For example, memory device 420 may include identification component 425, application component 430, generation component 435, transmission component 440, reception component 445, storage component 450, measurement component 455, determination component 460, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0058] The identification component 425 may be configured as or otherwise support means for identifying data for transmission as a multi-level signal on a conductive path, the data including first data processed by a first signaling component for transmission on a conductive path and second data processed by a second signaling component for transmission on a conductive path. The application component 430 may be configured as or otherwise support means for applying a first time adjustment to a clock signal received at the first signaling component. In some examples, the application component 430 may be configured as or otherwise support means for applying a second time adjustment to a clock signal received at the second signaling component. The generation component 435 may be configured as or otherwise support means for generating a multi-level signal based at least in part on the first signaling component generating a first portion of the multi-level signal including the first data and the second signaling component generating a second portion of the multi-level signal including the second data, wherein applying the first time adjustment and the second time adjustment to the clock signal is associated with aligning the timing of the first portion of the multi-level signal transmitted on the conductive path with the timing of the second portion of the multi-level signal transmitted on the conductive path.

[0059] In some examples, transmission component 440 can be configured as or otherwise support means for transmitting a multi-level signal based at least in part on generating the multi-level signal via a pad contacting a conductive path coupled with the first signaling component and the second signaling component.

[0060] In some examples, the first signaling component includes a first serialization component operable to serialize the first data, and the second signaling component includes a second serialization component operable to serialize the second data.

[0061] In some examples, the generating component 435 can be configured to or otherwise support means for serializing first data based at least in part on a first time adjustment of a clock signal, wherein generating the first portion of the multi-level signal is based at least in part on the serialized first data. In some examples, the generating component 435 can be configured to or otherwise support means for serializing second data based at least in part on a second time adjustment of a clock signal, wherein generating the second portion of the multi-level signal is based at least in part on the serialized second data.

[0062] In some examples, to support applying the first time adjustment to the clock signal, receiving component 445 can be configured or otherwise supports means for receiving the clock signal at the first adjustable delay circuit. In some examples, to support applying the first time adjustment to the clock signal, applying component 430 can be configured or otherwise supports means for applying a first delay to the clock signal via the first adjustable delay circuit, the first delay corresponding to the first time adjustment.

[0063] In some examples, to support applying the second time adjustment to the clock signal, receiving component 445 can be configured or otherwise supports means for receiving the clock signal at the second adjustable delay circuit. In some examples, to support applying the second time adjustment to the clock signal, applying component 430 can be configured or otherwise supports means for applying a second delay to the clock signal via the second adjustable delay circuit, the second delay corresponding to the second time adjustment.

[0064] In some examples, storage component 450 can be configured or otherwise support means for storing indications of the first time adjustment and the second time adjustment in a programmable read-only memory. In some examples, application component 430 can be configured or otherwise support means for applying the first time adjustment and the second time adjustment to the clock signal based at least in part on accessing the programmable read-only memory.

[0065] In some examples, the measuring component 455 may be configured as or otherwise support means for measuring a misalignment between the timing of a first portion of the multilevel signal transmitted on the conductive path and the timing of a second portion of the multilevel signal transmitted on the conductive path. In some examples, the determining component 460 may be configured as or otherwise support means for determining a first time adjustment and a second time adjustment based at least in part on the measured misalignment. In some examples, the storing component 450 may be configured as or otherwise support means for storing the first time adjustment and the second time adjustment in a programmable read-only memory, wherein applying the first time adjustment and applying the second time adjustment are based at least in part on the storage.

[0066] In some examples, the first signaling component includes a first driver operable to transmit a first portion of the multi-level signal. In some examples, the second signaling component includes a second driver operable to transmit a second portion of the multi-level signal.

[0067] In some examples, the transmission component 440 can be configured or otherwise support means for transmitting a first portion of the multilevel signal based at least in part on a first time adjustment to the clock signal. In some examples, the transmission component 440 can be configured or otherwise support means for transmitting a second portion of the multilevel signal based at least in part on a second time adjustment to the clock signal.

[0068] In some examples, to support aligning the timing of the first portion of the multilevel signal with the timing of the second portion of the multilevel signal, the generation component 435 may be configured as or otherwise support means for increasing a read window margin between a first read window of the first portion of the multilevel signal and a second read window of the second portion of the multilevel signal.

[0069] In some examples, the multi-level signal is modulated using a modulation scheme comprising three levels.

[0070] In some examples, the described functionality of the memory device 420 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more such elements). In some examples, the described functionality of the memory device 420 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0071] Figure 5 A flowchart illustrating a method 500 for supporting data alignment of a memory according to examples disclosed herein is shown. The operations of the method 500 may be implemented by a memory device or components thereof described herein. For example, the operations of the method 500 may be implemented by reference to Figures 1 to 4 The memory device described herein may be used to perform. In some examples, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. In addition, or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0072] At 505, the method may include identifying data for transmission on a conductive path as a multi-level signal, the data including first data processed by a first signaling component for transmission on the conductive path and second data processed by a second signaling component for transmission on the conductive path. In some examples, aspects of operation 505 may be as described with reference to Figure 4 The described identification component 425 is performed.

[0073] At 510, the method may include applying a first time adjustment to a clock signal received at a first signaling component. In some examples, aspects of operation 510 may be as described with reference to Figure 4 The described application component 430 is executed.

[0074] At 515, the method may include applying a second time adjustment to a clock signal received at a second signaling component. In some examples, aspects of operation 515 may be as described with reference to Figure 4 The described application component 430 is executed.

[0075] At 520, the method may include generating a multilevel signal based at least in part on a first signaling component generating a first portion of the multilevel signal including first data and a second signaling component generating a second portion of the multilevel signal including second data, wherein applying the first time adjustment and the second time adjustment to the clock signal is associated with aligning a timing of the first portion of the multilevel signal transmitted on the conductive path with a timing of the second portion of the multilevel signal transmitted on the conductive path. In some examples, aspects of operation 520 may be as described with reference to Figure 4 The described generation component 435 is executed.

[0076] In some examples, an apparatus as described herein may perform a method or several methods, such as method 500. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0077] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: identifying data for transmission as a multi-level signal on a conductive path, the data comprising first data processed by a first signaling component for transmission on the conductive path and second data processed by a second signaling component for transmission on the conductive path; applying a first time adjustment to a clock signal received at the first signaling component; applying a second time adjustment to the clock signal received at the second signaling component; and generating the multi-level signal based at least in part on the first signaling component generating a first portion of the multi-level signal including the first data and the second signaling component generating a second portion of the multi-level signal including the second data, wherein applying the first time adjustment and the second time adjustment to the clock signal is associated with aligning the timing of the first portion of the multi-level signal transmitted on the conductive path with the timing of the second portion of the multi-level signal transmitted on the conductive path.

[0078] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: transmitting the multi-level signal based at least in part on generating the multi-level signal via a pad contacting the conductive path, the pad being coupled to the first signaling component and the second signaling component.

[0079] Aspect 3: A method, device or non-transitory computer-readable medium according to any one of Aspects 1 to 2, wherein the first signaling component includes a first serialization component operable to serialize the first data, and the second signaling component includes a second serialization component operable to serialize the second data.

[0080] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of Aspect 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for serializing the first data based at least in part on the first time adjustment of the clock signal and serializing the second data based at least in part on the second time adjustment of the clock signal, wherein generating the first portion of the multi-level signal is based at least in part on serializing the first data, and wherein generating the second portion of the multi-level signal is based at least in part on serializing the second data.

[0081] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 4, wherein applying the first time adjustment to the clock signal includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving the clock signal at a first adjustable delay circuit and applying a first delay to the clock signal via the first adjustable delay circuit, the first delay corresponding to the first time adjustment.

[0082] Aspect 6: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 5, wherein applying the second time adjustment to the clock signal includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving the clock signal at a second adjustable delay circuit and applying a second delay to the clock signal via the second adjustable delay circuit, the second delay corresponding to the second time adjustment.

[0083] Aspect 7: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: storing indications of a first time adjustment and a second time adjustment in a programmable read-only memory, and wherein applying the first time adjustment and the second time adjustment to the clock signal is based at least in part on accessing the programmable read-only memory.

[0084] Aspect 8: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: measuring a misalignment between the timing of the first portion of the multi-level signal transmitted on the conductive path and the timing of the second portion of the multi-level signal transmitted on the conductive path; determining the first time adjustment and the second time adjustment based at least in part on measuring the misalignment; and storing the first time adjustment and the second time adjustment in a programmable read-only memory, wherein applying the first time adjustment and applying the second time adjustment are based at least in part on the storage.

[0085] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 8, wherein the first signaling component includes a first driver operable to serialize the first portion of the multi-level signal, and the second signaling component includes a second driver operable to serialize the second portion of the multi-level signal.

[0086] Aspect 10: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 9, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transmitting the first portion of the multi-level signal based at least in part on the first time adjustment to the clock signal and transmitting the second portion of the multi-level signal based at least in part on the second time adjustment to the clock signal.

[0087] Aspect 11: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 10, wherein aligning the timing of the first portion of the multi-level signal and the timing of the second portion of the multi-level signal includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for increasing a read window margin between a first read window of the first portion of the multi-level signal and a second read window of the second portion of the multi-level signal.

[0088] Aspect 12: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 11, wherein the multi-level signal is modulated using a modulation scheme comprising three levels.

[0089] It should be noted that the methods described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0090] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0091] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (e.g., conductive contact, connected, coupled) with each other if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. At any given time, the conductive path between components that are in electronic communication (e.g., conductive contact, connected, coupled) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0092] The term "coupled" (e.g., "electrically coupled") may refer to a condition that changes from an open circuit relationship between components (where signals are currently unable to be transmitted between the components (e.g., via a conductive path)) to a closed circuit relationship between the components (where signals are able to be transmitted between the components (e.g., via a conductive path). When a component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between the other components through conductive paths that previously did not allow signal flow.

[0093] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, when a switch positioned between two components is open, the components separated by the switch are isolated from one another. When a controller isolates two components, the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0094] As used herein, the term "electrode" may refer to an electrical conductor and, in some examples, may serve as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, or the like that provides a conductive path between components of a memory array.

[0095] As used herein (including in the claims), the article "a" before a noun is open-ended and is understood to refer to "at least one" of the noun or "one or more" of the noun. Therefore, the terms "one", "at least one", "one or more", and "at least one of one or more" are interchangeable. For example, if a claim sets forth a "component" that performs one or more functions, each of the individual functions may be performed by a single component or any combination of multiple components. Therefore, a "component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. A subsequent reference to a component incorporated with the article "a" using the term "the" may refer to any one or all of the one or more components. For example, a component incorporated with the article "a" may be understood to mean "one or more components", and a subsequent reference to "component" in a claim may be understood to be equivalent to a reference to "at least one of one or more components".

[0096] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0097] The switch components (e.g., transistors) discussed herein may represent field effect transistors (FETs) and may include three-terminal components including a source (e.g., a source terminal), a drain (e.g., a drain terminal), and a gate (e.g., a gate terminal). The terminals may be connected to other electronic components by conductive materials (e.g., metals, alloys). The source and drain may be conductive and may include doped (e.g., heavily doped, degenerate) semiconductor regions. The source and drain may be separated by doped (e.g., lightly doped) semiconductor regions or channels. If the channel is n-type (e.g., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (e.g., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated." A transistor may be “turned off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0098] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples". The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0099] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. When only the first reference label is used in the specification, the description may apply to any of the similar components with the same first reference label, regardless of the second reference label.

[0100] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions (e.g., code) on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0101] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed with a processor designed to perform the functions described herein, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0102] As used herein, "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one" or "one or more"), including as used in the claims, indicates an inclusive list, so that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

[0103] Computer-readable media include both non-transitory computer storage media and communication media, and the communication media include any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a computer. As an example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or can be used to carry or store the desired program code in the form of instructions or data structures and any other non-transitory media that can be accessed by a computer or processor. Moreover, any connection is appropriately referred to as computer-readable media. For example, if coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0104] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: at least one memory device; and at least one controller coupled to the at least one memory device and configured to cause the apparatus to: identifying data for transmission as a multi-level signal on a conductive path, the data comprising first data processed by a first signaling component for transmission on the conductive path and second data processed by a second signaling component for transmission on the conductive path; applying a first time adjustment to a clock signal received at the first signaling component; applying a second time adjustment to the clock signal received at the second signaling component; and The multilevel signal is generated based at least in part on the first signaling component generating a first portion of the multilevel signal including the first data and the second signaling component generating a second portion of the multilevel signal including the second data, wherein applying the first time adjustment and the second time adjustment to the clock signal is associated with aligning the timing of the first portion of the multilevel signal transmitted on the conductive path with the timing of the second portion of the multilevel signal transmitted on the conductive path.

2. The apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to: The multi-level signal is transmitted based at least in part on generating the multi-level signal via a pad contacting the conductive path, the pad being coupled to the first signaling component and the second signaling component. 3 . The apparatus of claim 1 , wherein the first signaling component comprises a first serialization component operable to serialize the first data, and the second signaling component comprises a second serialization component operable to serialize the second data.

4. The apparatus of claim 3, wherein the at least one controller is further configured to cause the apparatus to: serializing the first data based at least in part on the first time adjustment of the clock signal, wherein generating the first portion of the multi-level signal is based at least in part on serializing the first data; and The second data is serialized based at least in part on the second time adjustment to the clock signal, wherein generating the second portion of the multi-level signal is based at least in part on serializing the second data.

5. The apparatus of claim 1 , wherein applying the first time adjustment to the clock signal is configured to cause the apparatus to: receiving the clock signal at a first adjustable delay circuit; and A first delay is applied to the clock signal via the first adjustable delay circuit, the first delay corresponding to the first time adjustment.

6. The apparatus of claim 1 , wherein applying the second time adjustment to the clock signal is configured to cause the apparatus to: receiving the clock signal at a second adjustable delay circuit; and A second delay is applied to the clock signal via the second adjustable delay circuit, the second delay corresponding to the second time adjustment.

7. The apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to: storing an indication of the first time adjustment and the second time adjustment in a programmable read-only memory, Wherein applying the first timing adjustment and the second timing adjustment to the clock signal is based at least in part on accessing the programmable read-only memory.

8. The apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to: measuring a misalignment between the timing of the first portion of the multilevel signal transmitted on the conductive path and the timing of the second portion of the multilevel signal transmitted on the conductive path; determining the first time adjustment and the second time adjustment based at least in part on measuring the misalignment; and The first time adjustment and the second time adjustment are stored in a programmable read-only memory, wherein applying the first time adjustment and applying the second time adjustment are based at least in part on the storage.

9. The apparatus of claim 1, wherein: The first signaling component includes a first driver operable to transmit the first portion of the multi-level signal, and The second signaling component includes a second driver operable to transmit the second portion of the multi-level signal.

10. The apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to: transmitting the first portion of the multi-level signal based at least in part on the first time adjustment of the clock signal; and The second portion of the multi-level signal is transmitted based at least in part on the second time adjustment of the clock signal.

11. The apparatus of claim 1 , wherein aligning the timing of the first portion of the multilevel signal with the timing of the second portion of the multilevel signal is configured such that the apparatus: A read window margin between a first read window of the first portion of the multilevel signal and a second read window of the second portion of the multilevel signal is increased.

12. The apparatus of claim 1, wherein the multi-level signal is modulated using a modulation scheme including three levels.

13. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: identifying data for transmission as a multi-level signal on a conductive path, the data comprising first data processed by a first signaling component for transmission on the conductive path and second data processed by a second signaling component for transmission on the conductive path; applying a first time adjustment to a clock signal received at the first signaling component; applying a second time adjustment to the clock signal received at the second signaling component; and The multilevel signal is generated based at least in part on the first signaling component generating a first portion of the multilevel signal including the first data and the second signaling component generating a second portion of the multilevel signal including the second data, wherein applying the first time adjustment and the second time adjustment to the clock signal is associated with aligning the timing of the first portion of the multilevel signal transmitted on the conductive path with the timing of the second portion of the multilevel signal transmitted on the conductive path.

14. The non-transitory computer-readable medium of claim 13, wherein the instructions are further executable by the processor to: The multi-level signal is transmitted based at least in part on generating the multi-level signal via a pad contacting the conductive path, the pad being coupled to the first signaling component and the second signaling component.

15. The non-transitory computer-readable medium of claim 13, wherein the first signaling component comprises a first serialization component operable to serialize the first data based at least in part on the first time adjustment to the clock signal, and the second signaling component comprises a second serialization component operable to serialize the second data based at least in part on the second time adjustment to the clock signal.

16. The non-transitory computer-readable medium of claim 13, wherein the instructions to apply the first time adjustment to the clock signal are executable by the processor to: receiving the clock signal at a first adjustable delay circuit; and applying a first delay to the clock signal via the first adjustable delay circuit, the first delay corresponding to the first time adjustment; and wherein the instructions to apply the second time adjustment to the clock signal are executable by the processor to: receiving the clock signal at a second adjustable delay circuit; and A second delay is applied to the clock signal via the second adjustable delay circuit, the second delay corresponding to the second time adjustment.

17. The non-transitory computer-readable medium of claim 13, wherein the instructions are further executable by the processor to: storing an indication of the first time adjustment and the second time adjustment in a programmable read-only memory, Wherein applying the first timing adjustment and the second timing adjustment to the clock signal is based at least in part on accessing the programmable read-only memory.

18. The non-transitory computer-readable medium of claim 13, wherein the instructions are further executable by the processor to: measuring a misalignment between the timing of the first portion of the multilevel signal transmitted on the conductive path and the timing of the second portion of the multilevel signal transmitted on the conductive path; determining the first time adjustment and the second time adjustment based at least in part on measuring the misalignment; and The first time adjustment and the second time adjustment are stored in a programmable read-only memory, wherein applying the first time adjustment and applying the second time adjustment are based at least in part on the storage.

19. The non-transitory computer-readable medium of claim 13, wherein: The first signaling component includes a first driver operable to transmit the first portion of the multilevel signal based at least in part on the first time adjustment to the clock signal, and the second signaling component includes a second driver operable to transmit the second portion of the multilevel signal based at least in part on the second time adjustment to the clock signal.

20. A method comprising: identifying data for transmission as a multi-level signal on a conductive path, the data comprising first data processed by a first signaling component for transmission on the conductive path and second data processed by a second signaling component for transmission on the conductive path; applying a first time adjustment to a clock signal received at the first signaling component; applying a second time adjustment to the clock signal received at the second signaling component; and The multilevel signal is generated based at least in part on the first signaling component generating a first portion of the multilevel signal including the first data and the second signaling component generating a second portion of the multilevel signal including the second data, wherein applying the first time adjustment and the second time adjustment to the clock signal is associated with aligning the timing of the first portion of the multilevel signal transmitted on the conductive path with the timing of the second portion of the multilevel signal transmitted on the conductive path.

Images