Semiconductor memory device and self-refresh method of semiconductor memory device

Abstract

A semiconductor memory device and a self-refresh method of the semiconductor memory device are provided. The self-refresh method of the semiconductor memory device includes: receiving a self-refresh entry command associated with a self-refresh operation; counting a time elapsed from a time when the self-refresh entry command is received; and skipping the self-refresh operation according to whether a self-refresh exit command is received before the counted elapsed time exceeds a reference time.

Description

[0001] This patent application claims the priority benefit of Korean Patent Application No. 10-2023-0110775 filed on August 23, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a semiconductor memory device, and more particularly, to a semiconductor memory device that selectively performs a self-refresh operation and a self-refresh method thereof. Background Art

[0003] The semiconductor memory device may be a voltage memory such as a dynamic random access memory (DRAM) device, which uses charges stored in capacitors to store data. However, DRAM devices have limited data retention characteristics because the charges stored in the capacitors may leak through various paths over time. Therefore, DRAM devices use a refresh operation that periodically rewrites the data stored in the capacitors.

[0004] A DRAM self-refresh command may be used to perform a refresh of a DRAM device. For example, a self-refresh of a DRAM device may start in response to a self-refresh entry command and stop in response to a self-refresh exit command. The time between a self-refresh entry command and a self-refresh exit command is defined as the duration of a self-refresh operation. In certain operations, a DRAM self-refresh command may occur unnecessarily. For example, a self-refresh entry command and a self-refresh exit command may be set frequently without considering the duration. When self-refresh is repeatedly forced to be performed without requiring self-refresh, a logic error may occur. Summary of the invention

[0005] At least one embodiment of the present disclosure provides a semiconductor memory device which can autonomously perform a self-refresh operation in response to an externally input self-refresh command by considering a self-refresh duration time and a self-refresh method thereof.

[0006] According to an embodiment, a self-refresh method for a semiconductor memory device includes: receiving a self-refresh entry command associated with a self-refresh operation; counting the time elapsed from the time the self-refresh entry command is received; and skipping the self-refresh operation based on whether a self-refresh exit command is received before the counted elapsed time exceeds a reference time.

[0007] According to an embodiment, a semiconductor memory device includes a cell array, a command decoder, a control circuit, and a refresh controller. The cell array includes a plurality of dynamic random access memory (DRAM) cells. The command decoder is configured to decode a command associated with a self-refresh operation to generate a self-refresh entry command and a self-refresh exit command. The control circuit is configured to generate a control signal to skip the self-refresh operation when the time difference between the reception time of the self-refresh entry command and the reception time of the self-refresh exit command is shorter than a reference time. The refresh controller is configured to perform one of the following items in response to the control signal: (i) perform a self-refresh operation on a selected memory area of ​​the cell array, and (ii) skip the self-refresh operation.

[0008] According to an embodiment, a self-refresh method for a semiconductor memory device includes: receiving a self-refresh entry command associated with a self-refresh operation; delaying the self-refresh operation by a reference time in response to the self-refresh entry command; detecting whether a self-refresh exit command is input before the time elapsed from receiving the self-refresh entry command reaches the reference time; and skipping the self-refresh operation when the self-refresh exit command is received before the elapsed time reaches the reference time. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a memory system including a memory device according to an embodiment of the present invention.

[0010] Figure 2 is a block diagram illustrating a memory device according to an embodiment of the present invention.

[0011] Figure 3 is a block diagram illustrating the operation of a self-refresh skip circuit of a memory device according to an embodiment of the present invention.

[0012] Figure 4 is a diagram showing an embodiment of the present invention Figure 3 Block diagram of an oscillator duty cycle controller.

[0013] Figure 5 is a diagram showing an embodiment of the present invention Figure 3 Block diagram of a duration detector.

[0014] Figure 6 is a flow chart illustrating a method of operating a self-refresh skip circuit according to an embodiment of the present invention.

[0015] Figure 7 is a timing diagram illustrating an example operation of a self-refresh skip circuit.

[0016] Figure 8 is a timing diagram illustrating an example operation of a self-refresh skip circuit.

[0017] Fig. 9 is a flow chart illustrating a method of operating a self-refresh skip circuit according to an embodiment of the present invention.

[0018] Fig.10 It is shown Fig. 9 A timing diagram of an example operation of the self-refresh skip circuit described in .

[0019] Fig.11 is a timing diagram illustrating an example operation of a self-refresh skip circuit.

[0020] Fig.12 is a flow chart illustrating a method of operating a self-refresh skip circuit according to an embodiment of the present invention.

[0021] Fig.13 yes Fig.12 Timing diagram of the self-refresh method.

[0022] Fig.14 is a cross-sectional view showing a memory system according to an embodiment of the present invention.

[0023] Fig.15 is a block diagram illustrating an example of applying a memory device including a self-refresh skip circuit according to an embodiment of the present invention to a computing system. DETAILED DESCRIPTION

[0024] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the present disclosure are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. The same reference numerals are used in the specification and the drawings to refer to the same or similar parts.

[0025] Hereinafter, a DRAM device will be used as an example of a semiconductor memory device to explain the features and functions of the present invention. However, the semiconductor memory device is not limited thereto. In addition, the term "duration" used in this specification refers to the time between a self-refresh entry command SRE and a self-refresh exit command SRX.

[0026] Figure 1 is a block diagram showing a memory system including a memory device according to an embodiment of the present invention. Figure 1 , the memory system 1000 may include a memory controller 1100 (eg, a control circuit) and a memory device 1200 .

[0027] The memory controller 1100 may perform an access operation to write data to the memory device 1200 or read data stored in the memory device 1200. Data exchange between the memory controller 1100 and the memory device 1200 occurs through a data pad DQ. The memory controller 1100 may generate a command CMD and an address ADDR for writing data to the memory device 1200 or reading data stored in the memory device 1200. The memory controller 1100 may be at least one of a memory controller for controlling the memory device 1200, a system on chip SoC such as an application processor (AP), a central processing unit (CPU), and a graphics processing unit (GPU).

[0028] The memory controller 1100 may issue a refresh command to control a refresh operation in the memory device 1200. Examples of refresh commands include an all bank refresh ABR command and a per-bank refresh PBR command. In one embodiment, the ABR command causes all banks of a portion of the memory device 1200 to be refreshed simultaneously. In one embodiment, the per-bank refresh PBR command causes a separate bank of the memory device 1200 to be refreshed. In addition, the memory controller 1100 may provide commands (SRE, SRX) for controlling a self-refresh operation to the memory device 1200. The self-refresh entry command SRE is a command that indicates the start of a self-refresh operation, and the self-refresh exit command SRX is a command that indicates the end of a self-refresh operation that has been entered.

[0029] In one embodiment, the all bank refresh ABR command is a command for refreshing all banks of a selected cell row of memory cells of the memory device 1200. In one embodiment, when a refresh operation occurs in all memory banks, a read or write command to the memory bank being refreshed cannot be provided after providing the ABR command. In some embodiments, when an SRE command is provided, an all bank refresh ABR operation may be automatically initiated. When a per bank refresh PBR command is provided with an address specifying a bank, reading and writing to unselected banks is possible.

[0030] The memory controller 1100 does not consider the duration for the self-refresh operation, which is the time difference between the self-refresh entry command SRE and the self-refresh exit command SRX. In other words, the operation of issuing the self-refresh exit command SRX immediately after issuing the self-refresh entry command SRE may be repeated. In this case, the memory device 1200 may need to terminate immediately after starting the self-refresh operation. That is, the refresh operation may need to terminate before "the refresh cycle tREFi required to refresh the selected row" has passed. If this operation occurs frequently, a logic error or performance degradation may occur.

[0031] The memory device 1200 outputs the read data requested by the memory controller 1100 to the memory controller 1100, or stores the data requested to be written by the memory controller 1100 in the memory cell. In one embodiment, the memory device 1200 is configured to detect or determine whether the self-refresh command has a short duration (e.g., a duration less than a threshold). According to the detection result, the self-refresh operation can be skipped internally. That is, the memory device 1200 can detect the situation where the duration between the self-refresh entry command SRE and the self-refresh exit command SRX is shorter than or less than the threshold. When a self-refresh command with a short duration is detected, the self-refresh operation can be omitted. This function will be referred to as "self-refresh skip". For example, a previous set of received SRE commands and SRX commands with a short duration between them can be ignored in certain circumstances.

[0032] The memory device 1200 includes a self-refresh skip circuit 1280 and a refresh controller 1250 (e.g., a controller circuit) for self-refresh skipping. When a self-refresh entry command SRE is received, the self-refresh skip circuit 1280 delays the start of a self-refresh operation by a specific delay time. In one embodiment, the self-refresh skip circuit 1280 determines the self-refresh skip according to the reception time (e.g., time point) of the subsequent self-refresh exit command SRX. For example, when the self-refresh exit command SRX is received before the reference time Tref from the time when the self-refresh entry command SRE is received, the self-refresh skip circuit 1280 is configured to skip the delayed self-refresh operation. In one embodiment, when the subsequent self-refresh exit command SRX is received after the reference time Tref from the time when the self-refresh entry command SRE is received, the self-refresh skip circuit 1280 starts the delayed self-refresh operation. For example, when the subsequent self-refresh exit command SRX is received after the reference time Tref from the time when the self-refresh entry command SRE is received, the self-refresh skip circuit 1280 may immediately start the delayed self-refresh operation. In one embodiment, the reference time Tref may be set based on the refresh period tREFi of the memory device 1200. In one embodiment, the reference time Tref may be set to be shorter than or equal to the refresh period tREFi. In order to set the reference time Tref, the self-refresh skip circuit 1280 may further include a lookup table LUT set by a mode register setting MRS command. For example, the self-refresh skip circuit 1280 may refer to the lookup table LUT to determine the reference time Tref.

[0033] The refresh controller 1250 performs a self-refresh operation on the memory cells according to the control signal SR_Master generated by the self-refresh skip circuit 1280. In other words, the refresh controller 1250 may activate or control word lines of the memory cells to start and end the self-refresh operation according to the control signal SR_Master.

[0034] Here, the memory device 1200 may be a high bandwidth memory (HBM) or a next-generation DRAM (e.g., LPDDR6 or LPDDR7) operating at ultra-high speed. The memory device 1200 may be a semiconductor memory device in a system-in-package (SiP). Optionally, the memory device 1200 may include a volatile memory device (such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), and a static random access memory (SRAM)). Optionally, the memory device 1200 may be a non-volatile memory device (such as a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive memory (MRAM), a ferroelectric memory (FRAM), and a spin injection magnetization reversal memory (STT-RAM)). In this specification, the present invention is described based on DRAM, but the technical idea of ​​the present disclosure is not limited thereto.

[0035] As described above, according to the self-refresh skip operation autonomously performed in the memory device 1200 according to the embodiment of the present invention, unnecessary self-refresh operations can be omitted or skipped. Therefore, logical errors or power consumption in the memory device 1200 due to unnecessary self-refresh operations can be reduced.

[0036] Figure 2 is a block diagram showing a memory device according to an embodiment of the present invention. Figure 2 , the memory device 1200 includes a cell array 1210, a sense amplifier 1215, an address decoder 1220 (e.g., a first decoder circuit), a command decoder 1230 (e.g., a second decoder circuit), an activation controller 1240 (e.g., a first controller circuit), a refresh controller 1250 (e.g., a second controller circuit), a row decoder 1260 (e.g., a third decoder circuit), a column decoder 1265 (e.g., a fourth decoder circuit), an input / output (I / O) driver 1270 (e.g., a driver circuit), a self-refresh skip circuit 1280, and a mode register set (MRS) 1290.

[0037] The cell array 1210 includes a plurality of memory cells MC. Data stored in the memory cells MC may be provided to the input / output driver 1270 through the sense amplifier 1215. Alternatively, write data received from the input / output driver 1270 may be stored in a selected memory cell through the sense amplifier 1215. The column decoder 1265 and the row decoder 1260 may select a memory cell corresponding to the address ADDR.

[0038] The address decoder 1220 receives the address ADDR of the memory cell to be accessed. When data is stored in the cell array 1210 or read from the cell array 1210, the address ADDR is received and decoded in the address decoder 1220 to generate a decoded address. The decoded address may be delivered to the activation controller 1240, the row decoder 1260, and the column decoder 1265. The row decoder 1260 and the column decoder 1265 select the row and column specified by the address ADDR.

[0039] The command decoder 1230 receives various commands input through the command / address line. The command decoder 1230 decodes the command and may provide the decoded command to the circuit blocks such as the self-refresh skip circuit 1280, the activation controller 1240, and the refresh controller 1250. The command decoder 1230 may determine the input command by referring to externally applied signals such as row address strobe ( / RAS), column address strobe ( / CAS), and write enable ( / WE). Optionally, the command decoder 1230 may write data to a mode register set (MRS, not shown) according to the externally provided command and address. For example, a general auto-refresh operation may be input through a combination of control signals / RAS, / CAS, and / WE. Then, the refresh operation will be determined by the command decoder 1230, and the command decoder 1230 will provide the corresponding refresh command to the refresh controller 1250. In one embodiment, the command decoder 1230 sends a self-refresh entry command SRE and a subsequent self-refresh exit command SRX to the self-refresh skip circuit 1280 according to the decoding result of the input command.

[0040] In one embodiment, the activation controller 1240 generates an activation address and an activation signal according to the address ADDR and the command CMD provided from the address decoder 1220 and the command decoder 1230 , and then provides the activation address and the activation signal to the row decoder 1260 .

[0041] When a refresh command is input to the memory device 1200, the refresh controller 1250 performs a refresh operation corresponding to the refresh command. For example, when an all-bank refresh ABR command is received, the refresh controller 1250 simultaneously refreshes all memory banks corresponding to the selected row. When a per-bank refresh PBR command is received, the refresh controller 1250 will perform a refresh operation on a single bank selected by a bank address among a plurality of memory banks.

[0042] In one embodiment, the refresh controller 1250 generates an internal address for refreshing the selected memory cell during the self-refresh operation, and performs a refresh operation on the memory cell selected by the internal address. During the self-refresh operation, the refresh controller 1250 may delay the self-refresh operation for the selected memory cell according to the control signal SR_Master provided from the self-refresh skip circuit 1280. Alternatively, the refresh controller 1250 may start or skip the self-refresh operation for the selected memory cell according to the control signal SR_Master provided from the self-refresh skip circuit 1280.

[0043] The row decoder 1260 controls the operation of the cell array 1210 by providing an activation address, an activation signal, a refresh activation signal, and a refresh address. During a self-refresh cycle, the row decoder 1260 activates a cell row selected by the refresh controller 1250. The row decoder 1260 will activate a cell row of a selected memory bank during a self-refresh operation.

[0044] The input / output driver 1270 may receive data provided through the data pad DQ and provide the data to the sense amplifier 1215. The input / output driver 1270 may output data stored in the cell array 1210 through the data pad DQ. The input / output driver 1270 may receive a data strobe signal DQS when receiving the data. In addition, the input / output driver 1270 may output data using the data strobe signal DQS.

[0045] Upon receiving a self-refresh entry command (SRE) from the command decoder 1230, the self-refresh skip circuit 1280 delays the start of the self-refresh operation by a specific delay time. When a subsequent self-refresh exit command SRX is received before a reference time Tref from the time when the self-refresh entry command SRE is received, the self-refresh skip circuit 1280 may generate a control signal SR_Master to skip or omit the delayed self-refresh operation. In one embodiment, if a subsequent SRX command is not received even when the reference time Tref has passed since the self-refresh entry command SRE was received, the self-refresh skip circuit 1280 immediately performs the delayed self-refresh operation. In one embodiment, the reference time Tref is set to be shorter than the refresh period tREFi. In order to set the reference time Tref, the self-refresh skip circuit 1280 may also include a lookup table LUT set by a selection signal SEL provided from the mode register group 1290.

[0046] The mode register set 1290 sets the internal mode register in response to the MRS command and the address ADDR for specifying the operation mode of the memory device 1200. The mode register set 1290 according to an embodiment of the present invention may include a register for setting the length of the reference time Tref of the self-refresh skip circuit 1280. Alternatively, the mode register set 1290 may include a separate test mode register set TMRS for setting the reference time Tref of the self-refresh skip circuit 1280. In an embodiment of the present invention, the mode register set 1290 may generate a selection signal SEL for setting the length of the reference time Tref by a setting command (e.g., an MR4 operation (OP) code) provided externally.

[0047] Above, an exemplary structure of the memory device 1200 of the present invention has been described. The memory device 1200 according to an embodiment of the present invention is internally set to skip the self-refresh operation in the case of a self-refresh command (SRE to SRX) with a short duration. Therefore, the memory device 1200 can prevent or ignore the execution of unnecessary self-refresh operations. In addition, the memory device 1200 can reduce logic errors and power consumption caused by unnecessary self-refresh operations.

[0048] Figure 3 is a block diagram showing the operation of a self-refresh skip circuit according to an embodiment of the present invention. Figure 3 , the self-refresh skip circuit 1280 includes an oscillator duty cycle controller 1282 (eg, a controller circuit) and a duration detector 1284 (eg, a detector circuit). Here, the command decoder 1230 and the refresh controller 1250 are connected to Figure 2 The command decoder and refresh controller are the same, so their description will be omitted.

[0049] The oscillator duty cycle controller 1282 sets the length of the duration through, for example, an MRS command (e.g., MR4 OP code). In other words, the oscillator duty cycle controller 1282 can set the length of the interval between the self-refresh entry command SRE and the self-refresh exit command SRX corresponding to the skip condition of the self-refresh operation (i.e., "duration"). The duration detector 1284 can determine whether the length of the duration has exceeded the reference time Tref based on the oscillator cycle "OSC cycle" selected by the MRS command (MR4 OP code).

[0050] The duration detector 1284 may generate a clock signal (e.g., a clock signal iCLK to be described below) according to an oscillator cycle (or a period of an oscillator), and may generate a control signal SR_Master by comparing the length of the duration with a reference time Tref based on the clock signal. The duration detector 1284 determines the period of the oscillator according to the period defined by the oscillator cycle. For example, if the oscillator cycle "OSC cycle" is set to 0.6 times the refresh period tREFi of the memory device 1200, the reference time Tref for determining whether to skip the self-refresh operation is set to "0.6×tREFi" corresponding to 1 cycle of the oscillator cycle "OSC cycle". If the self-refresh exit command SRX is not input when the reference time Tref corresponding to 1 cycle (0.6×tREFi) passes after the self-refresh entry command SRE is received, the duration detector 1284 generates a control signal SR_Master to actually perform the self-refresh operation when the self-refresh exit command SRX is not received when "0.6×tREFi" passes after the SRE command is received. However, the self refresh exit command SRX may be received before the reference time Tref of “0.6×tREFi” elapses after the self refresh entry command SRE is provided, the duration detector 1284 may generate the control signal SR_Master to skip or omit the self refresh operation.

[0051] In one embodiment, the duration detector 1284 operates to prevent the self-refresh operation from being skipped more than a certain number of times when the self-refresh operation is skipped continuously. That is, the event of providing the self-refresh exit command SRX may occur continuously before the reference time Tref has passed after the self-refresh entry command SRE has been received. In this case, the self-refresh operation may be skipped continuously. Therefore, when the skip event of the self-refresh operation based on the reference time Tref occurs continuously for more than the reference number of times, the duration detector 1284 may generate a control signal SR_Master to force the start of the self-refresh operation. For example, if too many pairs of SRE and SRX commands are received before the reference time Tref has passed, the event may be interpreted as the need to perform a self-refresh operation.

[0052] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 3 The block diagram of the oscillator duty cycle controller is shown in Figure 1. Figure 4 , the oscillator duty cycle controller 1282 may include a lookup table 1281 and a multiplexer (MUX) 1283 .

[0053] In the lookup table 1281, a value for setting a period or duty cycle of the oscillator 1285 included in the duration detector 1284 is set. The lookup table 1281 provides a delay time value from when the self-refresh entry command SRE is input until the self-refresh operation occurs in the form of a table. The oscillator cycle "OSCcycle" selected by the multiplexer 1283 (for example, based on the selection signal SEL) may be output by the MR4 opcode. In one embodiment, the multiplexer 1283 may be configured to select and output one of a plurality of period setting values ​​included in the lookup table 1281 in response to the mode register setting command.

[0054] For example, if the reference time Tref as the skip criterion of the self-refresh operation needs to be set to 0.7 times the refresh period (tREFi), "0.70×tREFi" of the lookup table 1281 can be selected. Then, the multiplexer 1283 will output the oscillator cycle "OSC cycle" corresponding to "0.70×tREFi" through the MR4 operation code. The lookup table 1281 and the multiplexer 1283 can be implemented using a memory and a logic circuit.

[0055] Figure 5 is a diagram showing a method according to an embodiment of the present invention. Figure 3 The block diagram of the duration detector is shown in Figure 1. Figure 5 , the duration detector 1284 may include an oscillator 1285 and a counter 1287 (eg, a counter circuit).

[0056] The oscillator 1285 generates a clock signal iCLK according to an oscillator cycle "OSC cycle" provided by the oscillator duty cycle controller 1282. For example, the clock signal iCLK may be generated with a period of 0.5 to 1 times the refresh period tREFi according to a set value. If the oscillator cycle "OSC cycle" is set to "0.70×tREFi", the oscillator 1285 will generate a clock signal iCLK of a corresponding cycle and provide the clock signal iCLK to the counter 1287. The oscillator 1285 may be configured using various clock generation circuits. For example, the oscillator 1285 may use a device such as a phase-locked loop (PLL) or a delay-locked loop (DLL) to generate a clock signal iCLK having a set period.

[0057] The counter 1287 uses the clock signal iCLK to count from the moment when the self-refresh entry (SRE) command is input. The counter 1287 may increment the value to perform counting each time it detects a rising edge or a falling edge of the clock signal iCLK. The counter 1287 may check whether the self-refresh exit command SRX is received from the time when the self-refresh entry command SRE is received until the reference time Tref has passed. The counter 1287 generates a control signal SR_Master according to whether the self-refresh exit command SRX is received, and the control signal SR_Master indicates whether the self-refresh command is actually executed. For example, it can be assumed that the cycle of the clock signal iCLK is set to 0.8 times the refresh cycle tREFi of the memory device 1200. Then, if the self-refresh exit command SRX is not input when the reference time (Tref=0.8×tREFi) has passed after the self-refresh entry command SRE is received, the counter 1287 activates the control signal SR_Master so that the actual self-refresh starts. If the self refresh exit command SRX is received before the reference time Tref of “0.8×tREFi” elapses after the self refresh enter command SRE is provided, the counter 1287 keeps the control signal SR_Master in an inactive state so that the self refresh operation is skipped.

[0058] Figure 6 is a flow chart showing a method of operating a self-refresh skip circuit according to an embodiment of the present invention. Figure 6 The self-refresh skip circuit 1280 detects whether a self-refresh exit command SRX is received before a reference time Tref elapses after receiving the self-refresh enter command SRE. The self-refresh skip circuit 1280 may skip or execute the requested self-refresh operation according to the detection result.

[0059] In step S110, the self-refresh skip circuit 1280 receives a self-refresh entry command SRE provided from the outside. The self-refresh entry command SRE may be received by the command decoder 1230 (see Figure 2 ) is decoded and provided to the self-refresh skip circuit 1280.

[0060] In step S120, the time elapsed from the time point when the self-refresh entry command SRE is received is counted. For example, the time elapsed from the oscillator 1285 (see Figure 5 ) outputs a clock signal iCLK to count the elapsed time, and the clock signal iCLK is set to a period corresponding to the reference time Tref. Meanwhile, the self-refresh skip circuit 1280 can detect whether a self-refresh exit command SRX is received after a self-refresh entry command SRE.

[0061] In step S130, the self-refresh skip circuit 1280 determines whether the self-refresh exit command SRX is received before the reference time Tref elapses after the self-refresh entry command SRE is received. If the self-refresh exit command SRX is not received before the reference time Tref elapses (“No” direction), the program proceeds to step S140. On the other hand, if it is determined that the self-refresh exit command SRX has been received before the reference time Tref elapses (“Yes” direction), the program proceeds to step S150.

[0062] In step S140, the self-refresh skip circuit 1280 activates the control signal SR_Master to start the self-refresh operation requested by the self-refresh entry command SRE. Then, in response to the activated control signal SR_Master, the refresh controller 1250 (see Figure 3 ) starts a requested self-refresh operation (e.g., all bank refresh).

[0063] In step S150 , the self refresh skip circuit 1280 deactivates the control signal SR_Master to skip the self refresh operation requested by the self refresh entry command SRE. Then, in response to the deactivated control signal SR_Master, the refresh controller 1250 skips the requested self refresh operation.

[0064] According to an embodiment of the present invention, the memory device 1200 may skip a self-refresh operation when the duration between the self-refresh entry command SRE and the self-refresh exit command SRX is shorter than the reference time Tref. Therefore, when a self-refresh entry / exit command with a short duration is provided, the memory device 1200 determines to skip the self-refresh operation. Therefore, the memory device 1200 may autonomously skip an unnecessary self-refresh operation. Therefore, the occurrence of logic errors and power consumption caused by unnecessary self-refresh operations occurring in the memory device 1200 may be reduced.

[0065] Figure 7 is a timing diagram showing an example operation of a self-refresh skip circuit according to an embodiment. Figure 7 , showing that when the duration (ΔT1) between the self-refresh entry command SRE and the self-refresh exit command SRX is longer than the reference time Tref, the self-refresh skip circuit 1280 (see Figure 3 That is, a case where a self refresh exit command SRX is received after a reference time Tref has passed since a self refresh enter command SRE was received is shown.

[0066] At time point T0, a self-refresh entry command SRE is input from the outside. Then, the self-refresh skip circuit 1280 uses the duration detector 1284 (see Figure 5) counts the time elapsed from the time point T0 when the self-refresh entry command SRE is received. At this time, the self-refresh entry command SRE is received, but the self-refresh operation is not started. Therefore, the control signal SR_Master will maintain an inactive low level "L" from the time point T0 to the time point T1. Due to the inactive state of the control signal SR_Master, the refresh controller 1250 does not start the self-refresh operation of the selected memory area.

[0067] The time point T1 corresponds to the time when the reference time Tref has passed since the time point T0 when the self-refresh entry command SRE is received. However, when the reference time Tref has passed since the self-refresh entry command SRE has been received, the self-refresh exit command SRX has not been received. Therefore, the self-refresh skip circuit 1280 activates the level of the control signal SR_Master to a high level "H". When the control signal SR_Master is activated, the refresh controller 1250 starts the self-refresh operation of the selected memory area. For example, the refresh controller 1250 may start an all-bank refresh ABR operation. The self-refresh operation for the selected memory area will continue until the self-refresh exit command SRX is detected at the time point T3.

[0068] At time point T2, the self-refresh exit command SRX is received. Therefore, the duration corresponding to the time difference between the self-refresh entry command SRE and the self-refresh exit command SRX will be counted as "ΔT1". Since the duration is longer than the reference time Tref, the self-refresh operation of the memory device 1200 can be activated. In response to the self-refresh exit command SRX, the control signal SR_Master is deactivated to a low level "L" at time point T3. Therefore, the self-refresh operation triggered by the self-refresh entry command SRE is terminated.

[0069] In the above, the operation of the self-refresh skip circuit 1280 has been described when the duration ΔT1 between the self-refresh entry command SRE and the self-refresh exit command SRX is longer than the reference time Tref. In other words, if the self-refresh exit command SRX is not received until the reference time Tref has passed since the self-refresh entry command SRE was received, the self-refresh operation of the selected memory area is started. Although not shown, in one embodiment, the case where the duration between the self-refresh entry command SRE and the self-refresh exit command SRX is equal to the reference time Tref is similar to the case described above where the duration is longer than the reference time Tref, that is, the level of the control signal SR_Master is activated to the high level "H" and the self-refresh operation of the selected memory area is started.

[0070] Figure 8 is a timing diagram showing a self-refresh skip operation of a self-refresh skip circuit according to an embodiment. Figure 8 , showing that the self-refresh skip circuit 1280 (see Figure 3 ) operation.

[0071] At time point T0, a self-refresh entry command SRE is input from the outside. Then, the self-refresh skip circuit 1280 uses the duration detector 1284 (see Figure 5 ) counts the time elapsed from the time point T0 when the self-refresh entry command SRE is received. At this time, the self-refresh operation does not start immediately after the self-refresh entry command SRE is received. Therefore, the control signal SR_Master will maintain an inactive low level "L" until a reference time Tref has passed from the time point T0. Due to the inactive state of the control signal SR_Master, the refresh controller 1250 maintains the self-refresh operation of the selected memory area in an inactive state.

[0072] The self-refresh exit command SRX is received at time point T1. Time point T1 corresponds to the time before the reference time Tref has passed since time point T0 when the self-refresh entry command SRE is received. Since the self-refresh exit command SRX is received before the reference time Tref has passed, the self-refresh skip circuit 1280 maintains the level of the control signal SR_Master at an inactive low level "L". The duration corresponding to the time difference between the self-refresh entry command SRE and the self-refresh exit command SRX will be counted as "ΔT2". Because the duration ΔT2 is shorter than the reference time Tref, the self-refresh operation of the memory device 1200 is skipped.

[0073] In the above, the operation of the self refresh skip circuit 1280 has been described when the duration ΔT2 between the self refresh entry command SRE and the self refresh exit command SRX is shorter than the reference time Tref. That is, if the self refresh exit command SRX is received before the reference time Tref elapses after the self refresh entry command SRE is received, the self refresh operation of the selected memory area may be skipped.

[0074] Fig. 9 is a flow chart showing a method of operating a self-refresh skip circuit according to an embodiment of the present invention. Fig. 9 When receiving the self-refresh entry command SRE, the self-refresh skip circuit 1280 delays the execution of the all-bank refresh ABR operation by the reference time Tref. In addition, the execution or skipping of the delayed all-bank refresh ABR operation is determined according to whether the self-refresh exit command SRX is received within the reference time Tref.

[0075] In step S210, the self-refresh skip circuit 1280 receives a self-refresh entry command SRE provided from the outside. The self-refresh entry command SRE is received by the command decoder 1230 (see Figure 2 ) is decoded and then provided to the self-refresh skip circuit 1280.

[0076] In step S220, the self-refresh skip circuit 1280 delays the all-bank refresh (ABR) operation that would otherwise start immediately upon receiving the existing self-refresh entry command SRE by a reference time Tref. In the case of the memory device 1200 in some embodiments, the all-bank refresh (ABR) operation may be set to start upon receiving the self-refresh entry command SRE. When the self-refresh entry command SRE is received, the self-refresh skip circuit 1280 according to an embodiment of the present invention may delay the start time of the all-bank refresh (ABR) operation by a reference time Tref. At the same time, the self-refresh skip circuit 1280 may detect whether the self-refresh exit command SRX is received.

[0077] In step S230, the self-refresh skip circuit 1280 determines whether the self-refresh exit command SRX is received before the reference time Tref has passed from the time point T1 at which the self-refresh entry command SRE was received. If it is determined that the self-refresh exit command SRX has not been received before the reference time Tref has passed (the "No" direction), the program proceeds to step S240. On the other hand, if it is determined that the self-refresh exit command SRX has been received before the reference time Tref has passed (the "Yes" direction), the program proceeds to step S250.

[0078] In step S240, the self-refresh skip circuit 1280 activates the control signal SR_Master to start the all-bank refresh ABR operation requested by the self-refresh entry command SRE. Then, in response to the activated control signal SR_Master, the refresh controller 1250 (see Figure 3 ) starts refreshing the ABR operation for all memory banks in the selected memory area.

[0079] In step S250, the self-refresh skip circuit 1280 deactivates the control signal SR_Master to skip the self-refresh operation requested by the self-refresh entry command SRE. Then, in response to the deactivated control signal SR_Master, the refresh controller 1250 (see Figure 3 ) can cancel or ignore the requested self-refresh command.

[0080] Due to the function of the self-refresh skip circuit 1280 according to an embodiment of the present invention, when the duration as the time interval between the self-refresh entry command SRE and the self-refresh exit command SRX is shorter than the reference time Tref, the memory device 1200 can skip all bank refresh ABR operations. In other words, when a self-refresh entry / exit command with a short duration is provided, the memory device 1200 determines to skip all bank refresh ABR operations. In this way, the memory device 1200 can autonomously skip unnecessary self-refresh operations. Therefore, logical errors and power consumption caused by unnecessary self-refresh operations can be reduced.

[0081] Fig.10 It is shown Fig. 9 A timing diagram of an example operation of the self-refresh skip circuit described in . Fig.10 , showing that the self-refresh skip circuit 1280 (see FIG. 1 ) is activated when the duration (ΔT3) between the self-refresh entry command SRE and the self-refresh exit command SRX is longer than the reference time Tref. Figure 3 ) operation.

[0082] At time point T0, a self-refresh entry command SRE is input from the outside. Then, the self-refresh skip circuit 1280 delays the entire bank refresh ABR operation (e.g., ABR1') that would otherwise start immediately upon receiving the self-refresh entry command SRE by a reference time Tref. That is, the self-refresh skip circuit 1280 maintains the control signal SR_Master at an inactive low level "L" (e.g., a first logic level) at time point T0 for a reference time Tref. Due to the inactive state of the control signal SR_Master, the refresh controller 1250 does not start the self-refresh operation of the selected memory area. At the same time, the self-refresh skip circuit 1280 can detect whether the self-refresh exit command SRX is received.

[0083] The time point T1 corresponds to the time after the reference time Tref has passed since the time point T0 when the self-refresh entry command SRE is received. However, when the reference time Tref has passed after the self-refresh entry command SRE is received, the self-refresh exit command SRX is not received. Therefore, the self-refresh skip circuit 1280 activates the level of the control signal SR_Master to a high level "H" (e.g., a second logic level). When the control signal SR_Master is activated, the refresh controller 1250 starts the self-refresh operation of the selected memory area. That is, the refresh controller 1250 (e.g., at the time point T1) starts the delayed full bank refresh ABR1 operation. Afterwards, the full bank refresh (ABR2 (e.g., starting at the time point T2), ABR3, ..., ABRn (e.g., starting at the time point T3), where n is an integer greater than 0) operation will continue at each refresh cycle tREFi until the self-refresh exit command SRX is received. For example, the full bank refresh operation may be performed periodically according to the refresh cycle tREFi until the self-refresh exit command SRX is received.

[0084] At time point T4, the self-refresh exit command SRX is received. Therefore, the duration corresponding to the time difference between the self-refresh entry command SRE and the self-refresh exit command SRX will be counted as "ΔT3". As a result, since the duration is longer than the reference time Tref, the self-refresh operation of the memory device 1200 is activated. In response to the self-refresh exit command SRX, the control signal SR_Master is deactivated to a low level "L" at time point T5. Therefore, the self-refresh operation triggered by the self-refresh entry command SRE is terminated.

[0085] In the above, the operation of the self refresh skip circuit 1280 has been described when the duration ΔT3 between the self refresh entry command SRE and the self refresh exit command SRX is longer than the reference time Tref. That is, if the self refresh exit command SRX is not received until the reference time Tref has passed since the self refresh entry command SRE was received, the self refresh operation of the selected memory area may be started.

[0086] Fig.11 It is shown Fig. 9 A timing diagram of an example operation of the self-refresh skip circuit described in . Fig.11 , showing a case where the duration ΔT4 between the self-refresh entry command SRE and the self-refresh exit command SRX is shorter than the reference time Tref. That is, the self-refresh skip circuit 1280 (see Figure 3 ) as an example.

[0087] At time point T0, a self-refresh entry command SRE is input from the outside. Then, the self-refresh skip circuit 1280 delays the full bank refresh ABR operation that would otherwise start immediately upon receiving the self-refresh entry command SRE by a reference time Tref. That is, the self-refresh skip circuit 1280 will maintain the control signal SR_Master at an inactive low level "L" for a reference time Tref at time point T0. Due to the inactive state of the control signal SR_Master, the refresh controller 1250 does not start the self-refresh operation of the selected memory area. At the same time, the self-refresh skip circuit 1280 can detect whether the self-refresh exit command SRX is received.

[0088] At time point T1, the self-refresh exit command SRX is received. Time point T1 corresponds to the time before the reference time Tref has passed since time point T0 when the self-refresh entry command SRE is received. Since the self-refresh exit command SRX is received before the reference time Tref has passed, the self-refresh skip circuit 1280 maintains the level of the control signal SR_Master at the low level "L" as an inactive state. The duration corresponding to the time difference between the self-refresh entry command SRE and the self-refresh exit command SRX will be counted as "ΔT4". Since the duration ΔT4 is shorter than the reference time Tref, the self-refresh operation of the memory device 1200 can be skipped or omitted.

[0089] In the above, the operation of the self-refresh skip circuit 1280 has been described when the duration ΔT4 between the self-refresh entry command SRE and the self-refresh exit command SRX is shorter than the reference time Tref. That is, if the self-refresh exit command SRX is received before the reference time Tref elapses after the self-refresh entry command SRE is received, the refresh operation of all banks of the selected memory area can be skipped.

[0090] Fig.12 1 is a flow chart showing a method of operating a self-refresh skip circuit according to an embodiment of the present invention. Because events having a duration shorter than the reference time Tref occur continuously, the self-refresh operation may be skipped continuously. In this case, the self-refresh skip circuit 1280 may detect the event and prevent the self-refresh operation from being skipped excessively. Fig.12 When the self-refresh operation is continuously skipped exceeding a reference number (or a threshold number) nTH, the self-refresh skip circuit 1280 may force a self-refresh operation thereafter even if the skip condition is satisfied.

[0091] In step S310, the self-refresh skip circuit 1280 detects an event in which the self-refresh operation is skipped twice or more in succession. For example, there may be a situation in which the duration between the self-refresh entry command SRE and the self-refresh exit command SRX is shorter than the reference time Tref, and the interval between the self-refresh entry command SRE and the subsequent self-refresh entry command SRE is shorter than the refresh period tREFi. Therefore, this corresponds to a situation in which the self-refresh operation is skipped twice or more in succession. If the self-refresh operation is skipped continuously and repeatedly, the self-refresh operation required to ensure data integrity may also be skipped, resulting in an error.

[0092] In step S320, the self-refresh skip circuit 1280 counts the number of times nSK_SR that the self-refresh operation is skipped when the self-refresh operation is skipped two or more times in succession. For example, the self-refresh skip circuit 1280 may count the number of self-refresh operations that are skipped in succession. For example, the self-refresh skip circuit 1280 may include a separate counter for counting the number of times the self-refresh operation is skipped in succession.

[0093] In step S330, the self-refresh skip circuit 1280 determines whether the number of consecutive skips nSK_SR of the self-refresh operation has reached the threshold number nTH. In one example, it is assumed that the threshold number nTH is "3". Then, when the number of skips nSK_SR of the consecutive self-refresh operation reaches "3", the self-refresh skip circuit 1280 performs the externally requested self-refresh operation regardless of the duration. If it is determined that the number of skips nSK_SR of the consecutive self-refresh operation is equal to the threshold number nTH ("Yes" direction), the program proceeds to step S340. On the other hand, if it is determined that the number of skips nSK_SR of the consecutive self-refresh operation is not equal to the threshold number nTH ("No" direction), the program returns to step S320.

[0094] In step S340, the self-refresh skip circuit 1280 activates the control signal SR_Master to start the self-refresh operation requested by the self-refresh entry command SRE. Then, in response to the activated control signal SR_Master, the refresh controller 1250 (see Figure 3 ) to start a self-refresh operation (e.g., an ABR operation).

[0095] In the above, the function of the embodiment of the self-refresh skip circuit 1280 according to the present invention has been described. An event in which the duration between the self-refresh entry command SRE and the self-refresh exit command SRX is shorter than the reference time Tref may occur continuously and repeatedly. In this case, in the worst case, the self-refresh operation may not be performed in time, and the stored data may be lost. Therefore, when the self-refresh operation is continuously skipped exceeding the reference number nTH, the self-refresh skip circuit 1280 may be set to perform the self-refresh operation thereafter even if the skip condition is met.

[0096] Fig.13 It is shown Fig.12 The timing diagram of the self-refresh method. Fig.13 , an event in which the duration (ΔT1, ΔT2, and ΔT3) between the self refresh entry command SRE and the self refresh exit command SRX is shorter than the reference time Tref may occur continuously. Here, it is assumed that the threshold number nTH is "2".

[0097] The self-refresh entry command SRE is received at time point T0, and the self-refresh exit command SRX is applied at time point T1. At this time, the duration ΔT1 between the self-refresh entry command SRE and the self-refresh exit command SRX is shorter than the reference time Tref and corresponds to the self-refresh skip condition. Therefore, the self-refresh entry command SRE requested at time point T0 is ignored.

[0098] The self-refresh entry command SRE is received at time point T2, and the self-refresh exit command SRX is applied at time point T3. At this time, the duration ΔT2 between the self-refresh entry command SRE and the self-refresh exit command SRX is shorter than the reference time Tref and corresponds to the self-refresh skip condition. Therefore, the self-refresh entry command SRE requested at time point T2 is also ignored. Finally, two self-refresh operations are skipped in succession.

[0099] The self-refresh entry command SRE is received at time point T4, and the self-refresh exit command SRX is applied at time point T5. At this time, the duration ΔT3 between the self-refresh entry command SRE and the self-refresh exit command SRX is shorter than the reference time Tref, corresponding to the self-refresh skip condition. However, since the number of consecutive self-refresh skips nSK_SR has reached the threshold number (nTH=2) at time point T3, the self-refresh skip circuit 1280 activates the control signal SR_Master to a high level "H" at time point T4. Then, a self-refresh operation (e.g., ABR1) may be started in the refresh controller 1250. In one example, in response to the self-refresh exit command SRX, the control signal SR_Master may be deactivated to a low level "L" at time point T6. Therefore, the self-refresh operation triggered by the self-refresh entry command SRE may be terminated.

[0100] In the above, the method is described for the event that the duration between the self-refresh entry command SRE and the self-refresh exit command SRX is shorter than the reference time Tref continuously and repeatedly occurs. In this case, in the worst case, the self-refresh operation may not be performed in time, and the stored data may be lost. However, the memory device 1200 according to an embodiment of the present invention can detect this situation and force the self-refresh operation to be performed.

[0101] Fig.14 2 is a cross-sectional view showing a memory system according to an embodiment of the present invention. Fig.14 , a memory system 2000 implemented as a stacked memory includes a printed circuit board (PCB) substrate (SUB) 2100, an interposer 2150, a host die (e.g., SOC) 2200, a logic die 2300, and high-bandwidth DRAMs 2310 (DRAM0), 2320 (DRAM1), 2330 (DRAM2), and 2340 (DRAM3).

[0102] The memory system 2000 connects the high bandwidth DRAMs 2310, 2320, 2330, and 2340 with the host die 2200 using an interposer 2150. The interposer 2150 is disposed on an upper portion of the PCB substrate 2100 and is electrically connected to the PCB substrate 2100 through flip chip bumps FB.

[0103] The host die 2200, the logic die 2300, and the high-bandwidth DRAMs 2310, 2320, 2330, and 2340 in the stacked structure may be disposed on the interposer 2150. To implement the memory system 2000, through-silicon via (TSV, or through-silicon via) lines are formed in the plurality of high-bandwidth DRAMs 2310, 2320, 2330, and 2340. The TSV lines may be electrically connected to micro-bumps formed between the plurality of high-bandwidth DRAMs 2310, 2320, 2330, and 2340. Signals may be sent and received between the logic die 2300 and the host die 2200 through a physical layer (PHY).

[0104] Here, the plurality of high bandwidth DRAMs 2310, 2320, 2330, and 2340 may each skip a self-refresh operation according to a duration between a self-refresh entry command SRE and a self-refresh exit command SRX. Therefore, each of the plurality of high bandwidth DRAMs 2310, 2320, 2330, and 2340 may reduce logic errors or reduce power consumption by omitting unnecessary self-refresh operations.

[0105] Fig.15 is a block diagram showing an example of applying a memory device including a self-refresh skip circuit according to an embodiment of the present invention to a computing system. Fig.15 , the computing system 3000 includes a processor 3100, an input / output hub (IOH) 3200, an input / output controller hub (ICH) 3300, a memory device 3400, and a graphic card 3500. According to an embodiment, the computing system 3000 may be at least one of a personal computer (PC), a server computer, a workstation, a laptop computer, a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, a music player, a portable game console, a navigation system, and the like.

[0106] The processor 3100 may perform various computing functions (such as specific calculations or tasks). For example, the processor 3100 may be a microprocessor or a central processing unit CPU. According to an embodiment, the processor 3100 may include one processor core (single core) or may include multiple processor cores (multi-core). For example, the processor 3100 may include dual cores, quad cores, hexa cores, etc. In addition, Fig.15 The computing system 3000 including a single processor 3100 is shown, but according to an alternative embodiment, the computing system 3000 may include multiple processors. In addition, according to an embodiment, the processor 3100 may also include a cache memory located internally or externally. The processor 3100 may include a memory controller 3150 that controls the operation of the memory device 3400. According to an embodiment, the memory controller 3150 is located within the input / output hub 3200.

[0107] The memory device 3400 includes a self-refresh skip circuit 3420 and a refresh controller 3450 for self-refresh skipping. When the self-refresh skip circuit 3420 receives a self-refresh entry command SRE, the self-refresh skip circuit 3420 may delay the start of the self-refresh operation for a specific time. In addition, when a subsequent self-refresh exit command SRX is received before a reference time Tref has passed since the time when the self-refresh entry command SRE was received, the self-refresh skip circuit 3420 determines to skip the delayed self-refresh operation. On the other hand, when a subsequent self-refresh exit command SRX is received after a reference time Tref has passed since the time when the self-refresh entry command SRE was received, the self-refresh skip circuit 3420 may determine to immediately start the delayed self-refresh operation. Here, the reference time Tref may be set to be shorter than the refresh period tREFi. In order to set the reference time Tref, the self-refresh skip circuit 3420 may also include a lookup table LUT set by a mode register setting MRS command. The refresh controller 3450 performs self-refresh on the memory cell under the control of the self-refresh skip circuit 3420. The self-refresh skip circuit 3420 may be implemented by the self-refresh skip circuit 1280 , and the refresh controller 3450 may be implemented by the refresh controller 1250 .

[0108] The input / output hub 3200 may manage data transfer between devices such as the graphics card 3500 and the processor 3100. The input / output hub 3200 may be connected to the processor 3100 through various interfaces. For example, the input / output hub 3200 and the processor 3100 may be connected to various standard interfaces such as a front-side bus FSB, a system bus, HyperTransport, a lightning data transfer (LDT), a QuickPath Interconnect (QPI), a common system interface (CSI), and a peripheral component interface express (PCIe). Although Fig.15 The computing system 3000 is shown to include one input / output hub 3200 , but according to embodiments, the computing system 3000 may include a plurality of input / output hubs.

[0109] The input / output hub 3200 may provide various interfaces with devices. For example, the input / output hub 3200 may include an accelerated graphics port (AGP) interface, a peripheral component interface express (PCIe) interface, a communication stream architecture (CSA) interface, and the like.

[0110] The graphics card 3500 may be connected to the input / output hub 3200 via AGP or PCIe. The graphics card 3500 may control a display device for displaying an image. The graphics card 3500 may include an internal processor for processing image data, an internal processor, and an internal semiconductor memory device. According to an embodiment, the input / output hub 3200 may include a graphics device together with the graphics card 3500 located outside the input / output hub 3200 or in the input / output hub 3200 instead of the graphics card 3500. The graphics device included in the input / output hub 3200 may be an integrated graphics device. In addition, the input / output hub 3200 including a memory controller and a graphics device may be referred to as a graphics and memory controller hub (GMCH).

[0111] The input / output controller hub 3300 can perform data buffering and interface arbitration so that various system interfaces operate efficiently. The input / output controller hub 3300 can be connected to the input / output hub 3200 through an internal bus. For example, the input / output hub 3200 and the input / output controller hub 3300 can be connected through a direct media interface (DMI), a hub interface, an enterprise south bridge interface (ESI), PCIe, etc. The input / output controller hub 3300 can provide various interfaces with peripheral devices. For example, the input / output controller hub 3300 may include a universal serial bus (USB) port, a serial ATA (serial advanced technology attachment, SATA) port, a general input / output (GPIO) and a low pin count, (LPC) bus, a serial peripheral interface (SPI), PCI, PCIe, etc. At least one of the like.

[0112] According to an embodiment, two or more components among the processor 3100 , the input / output hub 3200 , and the input / output controller hub 3300 are implemented by a single chipset.

[0113] In addition to the above-described embodiments, the present invention may include simple design changes. Therefore, the scope of the present invention should not be limited thereto.

Claims

1. A self-refresh method for a semiconductor memory device, comprising: receiving a self-refresh entry command associated with a self-refresh operation; counting the time that has passed since the time when the self-refresh entry command was received; as well as The self refresh operation is skipped according to whether a self refresh exit command is received before the counted elapsed time exceeds a reference time.

2. The method according to claim 1, wherein: The reference time is shorter than or equal to a refresh period of the semiconductor memory device.

3. The method according to claim 1, wherein: When a self refresh exit command is received before the elapsed time exceeds the reference time, the self refresh operation is skipped.

4. The method according to claim 3, further comprising: When the self refresh exit command is not received before the elapsed time exceeds the reference time, the self refresh operation is performed.

5. The method according to claim 4, wherein: The step of performing a self-refresh operation includes performing a full memory bank refresh operation.

6. The method according to claim 5, wherein: The self-refresh operation is terminated in response to receiving a self-refresh exit command.

7. The method according to any one of claims 1 to 6, further comprising: Counting the number of consecutive skipped self-refresh operations; determining whether the number of times reaches a threshold number; as well as A self-refresh operation is performed when the number of times reaches a threshold number regardless of a time difference between receiving a self-refresh entry command and receiving a self-refresh exit command.

8. A semiconductor memory device comprising: a cell array comprising a plurality of dynamic random access memory cells; a command decoder configured to: decode a command associated with a self-refresh operation to output a self-refresh entry command and a self-refresh exit command; a control circuit configured to: generate a control signal for skipping a self refresh operation when a time difference between a reception time of a self refresh entry command and a reception time of a self refresh exit command is shorter than a reference time; as well as The refresh controller is configured to skip the self-refresh operation in response to a control signal for skipping the self-refresh operation.

9. The semiconductor memory device according to claim 8, wherein: The control circuit includes: an oscillator duty cycle controller configured to select a period based on a mode register set command; and The duration detector is configured to generate a clock signal according to a selected period, and generate a control signal by comparing the time difference with a reference time based on the clock signal.

10. The semiconductor memory device according to claim 9, wherein: Duration detectors include: an oscillator configured to generate a clock signal according to a selected period; and A counter is configured to count an elapsed time from a reception time of a self refresh entry command based on a clock signal, and generate a control signal for skipping a self refresh operation when a self refresh exit command is received before the elapsed time reaches a reference time.

11. The semiconductor memory device according to claim 9, wherein: The oscillator duty cycle controller includes: a lookup table including a plurality of period setting values; and A multiplexer is configured to select one of the plurality of period setting values ​​in response to a mode register setting command to output the period.

12. The semiconductor memory device according to claim 8, wherein: The control circuit is further configured to: generate a control signal for performing a self refresh operation when a time difference between a reception time of a self refresh entry command and a reception time of a self refresh exit command is equal to or longer than a reference time; and The refresh controller is further configured to perform a self-refresh operation on a selected memory region of the cell array or perform an all-bank refresh operation on the selected memory region in response to a control signal for performing a self-refresh operation.

13. The semiconductor memory device according to claim 8, wherein: The control circuit activates the control signal according to the number of times the self-refresh operation is continuously skipped regardless of the length of the time difference.

14. A self-refresh method for a semiconductor memory device, comprising: receiving a self-refresh entry command associated with a self-refresh operation; delaying a self-refresh operation by a reference time in response to a self-refresh entry command; detecting whether a self refresh exit command is input before a time elapsed from receipt of a self refresh enter command reaches a reference time; as well as When a self refresh exit command is received before the elapsed time reaches the reference time, the self refresh operation is skipped.

15. The method according to claim 14, wherein: The reference time is set based on a refresh cycle of the semiconductor memory device.

16. The method according to claim 14, wherein: The reference time is selected by adjusting the duty cycle of the internal oscillator set via the mode register set command.

17. The method according to claim 14, further comprising: If the self refresh exit command is not received before the elapsed time reaches the reference time, the self refresh operation is performed.

18. The method according to claim 17, further comprising: The self-refresh operation is stopped in response to receiving the self-refresh exit command.

19. The method according to any one of claims 14 to 18, further comprising: Counts the number of consecutive skips of self-refresh operations.

20. The method according to claim 19, further comprising: When the counted number of times reaches a threshold number, the self refresh operation is performed regardless of a time difference between a reception time of a self refresh entry command and a reception time of a self refresh exit command.

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