Semiconductor manufacturing apparatus, wafer supply apparatus, and method of manufacturing semiconductor device

Abstract

The invention provides a technology capable of easily managing a wafer. The semiconductor manufacturing apparatus includes: a cartridge mounting table on which a cartridge accommodating a wafer ring is mounted; a wafer holding stage that holds the wafer ring; the UV irradiator is arranged between the box carrying table and the wafer holding table; and a control device configured to perform UV irradiation on a dicing tape attached to the wafer ring by the UV irradiator when the wafer ring is taken out from the cartridge and conveyed to the wafer holding table.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor manufacturing apparatus, and can be applied to, for example, a die mounter that picks up a bare chip from a wafer to which an ultraviolet curing tape is attached. Background Art

[0002] As one of the steps in the manufacturing process of semiconductor devices, there is a peeling step of peeling the bare chips from the dicing tape to which the wafer divided into bare chips is attached. In the peeling step, for example, the bare chips are pushed up from the back of the dicing tape by a push-up unit, and are peeled off one by one from the dicing tape held by the wafer supply unit, and the bare chips are picked up by a suction nozzle such as a collet provided on a pickup head or a placement head.

[0003] When an ultraviolet (UV) curing tape is used as the dicing tape, the dicing tape may be irradiated with UV light before the peeling step to reduce the adhesive strength of the adhesive in advance in order to facilitate the pickup operation (for example, Patent Document 1).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2009-4403 Summary of the invention

[0007] Since the dicing tape irradiated with UV deteriorates, when the dicing tape is irradiated with UV before being carried into the die mounter, it is necessary to manage the dicing tape (wafer) irradiated with UV.

[0008] The object of the present disclosure is to provide a technology that can facilitate wafer management. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0009] The typical outline of the present disclosure is briefly described below.

[0010] That is, the semiconductor manufacturing device comprises: a box loading table for loading a box containing a wafer ring; a wafer holding table for holding the wafer ring; a UV irradiator provided between the box loading table and the wafer holding table; and a control device, which is configured to use the UV irradiator to perform UV irradiation on a dicing tape installed on the wafer ring when the wafer ring is taken out of the box and transported to the wafer holding table.

[0011] Effects of the Invention

[0012] According to the present disclosure, wafer management can be easily performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1It is a schematic plan view showing a configuration example of a die mounter in the embodiment.

[0014] Figure 2 yes Figure 1 A schematic front view of the periphery of a pickup unit in a die mounter is shown.

[0015] Figure 3 yes Figure 1 A schematic side view of a placement section in a chip placement machine is shown.

[0016] Figure 4 It is shown Figure 1 A schematic cross-sectional view of a main portion of a wafer holding table is shown.

[0017] Figure 5 It shows the use of Figure 1 A flow chart showing a method for manufacturing a semiconductor device by a die mounter.

[0018] Figure 6 It is shown Figure 1 A block diagram showing a schematic configuration of a control system of a die mounter.

[0019] Figure 7 This is a flowchart showing the operation of the wafer supply unit.

[0020] Figure 8 It is a figure which shows the structure and lighting range of a UV irradiator.

[0021] Fig. 9 It is a diagram for explaining the UV irradiation method in the first modification example.

[0022] Fig.10 : is a flowchart showing the operation of the wafer supply unit in the second modification.

[0023] The reference numerals are described as follows:

[0024] 1Chip mounter (semiconductor manufacturing equipment)

[0025] 111 Wafer box elevator (box loading platform)

[0026] 114 UV irradiator

[0027] 12 Wafer holding table

[0028] 21A, 21B Pickup head (head)

[0029] 80 control unit (control device) DETAILED DESCRIPTION

[0030] Hereinafter, the embodiments and variations are described using the accompanying drawings. However, in the following description, the same components are sometimes marked with the same reference numerals and repeated descriptions are omitted. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each part of the drawings are sometimes schematically shown compared with the actual form. In addition, the relationship between the dimensions of each element, the ratio of each element, etc., are not necessarily consistent between multiple drawings.

[0031] [Implementation Method]

[0032] use Figure 1 to Figure 4 The configuration of a die mounter as one embodiment of a semiconductor manufacturing apparatus will be described. Figure 1 It is a schematic plan view showing a configuration example of a die mounter in the embodiment. Figure 2 It is shown Figure 1 A schematic front view of the periphery of a pickup unit in a die mounter is shown. Figure 3 yes Figure 1 A schematic side view of a placement section in a chip placement machine is shown. Figure 4 It is shown Figure 1 A schematic cross-sectional view of a main portion of a wafer holding table is shown.

[0033] The die mounter 1 generally includes a wafer supply unit 10, a pickup unit 20, an intermediate stage unit 30, a mount unit 40, a conveying unit 50, a substrate supply unit 60, a substrate unloading unit 70, and a control unit (control device) 80. The Y2-Y1 direction is the front-to-back direction of the die mounter 1, the X2-X1 direction is the left-to-right direction, and the Z1-Z2 direction is the up-down direction. The wafer supply unit 10 is arranged at the front side of the die mounter 1, and the mount unit 40 is arranged at the rear side.

[0034] The wafer supply unit 10 includes a wafer transfer unit 11 , a wafer holding stage 12 , and a peeling unit 13 . The wafer transfer unit 11 includes a wafer cassette elevator 111 as a cassette placement stage, a wafer correction tank 112 , a wafer extractor 113 , a UV irradiator 114 , and a support table 115 .

[0035] The cassette elevator 111 moves a wafer cassette WC storing a plurality of wafer rings WR up and down to a wafer transfer height. The wafer correction tank 112 is provided on the support table 115 and performs alignment of the wafer ring WR supplied from the cassette elevator 111 .

[0036] The wafer unloader 113 takes out a wafer ring WR from a wafer box WC and supplies it to the wafer holding table 12, or takes out a wafer ring WR from the wafer holding table 12 and stores it in the wafer box WC. The wafer unloader 113 includes a guide rail 113a, a movable portion 113b that moves along the guide rail 113a, an arm portion 113c extending from the movable portion 113b, and a gripping portion 113d provided at the front end of the arm portion 113c.

[0037] The UV irradiator 114 is provided on a support table 115 disposed between a wafer cassette elevator 111 on which the wafer cassette WC is placed and the wafer holding table 12. The UV irradiator 114 will be described in detail later.

[0038] like Figure 4 As shown, the wafer holding table 12 includes an expansion ring 121 that holds the wafer ring WR, and a support ring 122 that is held by the wafer ring WR and horizontally positions the dicing tape DT. The peeling unit 13 is disposed inside the support ring 122 .

[0039] The wafer holding table 12 moves in the X1-X2 direction and the Y1-Y2 direction by a driving unit not shown in the figure, so that the picked-up bare chip D moves to the position of the peeling unit 13. In addition, the wafer holding table 12 rotates the wafer ring WR in the XY plane by a driving unit not shown in the figure. The peeling unit 13 moves in the up and down direction by a driving unit not shown in the figure. The peeling unit 13 peels the bare chip D from the dicing tape DT by, for example, pushing up a plurality of blocks.

[0040] When the wafer holding table 12 peels off the bare chip D, the expansion ring 121 holding the wafer ring WR is lowered. As a result, the dicing tape DT held by the wafer ring WR is stretched, so that the interval between the bare chips D is expanded, and the bare chip D is pushed up from below by the peeling unit 13, so that the pick-up performance of the bare chip D is improved.

[0041] A wafer W is bonded (attached) to the dicing tape DT, and the wafer W is divided into a plurality of bare chips D. The wafer W is, for example, a semiconductor wafer, and the bare chip D is a semiconductor chip. The dicing tape DT is an ultraviolet curing tape. A film-like adhesive material DF called a bare chip adhesive film (DAF) is bonded between the wafer W and the dicing tape DT. The adhesive material DF is cured by heating.

[0042] The pickup unit 20 includes pickup heads 21A, 21B, X drive units 23A, 23B, and a wafer recognition camera 24. The pickup heads 21A, 21B are provided with cartridges 22A, 22B for adsorbing and holding the bare chip D after peeling at the front end. The pickup heads 21A, 21B pick up the bare chip D from the wafer holding table 12 and place it on the intermediate table 31A, 31B. The X drive units 23A, 23B move the pickup heads 21A, 21B in the X1-X2 direction. The pickup unit 20 has various drive units (not shown) for lifting, rotating, and moving the pickup heads 21A, 21B in the Y1-Y2 direction. The wafer recognition camera 24 grasps the pickup position of the bare chip D picked up from the wafer W, or performs a surface inspection of the bare chip D.

[0043] The intermediate stage 30 includes intermediate stages 31A and 31B on which the bare chip D is placed, and stage recognition cameras 34A and 34B for recognizing the bare chip D on the intermediate stages 31A and 31B. The intermediate stages 31A and 31B have suction holes for adsorbing the placed bare chip D. The placed bare chip D is temporarily held on the intermediate stages 31A and 31B. The intermediate stages 31A and 31B are the placement stages on which the bare chip D is placed, and are also the pickup stages for picking up the bare chip D.

[0044] The mounting section 40 includes mounting heads 41A, 41B, Y drive sections 43A, 43B, substrate recognition cameras 44A, 44B, and mounting tables 46A, 46B. The mounting heads 41A, 41B are provided with cartridges 42A, 42B for adsorbing and holding the bare chip D at the front end. The Y drive sections 43A, 43B move the mounting heads 41A, 41B in the Y1-Y2 direction. The substrate recognition cameras 44A, 44B capture the position recognition mark (not shown) of the substrate S to identify the mounting position. Here, a plurality of product areas (hereinafter referred to as package areas P) that eventually become one package are formed on the substrate S. A position recognition mark is provided for each package area P. The mounting tables 46A, 46B rise when the bare chip D is placed on the substrate S, and support the substrate S from below. The mounting tables 46A, 46B have suction ports (not shown) for vacuum adsorption of the substrate S, and are capable of fixing the substrate S. The mounting stages 46A and 46B include heating units (not shown) for heating the substrate S. The mounting unit 40 includes driving units (not shown) for lifting, rotating, and moving the mounting heads 41A and 41B in the X direction.

[0045] According to this configuration, the placement heads 41A and 41B correct the pickup position or posture based on the imaging data of the stage recognition cameras 34A and 34B, and pick up the bare chip D from the intermediate stage 31A and 31B. Then, the placement heads 41A and 41B place the bare chip D on the package area P of the substrate S based on the imaging data of the substrate recognition cameras 44A and 44B, or place the bare chip D in a stacked form on the bare chip already placed on the package area P of the substrate S.

[0046] The conveying section 50 has a conveying passage 52 for moving the substrate S. The substrate S moves in the X1 direction by driving a nut of a conveying claw provided on the conveying passage 52 using a ball screw provided along the conveying passage 52. According to this configuration, the substrate S moves from the substrate supply section 60 along the conveying passage 52 to the mounting position, and after mounting, moves to the substrate unloading section 70, and the substrate S is delivered to the substrate unloading section 70.

[0047] The substrate supply unit 60 takes out the substrate S stored and carried in the transport jig from the transport jig, and supplies it to the transport unit 50. The substrate unloading unit 70 stores the substrate S transported by the transport unit 50 in the transport jig.

[0048] Next, use Figure 6 The control unit 80 will be described. Figure 6 It is shown Figure 1 A block diagram showing a schematic configuration of a control system of a die mounter.

[0049] The control system 8 has a control unit (control device) 80, a drive unit 86, a signal unit 87, an optical system 88, etc. The control unit 80 generally mainly has a control / calculation device 81 composed of a CPU (Central Processing Unit), a storage device 82, an input / output device 83, a bus 84, and a power supply unit 85. The storage device 82 has a main storage device 82a and an auxiliary storage device 82b. The main storage device 82a is composed of a RAM (Random Access Memory) storing a processing program, etc. The auxiliary storage device 82b is composed of a HDD (Hard Disk Drive) or SSD (Solid State Drive) storing control data or image data required for control.

[0050] The input / output device 83 includes: a monitor 83a for displaying device status or information, etc.; a touch panel 83b for inputting operator's instructions; a mouse 83c for operating the monitor 83a; and an image acquisition device 83d for acquiring image data from the optical system 88. The input / output device 83 also includes a motor control device 83e and an I / O signal control device 83f. The motor control device 83e controls the ZY drive axis of the wafer pick-up device 113 or the mounting head stage of the wafer supply unit 10, the drive unit of the peeling unit 13, etc. The I / O signal control device 83f acquires a signal from the signal unit 87 or controls the signal unit 87. The signal unit 87 includes switches or knobs for controlling the brightness of various sensors or lighting devices, the UV irradiator 114, etc. The optical system 88 includes a wafer recognition camera 24, stage recognition cameras 34A, 34B, and substrate recognition cameras 44A, 44B. The control / calculation device 81 acquires necessary data via the bus 84 and performs calculations to control the pickup head 21 and the like, or transmit information to the monitor 83 a and the like.

[0051] use Figure 5 as well as Figure 7 A part of the manufacturing process of a semiconductor device (a manufacturing method of a semiconductor device) using the die mounter 1 will be described. Figure 5 It shows that the Figure 1 A flow chart showing a method for manufacturing a semiconductor device by a die mounter. Figure 7 1 is a flowchart showing the operation of the wafer supply unit. In the following description, the operation of each unit constituting the die mounter 1 is controlled by the control unit 80 .

[0052] (Wafer loading process: process S1)

[0053] The wafer box WC containing the wafer ring WR is put into the wafer box elevator 111. The wafer box elevator 111 raises the wafer box WC to the wafer transfer height. The wafer extractor 113 uses the gripping portion 113d to grip the wafer ring WR and take it out from the wafer box WC (process S11). Then, the wafer extractor 113 aligns the wafer ring WR through the wafer correction groove 112. At this time, the UV irradiator 114 irradiates ultraviolet rays from below (back side) of the dicing tape DT held by the wafer ring WR (process S12). The wafer extractor 113 supplies (carries in) the wafer ring WR to the wafer holding table 12 (process S13). At this time, the wafer holding table 12 is located near the X1 side of the wafer correction groove 112. Thereafter, the wafer holding table 12 is moved to the pickup position (process S14).

[0054] (Substrate loading process: process S2)

[0055] The transport jig holding the substrate S is supplied (put in) to the substrate supply unit 60 . In the substrate supply unit 60 , the substrate S held by the transport jig is taken out from the transport jig. Then, the substrate S is supplied (carried in) to the mounting unit 40 via the transport unit 50 .

[0056] (Picking process: process S3)

[0057] After step S1, the wafer holding table 12 is moved in such a way that the desired bare chip D can be picked up from the dicing tape DT. The bare chip D is photographed by the wafer recognition camera 24. The bare chip D is positioned and the surface inspected based on the image data obtained by photographing. The image data is processed to calculate the offset (X, Y, θ directions) of the bare chip D on the wafer holding table 12 relative to the bare chip position reference point of the chip mounter for positioning. In addition, with respect to the bare chip position reference point, the specified position of the wafer holding table 12 is maintained as the initial setting of the device in advance. The surface inspection of the bare chip D is performed by processing the image data.

[0058] The positioned bare chip D is peeled from the dicing tape DT by the peeling unit 13 and the pickup heads 21A and 21B. The bare chip D peeled from the dicing tape DT is sucked and held by the collets 22A and 22B provided on the pickup heads 21A and 21B, and is transported and placed on the intermediate stages 31A and 31B.

[0059] The bare chip D on the intermediate stage 31A, 31B is photographed by the stage recognition cameras 34A, 34B, and the bare chip D is positioned and inspected on the surface based on the image data obtained by the photographing. By performing image processing on the image data, the offset (X, Y, θ directions) of the bare chip D on the intermediate stage 31A, 31B relative to the bare chip position reference point of the die mounter is calculated and positioned. In addition, regarding the bare chip position reference point, the predetermined position of the intermediate stage 31A, 31B is maintained as the initial setting of the device in advance. By performing image processing on the image data, the surface inspection of the bare chip D is performed.

[0060] The pickup heads 21A and 21B that have conveyed the bare chip D to the intermediate stages 31A and 31B are returned to the wafer holding stage 12. According to the above steps, the next bare chip D is peeled off from the dicing tape DT, and thereafter, the bare chips D are peeled off one by one from the dicing tape DT according to the same steps.

[0061] (Mounting process: process S4)

[0062] The substrate S is transported to the mounting table 46A, 46B by the transport unit 50. The substrate S placed on the mounting table 46A, 46B is photographed by the substrate recognition cameras 44A, 44B, and the positioning and surface inspection of the substrate S are performed based on the image data obtained by the photographing. By performing image processing on the image data, the offset (X, Y, θ direction) of the substrate S relative to the substrate position reference point of the chip mounting machine 1 is calculated. In addition, with respect to the substrate position reference point, the specified position of the mounting unit 40 is maintained as the initial setting of the device in advance. By performing image processing on the image data, the surface inspection of the substrate S is performed.

[0063] In step S3, the adsorption position of the mounting heads 41A and 41B is corrected according to the calculated offset of the bare chip D on the intermediate stages 31A and 31B, so that the bare chip D is adsorbed by the collets 42A and 42B. The bare chip D is mounted on a specified position of the substrate S supported by the mounting stages 46A and 46B by the mounting heads 41A and 41B that adsorb the bare chip D from the intermediate stages 31A and 31B. Here, the specified position of the substrate S is the packaging area P of the substrate S, or the area where additional components are mounted on the basis of components that have already been mounted, or the mounting area of ​​stacked components. The bare chip D mounted on the substrate S is photographed by the substrate recognition cameras 44A and 44B, and based on the image data obtained by the photographing, an inspection is performed to determine whether the bare chip D has been mounted to the desired position.

[0064] The mounting heads 41A and 41B that mounted the bare chip D on the substrate S return to the intermediate stages 31A and 31B. According to the above steps, the next bare chip D is picked up from the intermediate stages 31A and 31B and mounted on the substrate S. These steps are repeated to mount bare chips D on all the packaging areas P of the substrate S.

[0065] (Substrate unloading process: process S5)

[0066] The substrate S with the bare chip D mounted thereon is transported from the mounting section 40 to the substrate unloading section 70 by the transport section 50 . In the substrate unloading section 70 , the substrate S is taken out and stored in a transport jig to unload the substrate S. The transport jig storing the substrate S is unloaded from the die mounter 1 .

[0067] (Wafer unloading process: process S6)

[0068] In step S3, after all the bare chips D to be picked up are picked up, the wafer holding table 12 is moved to the vicinity of the X1 side of the wafer correction groove 112 (step S61). The wafer unloader 113 uses the gripping portion 113d to grip the wafer ring WR and unload it to the wafer box WC (step S62). When all the wafer rings are stored, the wafer box elevator 111 lowers the wafer box WC to the unloading height.

[0069] As described above, the bare chip D is mounted on the substrate S and is carried out from the die mounter 1. Thereafter, for example, a transport jig storing the substrate S mounted with the bare chip D is transported to a wire bonding process, and the electrodes of the bare chip D are electrically connected to the electrodes of the substrate S via Au wires or the like. Then, the substrate S is transported to an injection molding process, and the bare chip D and the Au wires are sealed with an injection molding resin (not shown), thereby completing semiconductor packaging.

[0070] In the case of stacking, after the wire bonding process, the conveying jig carrying the substrate S on which the bare chip D is mounted is carried into the die mounter, and the bare chip D is stacked on the bare chip D mounted on the substrate S. Then, after being carried out from the die mounter, it is electrically connected to the electrode of the substrate S via the Au wire in the wire bonding process. The bare chip D above the second layer is peeled off from the dicing tape DT by the above method, and then conveyed to the mounting section to be stacked on the bare chip D. After repeating the above process a predetermined number of times, the substrate S is conveyed to the injection molding process, and the plurality of bare chips D and the Au wire are sealed with an injection resin (not shown), thereby completing the stacking package.

[0071] use Figure 8 The UV irradiator 114 will be described. Figure 8 It is a figure which shows the structure and lighting range of a UV irradiator.

[0072] The UV irradiator 114 has a plurality of UV light emitting diodes (LEDs) 114a. The UV light emitting diodes 114a are arranged in a straight line in a direction (Y1-Y2 direction) orthogonal to the conveying direction (X1-X2 direction) of the conveyed wafer ring WR. In other words, the UV irradiator 114 is in a long strip shape in the Y1-Y2 direction. The UV irradiator 114 is arranged in a range of length that is equal to or shorter than the diameter of the wafer W mounted on the wafer ring WR. In addition, since the bare chip at the end of the wafer W is not a pick-up object, it is not necessary to irradiate UV.

[0073] The UV irradiator 114 is composed of a plurality of channels, and one channel is composed of one or more UV light emitting diodes 114a. Figure 8 As shown, the UV irradiator 114 is composed of five channels. The first channel CH1 is composed of four UV light emitting diodes 114a in the central portion. The second channel CH2 is composed of two UV light emitting diodes 114a adjacent to the first channel CH1. The third channel CH3 is composed of two UV light emitting diodes 114a adjacent to the second channel CH2. The fourth channel CH4 is composed of two UV light emitting diodes 114a adjacent to the third channel CH3. The fifth channel CH5 is composed of two UV light emitting diodes 114a adjacent to the fourth channel CH4.

[0074] The UV irradiator 114 can be turned on and off for each channel. In addition, the UV irradiator 114 can set the irradiation time and irradiation intensity for each channel. In addition, the UV irradiator 114 can also set the number of channels or the range of channels. Thus, the UV irradiation conditions for each channel can be changed according to the peeling results such as poor pickup.

[0075] Since the wafer W mounted on the wafer ring WR is transported above the UV irradiator 114, the positional relationship between the wafer W and the UV irradiator 114 changes. Since the wafer W is circular, the area required for UV irradiation changes in stages, and there is also a range where it is better not to perform UV irradiation. According to the positional relationship between the wafer W and the UV irradiator 114, the channel for lighting the UV irradiator 114 is changed. In addition, the transportation of the wafer W is carried out by pitch feeding, and the UV irradiator 114 is lit intermittently. In other words, the UV irradiator 114 is turned off during the movement of the wafer W, and the UV irradiator 114 is lit when the wafer W stops.

[0076] For example, Figure 8As shown, the wafer W is divided into nine regions R1 to R9 in the X1-X2 direction. When the UV irradiator 114 irradiates the regions R1 and R9, the first channel CH1 is turned on, and the second channel CH2, the third channel CH3, the fourth channel CH4, and the fifth channel CH5 are turned off. When the UV irradiator 114 irradiates the regions R2 and R8, the first channel CH1 and the second channel CH2 are turned on, and the third channel CH3, the fourth channel CH4, and the fifth channel CH5 are turned off. When the UV irradiator 114 irradiates the regions R3 and R7, the first channel CH1, the second channel CH2, and the third channel CH3 are turned on, and the fourth channel CH4 and the fifth channel CH5 are turned off. When the UV irradiator 114 irradiates the regions R4 and R6, the first channel CH1, the second channel CH2, the third channel CH3, and the fourth channel CH4 are turned on, and the fifth channel CH5 is turned off. When the UV irradiator 114 irradiates the region R5 , the first channel CH1 , the second channel CH2 , the third channel CH3 , the fourth channel CH4 , and the fifth channel CH5 are lit.

[0077] In other words, in regions R1 to R9, the first channel CH1 is turned on. In regions R2 to R8, the second channel CH2 is turned on. In regions R3 to R7, the third channel CH3 is turned on. In regions R4 to R6, the fourth channel CH4 is turned on. In region R5, the fifth channel CH5 is turned on.

[0078] According to the present embodiment, after being carried into the die mounter (just before the bare chip D is peeled off from the dicing tape DT), UV irradiation can be performed to prevent the wafer from being degraded over time. This makes it possible to facilitate wafer storage (wafer management).

[0079] According to the present embodiment, since UV irradiation is performed immediately before expansion (extension of the dicing tape DT) on the wafer holding table 12 , the wafer is less susceptible to oxygen inhibition and can reduce peeling failure.

[0080] According to this embodiment, since the UV light-emitting diodes in the range corresponding to the shape of the light-receiving surface directly above the UV irradiator 114 (the part with the wafer W) are lit, it is possible to prevent irradiation to the unnecessary irradiation area (the dicing tape DT of the part without the wafer W attached). There is no need for a physical mask corresponding to the part to which the wafer W is attached. The irradiation area can be easily changed according to the product switching. Thus, it can cope with a variety of products.

[0081] According to this embodiment, since the UV irradiation conditions of each channel can be changed according to the peeling results such as poor pick-up, it is possible to reduce the bare chip peeling failure. The degradation of the UV irradiator can be detected according to the peeling results such as poor pick-up. Therefore, the UV irradiation conditions such as irradiation time and irradiation intensity can be adjusted to ensure fixed peeling properties and reduce the bare chip peeling failure.

[0082] <Modification>

[0083] Hereinafter, representative modified examples of several embodiments are illustrated. In the following description of the modified examples, the same reference numerals as those in the above-mentioned embodiment are used for the parts having the same structure and function as the parts described in the above-mentioned embodiment. Then, the description of this part can be appropriately cited in the scope of technical non-contradiction. In addition, part of the above-mentioned embodiment and all or part of the multiple modified examples can be appropriately combined and applied in the scope of technical non-contradiction.

[0084] (First Modification)

[0085] Fig. 9 It is a diagram for explaining the UV irradiation method in the first modification example.

[0086] In the embodiment, an example in which all five channels of the UV irradiator 114 are used is described, but not all five channels may be used. The first modified example is an example in which the fifth channel CH5 is not used.

[0087] (a) First, when the first row of wafers W is conveyed onto the UV irradiator 114, the UV irradiator 114 turns on only the first channel CH1 to irradiate UV onto the dicing tape DT on the back side of the wafer W. After a predetermined time has passed, the UV irradiator 114 turns off all channels.

[0088] (b) Next, when the second row of wafers W is conveyed onto the UV irradiator 114, the UV irradiator 114 turns on the first channel CH1 and the second channel CH2 to irradiate UV light onto the dicing tape DT on the back side of the wafer W. After a predetermined time has passed, the UV irradiator 114 turns off all channels.

[0089] (c) Next, when the third row of wafers W is conveyed onto the UV irradiator 114, the UV irradiator 114 turns on the first channel CH1, the second channel CH2, and the third channel CH3 to irradiate UV onto the dicing tape DT on the back side of the wafer W. After a predetermined time, the UV irradiator 114 turns off all the channels.

[0090] (d) Next, when the fourth row of wafers W is conveyed to the UV irradiator 114, the UV irradiator 114 turns on the first channel CH1, the second channel CH2, the third channel CH3, and the fourth channel CH4, and irradiates UV light onto the dicing tape DT on the back side of the wafer W. After a predetermined time has passed, the UV irradiator 114 turns off all the channels. The fifth to ninth rows of wafers W perform the same operation as the fourth row.

[0091] (e) Next, when the tenth row of wafers W is conveyed onto the UV irradiator 114, the UV irradiator 114 turns on the first channel CH1, the second channel CH2, and the third channel CH3 to irradiate UV onto the dicing tape DT on the back side of the wafer W. After a predetermined time, the UV irradiator 114 turns off all the channels.

[0092] (f) Next, when the eleventh row of wafers W is conveyed onto the UV irradiator 114, the UV irradiator 114 turns on the first channel CH1 and the second channel CH2 to irradiate UV light onto the dicing tape DT on the back side of the wafer W. After a predetermined time has passed, the UV irradiator 114 turns off all channels.

[0093] (g) Finally, when the twelfth row of wafers W is transferred onto the UV irradiator 114, the UV irradiator 114 turns on the first channel CH1 to irradiate UV light onto the dicing tape DT on the back side of the wafer W. After a predetermined time has passed, the UV irradiator 114 turns off all channels.

[0094] (Second Modification)

[0095] Fig.10 : is a flowchart showing the operation of the wafer supply unit in the second modification.

[0096] In the embodiment, an example of UV irradiation is described whenever a wafer ring WR is taken out from a wafer box WC and transported to a wafer holding table 12. The UV irradiation time of the dicing tape DT mounted on the wafer ring WR is, for example, about 20 to 30 seconds. The UV irradiation time is very long compared to the transport time of transporting the wafer ring WR from the wafer box WC to the wafer holding table 12, and the transport time is determined according to the UV irradiation time. In other words, the start of picking up will be delayed compared to the case where UV irradiation is not performed.

[0097] In the second variant, the first wafer ring WR of the wafer box WC is transported to the wafer holding table while UV irradiation is performed in the same manner as in the embodiment. For the second and subsequent wafer rings WR, UV action is performed in parallel with the production action (pick-up, mounting). The wafer ring WR after UV irradiation is returned to the wafer box WC, and the next wafer ring WR is taken out and UV irradiation is performed. This action is performed for all wafer rings WR in the wafer box WC.

[0098] In the process of picking up the wafer W held by the first wafer ring WR (step S3 ), the following operations are performed.

[0099] The wafer unloader 113 uses the gripping portion 113d to grip the second wafer ring WR and takes it out from the wafer box WC (process S11). Then, the UV irradiator 114 irradiates UV from below (on the back side) the dicing tape DT held by the wafer ring WR (process S12). After that, the wafer unloader 113 stores the wafer ring WR gripped by the gripping portion 113d in the wafer box WC (process S15). Thereafter, the same action is performed for the third to last wafer rings WR.

[0100] After the first wafer ring WR is carried out to the wafer box WC (process S62), the wafer takeout device 113 takes out the second wafer ring WR that has been UV irradiated from the wafer box WC (process S11). The wafer takeout device 113 supplies the second wafer ring WR to the wafer holding table 12 (process S13). Thereafter, the same action is performed for the third to last wafer ring WR.

[0101] In the second variant, the UV irradiation action of the dicing tape DT mounted on the second and subsequent wafer rings WR is performed in parallel with the picking action and the mounting action, thereby reducing the decrease in production efficiency. In addition, the UV irradiator 114 may not be linear as in the embodiment. The UV irradiator 114 may irradiate in a circular shape, or may irradiate in a circular shape using a mask, for example.

[0102] As mentioned above, the disclosure proposed by the inventor of the present disclosure has been specifically described based on the embodiment and the modified example, but the present disclosure is not limited to the above-mentioned embodiment and the modified example, and various changes can be made.

[0103] For example, a photoreceiver may be provided in the UV irradiation direction (above the UV irradiator 114 ) to detect changes in UV irradiation intensity and to feed back to the set value of the UV irradiator 114 .

[0104] The UV light emitting diodes of the UV irradiator 114 may be replaced for each channel. For example, the degradation progress of the channel (first channel CH1) with high usage frequency is fast, and the degradation progress of each channel is different. Not all UV light emitting diodes may be replaced.

[0105] Gas may be passed through the UV irradiator 114 to prevent excessive heating or adhesion of sublimates due to UV irradiation.

[0106] It is also possible to calculate the cumulative exposure amount for each area of ​​the wafer W (dicing tape DT) based on the transport speed of the wafer ring WR and the irradiation intensity, and feed forward to the peeling conditions.

[0107] Picking can also be done in the order of the areas of the UV-irradiated wafer.

[0108] The bent dicing tape DT may be shrunk by utilizing the heat generated during UV irradiation.

[0109] It is also possible to determine whether to irradiate the dicing tape DT attached to the next wafer ring WR with UV light based on the number of bare chips expected to be produced. It is possible to stop irradiating the wafer that does not require UV light, making wafer management easier.

[0110] In the embodiment, an example is described in which the wafer W is transported by pitch feeding and the UV irradiator 114 is intermittently turned on. However, the UV irradiator 114 may be continuously turned on during the wafer W pitch feeding and stop.

[0111] In the embodiment, an example in which the light source of the UV irradiator 114 is formed of a UV light emitting diode has been described, but a light source such as a metal halide or mercury may be used.

[0112] In the embodiment, an example using a bare die bonding film has been described, but the pre-molding portion to which the adhesive is applied to the substrate may be provided without using a bare die bonding film.

[0113] In the embodiment, a die mounter is described that picks up a bare die from a wafer supply unit using a pickup head and places it on an intermediate stage, and places the bare die placed on the intermediate stage on a substrate using a placement head. However, the present invention is not limited to this, and can also be applied to a bare die placement device that picks up a bare die from a bare die supply unit.

[0114] For example, the present invention can also be applied to a mounter that does not have an intermediate stage and a pickup head and mounts a bare chip of a wafer supply unit on a substrate using a mounting head.

[0115] Furthermore, the present invention can also be applied to a flip chip mounter that does not have an intermediate stage, picks up a bare chip from a wafer supply unit, rotates a bare chip pickup head upward, delivers the bare chip to a mounting head, and then mounts the bare chip on a substrate using the mounting head.

[0116] In the embodiment, an example is described in which two pick-up units, two intermediate stages, and two placement units are provided, but the present invention is not limited thereto, and the pick-up unit, the intermediate stage, and the placement unit may each be one.

[0117] In the embodiment, the die mounter is described as an example, but the invention can also be applied to a semiconductor manufacturing apparatus that places picked-up bare chips on a tray.

Claims

1. A semiconductor manufacturing device, characterized in that: have: a cassette placement table for placing a cassette containing a wafer ring; a wafer holding table for holding the wafer ring; a head that picks up the bare chips from a dicing tape mounted on the wafer ring and to which the wafer divided into bare chips is attached; a UV irradiator disposed between the cassette mounting table and the wafer holding table; as well as A control device irradiates the dicing tape with UV light using the UV irradiator when the wafer ring is taken out from the cassette and conveyed to the wafer holding table.

2. The semiconductor manufacturing device according to claim 1, characterized in that The UV irradiator is a linear light source composed of multiple channels.

3. The semiconductor manufacturing device according to claim 2, characterized in that: The UV irradiator can be turned on and off for each of the channels.

4. The semiconductor manufacturing device according to claim 3, characterized in that: The range of the channel can be varied.

5. The semiconductor manufacturing device according to claim 2, characterized in that: The UV irradiator can set the irradiation time and irradiation intensity for each of the channels.

6. The semiconductor manufacturing device according to claim 5, characterized in that The control device is configured to change the setting of at least one of the irradiation time and the irradiation intensity based on the picking result.

7. The semiconductor manufacturing device according to claim 2, characterized in that: The control device is configured to feed the wafer ring in intervals and to continuously light the UV irradiator regardless of whether the wafer ring is stopped.

8. The semiconductor manufacturing device according to claim 2, characterized in that: The control device is configured to feed the wafer ring in intervals and to turn off the UV irradiator during the interval feeding and to turn on the UV irradiator during the interval feeding.

9. The semiconductor manufacturing device according to claim 1, characterized in that: The control device is configured to perform UV irradiation on the dicing tapes attached to the second and subsequent wafer rings housed in the cassette in parallel with the picking-up operation of picking up the bare chip from the dicing tape attached to the first wafer ring.

10. A wafer supply device, characterized in that: have: A cassette mounting table for mounting a cassette containing a wafer ring with a dicing tape mounted thereon; a wafer holding table for holding the wafer ring; A conveying section that takes out the wafer ring from the box and conveys it to the wafer holding table; as well as A UV irradiator is provided between the cassette mounting table and the wafer holding table, and irradiates the conveyed dicing tape with UV.

11. A method for manufacturing a semiconductor device, characterized in that: The semiconductor manufacturing device is provided with a cassette stage for placing a cassette containing a wafer ring with a dicing tape mounted thereon, a wafer holding stage for holding the wafer ring, and a UV irradiator provided between the cassette stage and the wafer holding stage. The method for manufacturing the semiconductor device comprises the following steps: When the wafer ring is taken out from the cassette and transported to the wafer holding table, the dicing tape is irradiated with UV by the UV irradiator; and The bare chips are picked up from the dicing tape to which the wafer divided into bare chips is attached.

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