Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a package substrate and at least two semiconductor chips stacked on the package substrate and electrically connected to the package substrate via leads, wherein a first semiconductor chip located on the lower side among the at least two semiconductor chips is coupled to a second semiconductor chip located above the first semiconductor chip without an adhesive.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0110034 filed on August 22, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor package and a method of manufacturing the same. Background Art

[0004] According to the rapid development of the electronics industry and the needs of users, electronic devices are becoming more compact and lightweight. As electronic devices become smaller and lighter, the semiconductor packages used therein are also smaller and lighter. In addition, semiconductor packages require high reliability as well as high performance and large capacity. In order to achieve high capacity and high performance, the thickness of semiconductor packages continues to increase, and the power supply also continues to increase. However, the increase in its thickness makes it difficult to achieve a reduction in the size and weight of the semiconductor package, and the increase in its power supply may greatly affect the high reliability. Summary of the invention

[0005] In general, in some aspects, the present disclosure relates to a semiconductor package having a minimum overall thickness and a method of manufacturing a semiconductor package.

[0006] According to some aspects of the present disclosure, a semiconductor package includes a package substrate and at least two semiconductor chips stacked on the package substrate and electrically connected to the package substrate via leads, wherein a first semiconductor chip located on the lower side of the at least two semiconductor chips is coupled to a second semiconductor chip located above the first semiconductor chip without an adhesive.

[0007] According to some aspects of the present disclosure, a semiconductor package includes: a package substrate, on the upper surface of which a solder resist (SR) layer is formed; a first semiconductor chip, which is coupled to the package substrate without an adhesive and is electrically connected to the package substrate via leads; and at least two second semiconductor chips, which are coupled to the first semiconductor chip without an adhesive and are electrically connected to the package substrate via leads, wherein a lower second semiconductor chip located on the lower side of the at least two second semiconductor chips is coupled to an upper second semiconductor chip located above the lower second semiconductor chip without an adhesive, and the lowest lower second semiconductor chip among the at least two second semiconductor chips is self-aligned with a first alignment pattern line on the upper surface of the first semiconductor chip, and the upper second semiconductor chip is self-aligned with a second alignment pattern line on the upper surface of the lower second semiconductor chip.

[0008] According to some aspects of the present disclosure, a semiconductor package includes a package substrate and at least two semiconductor chips stacked on the package substrate, each semiconductor chip having an upper surface and a lower surface in a rectangular shape, wherein the upper surface of each of the at least two semiconductor chips includes an active surface, and the lower surface of each of the at least two semiconductor chips includes an inactive surface, and a chip pad is arranged along a first direction on the upper surface of each of the at least two semiconductor chips and is adjacent to a first edge, the first edge corresponds to a line of the rectangular shape of the upper surface and the lower surface of each of the at least two semiconductor chips and extends in the first direction, the at least two semiconductor chips are stacked on each other so that their chip pads are exposed to the outside, and the chip pads are electrically connected to the substrate pads of the package substrate via leads, and a first semiconductor chip located on the lower side among the at least two semiconductor chips is coupled to a second semiconductor chip located above the first semiconductor chip without an adhesive.

[0009] According to some aspects of the present disclosure, a method for manufacturing a semiconductor package includes: forming alignment pattern lines on an upper surface of a semiconductor chip; stacking a first semiconductor chip among the semiconductor chips on a package substrate; applying a hydrophilic liquid on the upper surface of the first semiconductor chip; stacking a second semiconductor chip among the semiconductor chips on the first semiconductor chip; and heat-treating the first semiconductor chip and the second semiconductor chip, wherein during the heat treatment of the first semiconductor chip and the second semiconductor chip, the hydrophilic liquid is removed and the first semiconductor chip and the second semiconductor chip are coupled to each other by van der Waals forces in the absence of an adhesive. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Exemplary implementations will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1A is a cross-sectional view of an example of a semiconductor package according to some implementations, Figure 1B According to some implementation methods Figure 1A A plan view of a semiconductor chip included in a semiconductor package.

[0012] Figure 2 is a cross-sectional view of an example of a semiconductor package according to some implementations.

[0013] Figure 3A and Figure 3B According to some implementation methods Figure 1A FIG. 1 is a plan view of an example of a semiconductor chip included in a semiconductor package.

[0014] Figure 4A is a cross-sectional view of an example of a semiconductor package according to some implementations, Figure 4B According to some implementation methods Figure 4A A plan view of a semiconductor chip included in a semiconductor package.

[0015] Figure 5A is a cross-sectional view of an example of a semiconductor package according to some implementations, Figure 5B According to some implementation methods Figure 5A A plan view of an example of a semiconductor chip included in a semiconductor package of Figure 5C According to some implementation methods Figure 5A Magnified view of area A.

[0016] Fig. 6A and Figure 6B is a cross-sectional view of an example of a semiconductor package according to some implementations.

[0017] Fig. 7A is a graph illustrating the thickness of a die attach film (DAF) relative to the number of semiconductor chips according to some implementations, Figure 7B is a graph illustrating chip thickness relative to an overall height of a semiconductor package according to various chip stacking structures according to some implementations.

[0018] Fig. 8A is a cross-sectional view of an example of a semiconductor package according to some implementations, Figure 8B According to some implementation methods Fig. 8A 0014 is a plan view of an example of a package substrate included in a semiconductor package of FIG.

[0019] FIG. 9A to FIG. 13 are cross-sectional views and plan views illustrating an example of a process of manufacturing a semiconductor package according to some implementations.

[0020] FIG. 14A to FIG. 16B are cross-sectional views and plan views illustrating an example of a process of manufacturing a semiconductor package according to some implementations.

[0021] FIG. 17A to FIG. 19B are cross-sectional views and plan views illustrating an example of a process of manufacturing a semiconductor package according to some implementations.

[0022] FIG. 20A to FIG. 22B are cross-sectional views and plan views illustrating an example of a process of manufacturing a semiconductor package according to some implementations. DETAILED DESCRIPTION

[0023] Hereinafter, exemplary implementations will be described in detail with reference to the accompanying drawings. The same reference numerals are given to the same elements in the drawings, and repeated descriptions thereof are omitted.

[0024] Figure 1Ais a cross-sectional view of an example of a semiconductor package 100 according to some implementations, Figure 1B According to some implementation methods Figure 1A FIG. 1 is a plan view of an example of a semiconductor chip included in a semiconductor package 100 of FIG. Figure 1A and Figure 1B , the semiconductor package 100 may include a package substrate 110 , a chip stack structure 120 , a sealing material 140 , and external connection terminals 150 .

[0025] The package substrate 110 may include a substrate main layer 110B (see Fig. 8A ), substrate protection layer 110SR (see Fig. 8A ), substrate pad 112 and external pad. External connection terminal 150 may be disposed on the external pad. Figure 1A In the figure, for the convenience of illustration, the substrate main layer and the substrate protection layer are not distinguished from each other but are represented as a single layer, and the external pads are not shown.

[0026] The substrate main body layer may include various materials. For example, depending on the type of the package substrate, the substrate main body layer may include silicon, ceramics, organic materials, glass, epoxy resin, etc. In the semiconductor package 100, the package substrate 110 may include a printed circuit board (PCB), and the substrate main body layer may be formed based on glass epoxy (or FR-4) resin, phenolic resin, or bismaleimide triazine (BT) resin. However, the material of the substrate main layer is not limited to the above materials.

[0027] In some implementations, the substrate body layer may include a single layer or multiple layers. For example, the package substrate 110 may include a single-layer PCB with leads formed only on one side thereof or a double-layer PCB with leads formed on both sides thereof. In the double-layer PCB, the upper lead and the lower lead may be electrically connected to each other through via contacts passing through the substrate body layer. In addition, three or more layers of copper foil (Cu foil) may be formed on the substrate body layer using an insulator including a prepreg. In some implementations, three or more layers of leads may be formed on the substrate body layer according to the number of layers of the Cu foil.

[0028] The substrate protection layer may be disposed on the lower surface and the upper surface of the substrate main body layer, respectively. The substrate protection layer may cover and protect the leads arranged on the upper surface and the lower surface of the substrate main body layer. For example, the substrate protection layer may include a solder resist (SR), in particular a photo SR (PSR). Here, the PSR may include an SR that can be patterned by an exposure process. However, in some implementations, the material of the substrate protection layer is not limited to SR or PSR. For example, depending on the type or function of the substrate main body layer, the substrate protection layer may include a passivation layer such as an oxide film and a nitride film. In addition, the substrate pad 112 on the upper surface of the substrate main body layer and the external pad on the lower surface of the substrate main body layer may be exposed through the substrate protection layer. In addition, the substrate main body layer may occupy most of the package substrate 110 and may be substantially the same as the package substrate 110 in appearance. Therefore, in some implementations, the substrate main body layer and the package substrate 110 may be used as substantially the same concept.

[0029] The substrate pads 112 may be disposed on the upper surface of the package substrate 110 and electrically connected to corresponding chip pads 126 of the semiconductor chips of the chip stack structure 120 through wires 130. Figure 1A As shown, the chip pads 126 of the semiconductor chips in the chip stacking structure 120 may all be connected to the substrate pads 112. Therefore, the number of substrate pads 112 and the number of chip pads 126 of each of the semiconductor chips may be equal to each other. However, in some implementations, different substrate pads may be arranged corresponding to the semiconductor chips, respectively. In some implementations, the substrate pads 112 connected to the semiconductor chip at a low position may be close to the chip stacking structure 120, and the substrate pads 112 connected to the semiconductor chip at a high position may be away from the chip stacking structure 120.

[0030] The external pad may be disposed on the lower surface of the package substrate 110. As described above, the substrate protection layer may be disposed on the lower surface of the package substrate 110, and the external pad may pass through the substrate protection layer and be exposed to the outside. The external pad may be connected to the lead inside the substrate body layer through a via contact, and the external connection terminal 150 may be disposed on the external pad.

[0031] The chip stacking structure 120 may be mounted on the package substrate 110 and include four semiconductor chips 120-1 to 120-4 (or referred to as the first semiconductor chip 120-1 to the fourth semiconductor chip 120-4). In the semiconductor package 100, the chip stacking structure 120 includes four semiconductor chips 120-1 to 120-4, but the number of semiconductor chips in the chip stacking structure 120 is not limited to four. For example, in some implementations, the chip stacking structure 120 may include two, three, or five or more semiconductor chips. In some implementations, the chip stacking structure may include eight semiconductor chips, as described below with reference to Fig. 6A as described.

[0032] In the chip stacking structure 120, the first semiconductor chip 120-1, the second semiconductor chip 120-2, the third semiconductor chip 120-3 and the fourth semiconductor chip 120-4 may be sequentially stacked in a stair shape on the package substrate 110. In some implementations, the four semiconductor chips 120-1 to 120-4 may be identical to each other in size and function. Therefore, for simplicity, the first semiconductor chip 120-1 is described below.

[0033] The first semiconductor chip 120-1 may include a chip body layer 122, a chip protection layer 124 and a chip pad 126. The chip body layer 122 may include a semiconductor substrate, an element layer and a multi-wiring layer. The semiconductor substrate may be based on a semiconductor material, such as a silicon wafer. The element layer may be formed on the semiconductor substrate and include various types of elements. For example, in some implementations, the element layer may include various semiconductor elements, such as field effect transistors (FETs) (including planar FETs or FinFETs), memory elements (including flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM) and resistance random access memory (RRAM)), logic elements (including AND, OR and NOT), system large-scale integration (LSI), complementary metal oxide semiconductor imaging sensor (CIS) and micro-electromechanical system (MEMS). In the semiconductor package 100 according to some implementations, the first semiconductor chip 120 - 1 may include a DRAM chip including a DRAM element in an element layer. However, in the semiconductor package 100 according to some implementations, the type of the first semiconductor chip 120 - 1 is not limited to a DRAM chip.

[0034] The chip protection layer 124 may cover and protect the upper surface of the chip body layer 122. For example, the chip protection layer 124 may include polyimide (PI). In particular, the chip protection layer 124 may include a photosensitive (PS) PI that is easy to pattern. However, the material of the chip protection layer 124 is not limited to PI or PSPI. In addition, in the semiconductor package 100 according to some implementations, the upper surface of the chip protection layer 124 may have hydrophilicity. Here, hydrophilicity may refer to the property of being easily combined with polar molecules such as water molecules. The opposite property to hydrophilicity is defined as hydrophobicity, which may refer to the property of not combining with polar molecules such as water molecules. In addition, the hydrophilicity of the upper surface of the chip protection layer 124 may be derived from the characteristics of the material of the chip protection layer 124, or may be given by a separate plasma treatment. In the semiconductor package 100 according to some implementations, the chip protection layer 124 may include, for example, PSPI, and have an upper surface that is given hydrophilicity by plasma treatment.

[0035] The chip pad 126 may be arranged on the upper surface of the first semiconductor chip 120-1. Therefore, the upper surface of the first semiconductor chip 120-1 may have an active surface, and the lower surface of the first semiconductor chip 120-1 may have an inactive surface. In some implementations, the chip pad 126 may be arranged to be offset to an area in the x direction. For example, the chip pad 126 may be adjacent to the first edge E1 and arranged along the y direction. When the upper surface or the lower surface of the first semiconductor chip 120-1 has a rectangular shape, the first edge E1 may correspond to a line adjacent to the chip pad 126 and extending in the y direction. Here, the chip pad 126 may be exposed from the chip protection layer 124 and may be electrically connected to the substrate pad 112 of the package substrate 110 respectively through the lead 130.

[0036] An alignment pattern line APL may be formed in the chip protection layer 124. In the semiconductor package 100 according to some implementations, the alignment pattern line APL may be formed as a first groove T1 having a line shape. For example, the first groove T1 may be adjacent to the first edge E1 of the first semiconductor chip 120-1 in the x direction and extend in the y direction parallel to the first edge E1. The first groove T1 may pass through the chip protection layer 124 (extend into the chip protection layer 124) and expose the chip body layer 122 at its bottom surface. As described above, the upper surface of the chip protection layer 124 may be hydrophilic, and the upper surface of the chip body layer 122 exposed in a line shape through the first groove T1 may be hydrophobic.

[0037] In some implementations, the first trench T1 may have a first width W1 in a direction perpendicular to the direction in which the first trench T1 extends. For example, the first trench T1 may extend in the y direction and have a first width W1 in the x direction. For example, the first width W1 may be about 10 μm. However, the first width W1 of the first trench T1 is not limited to 10 μm.

[0038] In some implementations, the first semiconductor chip 120-1 may be directly coupled to and stacked on the upper surface of the package substrate 110. Therefore, there may be no adhesive layer between the first semiconductor chip 120-1 and the package substrate 110. Fig. 8A and Figure 8B The structure in which the first semiconductor chip 120 - 1 is directly coupled to the upper surface of the package substrate 110 is described in more detail.

[0039] In some implementations, the second semiconductor chip 120-2 may be directly coupled to the first semiconductor chip 120-1 without an adhesive layer and stacked on the first semiconductor chip 120-1. In addition, the third semiconductor chip 120-3 may be directly coupled to the second semiconductor chip 120-2 without an adhesive layer and stacked on the second semiconductor chip 120-2, and the fourth semiconductor chip 120-4 may be directly coupled to the third semiconductor chip 120-3 without an adhesive layer and stacked on the third semiconductor chip 120-3. Since in some implementations, the coupling and stacking structures between the semiconductor chips are all the same, the description focuses on the coupling and stacking structures between the first semiconductor chip 120-1 and the second semiconductor chip 120-2.

[0040] In some implementations, the second semiconductor chip 120-2 may be directly coupled to the first semiconductor chip 120-1 without an adhesive layer. For example, the second semiconductor chip 120-2 may be directly coupled to the first semiconductor chip 120-1 by van der Waals forces rather than by adhesive forces from the adhesive layer. In addition, the second semiconductor chip 120-2 may be self-aligned with the alignment pattern line APL of the first semiconductor chip 120-1. For example, the first edge E1 of the second semiconductor chip 120-2 may be self-aligned with the first groove T1 which is the alignment pattern line APL of the first semiconductor chip 120-1. Here, self-alignment may refer to a state in which alignment is automatically performed through the structure or characteristics of the semiconductor chip itself without performing a manual alignment process. In the semiconductor package 100, according to some implementations, self-alignment of the second semiconductor chip 120-2 may be performed due to the surface tension of the hydrophilic liquid. Refer to the following FIG. 9A to FIG. 13 The self-alignment of the second semiconductor chip 120 - 2 is described in more detail.

[0041] The first edge E1 of the second semiconductor chip 120-2 is self-aligned with the first trench T1 of the first semiconductor chip 120-1, and other semiconductor chips are self-aligned with the underlying semiconductor chip in the same structure. Figure 1A As shown, four semiconductor chips 120-1 to 120-4 may be stacked in a stepped shape on a package substrate 110. Due to this stepped stacking structure, a chip pad 126 of each of the four semiconductor chips 120-1 to 120-4 may be exposed to the outside. Therefore, the chip pad 126 may be connected to the substrate pad 112 through a lead 130.

[0042] However, in some implementations, when semiconductor chips are stacked in a staircase shape in only one direction, as the number of semiconductor chips increases, the width of the semiconductor package in one direction may become too large. Therefore, as the number of semiconductor chips increases, the semiconductor chips may be stacked in the form of Z-shaped steps. In some implementations, the semiconductor chips may be stacked in a zigzag shape instead of a staircase shape. Fig. 6A and Figure 6B The chip stacking structure in the Z-shaped step form or the chip stacking structure in the zigzag form is described in more detail.

[0043] The sealing material 140 may cover the upper surface and side surface of the chip stacking structure 120 above the upper surface of the package substrate 110 and the lead 130. The sealing material 140 may have a specific thickness and cover the upper surface of the chip stacking structure 120. The sealing material 140 may include a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., PI), or a resin (e.g., ABF, FR-4, and BT) formed by adding a reinforcing material (e.g., an inorganic filler) to a thermosetting resin or a thermoplastic resin. In addition, the sealing material 140 may include a molding material, such as an epoxy molding compound (EMC). However, the material of the sealing material 140 is not limited to the above materials.

[0044] In some implementations, the external connection terminals 150 may be disposed on the lower surface of the package substrate 110. For example, the external connection terminals 150 may be disposed on external pads on the lower surface of the package substrate 110. The external connection terminals 150 may be electrically connected to the leads of the package substrate 110 through the external pads. In addition, the external connection terminals 150 may include solder balls. In some implementations, the external connection terminals 150 may include pillars and solder. In some implementations, the semiconductor package 100 may be mounted on an external substrate such as an interposer or a base substrate through the external connection terminals 150.

[0045] In some implementations, the semiconductor package 100 may include a chip stacking structure 120 stacked on a package substrate 110, and the chip stacking structure 120 may include four semiconductor chips 120-1 to 120-4. In the chip stacking structure 120, the upper semiconductor chip may be self-aligned and directly coupled to the lower semiconductor chip located below the upper semiconductor chip without an adhesive layer. For example, there is no separate adhesive layer between the upper semiconductor chip and the lower semiconductor chip, and the upper semiconductor chip and the lower semiconductor chip may be directly coupled to each other by van der Waals forces. In addition, the first edge E1 of the upper semiconductor chip may be self-aligned with the alignment pattern line APL (e.g., the first trench T1) on the upper surface of the lower semiconductor chip. As described above, the semiconductor chips are coupled to each other without an adhesive layer, and the total thickness of the semiconductor package 100 may be reduced or the thickness of each semiconductor chip may be increased. In addition, the semiconductor chips are self-aligned and stacked with each other, and in the chip stacking structure 120 of the semiconductor package 100, the stacking accuracy of the semiconductor chips may be improved.

[0046] In the semiconductor package 100, the structure in which semiconductor chips are self-aligned and stacked with each other without an adhesive layer can be applied not only to a semiconductor package including a chip stacking structure in a general step form, but also to a semiconductor package including a chip stacking structure in a Z-shaped step form or a semiconductor package including a chip stacking structure in a zigzag form. In addition, the structure in which semiconductor chips are self-aligned and stacked with each other without an adhesive layer is not limited to the chip stacking structure in the step or zigzag form, and the structure can also be applied to a semiconductor package including other types of chip stacking structures, in which semiconductor chips are stacked with each other with chip pads exposed.

[0047] Figure 2 is a cross-sectional view of an example of a semiconductor package 100a according to some implementations. Figure 1A and Figure 1B The description provided is given briefly or omitted. Figure 2 In the embodiment, the semiconductor package 100a and Figure 1A The semiconductor package 100 may be different in that, Figure 2 The chip stacking structure 120 is stacked on the upper surface of the package substrate 110 through the adhesive layer 142. For example, the semiconductor package 100a may include the package substrate 110, the chip stacking structure 120, the sealing material 140 and the external connection terminal 150. The package substrate 110, the sealing material 140 and the external connection terminal 150 are similar to those described above. Figure 1A Those of the described semiconductor package 100 are the same.

[0048] The chip stacking structure 120 may include four semiconductor chips 120-1 to 120-4, and the four semiconductor chips 120-1 to 120-4 may be stacked in a stepped form. In addition, the chip stacking structure 120 may be adhered and fixed to the upper surface of the package substrate 110 through the adhesive layer 142. For example, the first semiconductor chip 120-1 of the chip stacking structure 120 may be adhered and fixed to the upper surface of the package substrate 110 through the adhesive layer 142. Other features of the chip stacking structure 120 are similar to those described above with reference to Figure 1A The semiconductor package 100 described above is the same as that of the semiconductor package 100. Therefore, in the semiconductor package 100a, each of the second to fourth semiconductor chips 120-2 to 120-4 of the chip stack structure 120 may be self-aligned with and stacked on a corresponding lower semiconductor chip without an adhesive layer.

[0049] Figure 3A and Figure 3B According to some implementation methods Figure 1A FIG. 1 is a plan view of an example of a semiconductor chip included in a semiconductor package 100. Figure 1A Give a description together, and refer to the above Figures 1A to 2 The description provided is simplified or omitted. Figure 3A In the semiconductor package 100, the semiconductor chips of the chip stack structure 120a may be different from Figure 1A Specifically, in the semiconductor package 100, similar to Figure 1A The chip stacking structure 120a may include four semiconductor chips 120a-1 to 120a-4 stacked in a stair form. However, the stacking form of the chip stacking structure 120a is not limited to the stair form, and the number of semiconductor chips of the chip stacking structure 120a is not limited to four. Figure 3A A first semiconductor chip 120 a - 1 is shown as one of four semiconductor chips 120 a - 1 to 120 a - 4 of the chip stack structure 120 a .

[0050] The first semiconductor chip 120a-1 may include a chip body layer 122, a chip protection layer 124, and a chip pad 126. Alignment pattern lines APL may be formed on the upper surface of the first semiconductor chip 120a-1. Alignment pattern lines APL may be formed by a portion of the second trench T2. For example, a second trench T2 having a quadrilateral ring shape may be formed in the upper surface of the first semiconductor chip 120a-1. The second trench T2 may pass through the chip protection layer 124 (extending into the chip protection layer 124), and the chip body layer 122 may be exposed at the bottom of the second trench T2. The second trench T2 may include four lines corresponding to the four edges on the upper surface of the first semiconductor chip 120a-1. Among the four lines of the second trench T2, the first line L1 adjacent to the first edge E1 of the first semiconductor chip 120a-1 and extending in the y direction parallel to the first edge E1 may form the alignment pattern line APL.

[0051] In some implementations, the second trench T2 may have a first width W1 in a direction perpendicular to the direction in which the second trench T2 extends. For example, a line extending in the y direction may have a first width W1 in the x direction, and a line extending in the x direction may have a first width W1 in the y direction. The first width W1 may be, for example, about 10 μm. However, the first width W1 of the second trench T2 is not limited to 10 μm. For example, in addition to the first line L1, other lines of the second trench T2 may be spaced apart from the corresponding edge of the first semiconductor chip 120 a - 1 by a first distance S1. The first distance S1 may be, for example, about 10 μm. However, the first distance S1 is not limited to 10 μm.

[0052] In the semiconductor package 100, the semiconductor chips of the chip stacking structure 120a can also be self-aligned and stacked with each other without an adhesive layer. For example, in the chip stacking structure 120a, there is no adhesive layer between the second semiconductor chip 120a-2 and the first semiconductor chip 120a-1, and the second semiconductor chip 120a-2 and the first semiconductor chip 120a-1 can be directly coupled to each other by van der Waals force. In addition, the first edge E1 of the second semiconductor chip 120a-2 can be self-aligned with the alignment pattern line APL of the first semiconductor chip 120a-1. For example, the first edge E1 of the second semiconductor chip 120a-2 can be self-aligned with the first line L1 of the second trench T2 of the first semiconductor chip 120a-1. In addition, the stacking structure between the third semiconductor chip 120a-3 and the second semiconductor chip 120a-2 and the stacking structure between the fourth semiconductor chip 120a-4 and the third semiconductor chip 120a-3 can be substantially the same as the stacking structure between the second semiconductor chip 120a-2 and the first semiconductor chip 120a-1.

[0053] exist Figure 3BIn the semiconductor package 100, the semiconductor chips of the chip stack structure 120b may be different from Figure 1A The semiconductor chip of the chip stacking structure 120 of the semiconductor package 100 is shown in FIG. Figure 1A The chip stacking structure 120b may include four semiconductor chips 120b-1 to 120b-4 stacked in a stair form. However, the stacking form of the chip stacking structure 120b is not limited to the stair form, and the number of semiconductor chips of the chip stacking structure 120b is not limited to four. Figure 3B A first semiconductor chip 120 b - 1 is shown as one of four semiconductor chips 120 b - 1 to 120 b - 4 of the chip stack structure 120 b .

[0054] The first semiconductor chip 120b-1 may include a chip body layer 122, a chip protection layer 124, and a chip pad 126. Alignment pattern lines APL may be formed on the upper surface of the first semiconductor chip 120b-1. The alignment pattern lines APL may be formed by a portion of the third trench T3. For example, a third trench T3 having a quadrilateral ring shape may be formed in the upper surface of the first semiconductor chip 120b-1. The third trench T3 may pass through the chip protection layer 124, and the chip body layer 122 may be exposed at the bottom of the third trench T3. The third trench T3 may include four lines corresponding to the four edges on the upper surface of the first semiconductor chip 120b-1. Among the four lines of the third trench T3, the first line L1 adjacent to the first edge E1 of the first semiconductor chip 120b-1 and extending in the y direction parallel to the first edge E1 may form the alignment pattern line APL.

[0055] In some implementations, the third trench T3 may have a first width W1 in a direction perpendicular to the direction in which the third trench T3 extends. For example, a line extending in the y direction may have a first width W1 in the x direction, and a line extending in the x direction may have a first width W1 in the y direction. The first width W1 may be, for example, about 10 μm. However, the first width W1 of the third trench T3 is not limited to 10 μm. Here, in addition to the first line L1, other lines of the third trench T3 may expose the corresponding edge of the first semiconductor chip 120 b - 1. For example, the upper surface portion of the remaining edge of the first semiconductor chip 120 b - 1 other than the first edge E1 may not be covered by the chip protection layer 124 by the amount of the first width W1, but may be exposed through the third trench T3.

[0056] In the semiconductor package 100, the semiconductor chips of the chip stacking structure 120b may also be self-aligned and stacked with each other without an adhesive layer. For example, there may be no adhesive layer between the second semiconductor chip 120b-2 and the first semiconductor chip 120b-1 in the chip stacking structure 120b. In addition, the first edge E1 of the second semiconductor chip 120b-2 may be self-aligned with the alignment pattern line APL (e.g., the first line L1 of the third trench T3) of the first semiconductor chip 120b-1.

[0057] Figure 4A is a cross-sectional view of an example of a semiconductor package 100b according to some implementations, Figure 4B yes Figure 4A FIG. 1 is a plan view of an example of a semiconductor chip included in a semiconductor package 100 b. Figures 1A to 3B The description given is given briefly or omitted. Figure 4A and Figure 4B In the embodiment, the semiconductor package 100b may be different from the configuration of the chip stack structure 120c. Figure 1A For example, the semiconductor package 100b may include a package substrate 110, a chip stack structure 120c, a sealing material 140, and an external connection terminal 150. In some implementations, the package substrate 110, the sealing material 140, and the external connection terminal 150 are the same as those described above with reference to FIG. Figure 1A Those of the described semiconductor package 100 are the same.

[0058] In the semiconductor package 100b, similar to Figure 1A The chip stacking structure 120c may include four semiconductor chips 120c-1 to 120c-4 stacked in a stair form. However, the stacking form of the chip stacking structure 120c is not limited to the stair form, and the number of semiconductor chips of the chip stacking structure 120c is not limited to four. Figure 4B A first semiconductor chip 120 c - 1 is shown as one of four semiconductor chips 120 c - 1 to 120 c - 4 of the chip stack structure 120 c .

[0059] The first semiconductor chip 120c-1 includes a chip body layer 122 and a chip pad 126, but may not include a separate chip protection layer on its upper surface. Therefore, the upper surface of the first semiconductor chip 120c-1 may correspond to the upper surface of the chip body layer 122. In addition, in the semiconductor package 100b, the upper surface of the first semiconductor chip 120c-1 (i.e., the upper surface of the chip body layer 122) may be hydrophilic. For example, the upper surface of the first semiconductor chip 120c-1 may be plasma treated and have hydrophilicity.

[0060] The alignment pattern line APL may be formed on the upper surface of the first semiconductor chip 120c-1. The alignment pattern line APL may be formed as a first dam D1 having a line shape. For example, the first dam D1 may be formed in a line shape on the upper surface of the chip body layer 122. In addition, the first dam D1 may be adjacent to the first edge E1 of the first semiconductor chip 120c-1 in the x direction and extend in the y direction parallel to the first edge E1. The first dam D1 may have a structure protruding from the upper surface of the chip body layer 122 in a line shape. The first dam D1 may include PI (e.g., PSPI). However, the material of the first dam D1 is not limited to PI or PSPI.

[0061] In some implementations, the first dam D1 may have a second width W2 in a direction perpendicular to the direction in which the first dam D1 extends. For example, the first dam D1 may extend in the y direction and have a second width W2 in the x direction. The second width W2 may be, for example, about 20 μm. However, the second width W2 of the first dam D1 is not limited to 20 μm.

[0062] In the semiconductor package 100b, the semiconductor chips of the chip stacking structure 120c can also be self-aligned and stacked with each other without an adhesive layer. For example, in the chip stacking structure 120c, there is no adhesive layer between the second semiconductor chip 120c-2 and the first semiconductor chip 120c-1, and the second semiconductor chip 120c-2 and the first semiconductor chip 120c-1 can be directly coupled to each other by van der Waals force. In addition, the first edge E1 of the second semiconductor chip 120c-2 can be self-aligned with the alignment pattern line APL of the first semiconductor chip 120c-1. For example, the first edge E1 of the second semiconductor chip 120c-2 can be self-aligned with the first dam D1 of the first semiconductor chip 120c-1. In addition, the stacking structure between the third semiconductor chip 120c-3 and the second semiconductor chip 120c-2 and the stacking structure between the fourth semiconductor chip 120c-4 and the third semiconductor chip 120c-3 can be substantially the same as the stacking structure between the second semiconductor chip 120c-2 and the first semiconductor chip 120c-1.

[0063] Figure 5A is a cross-sectional view of an example of a semiconductor package 100c according to some implementations, Figure 5B According to some implementation methods Figure 5A A plan view of an example of a semiconductor chip included in a semiconductor package 100c, Figure 5C According to some implementation methods Figure 5A This is an enlarged view of area A. Figures 1A to 4B The description given is briefly given or omitted.

[0064] exist Figure 5A and Figure 5BIn the embodiment, the semiconductor package 100c may be different from the configuration of the chip stack structure 120d. Figure 1A For example, the semiconductor package 100c may include a package substrate 110, a chip stack structure 120d, a sealing material 140, and an external connection terminal 150. In some implementations, the package substrate 110, the sealing material 140, and the external connection terminal 150 may be the same as those described above with reference to Figure 1A Those of the described semiconductor package 100 are the same.

[0065] In the semiconductor package 100c, similar to Figure 1A The chip stacking structure 120d may include four semiconductor chips 120d-1 to 120d-4 stacked in a stair form. However, the stacking form of the chip stacking structure 120d is not limited to the stair form, and the number of semiconductor chips of the chip stacking structure 120d is not limited to four. Figure 5B A first semiconductor chip 120 d - 1 is shown as one of four semiconductor chips 120 d - 1 to 120 d - 4 of the chip stack structure 120 d .

[0066] The first semiconductor chip 120d-1 includes a chip body layer 122 and a chip pad 126, but may not include a separate chip protection layer on its upper surface. Therefore, the upper surface of the first semiconductor chip 120d-1 may correspond to the upper surface of the chip body layer 122. In addition, in the semiconductor package 100c, the upper surface of the first semiconductor chip 120d-1 (i.e., the upper surface of the chip body layer 122) may be hydrophilic. For example, the upper surface of the first semiconductor chip 120d-1 may be plasma treated and have hydrophilicity.

[0067] The alignment pattern line APL may be formed on the upper surface of the first semiconductor chip 120d-1. The alignment pattern line APL may be formed by a portion of the second dam D2 having a quadrilateral ring shape. For example, the second dam D2 may be formed in a quadrilateral ring shape protruding on the upper surface of the chip body layer 122. The second dam D2 may include four lines corresponding to the four edges on the upper surface of the first semiconductor chip 120d-1. Among the four lines of the second dam D2, the first line L1 adjacent to the first edge E1 of the first semiconductor chip 120d-1 and extending in the y direction parallel to the first edge E1 may form the alignment pattern line APL.

[0068] In some implementations, the second dam D2 may have a second width W2 in a direction perpendicular to the direction in which the second dam D2 extends. For example, a line extending in the y direction may have a second width W2 in the x direction, and a line extending in the x direction may have a second width W2 in the y direction. The second width W2 may be, for example, about 20 μm. However, the second width W2 of the second dam D2 is not limited to 20 μm. Here, in addition to the first line L1, other lines of the second dam D2 may cover the corresponding edges of the first semiconductor chip 120d-1. For example, the upper surface portion of the remaining edge of the first semiconductor chip 120d-1 other than the first edge E1 may be covered by the second dam D2 by the amount of the second width W2.

[0069] like Figure 5C As shown, due to the protruding structure of the second dam D2, a gap G may exist between the second semiconductor chip 120d-2 and the first semiconductor chip 120d-1, and the gap G may be adjacent to the remaining lines of the second dam D2 except the first line L1 adjacent to the first edge E1 of the first semiconductor chip 120d-1. For example, a gap G having a size of the protruding thickness of the second dam D2 exists adjacent to the remaining lines of the second dam D2, and the gap G may gradually decrease in a direction toward the inside of the second dam D2.

[0070] In the semiconductor package 100c, the semiconductor chips of the chip stacking structure 120d can also be self-aligned and stacked with each other without an adhesive layer. For example, in the chip stacking structure 120d, there is no adhesive layer between the second semiconductor chip 120d-2 and the first semiconductor chip 120d-1, and the second semiconductor chip 120d-2 and the first semiconductor chip 120d-1 can be directly coupled to each other by van der Waals force. In addition, the first edge E1 of the second semiconductor chip 120d-2 can be self-aligned with the alignment pattern line APL of the first semiconductor chip 120d-1. For example, the first edge E1 of the second semiconductor chip 120d-2 can be self-aligned with the first line L1 of the second dam D2 of the first semiconductor chip 120d-1. In addition, the stacking structure between the third semiconductor chip 120d-3 and the second semiconductor chip 120d-2 and the stacking structure between the fourth semiconductor chip 120d-4 and the third semiconductor chip 120d-3 can be substantially the same as the stacking structure between the second semiconductor chip 120d-2 and the first semiconductor chip 120d-1.

[0071] Fig. 6A and Figure 6B is a cross-sectional view of an example of a semiconductor package 100d and 100e according to some implementations. Figures 1A to 5B The description given is briefly given or omitted.

[0072] exist Fig. 6AIn the embodiment, the semiconductor package 100d may be configured differently from the chip stack structure 120e. Figure 1A For example, the semiconductor package 100d may include a package substrate 110, a chip stack structure 120e, a sealing material 140, and an external connection terminal 150. In some implementations, the package substrate 110, the sealing material 140, and the external connection terminal 150 may be the same as those described above with reference to Figure 1A The semiconductor package 100 described in the drawings is the same as that of the semiconductor package 100 described in the drawings. Fig. 6A The lead wire 130 and the sealing material 140 are omitted, and Figure 6B These components are also omitted.

[0073] In the semiconductor package 100d, Figure 1A Unlike the chip stacking structure 120 of FIG. 1 , the chip stacking structure 120e may include eight semiconductor chips 120-1 to 120-8 stacked in a staircase form. Each of the eight semiconductor chips 120-1 to 120-8 (or referred to as the first semiconductor chip 120-1 to the eighth semiconductor chip 120-8) may be connected to Figure 1B The first semiconductor chip 120-1 is substantially the same as the first semiconductor chip 120-1. In addition, in the semiconductor package 100d, the semiconductor chips of the chip stacking structure 120e may be stacked in a step shape in the x direction and in a Z shape in the z direction. For example, in the chip stacking structure 120e of the semiconductor package 100d, the first semiconductor chip 120-1 to the fifth semiconductor chip 120-5 may be stacked on each other while their positions increase toward the left in the x direction, and the sixth semiconductor chip 120-6 to the eighth semiconductor chip 120-8 may be stacked on each other while their positions increase toward the right in the x direction.

[0074] As described above, when a large number of semiconductor chips are stacked in a staircase shape in only one direction, the width of the semiconductor package in one direction can be significantly increased. For example, when the semiconductor chips are stacked in a staircase shape toward only one side in the x direction on the package substrate, the width of the semiconductor package in the x direction can be significantly increased. However, in the semiconductor package 100d, the semiconductor chips of the chip stacking structure 120e are stacked in a staircase shape in the x direction and are also arranged in a Z shape in the z direction, and Figure 1A Compared with the width of the semiconductor package 100 in the x direction, the width of the semiconductor package 100 d in the x direction does not increase.

[0075] exist Figure 6B In the embodiment, the semiconductor package 100e may be configured differently from the chip stack structure 120f. Figure 1AFor example, the semiconductor package 100e may include a package substrate 110, a chip stacking structure 120f, a sealing material 140, and an external connection terminal 150. In some implementations, the package substrate 110, the sealing material 140, and the external connection terminal 150 may be the same as those described above with reference to Figure 1A Those of the described semiconductor package 100 are the same.

[0076] In the semiconductor package 100e, similar to Figure 1A The chip stack structure 120f may include four semiconductor chips 120-1 to 120-4. In addition, each of the four semiconductor chips 120-1 to 120-4 may be connected to Figure 1B The first semiconductor chip 120-1 is substantially the same as that of the first semiconductor chip 120-1. Figure 1A Unlike the chip stacking structure 120 of the embodiment of the present invention, the chip stacking structure 120f may have a zigzag shape instead of a step shape. For example, the first semiconductor chip 120-1 and the third semiconductor chip 120-3 may be arranged offset to the left in the x-direction, and the second semiconductor chip 120-2 and the fourth semiconductor chip 120-4 may be arranged offset to the right in the x-direction. In the semiconductor package 100e, when the four semiconductor chips 120-1 to 120-4 of the chip stacking structure 120f are stacked in a zigzag shape, the width of the semiconductor package 100e in the x-direction may be minimized.

[0077] Fig. 6A and Figure 6B An example of a chip stacking structure including eight semiconductor chips and having a Z-step shape and an example of a chip stacking structure including four semiconductor chips and having a zigzag shape are respectively shown. However, the number of semiconductor chips in the chip stacking structure having a Z-step form and the number of semiconductor chips in the chip stacking structure having a zigzag form are not limited to the above values.

[0078] Fig. 7A is a graph showing the thickness of the DAF relative to the number of semiconductor chips according to some implementations, Figure 7B is a graph showing chip thickness relative to the overall height of a semiconductor package according to various chip stacking structures according to some implementations. Fig. 7A In the present invention, DAF can be generally used as an adhesive layer when stacking a semiconductor chip on a package substrate or on another semiconductor chip. Fig. 7A It is shown that as the number of semiconductor chips in the chip stacking structure increases, the total thickness of the DAF increases. Fig. 7AIt is shown that due to the thickness difference of one DAF, the total thickness of the DAF in the chip stacking structure also varies significantly. For example, when the thickness of one DAF is 5μm, the total thickness of the DAF in the chip stacking structure including 8 semiconductor chips may be 40μm, and the total thickness of the DAF in the chip stacking structure including 16 semiconductor chips may be 80μm. In addition, when the thickness of one DAF is 10μm, the total thickness of the DAF in the chip stacking structure including 8 semiconductor chips may be 80μm, and the total thickness of the DAF in the chip stacking structure including 16 semiconductor chips may be 160μm. Therefore, in the chip stacking structure using DAF, as the number of semiconductor chips increases, the total thickness of the semiconductor package can be increased by DAF.

[0079] exist Figure 7B , the total height of the semiconductor package including the chip stacking structure of 4 stacks, 8 stacks, 16 stacks, and 32 stacks is shown according to the thickness of the semiconductor chip. Here, the chip thickness limit line (LLCT) indicated by the dotted line represents the minimum thickness of the chip that can be used in the semiconductor package. For example, a semiconductor chip having a thickness less than the LLCT may not be used in the semiconductor package.

[0080] exist Figure 7B In the semiconductor package of the chip stacking structure including 4 stacked pieces, all semiconductor packages having a height of 0.5 mm or more can be manufactured. For example, a semiconductor package having a height of 0.5 mm can be manufactured by stacking four semiconductor chips each having a thickness of about 60 μm. In addition, a semiconductor package having a height of 1.4 mm can be manufactured by stacking four semiconductor chips each having a thickness of about 280 μm.

[0081] In a semiconductor package including a chip stacking structure of 8 stacked pieces, only semiconductor packages having a height of 0.9 mm or more can be manufactured. For example, a semiconductor package having a height of 0.9 mm can be manufactured by stacking eight semiconductor chips each having a thickness of about 70 μm. In addition, a semiconductor package having a height of 1.4 mm can be manufactured by stacking eight semiconductor chips each having a thickness of about 140 μm.

[0082] In a semiconductor package including a chip stacking structure of 16 stacked pieces, only semiconductor packages having a height of 1.0 mm or more can be manufactured. For example, a semiconductor package having a height of 1.0 mm can be manufactured by stacking 16 semiconductor chips each having a thickness of about LLCT. In addition, a semiconductor package having a height of 1.4 mm can be manufactured by stacking 16 semiconductor chips each having a thickness of about 60 μm.

[0083] In a semiconductor package including a chip stacking structure of 32 stacked pieces, even a semiconductor package with a height of 1.4 mm cannot be manufactured. For example, 32 semiconductor chips each having a thickness of 30 μm must be stacked in order to manufacture a semiconductor package with a height of 1.4 mm. However, a thickness of 30 μm is less than LLCT, and a semiconductor chip with a thickness of 30 μm may not be used in a semiconductor package.

[0084] In a semiconductor package including a chip stacking structure, when the number of semiconductor chips is fixed, the total height of the semiconductor package can be reduced by removing an adhesive layer (e.g., DAF). Conversely, when the total height of the semiconductor package is fixed, the number of semiconductor chips can be increased by removing the adhesive layer. In addition, when the number of semiconductor chips and the total height of the semiconductor package are fixed, the thickness of the semiconductor chip can be increased by removing the adhesive layer. Therefore, according to some implementations, the semiconductor packages 100 and 100a to 100e can help reduce the total height of the semiconductor package, maximize the number of semiconductor chips, and maximize the thickness of the semiconductor chip.

[0085] In addition, in a general chip stacking process, due to the die bonding tolerance, a minimum design rule may be required for the chip to chip. For example, when stacking chips of the same type, a tolerance of about 25 μm is required, and when stacking chips of different types, a tolerance of about 50 μm is required. This tolerance increases the size of the semiconductor package in the horizontal direction, and as the number of semiconductor chips increases, the size of the semiconductor package in the horizontal direction may be further increased. On the other hand, in the semiconductor packages 100 and 100a to 100e according to some implementations, the semiconductor chips are self-aligned and stacked with each other without an adhesive layer. Therefore, it does not occur that the size of the semiconductor package in the horizontal direction increases due to the die bonding tolerance.

[0086] Fig. 8A is a cross-sectional view of an example of a semiconductor package 100f according to some implementations, Figure 8B According to some implementation methods Fig. 8A A plan view of an example of a package substrate included in a semiconductor package 100f. Figures 1A to 7B The description given is briefly given or omitted.

[0087] exist Fig. 8A and Figure 8B In the embodiment, the semiconductor package 100f may be configured differently with respect to the package substrate 110a. Figure 1AFor example, the semiconductor package 100f may include a package substrate 110a, a chip stacking structure 120, a sealing material 140, and an external connection terminal 150. In some implementations, the chip stacking structure 120, the sealing material 140, and the external connection terminal 150 may be the same as those described above with reference to FIG. Figure 1A The semiconductor package 100 described above is the same as that of the semiconductor package 100. For reference, for the convenience of illustration, Fig. 8A The lead wires 130, the sealing material 140 and the external connection terminals 150 are omitted.

[0088] exist Fig. 8A In the embodiment, the package substrate 110a may include a substrate main body layer 110B, a substrate protection layer 110SR, a substrate pad 112 and an external pad. The substrate main body layer 110B, the substrate pad 112 and the external pad are similar to those described above. Figure 1A Those of the described semiconductor package 100 are the same.

[0089] The substrate protection layer 110SR may include, for example, a solder resist (SR), more specifically, a photo solder resist (PSR). However, the material of the substrate protection layer 110SR is not limited to SR or PSR. In the semiconductor package 100f, the package substrate 110a may include an SR open area SROA formed in the substrate protection layer 110SR. The SR open area SROA may be formed by removing a portion of the substrate protection layer 110SR, and the upper surface of the substrate body layer 110B may be exposed through the SR open area SROA.

[0090] In some implementations, the SR open area SROA may have a size sufficient to accommodate the first semiconductor chip 120-1. For example, the plane area of ​​the SR open area SROA may be substantially the same as or slightly larger than the plane area of ​​the first semiconductor chip 120-1. Therefore, the first semiconductor chip 120-1 or the chip stacking structure 120 including the first semiconductor chip 120-1 may be inserted and stacked in the SR open area SROA of the substrate protection layer 110SR.

[0091] In the semiconductor package 100f, the first semiconductor chip 120-1 may be stacked on the package substrate 110a without an adhesive layer. For example, in the SR open area SROA of the package substrate 110a, the first semiconductor chip 120-1 may be directly coupled to the substrate body layer 110B using van der Waals force without an adhesive layer. In addition, in order to couple to the first semiconductor chip 120-1 by van der Waals force, the upper surface of the substrate body layer 110B exposed by the SR open area SROA may be hydrophilic.

[0092] In some implementations, the SR open area SROA may have a rectangular shape corresponding to the rectangular shape of the lower surface of the first semiconductor chip 120-1. Therefore, the SR open area SROA has four sides. Among the four sides, the first side SL1 extending in the y direction and located on the right side in the x direction may serve as an alignment pattern line APL. In some implementations, the first semiconductor chip 120-1 may be self-aligned with the package substrate 110a by the alignment pattern line APL. For example, the first edge E1 of the first semiconductor chip 120-1 may be self-aligned with the first side SL1 of the SR open area SROA.

[0093] In some implementations, the semiconductor package 100f is not limited to a structure in which the first semiconductor chip 120-1 is self-aligned with and stacked on the package substrate 110a using the SR open area SROA of the substrate protection layer 110SR without an adhesive layer. Figure 1A or Figure 3A In the semiconductor package 100 of the present invention, the first semiconductor chip 120-1 can be self-aligned with and stacked on the package substrate 110a using the linear groove or quadrangular ring groove formed in the substrate protection layer 110SR without an adhesive layer. Therefore, a hydrophilic treatment can be performed on the upper surface of the substrate protection layer 110SR.

[0094] FIG. 9A to FIG. 13 are cross-sectional views and plan views illustrating an example of a process for manufacturing a semiconductor package according to some implementations. Figure 1A and Figure 1B Give a description together, refer to Figures 1A to 8B The given description is simplified or omitted.

[0095] exist Fig. 9A and Fig. 9B For example, a method for manufacturing a semiconductor package according to some implementations is shown. Figure 1A In the semiconductor package manufacturing method, first, an alignment pattern line APL is formed on each of the semiconductor chips. The alignment pattern line APL may include a first trench T1 having a line shape and formed in a chip protection layer 124 of the semiconductor chip. For example, the chip protection layer 124 may include PSPI, and the first trench T1 may be formed by an exposure process. In some implementations, the shape of the first trench T1 may be the same as described above with reference to FIG. Figure 1A Same as described.

[0096] Before forming the alignment pattern line APL on each of the semiconductor chips, a hydrophilic treatment may be performed on the chip protection layer 124 of each of the semiconductor chips. For example, the hydrophilic treatment may be performed by plasma treatment. The upper surface of the chip protection layer 124 of each of the semiconductor chips may be given hydrophilicity by the hydrophilic treatment. In addition, during the hydrophilic treatment of the chip protection layer 124 of the semiconductor chip, a hydrophilic treatment may also be performed on the lower surface of the semiconductor chip. Here, the upper surface of the chip body layer 122 exposed by the alignment pattern line APL (e.g., the first trench T1) may be hydrophobic.

[0097] After forming the alignment pattern line APL, the first semiconductor chip 120-1 is stacked on the package substrate 110. The adhesive layer, the SR open area SROA (see Fig. 8A ) etc. The first semiconductor chip 120-1 is stacked on the package substrate 110. When the SR open region is used, the first semiconductor chip 120-1 may be stacked on the package substrate 110 without an adhesive layer by a process similar to the process of stacking the second semiconductor chip 120-2 described below.

[0098] Later, in Fig. 10A and Fig. 10B In the embodiment, the hydrophilic liquid 200 is applied on the chip protection layer 124 of the first semiconductor chip 120-1 using a dispenser 300. For example, the hydrophilic liquid may include a polar liquid substance such as water and alcohol. Due to the hydrophilicity of the chip protection layer 124 such as PSPI and the hydrophobicity of the inside of the first trench T1 as the alignment pattern line APL, the chip protection layer 124 may be wetted by the hydrophilic liquid 200 on the left side in the x direction based on the first trench T1, as shown in FIG. Fig. 10A and Fig. 10B shown.

[0099] exist Fig.11A and Fig. 11B In the embodiment, after applying the hydrophilic liquid 200, the second semiconductor chip 120-2 is stacked on the first semiconductor chip 120-1. As described above, the lower surface of the second semiconductor chip 120-2 may be hydrophilic. Therefore, when the second semiconductor chip 120-2 is stacked, the lower surface of the second semiconductor chip 120-2 may be wetted by the hydrophilic liquid 200 on the first semiconductor chip 120-1 and coupled to the hydrophilic liquid 200. In addition, as Fig. 11B As indicated by the circular arrow in FIG. 2 , the second semiconductor chip 120-2 can be automatically self-aligned with the first semiconductor chip 120-1 by rotational motion and / or linear motion due to the surface tension of the hydrophilic liquid 200. For example, the first edge E1 of the second semiconductor chip 120-2 can be self-aligned with the alignment pattern line APL (i.e., the first trench T1 of the first semiconductor chip 120-1).

[0100] Later, in Fig.12 In the embodiment, by the same process, the third semiconductor chip 120-3 is stacked on the second semiconductor chip 120-2 and the fourth semiconductor chip 120-4 is stacked on the third semiconductor chip 120-3. The third semiconductor chip 120-3 may be self-aligned (SA) to the second semiconductor chip 120-2, and the fourth semiconductor chip 120-4 may be self-aligned (SA) to the third semiconductor chip 120-3. Fig.12 As shown in the enlarged view of FIG. 1 , in the area near the first trench T1 of the first semiconductor chip 120-1, the hydrophilic liquid 200 can maintain a concave shape between the first semiconductor chip 120-1 and the second semiconductor chip 120-2 due to the surface tension ST. In addition, at the left end of the second semiconductor chip 120-2 in the x direction, the hydrophilic liquid 200 becomes thinner in the upward direction relative to the z direction due to the surface tension ST, and can maintain a shape that protrudes long to the left in the x direction.

[0101] Later, in Fig.13 In the process, a package substrate 110 including four semiconductor chips 120-1 to 120-4 is inserted into a chamber 400 and baked or thermally cured. For example, the baking process may refer to a heating process for removing the hydrophilic liquid 200. The hydrophilic liquid 200 is evaporated and removed by the baking process, and adjacent semiconductor chips can be directly coupled to each other by van der Waals forces. For example, the first semiconductor chip 120-1 and the second semiconductor chip 120-2, the second semiconductor chip 120-2 and the third semiconductor chip 120-3, and the third semiconductor chip 120-3 and the fourth semiconductor chip 120-4 can be directly coupled to each other by van der Waals forces. Therefore, a chip stacking structure 120 can be formed, in which the semiconductor chips are self-aligned with the package substrate 110 and stacked on the package substrate 110 without an adhesive layer. Subsequently, leads 130, a sealing material 140, and external connection terminals 150 can be formed to complete the process. Figure 1A A semiconductor package 100 is provided.

[0102] FIG. 14A to FIG. 16B are cross-sectional views and plan views illustrating an example of a process for manufacturing a semiconductor package according to some implementations. Figure 3A Give a description together, refer to FIG. 9A to FIG. 13 The given description is simplified or omitted.

[0103] exist Fig.14A and Fig. 14B For example, a method for manufacturing a semiconductor package according to some implementations is shown. Figure 3AIn the semiconductor package manufacturing method, first, an alignment pattern line APL is formed on each of the semiconductor chips. The alignment pattern line APL may include a second trench T2 having a quadrilateral ring shape and formed in a chip protection layer 124 of the semiconductor chip. For example, the chip protection layer 124 may include PSPI, and the second trench T2 may be formed by an exposure process. In some implementations, the shape of the second trench T2 and the first line L1 of the second trench T2 may be the same as described above with reference to Figure 3A Those of the described semiconductor package 100 are the same.

[0104] Before forming the alignment pattern line APL on each of the semiconductor chips, a hydrophilic treatment may be performed on the chip protection layer 124 of each of the semiconductor chips. For example, the hydrophilic treatment may be performed by plasma treatment. In addition, during the hydrophilic treatment of the chip protection layer 124 of the semiconductor chip, a hydrophilic treatment may also be performed on the lower surface of the semiconductor chip. For example, the upper surface of the chip body layer 122 exposed by the second trench T2 including the alignment pattern line APL may be hydrophobic.

[0105] After forming the alignment pattern line APL, the first semiconductor chip 120a-1 may be stacked on the package substrate 110. The first semiconductor chip 120a-1 may be formed using an adhesive layer, an SR open area SROA (see Fig. 8A ) and the like are stacked on the package substrate 110.

[0106] Later, in Fig.15A and Fig. 15B In the embodiment, the hydrophilic liquid 200 is applied on the chip protection layer 124 of the first semiconductor chip 120a-1 using the dispenser 300. Due to the hydrophilicity of the chip protection layer 124 and the hydrophobicity in the second trench T2 including the alignment pattern line APL, the chip protection layer 124 inside the second trench T2 can be wetted by the hydrophilic liquid 200, as shown in FIG. Fig.15A and Fig. 15B shown.

[0107] exist Fig.16A and Fig. 16B In the embodiment, after applying the hydrophilic liquid 200, the second semiconductor chip 120a-2 is stacked on the first semiconductor chip 120a-1. As described above, the lower surface of the second semiconductor chip 120a-2 may be hydrophilic. Therefore, when the second semiconductor chip 120a-2 is stacked, the lower surface of the second semiconductor chip 120a-2 may be wetted by the hydrophilic liquid 200 on the first semiconductor chip 120a-1 and coupled to the hydrophilic liquid 200. In addition, as Fig. 16BAs indicated by the circular arrow in FIG. 2 , the second semiconductor chip 120a-2 can be automatically self-aligned with the first semiconductor chip 120a-1 by rotational motion and / or linear motion due to the surface tension of the hydrophilic liquid 200. For example, the first edge E1 of the second semiconductor chip 120a-2 can be self-aligned with the alignment pattern line APL (i.e., the first line L1 of the second trench T2 of the first semiconductor chip 120a-1).

[0108] Subsequently, the third semiconductor chip 120 a - 3 and the fourth semiconductor chip 120 a - 4 are stacked and may be formed through a baking process. Figure 3A In addition, the lead 130, the sealing material 140 and the external connection terminal 150 may be formed to complete the chip stacking structure 120a. Figure 3A A semiconductor package 100 is provided.

[0109] FIG. 17A to FIG. 19B are cross-sectional views and plan views illustrating an example of a process for manufacturing a semiconductor package according to some implementations. Figure 4A and Figure 4B Give a description together, refer to FIG. 9A to FIG. 13 The given description is simplified or omitted.

[0110] exist Fig.17A and Fig. 17B For example, a method for manufacturing a semiconductor package according to some implementations is shown. Figure 4A In the semiconductor package manufacturing method, first, an alignment pattern line APL is formed on each of the semiconductor chips. The alignment pattern line APL may include a first dam D1 having a line shape and formed in a chip body layer 122 of the semiconductor chip. For example, the first dam D1 may include PSPI and be formed by an exposure process. The shape of the first dam D1 is similar to Figure 4A The shape of the first dam D1 of the semiconductor package 100 b is the same.

[0111] Before forming the alignment pattern line APL on each of the semiconductor chips, a hydrophilic treatment may be performed on the upper surface of the chip body layer 122 of each of the semiconductor chips. For example, the hydrophilic treatment may be performed by plasma treatment. In addition, during the hydrophilic treatment of the upper surface of the chip body layer 122 of the semiconductor chip, a hydrophilic treatment may also be performed on the lower surface of the semiconductor chip. Here, due to the material properties of PSPI, the alignment pattern line APL (e.g., the first dam D1) may be hydrophobic.

[0112] After forming the alignment pattern line APL, the first semiconductor chip 120c-1 is stacked on the package substrate 110. The adhesive layer, the SR open area SROA (see Fig. 8A) etc. to stack the first semiconductor chip 120 c - 1 on the package substrate 110 .

[0113] Later, in Fig.18A and Fig.18B In the embodiment, the hydrophilic liquid 200 is applied to the chip body layer 122 of the first semiconductor chip 120c-1 using the dispenser 300. Due to the hydrophilicity of the chip body layer 122 and the hydrophobicity of the first dam D1, the chip body layer 122 can be wetted by the hydrophilic liquid 200 on the left side in the x direction based on the first dam D1, as shown in FIG. Fig.18A and Fig.18B shown.

[0114] exist Fig.19A and Fig.19B In the embodiment, after applying the hydrophilic liquid 200, the second semiconductor chip 120c-2 is stacked on the first semiconductor chip 120c-1. As described above, the lower surface of the second semiconductor chip 120c-2 may be hydrophilic. Therefore, when the second semiconductor chip 120c-2 is stacked, the lower surface of the second semiconductor chip 120c-2 may be wetted by the hydrophilic liquid 200 on the first semiconductor chip 120c-1 and coupled to the hydrophilic liquid 200. In addition, as Fig.19B As indicated by the circular arrow in FIG. 2 , the second semiconductor chip 120c-2 can be automatically self-aligned with the first semiconductor chip 120c-1 by rotational motion and / or linear motion due to the surface tension of the hydrophilic liquid 200. For example, the first edge E1 of the second semiconductor chip 120c-2 can be self-aligned with the alignment pattern line APL (i.e., the first dam D1 of the first semiconductor chip 120c-1).

[0115] Subsequently, the third semiconductor chip 120 c - 3 and the fourth semiconductor chip 120 c - 4 are stacked and may be formed by a baking process. Figure 4A In addition, the lead wire 130, the sealing material 140 and the external connection terminal 150 may be formed to complete the chip stacking structure 120c. Figure 4A Semiconductor package 100b.

[0116] FIG. 20A to FIG. 22B are cross-sectional views and plan views illustrating an example of a process for manufacturing a semiconductor package according to some implementations. Figure 5A and Figure 5B Give a description together, refer to FIG. 9A to FIG. 13 The given description is simplified or omitted.

[0117] exist Fig. 20A and Fig. 20B For example, a method for manufacturing a semiconductor package according to some implementations is shown. Figure 5AIn the semiconductor package manufacturing method, first, an alignment pattern line APL is formed on each of the semiconductor chips. The alignment pattern line APL may include a second dam D2 having a quadrilateral ring shape and formed in a chip body layer 122 of the semiconductor chip. For example, the second dam D2 may include PSPI and be formed by an exposure process. In some implementations, the shape of the second dam D2 and the first line L1 of the second dam D2 may be the same as that of the first line L1 of the second dam D2. Figure 5A The described semiconductor package 100 c is the same as that of the semiconductor package 100 c .

[0118] Before forming the alignment pattern line APL on the semiconductor chip, a hydrophilic treatment may be performed on the upper surface of the chip body layer 122 of the semiconductor chip. For example, the hydrophilic treatment may be performed by plasma treatment. In addition, during the hydrophilic treatment of the upper surface of the chip body layer 122 of the semiconductor chip, a hydrophilic treatment may also be performed on the lower surface of the semiconductor chip. Here, due to the material properties of PSPI, the second dam D2 including the alignment pattern line APL may be hydrophobic.

[0119] After forming the alignment pattern line APL, the first semiconductor chip 120d-1 is stacked on the package substrate 110. The adhesive layer, the SR open area SROA (see Fig. 8A ) etc. to stack the first semiconductor chip 120d-1 on the package substrate 110.

[0120] exist Fig.21A and Fig.21B In the embodiment, the hydrophilic liquid 200 is applied on the chip body layer 122 of the first semiconductor chip 120d-1 using the dispenser 300. Due to the hydrophilicity of the chip body layer 122 and the hydrophobicity of the second dam D2 including the alignment pattern line APL, the chip body layer 122 inside the second dam D2 can be wetted by the hydrophilic liquid 200, as shown in FIG. Fig.21A and Fig.21B shown.

[0121] exist Fig.22A and Fig. 22B In the embodiment, after applying the hydrophilic liquid 200, the second semiconductor chip 120d-2 is stacked on the first semiconductor chip 120d-1. As described above, the lower surface of the second semiconductor chip 120d-2 may be hydrophilic. Therefore, when the second semiconductor chip 120d-2 is stacked, the lower surface of the second semiconductor chip 120d-2 may be wetted by the hydrophilic liquid 200 on the first semiconductor chip 120d-1 and coupled to the hydrophilic liquid 200. In addition, as Fig. 22BAs indicated by the circular arrow in FIG. 1 , the second semiconductor chip 120d-2 can be automatically self-aligned with the first semiconductor chip 120d-1 by rotational motion and / or linear motion due to the surface tension of the hydrophilic liquid 200. For example, the first edge E1 of the second semiconductor chip 120d-2 can be self-aligned with the alignment pattern line APL (i.e., the first line L1 of the second dam D2 of the first semiconductor chip 120d-1).

[0122] Subsequently, the third semiconductor chip 120d-3 and the fourth semiconductor chip 120d-4 are stacked and may be formed by a baking process. Figure 5A In addition, the lead 130, the sealing material 140 and the external connection terminal 150 may be formed to complete the chip stacking structure 120d. Figure 5A A semiconductor package 100c is provided.

[0123] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the protection that can be claimed. Certain features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually in multiple implementations or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, one or more features from a combination may be cut out from the combination in some cases, and a combination may involve a sub-combination or a variation of a sub-combination.

Claims

1. A semiconductor package, comprising: Package substrate; as well as at least two semiconductor chips stacked on the package substrate and electrically connected to the package substrate via leads, Among the at least two semiconductor chips, a first semiconductor chip located at a lower side is coupled to a second semiconductor chip located above the first semiconductor chip without an adhesive.

2. The semiconductor package according to claim 1, wherein: Each of the at least two semiconductor chips has an upper surface and a lower surface in a rectangular shape, and the upper surface includes an active surface and the lower surface includes an inactive surface, The chip pads are arranged along a first direction on the upper surface of each of the at least two semiconductor chips, the chip pads are adjacent to a first edge, the first edge corresponds to a line of a rectangular shape of the upper and lower surfaces of each of the at least two semiconductor chips and extends in the first direction, An alignment pattern line is formed on an upper surface of the first semiconductor chip and extends parallel to a first edge of the upper surface of the first semiconductor chip, and A first edge of a lower surface of the second semiconductor chip is self-aligned with the alignment pattern line of the first semiconductor chip.

3. The semiconductor package according to claim 2, wherein: The alignment pattern lines include trenches or dams formed in the first semiconductor chip.

4. The semiconductor package according to claim 2, wherein: The alignment pattern line comprises one of the following: a first trench having a line shape and formed in the protection layer on the upper surface of the first semiconductor chip, a first line of second trenches having a quadrilateral ring shape and formed in the protection layer, wherein the first line of the second trenches is adjacent to a first edge of an upper surface of the first semiconductor chip, a first dam having a line shape and formed on an upper surface of the first semiconductor chip, and A first line of a second dam having a quadrilateral ring shape and formed on the upper surface of the first semiconductor chip, wherein the first line of the second dam is adjacent to a first edge of the upper surface of the first semiconductor chip.

5. The semiconductor package according to claim 1, wherein: A lowermost semiconductor chip among the at least two semiconductor chips is bonded to the package substrate without an adhesive.

6. The semiconductor package according to claim 1, wherein: The semiconductor package has one of the following: a thickness that is smaller than a thickness of a first semiconductor package including an adhesive by a thickness of the adhesive, and A thickness substantially the same as a thickness of the first semiconductor package, wherein each of the at least two semiconductor chips is thicker than the semiconductor chip of the first semiconductor package.

7. The semiconductor package according to claim 1, wherein: A lowermost semiconductor chip among the at least two semiconductor chips is bonded to the package substrate using an adhesive.

8. The semiconductor package according to claim 1, wherein: The at least two semiconductor chips are stacked in a step shape or a zigzag shape on the package substrate.

9. A semiconductor package, comprising: a package substrate having a solder resist layer formed on an upper surface thereof; a first semiconductor chip coupled to the package substrate without an adhesive, the first semiconductor chip being electrically connected to the package substrate via first leads; as well as at least two second semiconductor chips coupled to the first semiconductor chip without adhesive, the at least two second semiconductor chips being electrically connected to the package substrate via second leads, wherein a lower second semiconductor chip located at the lower side among the at least two second semiconductor chips is coupled to an upper second semiconductor chip located above the lower second semiconductor chip without an adhesive, wherein the lower second semiconductor chip of the at least two second semiconductor chips is self-aligned with the first alignment pattern line on the upper surface of the first semiconductor chip, and The second alignment pattern lines on the upper surfaces of the upper second semiconductor chip and the lower second semiconductor chip are self-aligned.

10. The semiconductor package according to claim 9, in, Each of the first semiconductor chip and the at least two second semiconductor chips has an upper surface and a lower surface in a rectangular shape, and the upper surface includes an active surface and the lower surface includes an inactive surface, wherein the first alignment pattern line and the second alignment pattern line are adjacent to a first edge, the first edge corresponds to a line of a rectangular shape of upper and lower surfaces of the first semiconductor chip and the at least two second semiconductor chips and extends in a first direction, and the first alignment pattern line and the second alignment pattern line extend parallel to the first edge on the upper surfaces of the first semiconductor chip and the at least two second semiconductor chips, wherein a first edge of the lowermost second semiconductor chip among the at least two second semiconductor chips is self-aligned with a first alignment pattern line of the first semiconductor chip, and Wherein, the first edge of the upper second semiconductor chip is self-aligned with the second alignment pattern line of the lower second semiconductor chip.

11. The semiconductor package according to claim 10, wherein: The first alignment pattern line or the second alignment pattern line comprises one of the following: a first trench having a line shape and formed in the protection layer on the upper surface of the first semiconductor chip or the lower second semiconductor chip, a first line of a second trench having a quadrilateral ring shape and formed in the protective layer, wherein the first line of the second trench is adjacent to a first edge of an upper surface of the first semiconductor chip or the lower second semiconductor chip, a first dam having a line shape and formed on an upper surface of the first semiconductor chip or the lower second semiconductor chip, and A first line of a second dam having a quadrilateral ring shape and formed on an upper surface of the first semiconductor chip or the lower second semiconductor chip, wherein the first line of the second dam is adjacent to a first edge of an upper surface of the first semiconductor chip or the lower second semiconductor chip.

12. The semiconductor package according to claim 9, wherein: The first semiconductor chip is disposed on a solder resist open region formed by removing a portion of the solder resist layer.

13. The semiconductor package according to claim 9, wherein: The semiconductor package has one of the following: a thickness that is smaller than a thickness of a first semiconductor package including an adhesive by a thickness of the adhesive, and A thickness substantially the same as a thickness of the first semiconductor package, wherein each of the first semiconductor chip and the at least two second semiconductor chips is thicker than a semiconductor chip of the first semiconductor package.

14. A semiconductor package, comprising: Package substrate; as well as at least two semiconductor chips, the at least two semiconductor chips are stacked on the package substrate and each has an upper surface and a lower surface of a rectangular shape, wherein the upper surface of each of the at least two semiconductor chips includes an active surface, and the lower surface of each of the at least two semiconductor chips includes an inactive surface, and a chip pad is arranged along a first direction on the upper surface of each of the at least two semiconductor chips, the chip pad is adjacent to a first edge, the first edge corresponds to a line of a rectangular shape of the upper surface and the lower surface of each of the at least two semiconductor chips and extends in the first direction, wherein the at least two semiconductor chips are stacked on each other so that chip pads thereof are exposed to the outside, and the chip pads are electrically connected to substrate pads of the package substrate via wires, and Among the at least two semiconductor chips, a first semiconductor chip located at a lower side is coupled to a second semiconductor chip located above the first semiconductor chip without an adhesive.

15. The semiconductor package according to claim 14, further comprising an alignment pattern line formed on the upper surface of the first semiconductor chip, the alignment pattern line extending parallel to a first edge of the upper surface of the first semiconductor chip, in, A first edge of a lower surface of the second semiconductor chip is self-aligned with the alignment pattern line of the first semiconductor chip.

16. The semiconductor package according to claim 15, wherein: The alignment pattern line comprises one of the following: a first trench having a line shape and formed in the protection layer on the upper surface of the first semiconductor chip, a first line of second trenches having a quadrilateral ring shape and formed in the protection layer, wherein the first line of the second trenches is adjacent to a first edge of an upper surface of the first semiconductor chip, a first dam having a line shape and formed on an upper surface of the first semiconductor chip, and A first line of a second dam having a quadrilateral ring shape and formed on the upper surface of the first semiconductor chip, wherein the first line of the second dam is adjacent to a first edge of the upper surface of the first semiconductor chip.

17. The semiconductor package according to claim 14, wherein: A lowermost semiconductor chip among the at least two semiconductor chips is bonded to the package substrate without an adhesive.

18. A method for manufacturing a semiconductor package, the method comprising: forming alignment pattern lines on an upper surface of the semiconductor chip; stacking a first semiconductor chip among the semiconductor chips on a package substrate; applying a hydrophilic liquid onto the upper surface of the first semiconductor chip; stacking a second semiconductor chip among the semiconductor chips on the first semiconductor chip; as well as performing a heat treatment on the first semiconductor chip and the second semiconductor chip, During the heat treatment of the first semiconductor chip and the second semiconductor chip, the hydrophilic liquid is removed, and the first semiconductor chip and the second semiconductor chip are coupled to each other by van der Waals force without an adhesive.

19. The method according to claim 18, wherein: Each of the semiconductor chips has an upper surface and a lower surface in a rectangular shape, and the upper surface includes an active surface and the lower surface includes an inactive surface, Chip pads are arranged along a first direction on an upper surface of each of the semiconductor chips, the chip pads being adjacent to a first edge corresponding to a line of a rectangular shape of upper and lower surfaces of each of the semiconductor chips and extending in the first direction, and The alignment pattern line extends parallel to the first edge on the upper surface of the semiconductor chip, During stacking of the second semiconductor chip on the first semiconductor chip, a first edge of a lower surface of the second semiconductor chip is self-aligned with an alignment pattern line of the first semiconductor chip.

20. The method according to claim 18, further comprising performing a hydrophilic treatment on an upper surface and a lower surface of each of the semiconductor chips before forming the alignment pattern lines, in, The hydrophilic treatment is performed using plasma.

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