SEMICONDUCTOR PACKAGE WITH HIGH METAL BUMPS AND UltraTHIN SUBSTRATES

Abstract

The invention discloses a semiconductor package and a method for manufacturing a plurality of semiconductor packages, where the semiconductor package includes a semiconductor substrate, a plurality of contact pads, a plurality of metal bumps, a metal layer, and a molding package. The thickness of the semiconductor substrate is less than 35 microns. A first method comprises the steps of providing a device wafer; attaching a first carrier; a refining process is applied; forming a metal layer; pasting a first adhesive tape; removing the first carrier; applying a first segmentation process; tearing off the first adhesive tape; connecting a second carrier; molding packaging is formed; removing the second carrier; forming a plurality of metal bumps; pasting a second adhesive tape; and applying a segmentation process and removing the second adhesive tape. A second method includes a step of providing a device wafer; a connection carrier; a refining process is applied; forming a metal layer; molding packaging is formed; removing the carrier; forming a plurality of metal bumps; and a segmentation process is applied.

Description

Technical Field

[0001] The present invention generally relates to a semiconductor package having a thin semiconductor substrate less than 35 microns and a method of manufacturing a plurality of semiconductor packages. More particularly, the present invention relates to a semiconductor package having tall metal bumps. Background Art

[0002] The chip scale package (CSP) die usually needs to be connected to the printed circuit board (PCB) by using a flip chip process, including a capillary underfill (CUF) assembly process and a molded underfill (MUF) assembly process. The MUF assembly process is more popular because of its high productivity, low cost, and high reliability. The gap between the die and the PCB (the height of the metal bump or solder bump) is preferably at least 40 microns to facilitate improved compound filling. High metal bumps or high solder bumps (at least 40 microns) usually require a thicker semiconductor substrate (greater than 50 microns) to avoid wafer cracks when grinding the back of the semiconductor substrate.

[0003] Advantages of the present disclosure include suppression of solder bridge issues, improved structural strength, low warpage (less than 10 microns at 25 degrees Celsius and less than 40 microns at 245 degrees Celsius), and higher yield of semiconductor package products. Summary of the invention

[0004] The present invention discloses a semiconductor package, comprising a semiconductor substrate, a plurality of contact pads located in front of the semiconductor substrate, a plurality of metal bumps at least 35 microns high formed on the plurality of contact pads, a metal layer on the back of the semiconductor substrate, and a molded package. The thickness of the semiconductor substrate is 15 microns to 35 microns. The thickness of the metal layer can be as high as 30 microns or more.

[0005] The present invention discloses a method for manufacturing a plurality of semiconductor packages, comprising the following steps: providing a device wafer; attaching a first carrier; applying a back grinding process; forming a back metal layer; pasting a first tape; removing the first carrier; applying a first segmentation process; transferring a second carrier; forming a molded package; removing the second carrier; forming a plurality of metal bumps; and applying a segmentation process. The method is applicable to any metal layer thickness on the back of the semiconductor substrate, especially a thick metal layer thickness on the back exceeding 10 microns. For devices with a metal layer thickness on the back of the semiconductor substrate less than 10 microns, a simplified alternative method can be applied, the steps comprising providing a device wafer; connecting a carrier; applying a grinding process; forming a metal layer; forming a molded package; removing the carrier; forming a plurality of metal bumps; and applying a segmentation process.

[0006] The present invention discloses a semiconductor package, which comprises: a semiconductor substrate having a plurality of side surfaces, a front surface and a rear surface opposite to the front surface of the semiconductor substrate; a plurality of contact pads, including: a plurality of aluminum pads arranged on the front surface of the semiconductor substrate; and a plurality of openings of a passivation layer located above the plurality of aluminum pads; a plurality of metal bumps located above the plurality of aluminum pads; a metal layer having a plurality of side surfaces, a front surface and a rear surface opposite to the front surface of the metal layer, the front surface of the metal layer being directly attached to the rear surface of the semiconductor substrate; and a molded package directly contacting the back side of the semiconductor substrate; wherein the thickness of the semiconductor substrate is less than 35 microns; and wherein the height of the metal bumps is at least 35 microns.

[0007] Optionally, the thickness of the metal layer is greater than 10 micrometers, and the molded package directly contacts multiple side surfaces of the semiconductor substrate and multiple side surfaces of the metal layer.

[0008] Optionally, the molded package also directly contacts multiple side surfaces of the passivation layer located at the edge of the semiconductor substrate.

[0009] Optionally, each of the plurality of metal bumps includes a corresponding copper portion and a corresponding tin-silver portion above the corresponding copper portion.

[0010] Optionally, bottom surfaces of the plurality of metal bumps and top surfaces of the plurality of aluminum pads are coplanar.

[0011] Optionally, the thickness of the metal layer is less than 10 micrometers, and multiple side surfaces of the semiconductor substrate and multiple side surfaces of the metal layer are not covered by the molded package.

[0012] The present invention also discloses a method for manufacturing multiple semiconductor packages, which method includes the following steps: providing a device wafer, wherein the device wafer includes: a semiconductor substrate having a front surface and a rear surface opposite to the front surface of the semiconductor substrate; and a plurality of contact pads attached to the front surface of the semiconductor substrate; bonding the plurality of contact pads of the device wafer to a first carrier through a release layer and an adhesive layer; thinning the back side of the semiconductor substrate to form a thinned semiconductor substrate; forming a metal layer on the back side of the thinned semiconductor substrate; removing the first carrier; applying a first segmentation process to form a plurality of intermediate devices including a plurality of segmented semiconductor substrates and a plurality of segmented metal layers; transferring the plurality of intermediate devices to a second carrier; forming a molded package that directly contacts the side surfaces of the plurality of segmented semiconductor substrates, the side surfaces of the plurality of segmented metal layers, and the back surfaces of the plurality of segmented metal layers; removing the second carrier; forming a plurality of metal bumps; and applying a second segmentation process to form a plurality of semiconductor packages; wherein the thickness of the thinned semiconductor substrate is 15 microns to 35 microns; and wherein the thickness of each of the plurality of metal bumps is at least 35 microns.

[0013] Optionally, a total thickness variation TTV of the semiconductor substrate after thinning is less than 3 microns.

[0014] Optionally, each of the plurality of metal bumps includes a corresponding copper portion and a corresponding tin-silver portion above the corresponding copper portion.

[0015] Optionally, the plurality of contact pads include: a plurality of aluminum pads exposed from a plurality of openings of a passivation layer located above the aluminum pads; wherein bottom surfaces of the plurality of metal bumps are coplanar with top surfaces of the plurality of aluminum pads.

[0016] Optionally, the molded package also directly contacts a plurality of side surfaces of the passivation layer located at the edge of the semiconductor substrate.

[0017] The present invention also discloses a method for manufacturing multiple semiconductor packages, which method includes the following steps: providing a device wafer, wherein the device wafer includes: a semiconductor substrate having a front surface and a rear surface opposite to the front surface of the semiconductor substrate; and a plurality of contact pads attached to the front surface of the semiconductor substrate; bonding the plurality of contact pads of the device wafer to a carrier through a release layer and an adhesive layer; performing a thinning process on the back side of the semiconductor substrate to form a thinned semiconductor substrate; forming a metal layer on the back side of the thinned semiconductor substrate; forming a molded package directly contacting the back side of the metal layer; removing the carrier; forming a plurality of metal bumps; and applying a segmentation process to form a plurality of semiconductor packages; wherein the thickness of the thinned semiconductor substrate is 15 microns to 35 microns; and wherein the thickness of each of the plurality of metal bumps is at least 35 microns.

[0018] Optionally, a total thickness variation TTV of the semiconductor substrate after thinning is less than 3 microns.

[0019] Optionally, the thickness of the metal layer formed on the back side of the thinned semiconductor substrate is less than 10 microns.

[0020] Optionally, each of the plurality of metal bumps includes a corresponding copper portion and a corresponding tin-silver portion above the corresponding copper portion.

[0021] The semiconductor package with high metal bumps and ultra-thin substrate and the manufacturing method thereof disclosed in the present invention have the following beneficial effects: suppressing the solder bridge problem, improving the structural strength, having low warpage (less than 10 microns at 25 degrees Celsius and less than 40 microns at 245 degrees Celsius) and higher yield rate of semiconductor package products. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A and Figure 1B shows a cross-sectional view of a semiconductor package in an example of the present disclosure;

[0023] Figure 2 is developed in the examples of this disclosure Figure 1A a flow chart of a process for a plurality of semiconductor packages;

[0024] Figure 3A , 3B , 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L, 3M and 3N show Figure 2 cross-section of the corresponding steps of the process;

[0025] Figure 4 is developed in the examples of this disclosure Figure 1B a flow chart of a process for a plurality of semiconductor packages;

[0026] Figure 5A , 5B , 5C, 5D, 5E, 5F, 5G and 5H show Figure 4 Cross-section of the corresponding steps of the process. DETAILED DESCRIPTION

[0027] The technical solutions, structural features, achieved objectives and effects of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0028] It should be noted that the drawings are in a very simplified form and use non-precise proportions. They are only used to conveniently and clearly assist in explaining the embodiments of the present invention, and are not used to limit the conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention.

[0029] It should be noted that, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only the elements explicitly listed, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0030] Figure 1AA cross-sectional view of a semiconductor package 100 in an example of the present disclosure is shown. The semiconductor package 100 includes a semiconductor substrate 120, a plurality of contact pads 130, a plurality of metal bumps 160, a metal layer 180, and a molded package 190. In an example of the present disclosure, the coefficient of thermal expansion (CTE) of the molded package 190 is less than 7 ppm / °C, and the glass transition temperature (Tg) of the molded package 190 is greater than 150 degrees Celsius.

[0031] The semiconductor substrate 120 has a plurality of side surfaces 121, a front surface 122, and a rear surface 124 opposite to the front surface 122 of the semiconductor substrate 120. The plurality of contact pads 130 include a plurality of aluminum pads 132 exposed from a plurality of openings of a passivation layer 134. The plurality of aluminum pads 132 are disposed on the front surface 122 of the semiconductor substrate 120. The passivation layer 134 is located above the plurality of aluminum pads 132. A plurality of metal bumps 160 are connected to the upper surfaces of the plurality of aluminum pads 132.

[0032] The metal layer 180 has a plurality of side surfaces 181, a front surface 182, and a rear surface 184 opposite to the front surface 182 of the metal layer 180. The front surface 182 of the metal layer 180 is directly attached to the rear surface 124 of the semiconductor substrate 120. The plurality of side surfaces 181 define the edge of the metal layer 180. The molded package 190 directly contacts the plurality of side surfaces 121 of the semiconductor substrate 120, the plurality of side surfaces 181 of the metal layer 180, and the rear surface 184 of the metal layer 180. Silver fragments that may be generated during the separation process of the metal layer 180 are encapsulated by the molded package 190 to suppress device reliability failure caused by silver migration. The molded package 190 also directly contacts the plurality of side surfaces 167 of the passivation layer 134 located at the edge of the semiconductor substrate 120.

[0033] In the example of the present disclosure, the thickness of the semiconductor substrate 120 is less than 35 micrometers, preferably in the range of 15 micrometers to 35 micrometers. The thickness of the metal layer 180 may be up to 30 micrometers or more.

[0034] In one example, the metal layer 180 is a titanium copper layer (TiCu) having a thickness in a range of 1 micron to 30 microns. In another example, the metal layer 180 is a titanium nickel silver (TiNiAg) having a thickness in a range of 1 micron to 30 microns.

[0035] In an example of the present disclosure, each of the plurality of metal bumps 160 is columnar and has a height of at least 35 microns. Each of the plurality of metal bumps 160 includes a corresponding copper portion 162 and a corresponding tin-silver portion 164 above the corresponding copper portion 162. In an example of the present disclosure, the height of the corresponding copper portion 162 is in the range of 20 microns to 100 microns. The height of the corresponding tin-silver portion 164 is in the range of 15 microns to 30 microns.

[0036] In an example of the present disclosure, the bottom surfaces of the plurality of metal bumps 160 and the top surfaces of the plurality of aluminum pads 132 are coplanar.

[0037] In an example of the present disclosure, semiconductor package 100 is a common drain metal oxide semiconductor field effect transistor (MOSFET) chip scale package (CSP) for battery protection applications. Two gates and multiple sources are located on the front surface of the common drain MOSFET CSP. The common drain is located on the back side of the common drain MOSFET CSP.

[0038] Figure 1B A cross-sectional view of an alternative semiconductor package 100' in an example of the present disclosure is shown. The semiconductor package 100' is similar to the semiconductor package 100' except that the molded package 190' only covers the back surface 184 of the metal layer 180. Figure 1A The semiconductor package 100 ′ is the same as the semiconductor package 100 ′. A plurality of side surfaces 121 of the semiconductor substrate 120 and a plurality of side surfaces 181 of the metal layer 180 of the semiconductor package 100 ′ are exposed. The thickness of the metal layer 180 is less than 10 micrometers.

[0039] In the examples of the present disclosure, Figure 2 A flowchart of process 200 for Figure 1A The semiconductor package 100 , in particular, the semiconductor package wherein the thickness of the metal layer 380 is at least 10 μm. Figure 2 The flowchart embodiment of the process 200 includes a first singulation process (step 214) and a second singulation process (step 228) to release stress generated in the semiconductor wafer before forming the molded package 390, thereby reducing the mismatch between the CTE of the molded package 390 and the CTE of the molded package metal layer 380. In an example of the present disclosure, Figure 4 The process 400 is for Figure 1B The semiconductor package 100 ′, in particular, the semiconductor package having a thickness of the metal layer 580 less than 10 μm.

[0040] Figure 2 is a flow chart of a process 200 for developing a plurality of semiconductor packages in an example of the present disclosure. Figures 3A-3N Shows Figure 2 For simplicity, Figure 3A , 3B , 3C, 3D, 3E, 3F, 3H, 3I, 3J, 3K, 3L, and 3M only show the manufacturing process of one semiconductor package. For simplicity, Figure 3G and 3N Only the manufacturing process of two semiconductor packages being singulated is shown. The number of semiconductor packages manufactured from a wafer may vary. Process 200 may start from step 202 .

[0041] In step 202, now refer to Figure 3A , providing a device wafer 302. The device wafer 302 includes a semiconductor substrate 320 on which a plurality of semiconductor devices are formed. Each semiconductor device may have a plurality of contact pads 330 for providing a connection to an electrode of the semiconductor device. The plurality of contact pads 330 include a plurality of aluminum pads 332 exposed from a plurality of openings of a passivation layer 334. The plurality of aluminum pads 332 are disposed at a front surface 322 of the semiconductor substrate 320. The passivation layer 334 has a thickness of less than 10 microns, is located above the plurality of aluminum pads 332, and is patterned to form a plurality of openings exposing a middle portion of the plurality of aluminum pads 332. The semiconductor substrate 320 has a front surface 322 and a rear surface 324 opposite to the front surface 322 of the semiconductor substrate 320. The plurality of contact pads 330 are attached to the front surface 322 of the semiconductor substrate 320. Step 202 may be followed by step 204.

[0042] In step 204, now refer to Figure 3B As shown, the first carrier 340 is bonded to the plurality of contact pads 330 of the device wafer 302 by the release layer 341 and the adhesive layer 343. In the example of the present disclosure, the adhesive layer 343 is transparent. The adhesive layer 343 surrounds and protects the plurality of contact pads 330. In one example, the first carrier 340 is composed of a metal material. In another example, the first carrier 340 is composed of a glass material. The attachment of the first carrier 340 will increase the strength of the device wafer 302, thereby reducing the warpage during the subsequent processing steps. In the example of the present disclosure, step 204 is a bonding process, including a thermal curing process or an ultraviolet (UV) curing process in a bonding machine. Since the front surface of the device wafer 302 has not yet formed a large groove and a bump, only the thickness of the passivation layer 334 and the height difference between the aluminum pad 332 is less than 10 microns, and the front surface of the device wafer 302 is relatively smooth, so that the total thickness variation (TTV) of the bonding can be less than 3 microns. Step 204 may be followed by step 206.

[0043] In step 206, refer to Figure 3C , a thinning process is applied on the back surface 324 of the semiconductor substrate 320 to form a thinned semiconductor substrate 321. In the example of the present disclosure, the thickness of the thinned semiconductor substrate 321 is in the range of 15 microns to 35 microns, and a good consistency of total thickness variation (TTV) of less than 3 microns is maintained. The thinning process may include back grinding and back etching. Step 206 may be followed by step 208.

[0044] In step 208, refer to Figure 3D, a metal layer 380 is formed on the back side of the thinned semiconductor substrate 321. In an example of the present disclosure, the thickness of the metal layer 380 can be up to 30 microns or more. In one example, the metal layer 380 includes copper formed by electrochemical plating. In another example, the metal layer 380 includes silver or solder formed by electrochemical plating. In the present embodiment, the cross-section of the metal layer 380 is rectangular. In one example, the metal layer 380 is a titanium copper layer (TiCu) with a thickness in the range of 1 micron to 30 microns. In another example, the metal layer 380 is a titanium nickel silver (TiNiAg) with a thickness in the range of 1 micron to 30 microns. Step 208 may be followed by step 210.

[0045] In step 210, referring to Figure 3E , a first tape 381 is attached to the back side of the metal layer 380. In an example of the present disclosure, the first tape 381 is a double-sided tape that is heat-cured or UV-cured. Step 210 may be followed by step 212.

[0046] In step 212, refer to Figure 3F , removing the first carrier 340 so that the top surface 331 of the plurality of contact pads 330 is exposed. In the example of the present disclosure, step 212 is a debonding process by applying a laser irradiation process. Step 212 may be followed by step 214.

[0047] In step 214, reference Figure 3G , a first segmentation process 391 is applied to form a plurality of intermediate devices 373 including a plurality of segmented semiconductor substrates 325 and a plurality of segmented metal layers 385. Step 214 may be followed by step 216.

[0048] In step 216, refer to Figure 3H , removing the adhesive force of the first tape 381 so that the bottom surface 387 of the plurality of singulated metal layers 385 can be separated from the first tape 381. In an example of the present disclosure, the first tape 381 loses its adhesive force at high temperatures (greater than 150 degrees Celsius). Step 216 may be followed by step 218.

[0049] In step 218, if Fig. 3I As shown, the plurality of intermediate devices 373 are flipped and transferred to the second carrier 342, so that the plurality of contact pads 330 are located at the bottom, and are attached to the second carrier 342 through the double-sided adhesive layer 337. The plurality of intermediate devices 373 are attached to the second carrier 342 at a predetermined interval. In an example of the present disclosure, the second carrier 342 is made of a glass material. Step 218 may be followed by step 220.

[0050] In step 220, refer to Figure 3J, forming a molded package 390 to fill the predetermined spacing between adjacent intermediate devices 373 and cover the metal layer 385 of the back side of the plurality of intermediate devices 373 with a predetermined thickness, forming a molded wafer. The molded package 390 directly contacts the side surfaces 329 of the plurality of segmented semiconductor substrates 325, the side surfaces 389 of the plurality of segmented metal layers 385, and the rear surfaces 383 of the plurality of segmented metal layers 385. The molded package 390 prevents the rear surfaces 383 of the plurality of isolated metal layers 385 from oxidation, and the silver fragments that may be generated by the metal layer 385 during the segmentation process are encapsulated by the molded package 390 to suppress the reliability failure of the device caused by silver migration. The molded package 390 also directly contacts the side surfaces 333 of the passivation layer 334 at all edges of each intermediate device 373. In the example of the present disclosure, the CTE of the molded package 390 is less than 7ppm / °C, and the Tg of the molded package 190 is greater than 150 degrees Celsius. Step 220 may be followed by step 222.

[0051] In step 222, refer to Figure 3K , remove the second carrier 342. The openings between the passivation layer 334 are not filled by the molded package 390. The second carrier 342 can be removed by a debonding process. The top surface 331 of the plurality of contact pads 330 is exposed. The wafer is then flipped again so that the plurality of contact pads 330 are located at the top. Step 222 may be followed by step 224.

[0052] In step 224, refer to Figure 3L , a plurality of metal bumps 360 are formed on the top surface 331 of the plurality of contact pads 330. The plurality of metal bumps 360 connect the plurality of corresponding aluminum pads. In an example of the present disclosure, each of the plurality of metal bumps 360 is columnar. In an example of the present disclosure, each of the plurality of metal bumps 360 includes a corresponding 20-100 micron high copper portion 362 and a corresponding 15-30 micron high tin-silver portion 364 above the corresponding copper portion 362. The bottom surface of the plurality of metal bumps 360 and the top surface of the plurality of aluminum pads 332 are coplanar. The molding package step 224 may be followed by step 226.

[0053] In step 226, if Figure 3M As shown, a second tape 382 is attached. Step 226 may be followed by step 228.

[0054] In step 228, refer to Figure 3N , applying a second singulation process 398 and peeling off from the second tape 382 to form a plurality of semiconductor packages 399. Figure 3NTwo semiconductor packages are shown in the cross-sectional view of FIG. 1 , but the present invention is not limited thereto, and the number of semiconductor packages may vary. In one example, the separation process is a laser cutting process. In another example, the separation process is a saw blade cutting process.

[0055] In an example of the present disclosure, each of the plurality of semiconductor packages 399 is a common drain metal oxide semiconductor field effect transistor (MOSFET) chip scale package (CSP) for battery protection applications. In an example of the present disclosure, two gates and a plurality of sources are located on the front surface of the common drain MOSFET CSP. The common drain is located on the back side of the common drain MOSFET CSP.

[0056] Figure 4 is a flow chart of a process 400 for developing a plurality of semiconductor packages in an example of the present disclosure. Figure 5A , 5B , 5C, 5D, 5E, 5F, 5G and 5H show Figure 4 400. For simplicity, Figure 5A , 5B , 5C, 5D, 5E, 5F and 5G each illustrate only one manufacturing process of a semiconductor package. Figure 5H Only the manufacturing process of two semiconductor packages being singulated is shown. The number of semiconductor packages manufactured from a wafer may vary. Process 400 may begin at step 402.

[0057] In step 402, refer to Figure 5A , providing a device wafer 502. The device wafer 502 includes a semiconductor substrate 520 on which a plurality of semiconductor devices are formed. Each semiconductor device may have a plurality of contact pads 530 for providing connection to electrodes of the semiconductor device. The plurality of contact pads 530 include a plurality of aluminum pads 532 exposed from a plurality of openings of a passivation layer 534. The plurality of aluminum pads 532 are disposed at a front surface 522 of the semiconductor substrate 520. The passivation layer 534 has a thickness of less than 10 microns, is located above the plurality of aluminum pads 532, and is patterned to form a plurality of openings exposing a middle portion of the plurality of aluminum pads 332. The semiconductor substrate 520 has a front surface 522 and a rear surface 524 opposite to the front surface 522 of the semiconductor substrate 520. The plurality of contact pads 530 are attached to the front surface 522 of the semiconductor substrate 520. Step 404 may be followed by step 402.

[0058] In step 404, if Figure 5BAs shown, the carrier 540 is bonded to the plurality of contact pads 530 of the device wafer 502 by the release layer 541 and the adhesive layer 543. In the example of the present disclosure, the adhesive layer 543 is transparent. The adhesive layer 543 surrounds and protects the plurality of contact pads 530. In one example, the carrier 540 is composed of a metal material. In another example, the carrier 540 is composed of a glass material. The attachment of the carrier 540 will increase the strength of the device wafer 502, thereby reducing the warpage during the subsequent processing steps. In the example of the present disclosure, step 404 is a bonding process, including a thermal curing process or a UV curing process in a bonding machine. Since the front surface of the device wafer 502 has not yet formed a large groove and a bump, the front surface of the device wafer 502 is relatively smooth, and only the thickness of the passivation layer 534 and the height difference between the aluminum pad 532 is less than 10 microns, so that the total bonding thickness variation TTV can be less than 3 microns. Step 404 may be followed by step 406.

[0059] In step 406, now refer to Figure 4 . Reference Figure 5C , a thinning process is applied on the back surface 524 of the semiconductor substrate 520 to form a thinned semiconductor substrate 521. In the example of the present disclosure, the thickness of the thinned semiconductor substrate 521 is in the range of 15 microns to 35 microns, and a good consistency of a total thickness variation TTV of less than 3 microns is maintained. The thinning process may include back grinding and back etching. Step 406 may be followed by step 408.

[0060] In step 408, refer to Figure 5D , a metal layer 580 is formed on the back side of the thinned semiconductor substrate 521. In an example of the present disclosure, the thickness of each metal layer 580 is less than 10 microns. In one example, the metal layer 580 includes copper formed by electrochemical plating. In another example, the metal layer 580 includes silver or solder formed by electrochemical plating. In this embodiment, the cross-section of the metal layer 580 is rectangular. Step 408 may be followed by step 410.

[0061] In step 410, if Figure 5E As shown, the wafer is flipped so that the carrier 540 is at the bottom. A molded package 590 is formed on the back of the metal layer 580. The molded package 590 directly contacts the rear surface 583 of the metal layer 585. The molded package 590 prevents the rear surface 583 of the metal layer 585 from oxidizing. In an example of the present disclosure, the CTE of the molded package 590 is less than 7ppm / °C and the Tg of the molded package 590 is greater than 150 degrees Celsius. Step 410 may be followed by step 412.

[0062] In step 412, if Fig. 5FAs shown, the wafer is flipped again so that the molded package 590 is at the bottom. The carrier 540 is removed so that the top surface 531 of the plurality of contact pads 530 is exposed. In an example of the present disclosure, step 412 is a debonding process by applying a laser irradiation process. Step 412 may be followed by step 414.

[0063] In step 414, refer to Figure 5G , forming a plurality of metal bumps 560 on the plurality of aluminum pads. In an example of the present disclosure, each of the plurality of metal bumps 560 is columnar. In an example of the present disclosure, each of the plurality of metal bumps 560 includes a corresponding 20-100 micron copper portion 562 and a corresponding 15-30 micron tin-silver portion 564 above the corresponding copper portion 562. The bottom surface of the plurality of metal bumps 560 and the top surface aluminum pads of the plurality of aluminum pads 542 are coplanar. Step 414 may be followed by step 416.

[0064] In step 416, reference is now made to Figure 4 . Reference Figure 5H , a singulation process 598 is applied to form a plurality of semiconductor packages 599. Figure 5H Two semiconductor packages are shown in the cross-sectional view of FIG. , but the present invention is not limited thereto. Figure 5H As shown, the number of semiconductor packages can vary. In one example, the singulation process is a laser cutting process. In another example, the singulation process is a saw blade cutting process.

[0065] In an example of the present disclosure, each of the plurality of semiconductor packages 599 is a common drain metal oxide semiconductor field effect transistor (MOSFET) chip scale package (CSP) for battery protection applications. In an example of the present disclosure, two gates and a plurality of sources are located on the front surface of the common drain MOSFET CSP. The common drain is located on the back side of the common drain MOSFET CSP.

[0066] Those skilled in the art will recognize that modifications to the embodiments disclosed herein are possible. For example, the total number of the plurality of contact pads 330 may vary. Other modifications may occur to those skilled in the art, and all such modifications are considered to fall within the scope of the invention as defined in the claims.

Claims

1. A semiconductor package, characterized in that: include: a semiconductor substrate having a plurality of side surfaces, a front surface, and a rear surface opposite to the front surface of the semiconductor substrate; Multiple contact pads, including: A plurality of aluminum pads are disposed on the front surface of the semiconductor substrate; and A plurality of openings of a passivation layer are located above the plurality of aluminum pads; A plurality of metal bumps are located over the plurality of aluminum pads; a metal layer having a plurality of side surfaces, a front surface, and a rear surface opposite the front surface of the metal layer, the front surface of the metal layer being directly attached to the rear surface of the semiconductor substrate; and The molded package directly contacts the back side of the semiconductor substrate; Wherein, the thickness of the semiconductor substrate is less than 35 micrometers; and The height of the metal bump is at least 35 microns.

2. The semiconductor package according to claim 1, wherein: The thickness of the metal layer is greater than 10 micrometers, and the molded package directly contacts multiple side surfaces of the semiconductor substrate and multiple side surfaces of the metal layer.

3. The semiconductor package according to claim 2, wherein: The molded package also directly contacts a plurality of side surfaces of the passivation layer located at edges of the semiconductor substrate.

4. The semiconductor package according to claim 1, wherein: Each of the plurality of metal bumps includes a corresponding copper portion and a corresponding tin-silver portion over the corresponding copper portion.

5. The semiconductor package according to claim 1, wherein: Bottom surfaces of the plurality of metal bumps and top surfaces of the plurality of aluminum pads are coplanar.

6. The semiconductor package according to claim 1, wherein: The thickness of the metal layer is less than 10 micrometers, and multiple side surfaces of the semiconductor substrate and multiple side surfaces of the metal layer are not covered by the molded package.

7. A method for manufacturing a plurality of semiconductor packages, characterized in that: The method comprises the following steps: A device wafer is provided, wherein the device wafer comprises: a semiconductor substrate having a front surface and a rear surface opposite to the front surface of the semiconductor substrate; and a plurality of contact pads attached to the front surface of the semiconductor substrate; bonding a plurality of contact pads of the device wafer to a first carrier via a release layer and an adhesive layer; Thinning the back side of the semiconductor substrate to form a thinned semiconductor substrate; forming a metal layer on the back side of the thinned semiconductor substrate; removing the first carrier; Applying a first segmentation process to form a plurality of intermediate devices including a plurality of segmented semiconductor substrates and a plurality of segmented metal layers; transferring the plurality of intermediate devices to a second carrier; forming a molded package directly contacting side surfaces of the plurality of segmented semiconductor substrates, side surfaces of the plurality of segmented metal layers, and back surfaces of the plurality of segmented metal layers; removing the second carrier; forming a plurality of metal bumps; and Applying a second segmentation process to form a plurality of semiconductor packages; Wherein, the thickness of the semiconductor substrate after thinning is 15 micrometers to 35 micrometers; and Each of the plurality of metal bumps has a thickness of at least 35 micrometers.

8. The method according to claim 7, characterized in that The total thickness variation TTV of the semiconductor substrate after thinning is less than 3 microns.

9. The method according to claim 7, characterized in that: Each of the plurality of metal bumps includes a corresponding copper portion and a corresponding tin-silver portion over the corresponding copper portion.

10. The method according to claim 7, characterized in that The plurality of contact pads include: A plurality of aluminum pads are exposed from a plurality of openings in a passivation layer located above the aluminum pads; The bottom surfaces of the plurality of metal bumps are coplanar with the top surfaces of the plurality of aluminum pads.

11. The method according to claim 10, characterized in that The molded package also directly contacts the plurality of side surfaces of the passivation layer located at the edge of the semiconductor substrate.

12. A method for manufacturing a plurality of semiconductor packages, characterized in that: The method comprises the following steps: A device wafer is provided, wherein the device wafer comprises: a semiconductor substrate having a front surface and a rear surface opposite to the front surface of the semiconductor substrate; and a plurality of contact pads attached to the front surface of the semiconductor substrate; bonding a plurality of contact pads of the device wafer to a carrier via a release layer and an adhesive layer; Performing a thinning process on the back side of the semiconductor substrate to form a thinned semiconductor substrate; forming a metal layer on the back side of the thinned semiconductor substrate; forming a molded package directly contacting the back side of the metal layer; Remove the carrier; forming a plurality of metal bumps; and Applying a singulation process to form a plurality of semiconductor packages; Wherein, the thickness of the semiconductor substrate after thinning is 15 micrometers to 35 micrometers; and Each of the plurality of metal bumps has a thickness of at least 35 micrometers.

13. The method according to claim 12, characterized in that The total thickness variation TTV of the semiconductor substrate after thinning is less than 3 microns.

14. The method according to claim 12, characterized in that The thickness of the metal layer formed on the back side of the thinned semiconductor substrate is less than 10 microns.

15. The method according to claim 12, characterized in that Each of the plurality of metal bumps includes a corresponding copper portion and a corresponding tin-silver portion over the corresponding copper portion.

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