Integrated circuit (IC) structure and method of forming same

Abstract

The IC structure includes: a front-side interconnect structure on a front side of the device layer, the front-side interconnect structure including a first metal feature and a second metal feature isolated from each other by the IMD layer and embedded in the IMD layer, the first metal feature being electrically connected to the transistor device and the second metal feature being electrically isolated from the transistor device; and a backside interconnect structure on a backside of the device layer, the backside interconnect structure including a third metal feature and a fourth metal feature isolated from each other by the backside IMD layer and embedded in the backside IMD layer, the third metal feature being electrically connected to the transistor device, and the fourth metal feature being electrically isolated from the transistor device. The IC structure also includes a heat spreader layer having a thermally conductive and electrically insulating material on the backside of the backside interconnect structure. The embodiment of the invention also relates to an integrated circuit (IC) structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit (IC) structures and methods of forming the same. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can simultaneously support more increasingly complex and sophisticated functions. In order to meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance and low-power ICs. To date, these goals have been achieved to a large extent by reducing IC size (e.g., minimum IC component size), thereby improving production efficiency and reducing associated costs. However, such scaling also increases the complexity of IC manufacturing processes. Therefore, achieving continuous progress in IC devices and their performance requires similar progress in IC manufacturing processes and technologies.

[0003] As technology nodes become smaller, signal and power connections can be routed to the back side of the circuit structure for power and chip spacing optimization. In these examples, after forming the front side IC components, the device substrate of the circuit structure is thinned downward from the back side to prepare for forming the back side IC components. The device substrate can be partially or completely removed. However, removing the device substrate makes the IC circuit have poor heat dissipation, which may lead to higher temperatures that reduce device performance. The device substrate previously provided a thermal path to absorb the heat generated by the transistor device. Due to the downward thinning of the device substrate, more heat may be gathered in the device area, generating hot spots that may cause device breakdown due to self-heating.

[0004] Thus, while existing IC structures having backside components for signal and power connections are generally adequate for their intended purposes, they are not completely satisfactory in every respect. Summary of the invention

[0005] Some embodiments of the present application provide an integrated circuit structure, comprising: a device layer having a transistor device, the transistor device having a channel region located between source / drain regions and a gate stack located above the channel region; a front-side interconnect structure located on the front side of the device layer, wherein the front-side interconnect structure comprises a first metal component and a second metal component embedded in an intermetallic dielectric layer, the first metal component and the second metal component are isolated from each other by the intermetallic dielectric layer, the first metal component is electrically connected to the source / drain region or the gate stack of the transistor device, and the second metal component is electrically connected to the source / drain region or the gate stack of the transistor device, and the second metal component is electrically connected to the source / drain region or the gate stack of the transistor device. a back-side interconnect structure located on the back side of the device layer, wherein the back-side interconnect structure includes a third metal component and a fourth metal component embedded in a back-side intermetallic dielectric layer, the third metal component and the fourth metal component are isolated from each other by the back-side intermetallic dielectric layer, the third metal component is electrically connected to a source / drain region or a gate stack of the transistor device, and the fourth metal component is electrically isolated from the transistor device; and a heat sink layer located on the back side of the back-side interconnect structure, wherein the heat sink layer is made of a heat sink material that is thermally conductive and electrically insulating.

[0006] Still other embodiments of the present application provide an integrated circuit structure, comprising: a device layer having a transistor device, the transistor device having a channel region located between source / drain regions and a gate stack located above the channel region; a front-side interconnect structure located on the front side of the device layer, wherein the front-side interconnect structure comprises a first metal component and a second metal component embedded in an intermetallic dielectric layer, the first metal component and the second metal component being isolated from each other by the intermetallic dielectric layer, the first metal component being electrically connected to the source / drain region or the gate stack of the transistor device, and the second metal component being electrically isolated from the transistor device; a bonding oxide layer located above the front-side interconnect structure; and a substrate located above the bonding oxide layer.

[0007] Some other embodiments of the present application provide a method for forming an integrated circuit structure, comprising: forming transistor devices in a device layer above a device substrate, each transistor device having a channel region located between the source / drain regions and a gate stack located above the channel region; forming a device-level contact electrically coupled to the source / drain region and the gate stack of the transistor device above the source / drain region and the gate stack of the transistor device; forming a front-side interconnect structure above the device-level contact, the front-side interconnect structure having an electrical metal line, a vertically coupled The invention relates to a method of manufacturing a heat sink layer on the back side of the device layer, wherein the heat sink layer is made of a heat conducting and electrically insulating heat sink material. The method comprises the steps of: forming an electrical via between the electrical metal lines and the electrical vias electrically isolated from the electrical metal lines and the electrical vias; bonding a substrate to a top surface of the front-side interconnect structure; thinning the device substrate downward from the back side of the device layer; forming a back-side interconnect structure on the back side of the device layer, the back-side interconnect structure having back-side electrical metal lines, back-side electrical vias vertically coupled between the back-side electrical metal lines, and back-side thermal vias electrically isolated from the back-side electrical metal lines and the electrical vias; and forming a heat sink layer on the back side of the back-side interconnect structure, wherein the heat sink layer is made of a heat conducting and electrically insulating heat sink material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion. It is also emphasized that the accompanying drawings illustrate only typical embodiments of the disclosed embodiments and, therefore, should not be considered as limiting the scope, as the disclosed embodiments may be equally well adapted to other embodiments. In addition, the accompanying drawings may implicitly describe components that are not explicitly described in the detailed description.

[0009] Figure 1 A cross-sectional view of an integrated circuit (IC) structure with thermal vias and a heat spreader layer according to an embodiment of the present disclosure is shown.

[0010] Figure 2A A cross-sectional view of an IC structure with floating thermal vias according to an embodiment of the present disclosure is shown.

[0011] Figure 2B Cross-sectional views of IC structures with floating and non-floating thermal vias are shown according to embodiments of the present disclosure.

[0012] Figure 3A A cross-sectional view of an IC structure with floating thermal vias and a heat spreader layer according to an embodiment of the present disclosure is shown.

[0013] Figure 3BA cross-sectional view of an IC structure with floating thermal vias and a heat spreader layer according to another embodiment of the present disclosure is shown.

[0014] Figure 4A A cross-sectional view of an IC structure with floating and non-floating thermal vias and a heat spreader layer according to an embodiment of the present disclosure is shown.

[0015] Figure 4B A cross-sectional view of an IC structure with floating and non-floating thermal vias and a heat spreader layer according to another embodiment of the present disclosure is shown.

[0016] Figure 5 A top view of an IC chip having circuit areas with thermal vias of different shapes and size configurations according to an embodiment of the present disclosure is shown.

[0017] Fig. 6A , Fig. 7A and Fig. 8A A top view of a front-side interconnect structure in a circuit area of ​​an IC chip according to various embodiments of the present disclosure is shown.

[0018] Figure 6B , Figure 7B and Figure 8B A top view of a backside interconnect structure in a circuit area of ​​an IC chip according to various embodiments of the present disclosure is shown.

[0019] Fig. 9 A flow chart of a method of forming an IC structure with thermal vias and a heat spreader layer according to an embodiment of the present disclosure is shown.

[0020] Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 The embodiment of the present disclosure is shown in the intermediate stage of manufacturing. Fig. 9 The method processes an IC structure with thermal vias and a heat spreader layer.

[0021] Fig.15A , Fig. 15B and Fig. 15C A graph showing the thermal improvements that can be achieved with a heat sink and thermal vias is shown. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0024] In addition, when "about", "approximately", etc. are used to describe a numerical value or a range of numerical values, as understood by a person of ordinary skill in the art, the term is intended to cover numerical values ​​within a reasonable range taking into account the variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the numerical values, the numerical value or range of numerical values ​​covers a reasonable range including the described numerical value, such as within + / -10% of the described numerical value. For example, a material layer with a thickness of "about 5nm" may include a size range from 4.25nm to 5.75nm, where the manufacturing tolerance associated with the deposited material layer known to a person of ordinary skill in the art is + / -15%. In addition, the disclosed dimensions of different components may implicitly disclose the size ratios between the different components. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0025] The disclosed embodiments relate to integrated circuit (IC) structures having a backside power delivery network, and in particular to incorporating thermal vias and heat sink layers to reduce power consumption and improve power distribution. In contrast to IC structures having only a frontside power delivery network, IC structures having a backside power delivery network reduce the voltage drop from many metals in the frontside metal interconnects, thereby improving power delivery performance and allowing further standard cell height scaling. However, forming the backside power delivery network requires thinning down the original device substrate (e.g., to accommodate through vias (TSVs)), which results in higher temperatures that reduce device performance. The disclosed embodiments describe various solutions to reduce temperature and reduce device hot spots in IC structures having a backside power delivery network.

[0026] In various embodiments, the disclosed embodiments describe an IC structure (or IC chip) having a backside IC component formed on the backside of a transistor device layer. The backside IC component forms a backside power transmission network for transmitting power signals from the backside of the IC chip. The backside power transmission network reduces power dissipation and wiring congestion in the front side metal layer. The IC structure includes a heat sink layer (e.g., with diamond) and a thermal via (e.g., with copper or diamond) to effectively dissipate heat and reduce the hot spot temperature in the logic layer. The heat sink layer and the thermal via can be integrated in different parts of the IC structure, depending on the process requirements and to target the hot spot area of ​​the IC structure. The heat sink layer and the thermal via can be grown directly on the chip at low temperatures (less than 400 degrees Celsius) to be compatible with the back end of line (BEOL) process. This means that the heat sink layer and the thermal via do not need to withstand high temperature stress (greater than 900 degrees Celsius) during the front end of line (FEOL) process. In other words, the heat sink layer and thermal vias can be formed as part of one or more BEOL processes, so the high temperature stress during the FEOL process will not affect the formation of the heat sink layer and thermal vias. Therefore, there is greater freedom in selecting thermal materials for the heat sink layer and thermal vias. In addition, because the heat sink layer and thermal vias are formed at low temperatures, it will not affect the previously formed BEOL structure. FEOL generally refers to the part of the circuit that forms functional devices such as logic and memory devices. FEOL generally includes everything up to but not including the metal interconnect layer. These areas may include substrates, source / drain components, channel regions, gates, and device-level metal components (e.g., device-level contacts and vias). BEOL generally refers to circuit areas outside the FEOL. These areas may include metal interconnect layers, the back side of a substrate, or another wafer as part of a 3DIC structure.

[0027] Figure 1A cross-sectional view of an integrated circuit (IC) structure 100 according to an embodiment of the present disclosure is shown. The IC structure 100 may be an IC package mounted on a printed circuit board (PCB). As shown, the IC structure 100 includes a device layer 200 sandwiched between various IC layers and components. The device layer 200 is a location where device-level components such as transistor devices are formed. The transistor device may be a logic device, a memory device, etc. Each of the transistor devices includes a channel region between source / drain (S / D) regions and a gate stack above the channel region. The device layer 200 may also include other device-level components, such as S / D contacts, S / D vias, gate contacts, and / or gate vias, each of which may electrically connect the S / D region and / or the gate stack to a higher material layer of the IC structure 100. In an embodiment, the device layer 200 has a thickness between about 0.05 μm and about 0.5 μm. In an embodiment, the device layer 200 has a thermal conductivity k between about 10 W / m / K and about 100 W / m / K in the x and y directions. x / k y , and has a thermal conductivity k between about 10 W / m / K and about 100 W / m / K in the z direction z .

[0028] Still reference Figure 1 , on the front side of the device layer 200, the IC structure 100 includes a front side interconnect structure 300 above the device layer 200, a bonding layer 500 above the front side interconnect structure 300, a carrier substrate 502 above the bonding layer 500, a thermal interface material (TIM) layer 504 above the carrier substrate 502, and a top cover 506 above the TIM layer 504.

[0029] The front side interconnect structure 300 includes one or more thermal vias 112 embedded in the front side intermetallic dielectric (IMD) layer 302. As shown, the thermal vias 112 can vertically span the entire height of the front side interconnect structure 300, with one end directly contacting the device layer 200 and an opposite end directly contacting the bonding layer 500. The thermal vias 112 are not electrically connected to any transistor device in the device layer 200. Instead, they are used as heat diffusion components embedded in the front side IMD layer 302. To this end, they are used to capture heat and to transfer heat away from hot spots. The front side IMD layer 302 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable dielectric materials. In an embodiment, the front side interconnect structure 300 has a thickness between about 0.5 μm and about 2 μm. In an embodiment, the front side interconnect structure 300 has a thermal conductivity k between about 1 W / m / K and about 15 W / m / K in the x and y directions. x / k y, and has a thermal conductivity k in the z direction between about 0.1 W / m / K and about 1 W / m / K z .

[0030] The bonding layer 500 may be a metal bonding layer, an oxide bonding layer, or a bonding layer having a mixture of metal and oxide. In any case, the bonding layer 500 bonds the top surface of the front-side interconnect structure 300 to the carrier substrate 502. In an embodiment, the bonding layer 500 has a thickness between about 0.1 μm and about 0.5 μm. In an embodiment, the bonding layer 500 has a thermal conductivity k between about 0.5 W / m / K and about 2 W / m / K in the x and y directions. x / k y , and has a thermal conductivity k in the z direction between about 0.5 W / m / K and about 5 W / m / K z .

[0031] The carrier substrate 502 provides structural support in preparation for backside processing. The carrier substrate 502 may include silicon (Si) or other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe) or diamond. In the present embodiment, the carrier substrate 502 is made of silicon. In an embodiment, the carrier substrate 502 has a thickness between about 350 μm and about 450 μm, and exhibits a thermal conductivity k between about 100 W / m / K and about 150 W / m / K. It should be noted that in the present embodiment, even after the backside processing, the carrier substrate 502 remains in the IC structure 100. The carrier substrate 502 remains for structural support purposes and is also used as a heat sink. Then, the TIM layer 504 and the top cover 506 are formed above the carrier substrate 502.

[0032] The TIM layer 504 is disposed above the carrier substrate 502 and can be used as a thermal conductor and heat distributor on the front side of the workpiece to more evenly direct heat away from the IC structure 100 (e.g., via the top cover 506). The TIM layer 504 can also be used as a protective film to block moisture from outside the IC structure 100. The TIM layer 504 can include a polymer, resin, or epoxy resin as a base material and a filler to improve its thermal conductivity. The filler may include a dielectric filler such as aluminum oxide, magnesium oxide, aluminum nitride, boron nitride, and diamond powder. Optionally, the filler may include a metal filler such as silver, copper, aluminum, etc. In an embodiment, the TIM layer 504 has a thickness between about 50 μm and about 100 μm. In an embodiment, the TIM layer 504 has a thermal conductivity k between about 1 W / m / K and about 10 W / m / K in the x and y directions. x / k y , and has a thermal conductivity k in the z direction between about 1 W / m / K and about 10 W / m / K z .

[0033] A top cover 506 is disposed above the TIM layer 504. The top cover 506 may be a metal cap used as a cap for the IC structure 100. In an embodiment, the top cover 506 covers not only the top surface of the IC workpiece, but also the sides of the IC workpiece. In addition to being used as a cap, the top cover 506 also serves as a heat sink to absorb any heat emitted from the components of the IC structure 100. The top cover 506 is formed of a metal or a metal alloy having a high thermal conductivity, for example, greater than about 100 W / m / K. For example, the top cover 506 may be formed of a metal or a metal alloy selected from Al, Cu, Ni, Co, stainless steel, and alloys thereof. In an embodiment, the top cover 506 has a thickness between about 450 μm and about 550 μm, and exhibits a thermal conductivity k between about 350 W / m / K and about 400 W / m / K.

[0034] Still reference Figure 1 , on the back side of the device layer 200, the IC structure 100 includes a back side interconnect structure 400 below the device layer 200, a heat sink layer 600 below the back side interconnect structure 400, an aluminum bonding pad (AP) layer 602 below the heat sink layer 600, a controlled collapse chip connection (C4) layer 604 below the AP layer 602, a packaging substrate 606 below the C4 layer 604, a ball grid array (BGA) structure 608 below the packaging substrate 606, and a printed circuit board (PCB) 610 below the BGA structure 608.

[0035] The backside interconnect structure 400 includes one or more thermal vias 112 embedded in the backside IMD layer 402. As shown, the thermal vias 112 can vertically span the entire height of the backside interconnect structure 400, with one end directly contacting the back side of the device layer 200 and an opposite end directly contacting the top surface of the heat sink layer 600. The thermal vias 112 are not electrically connected to any transistor device in the device layer 200. Instead, they serve as heat sinks embedded in the backside IMD layer 402. The backside IMD layer 402 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable dielectric materials. In an embodiment, the backside interconnect structure 400 has a thickness between about 1 μm and about 2 μm. In an embodiment, the backside interconnect structure 400 has a thermal conductivity kx / ky between about 1 W / m / K and about 15 W / m / K in the x and y directions, and a thermal conductivity kx / ky between about 10 W / m / K and about 20 W / m / K in the z direction. z .

[0036] Although Figure 1Thermal vias 112 are shown in both the frontside IMD layer 302 and the backside IMD layer 402 , but the disclosed embodiments are not limited thereto. For example, thermal vias 112 may be located only in the frontside IMD layer 302 or only in the backside IMD layer 402 , depending on design considerations.

[0037] The heat sink layer 600 is disposed on the back side of the device layer 200. Figure 1 In the embodiment of the present invention, the heat sink layer 600 is disposed between the backside interconnect structure 400 and the AP layer 602, however, the heat sink layer 600 may alternatively be disposed between the AP layer 602 and the C4 layer 604 (see, for example, Figure 3B and Figure 4B ). In other words, the heat sink layer 600 can be disposed directly below the backside interconnect structure 400 or directly below the AP layer 602, depending on the process requirements. The heat sink layer can span the entire size of the IC chip, or it can be limited to certain parts of the chip. The heat sink layer 600 is made of a heat sink material that is thermally conductive and electrically insulating. The thermal conductivity k for the heat sink material should be between about 10 and 500 W / m / K for absorbing heat dissipation. The resistivity p of the heat sink material should be greater than 108 Ωm for isolating electrical signals (e.g., at 10 10 Ωm and 10 16 Ωm). For example, the heat spreader layer 600 may include a material such as diamond, AlN, BN, Al2O3, BeO, or a combination thereof. In an embodiment, the heat spreader layer has a thickness between about 0.1 μm and about 50 μm.

[0038] The AP layer 602 is disposed on the back side of the heat sink layer 600 (or optionally on the back side of the backside interconnect structure 400). The AP layer 602 includes aluminum bonding pads electrically connected to electrical metal lines of the backside interconnect structure 400. The aluminum bonding pads can be contact areas of a chip / die configured to connect to other chips / dies. The AP layer 602 can be part of a redistribution layer (RDL) structure. The RDL structure may include redistribution wiring embedded in one or more passivation layers. The redistribution wiring can route metal lines of the backside interconnect structure 400 to the aluminum bonding pads of the AP layer 602. In an embodiment, the AP layer 602 has a thickness between about 2 μm and about 3.5 μm. In an embodiment, the AP layer 602 has a thermal conductivity k between about 10 W / m / K and about 20 W / m / K in the x and y directions. x / k y , and has a thermal conductivity k between about 100 W / m / K and about 150 W / m / K in the z direction z .

[0039] The C4 layer 604 is disposed on the back side of the AP layer 602 (or optionally on the back side of the heat sink layer 600). The C4 layer 604 includes interconnect bumps, such as solder bumps or copper pillar (CuP) bumps. The solder bumps may include tin, lead and / or silver, and the CuP bumps may include copper pillars with solder caps at the ends. The solder caps may be made of tin, lead and / or silver. The interconnect bumps are used as a tool for connecting a chip / die to another chip / die that is part of an IC package. The interconnect bumps are bonded to the aluminum bonding pads of the AP layer 602. In an embodiment, the C4 layer 604 has a thickness between about 40 μm and about 80 μm. In an embodiment, the C4 layer 604 has a thermal conductivity k between about 1 W / m / K and about 5 W / m / K in the x and y directions. x / k y , and has a thermal conductivity k in the z direction between about 5 W / m / K and about 10 W / m / K z .

[0040] The package substrate 606 is disposed on the back side of the C4 layer 604. The package substrate 606 generally refers to a wafer or semiconductor structure including package components such as other device chips, silicon interposers, dielectric substrates, etc. The package components are electrically connected to the aluminum pads in the AP layer 602 through the interconnect bumps of the C4 layer 604. In an embodiment, the package substrate 606 includes a semiconductor substrate formed of silicon, silicon germanium, silicon carbon, etc. In an embodiment, the package substrate 606 has a thickness between about 250 μm and about 350 μm. In an embodiment, the package substrate layer 606 has a thermal conductivity k between about 10 W / m / K and about 50 W / m / K in the x and y directions. x / k y , and has a thermal conductivity k in the z direction between about 0.5 W / m / K and about 2 W / m / K z .

[0041] The BGA structure 608 is disposed on the back side of the package substrate 606. The BGA structure 608 includes solder joints attached to the back side of the package substrate 606. The BGA structure 608 is configured to join the IC package to a larger circuit board. In an embodiment, the BGA structure 608 has a thickness between about 100 μm and about 200 μm. In an embodiment, the BGA structure 608 has a thermal conductivity k between about 0.1 W / m / K and about 1 W / m / K in the x and y directions. x / k y , and has a thermal conductivity k between about 50 W / m / K and about 100 W / m / K in the z direction z .

[0042] A printed circuit board (PCB) 610 is disposed on the back side of the BGA structure 608. The PCB 610 may include a plurality of other IC packages mounted thereon, thereby forming a processor, a controller, a memory unit, or other electronic components. In an embodiment, the PCB 610 has a thickness between about 900 μm and about 1100 μm. In an embodiment, the PCB 610 has a thermal conductivity k between about 10 W / m / K and about 100 W / m / K in the x and y directions. x / k y , and has a thermal conductivity k in the z direction between about 1 W / m / K and about 5 W / m / K z .

[0043] Still reference Figure 1 , the thermal vias 112 can vary in width (from about 100 nm to 10 μm) and thickness, depending on the density of metal features in the front side interconnect structure 300 / back side interconnect structure 400. The thermal vias 112 can be uniformly or non-uniformly distributed throughout the IC structure 100 and penetrate one or more of the metal layers of the front side interconnect structure 300 / back side interconnect structure 400. The size of the thermal vias 112 can vary from nm to μm, depending on the density of metal interconnects (e.g., metal lines) in the front side interconnect structure 300 and the back side interconnect structure 400. In some embodiments, the thermal vias 112 in the front side interconnect structure 300 / back side interconnect structure 400 have a larger width than the electrical vias that route circuit signals in the front side interconnect structure 300 / back side interconnect structure 400.

[0044] Figure 2A A cross-sectional view of an IC structure 100 having thermal vias 112 (and in particular floating thermal vias 112a) according to an embodiment of the present disclosure is shown. Figure 2A The IC structure 100 is similar to Figure 1 1 and similar components will not be described again for the sake of brevity. The difference is that there is no heat spreader layer 600, and additional details are shown with respect to the device layer 200, the front side interconnect structure 300, and the back side interconnect structure 400.

[0045] like Figure 2AAs shown in , the device layer 200 includes a transistor device 205. Each of the transistor devices 205 includes a channel region 204a located between the S / D regions 204b and a gate stack 208 disposed above the channel region 204a. The transistor device 205 can be a planar MOSFET, a FinFET, or a full-ring gate FET. In an embodiment, the channel region 204a and the S / D region 204b are formed in an active region above the device substrate 202 or as a part of the device substrate 202. The device substrate 202 may include silicon (Si) or other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. In the present embodiment, the device substrate 202 is made of silicon. As described later, the device substrate 202 may be partially or completely removed as a part of forming a backside IC component. An interlayer dielectric (ILD) layer 211 is disposed above the device substrate 202 and embeds device-level metal features 212, such as S / D contacts bonded to the S / D regions 204b and S / D vias bonded to the S / D contacts, and gate contacts bonded to the gate stack 208 and gate vias bonded to the gate contacts. The ILD layer 211 may include materials similar to the front-side IMD layer 302 and the back-side IMD layer 402. The device layer 200 may also include a buried rail 214 extending below the ILD layer 211 and penetrating the device substrate 202 to bond to a back-side electrical metal line 412 in the back-side interconnect structure 400. The buried rail 214 may be electrically connected to the S / D regions 204b and / or the gate stack 208 of the transistor device 205. In an embodiment, the buried rail 214 can be routed through the device layer 200 to a front-side power delivery network (e.g., to the electrical metal line 312), which is then connected from the front side to the S / D region 204b and / or the gate stack 208. In another embodiment, although not shown, the buried rail 214 can be used as a back-side via that directly contacts the S / D region 204b of the transistor device 205 from the back side, and the back-side via is bonded to the back-side electrical metal line 412 in the back-side interconnect structure 400.

[0046] Still reference Figure 2A, the front-side interconnect structure 300 includes an electrical metal line 312 and an electrical via 313. The electrical metal line 312 and the electrical via 313 are electrically connected to the S / D region 204b or the gate stack 208 of the transistor device 205. The electrical metal line 312 extends horizontally and longitudinally in each metal layer, and the electrical via 313 is vertically arranged between the electrical metal lines 312. The electrical via 313 is a cylinder or column that connects the metal line 312 between each metal layer. In an embodiment, the first electrical metal line 312 extends longitudinally along the x-direction and is bonded to one or more device-level metal features 212 (e.g., S / D vias or gate vias). The first electrical via 313 is bonded to the first electrical metal line 312 as a vertical interconnect to route the first electrical metal 312 to the second electrical metal line 312. The second electrical metal line 312 is bonded to the first electrical via 313 and can extend longitudinally along the y-direction. Additional electrical vias 313 and metal lines 312 may be similarly disposed over the second electrical metal line 312. In any case, the electrical metal line 312 extends beyond the sides of the electrical via 313 in either the x or y direction.

[0047] Still reference Figure 2A , the front-side interconnect structure 300 also includes a thermal via 112 electrically isolated from the S / D region 204b and the gate stack 208 of the transistor device 205. The thermal via 112 is used to dissipate heat and does not route any actual circuit signals from the transistor device 205. The thermal via 112, the electrical metal line 312, and the electrical via 313 are each embedded in the front-side IMD layer 302. The front-side IMD layer 302 can be multi-layered, each layer embedding a metal layer in the front-side interconnect structure 300. As shown, the thermal via 112 is isolated from the electrical metal line 312 and the electrical via 313 by the front-side IMD layer 302. Each of the thermal vias 112 has a greater height in the vertical z-direction than each of the electrical metal line 312 and the electrical via 313. The thermal via 112 is a vertical cylinder that does not have a lateral extension that exceeds its vertical side, and the thermal via 112 more than penetrates the metal layer of the front-side interconnect structure 300. In other words, the thermal vias 112 may extend and penetrate more than one layer of the front-side interconnect structure 300 (e.g., through multiple metal line layers), while the electrical vias 313 extend through only one layer to connect between electrical metal lines 312 of different metal line layers. Therefore, each of the thermal vias 112 spans a vertical height in the vertical direction that is at least greater than the height of the electrical via plus the height of the electrical metal line 312. In the present embodiment, the thermal vias 112 penetrate and span the entire vertical height of the front-side IMD layer 302.

[0048] Still reference Figure 2A, the thermal vias 112 only include floating thermal vias 112a. The floating thermal vias 112a refer to thermal vias 112 that are not only electrically isolated but also physically isolated from the electrical metal lines 312 and the electrical vias 313. That is, no part of the floating thermal vias 112a is in direct contact with the electrical metal lines 312 and the electrical vias 313. In an embodiment, the floating thermal vias 112a are completely surrounded by a dielectric material and directly contact the dielectric material (e.g., the front side IMD layer 302 on the side, the ILD layer 211 on the bottom surface, and the oxide bonding layer 500 on the top surface). In the present embodiment, each of the floating thermal vias 112a includes copper.

[0049] Still reference Figure 2A , the backside interconnect structure 400 includes a backside electrical metal line 412 and a backside electrical via 413. The backside electrical metal line 412 and the backside electrical via 413 are electrically connected to the S / D region 204b or the gate stack 208 of the transistor device 205. The backside electrical metal line 412 extends horizontally and longitudinally in each metal layer, and the backside electrical via 413 is vertically arranged between the backside electrical metal lines 412. The backside electrical via 413 is a cylinder or column connecting the backside electrical metal line 412 between each backside metal layer. In an embodiment, the first backside electrical metal line 412 extends longitudinally along the x-direction and is bonded to one or more buried rails 214 or backside vias (not shown) from the back side of the device substrate 202. The first backside electrical via 413 is bonded to the first backside electrical metal line 412 as a vertical interconnect to route the first backside electrical metal line 412 to the second backside electrical metal line 412. The second backside electrical metal line 412 is bonded to the first backside electrical via 413 and can extend longitudinally in the y-direction. Additional backside electrical vias 413 and backside electrical metal lines 412 can be similarly disposed above the second backside electrical metal line 412. In any case, the backside electrical metal line 412 extends beyond the sides of the backside electrical via 413 in the x or y direction. In some embodiments, as shown, there can be one or more feedthrough vias 216 penetrating the entire device layer 200 to interconnect between the electrical metal line 312 in the frontside interconnect structure 300 and the backside electrical metal line 412 in the backside interconnect structure 400.

[0050] Still reference Figure 2A, the backside interconnect structure 400 also includes a thermal via 112 electrically isolated from the S / D region 204b and the gate stack 208 of the transistor device 205. The thermal via 112, the backside electrical metal line 412, and the backside electrical via 413 are each embedded in the backside IMD layer 402. The backside IMD layer 402 can be multi-layered, each layer embedding a metal layer in the backside interconnect structure 400. As shown, the thermal via 112 is isolated from the backside electrical metal line 412 and the backside electrical via 413 by the backside IMD layer 402. Similar to the thermal via 112 in the frontside interconnect structure 300, each of the thermal vias 112 in the backside interconnect structure 400 has a greater height in the vertical z direction than each backside electrical metal line 412 and the backside electrical via 413. These thermal vias 112 are vertical cylinders that do not have a lateral extension beyond their vertical sides, and they more than penetrate the metal layer of the backside interconnect structure 400. In other words, the thermal vias 112 in the backside interconnect structure may extend and penetrate more than one layer of the backside interconnect structure 400 (e.g., through multiple metal line layers), while the backside electrical vias 413 only extend through one layer to connect between backside electrical metal lines 412 of different metal line layers. Therefore, each of the thermal vias 112 spans a vertical height in the vertical direction that is at least greater than the height of the backside electrical via 413 plus the height of the backside electrical metal line 412. In the present embodiment, the thermal vias 112 in the backside interconnect structure 400 penetrate and span the entire vertical height of the backside IMD layer 402.

[0051] Still reference Figure 2A , the thermal vias 112 in the backside interconnect structure 400 only include floating thermal vias 112a. The floating thermal vias 112a have been previously described and will not be described again for the sake of brevity. In an embodiment, the floating thermal vias 112a in the backside interconnect structure 400 are completely surrounded by dielectric material and directly contact the dielectric material.

[0052] Figure 2B A cross-sectional view of an IC structure 100 having thermal vias 112 (and in particular non-floating thermal vias 112 b ) according to an embodiment of the present disclosure is shown. Figure 2B The IC structure 100 is similar to Figure 2A For the sake of brevity, similar components will not be described again. The difference is that, except for the floating thermal via 112a, Figure 2BA plurality of non-floating thermal vias 112b are additionally shown. Non-floating thermal vias 112b refer to thermal vias 112, wherein at least one end of the non-floating thermal via 112b is directly in contact with and bonded to a metal line in the front-side interconnect structure 300 and / or the back-side interconnect structure 400 (e.g., bonded to an electrical metal line 312 or a back-side electrical metal line 412). The other end may not be in contact with any metal layer. Because the non-floating thermal vias 112b are bonded to metal lines in the front-side interconnect structure 300 and / or the back-side interconnect structure 400, they may have a smaller vertical height than the floating thermal vias 112a. For each of the non-floating thermal vias 112b, there is a metal portion and a thermal insulation portion. The thermal insulation portion is located at the end that is in direct contact with the metal line in the front-side interconnect structure 300 and / or the back-side interconnect structure 400, and the metal portion is located at the end that is not in direct contact with any metal line in the front-side interconnect structure 300 and / or the back-side interconnect structure 400. In an embodiment, the thermal insulation portion includes about 1 nm to 50 nm of an insulating material with high resistivity and high thermal conductivity (such as diamond nanoparticles, AlN, c-BN, Al2O3 or BeO). The resistivity p of the insulating material should be greater than 10 8 Ωm for isolating electrical signals (e.g., at 10 10 Ωm and 10 16 Ωm). The thermal conductivity k for the insulating material should be between about 10 and 500 W / m / K for absorbing heat dissipation. The thermal insulation portion separates the metal layer electrically connected to the transistor device 205 from the metal portion. The metal portion includes a material similar to the floating thermal via 112a (e.g., copper). The thermal insulation portion is included because the metal portion of the non-floating thermal via 112b should not be electrically connected to the electrical metal line 312 or the backside electrical metal line 412. Otherwise, unexpected signal routing will occur. In other words, an insulating material is needed to isolate the metal portion. It should be noted that in a further embodiment, both ends of the non-floating thermal via 112b can contact the metal line, and therefore both ends include insulating portions, while the middle portion is a metal portion.

[0053] Figure 3A A cross-sectional view of an IC structure 100 with floating thermal vias 112a and a heat spreader layer 600 is shown in accordance with an embodiment of the present disclosure. Figure 3A Similar to Figure 2A , and for the sake of brevity, similar components will not be described again. The difference is that, in addition to the floating thermal via 112a, Figure 3AAdditionally shown is a heat sink layer 600 between the backside interconnect structure 400 and the AP layer 602. In this configuration, the backside electrical metal lines 412 can be connected to the aluminum bond pads in the AP layer 602 through one or more vias 613. In this way, electrical signals can still pass through the heat sink layer 600. The heat sink layer 600 can be a layer with electrical and thermal via holes that allow metal / signal lines to pass through. However, it should be noted that while electrical via holes are required to route circuit signals, thermal via holes through the heat sink layer 600 may be optional. This is because the heat sink layer 600 may already have a high thermal conductivity, and therefore the thermal vias do not have to pass through the heat sink layer 600, and can simply be connected to it.

[0054] As shown, the top surface of the heat sink layer 600 can be in direct contact with the bottom surface of the floating thermal via 112a, the backside electrical metal line 412, and / or the backside electrical via 413. In an embodiment, the floating thermal via 112a can be bonded on the heat sink layer 600 without penetrating it. The IC structure 100 also includes a through hole 613 that penetrates the heat sink layer 600 to route the backside electrical metal line 412 to the aluminum bonding pad in the AP layer 602. In an embodiment (as shown), there can also be one or more floating thermal vias 112a passing through the heat sink layer 600, so that the heat sink layer 600 surrounds the floating thermal via 112a. It should be noted that the floating thermal via 112a is isolated from the through hole 613 by the electrical isolation material (e.g., diamond) of the heat sink layer 600. In an embodiment, one or more floating thermal vias 112a can span the entire vertical height of the backside interconnect structure 400 plus the entire vertical height of the heat sink layer 600. These floating thermal vias 112a may bond on a top surface of the AP layer 602 (eg, a passivation layer), but not on metal features in the AP layer (eg, aluminum bond pads and / or redistribution wiring).

[0055] Figure 3B A cross-sectional view of an IC structure 100 having a floating thermal via 112a and a heat spreader layer 600 according to another embodiment of the present disclosure is shown. Figure 3B Similar to Figure 3A, and for the sake of brevity, similar components will not be described again. The difference is that the heat sink layer 600 is disposed between the AP layer 602 and the C4 layer 604. In this case, the AP layer 602 is disposed on the back side of the backside interconnect structure 400, the heat sink layer 600 is disposed on the back side of the AP layer 602, and the C4 layer 604 is disposed on the back side of the heat sink layer 600. In this configuration, the aluminum bonding pads in the AP layer 602 can be connected to the C4 bumps in the C4 layer 604 through one or more vias 613. In this way, electrical signals can still pass through the heat sink layer 600. The heat sink layer 600 can be a layer with electrical and thermal via holes that allow metal / signal lines to pass through. However, it should be noted that while electrical via holes are required to route circuit signals, thermal via holes passing through the heat sink layer 600 and / or the AP layer 602 may be optional. This is because the heat spreader layer 600 and / or the AP layer 602 may already have high thermal conductivity, and therefore the thermal vias do not have to pass through these layers, but may simply connect to them.

[0056] As shown, the top surface of the heat spreader layer 600 can be in direct contact with the aluminum bonding pads in the AP layer 602, which are then electrically routed to the backside electrical metal lines 412. The top surface of the heat spreader layer 600 can also be in direct contact with the bottom surface of one or more floating thermal vias 112a. The IC structure 100 includes vias 613 that penetrate the heat spreader layer 600 to route the aluminum bonding pads in the AP layer 602 to the interconnect bumps in the C4 layer 604. In an embodiment, one or more of the floating thermal vias 112a can be bonded to the AP layer 602 without penetrating it to bond to the heat spreader layer 600. In an embodiment, one or more of the floating thermal vias 112a can penetrate the AP layer 602 to bond to the heat spreader layer 600. In an embodiment, one or more of the floating thermal vias 112a can also penetrate the heat spreader layer 600 to bond to the C4 layer 604. It should be noted that the floating thermal vias 112a penetrating the heat sink layer 600 are isolated from the vias 613 by the electrical isolation material (e.g., diamond) of the heat sink layer 600. In an embodiment, the floating thermal vias 112a may span the entire vertical height of the backside interconnect structure 400 plus the entire vertical height of the AP layer 602 plus the entire vertical height of the heat sink layer 600. These floating thermal vias 112a are bonded on the top surface of the C4 layer 604, but not on metal features (e.g., interconnect bumps) in the C4 layer.

[0057] Figure 4A A cross-sectional view of an IC structure 100 having floating thermal vias 112 a and non-floating thermal vias 112 b and a heat spreader layer 600 is shown in accordance with an embodiment of the present disclosure. Figure 4A Similar to Figure 3A , and similar components will not be described again for the sake of brevity. The difference is that Figure 4A Also includes Figure 2B The non-floating thermal via 112b described and shown in FIG. Figure 4A In the embodiment shown in , the IC structure 100 may also include one or more non-floating thermal vias 112 b penetrating the heat spreader layer 600 , as shown. These non-floating thermal vias 112 b may be directly located below the backside electrical metal line 412 and have an insulating portion directly bonded to the backside electrical metal line 412 .

[0058] Figure 4B A cross-sectional view of an IC structure 100 having floating thermal vias 112 a and non-floating thermal vias 112 b and a heat spreader layer 600 is shown according to another embodiment of the present disclosure. Figure 4B Similar to Figure 4A , and similar components will not be described again for the sake of brevity. The difference is that Figure 4B The heat sink layer 600 is disposed between the AP layer 602 and the C4 layer 604. Figure 3B As shown, the non-floating thermal vias 112 b penetrating the heat spreader layer 600 may have a greater vertical height than the non-floating thermal vias 112 b in the front-side interconnect structure 300 and the back-side interconnect structure 400 .

[0059] Figure 5 A top view of an IC chip (or IC structure 100) having a circuit region 250 is shown. The circuit region 250 is where the different IC components described above are formed. The IC chip may also include one or more seal rings 114 located outside and surrounding the circuit region 250. The seal rings 114 protect the circuit region 250 from damage caused by sawing the IC chip, and they may be formed by metal lines and vias that interconnect the outer edges.

[0060] Still reference Figure 5, inside the circuit area 250, thermal vias 112 of different shapes and configurations may be formed. In one embodiment, the thermal vias 112 may have similar dimensions to the electrical vias 313 and the backside electrical vias 413 in the x and / or y directions. This promotes structural uniformity and easier process integration. In another embodiment, the thermal vias 112 may have larger dimensions in the x and / or y directions compared to the electrical vias 313 and the backside electrical vias 413. In an embodiment, the electrical vias 313 and the backside electrical vias 413 have a width between about 10 nm and about 3 μm in the x and / or y directions, and the thermal vias have a width between about 100 nm and about 10 μm in the x and / or y directions. Larger sizes promote better heat dissipation, and because the thermal vias 112 do not actually route signal or power lines, they can be positioned further away from signal and power routing to avoid short circuits, and therefore have more spacing for larger sizes. In an embodiment, the distance between the thermal via 112 and the electrical via 313 and the backside electrical via 413 is in a range between about 50 nm and about 500 nm. In an embodiment, the thermal via 112 can be, for example, a square via having equal dimensions in the x and y directions. In another embodiment, the thermal via 112 can be, for example, a rectangular slot via having unequal dimensions in the x and y directions, for example, one side extending longitudinally longer in the x or y direction. In another embodiment, the thermal via 112 can be, for example, an annular via that surrounds a specific area in the circuit area 250. It should be noted that the embodiments of the present disclosure contemplate any combination of square vias, rectangular slot vias, and annular vias, and vias of different shapes can have sides aligned along the y or x direction.

[0061] Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A and Figure 8B It shows the Figure 5 250 is a top view portion of the circuit area 250 in FIG. Fig. 6A , Fig. 7A and Fig. 8A A top view of thermal vias 112 and electrical vias 313 cut along an xy plane in front side interconnect structure 300 is shown. Figure 6B , Figure 7B and Figure 8B A top view of thermal vias 112 and backside electrical vias 413 cut along an xy plane in heat spreader layer 600 is shown. Fig. 6A , Fig. 7A and Fig. 8A Corresponding to Figure 6B , Figure 7B and Figure 8B , the difference is that the top view is cut at a different location. It should be noted that Figure 6B , Figure 7B and Figure 8B The same through-hole configuration in FIG. 4 can also be applied to the top view cut along the xy plane in the backside interconnect structure 400 (not shown). FIG. 6A to FIG. 8A In each of the IC chips (or IC structures 100), the IC chips (or IC structures 100) include an area of ​​electrical vias 313 surrounding transistor devices 205. Some of these transistor devices 205 may be high-power devices (e.g., memory transistor devices that require high read / write speeds), and some of the transistor devices 205 may be low-power devices (e.g., logic devices for simple switching functions). High-power devices may generate hot spots that concentrate heat.

[0062] Reference now FIG. 6A to FIG. 6B , the thermal vias 112 can be evenly distributed along the xy plane, regardless of the location of the hot spot. As shown in the figure, the thermal vias 112 are evenly distributed and adjacent to the electrical vias 313 in the front-side interconnect structure 300. And the thermal vias 112 in the heat sink layer 600 (or the back-side interconnect structure 400) are also evenly distributed and adjacent to the back-side electrical vias 413.

[0063] refer to FIG. 7A to FIG. 7B , the thermal vias 112 can be distributed non-uniformly along the xy plane. In this embodiment, the thermal vias 112 are more concentrated in the hot spot area (e.g., around the high-power device). In this way, more spacing can be saved for signal routing in non-hot spot areas. In other words, the thermal vias 112 can be limited to high-power devices to reduce area requirements.

[0064] refer to FIG. 8A to FIG. 8B The thermal via 112 may have different shapes, such as a ring shape, a thin strip shape, etc., much like Figure 5 As shown, the thermal vias 112 can be elongated in the x or y direction, and they can also be ring-shaped with continuous or discontinuous contact. These elongated thermal vias 112 further improve heat absorption.

[0065] Fig. 9 A flow chart of a method 1000 of forming an IC structure 100 having thermal vias 112 and a heat spreader layer 600 is shown according to an embodiment of the present disclosure. Figures 10 to 14 shows the formation of an intermediate stage of manufacturing according to Fig. 9 The method 1000 processes an IC structure 100 . Figures 10 to 14 Previously described components may be shown, and for the sake of brevity, some of these components will not be described again. At a high level, method 1000 includes: (1) FEOL processing to form transistor devices 205, device level metal features 212, and buried tracks 214, and then forming a front-side interconnect structure 300 having electrical metal lines 312, electrical vias 313, and thermal vias 112, as described herein (see Fig.10 ); (2) bonding the IC workpiece to the silicon carrier substrate 502 (see Fig.11 ); (3) thinning down the device substrate 202 in the device layer 200 and forming a backside interconnect structure 400 having a backside electrical metal line 412, a backside electrical via 413 and a thermal via 112, as described herein (see Fig.11 ); (4) CMP is performed on the back side of the back side interconnect structure 400 to reduce the surface roughness, and then the heat sink layer 600 is deposited (see Fig.12 ); (5) making a through-hole connection through the heat sink layer 600, and depositing the AP layer 602 and the C4 layer 604 (see Figure 12 to Figure 13 ); and (6) completing the processing of the IC structure 100 by depositing the TIM layer 504, the top cover 506, the package substrate 606, the BGA structure 608 and the PCB 610 (see Fig.14 ).

[0066] Reference now Fig.10 , method 1000 forms transistor devices 205 in device layer 200 in operation 1002. Transistor devices 205 may be formed above or within device substrate 202 in device layer 200. Each transistor device 205 includes a channel region 204a between source / drain (S / D) regions 204b and a gate stack 208 above the channel region 204a. Transistor devices 205 may be formed by any suitable deposition and patterning techniques.

[0067] Each of the S / D regions 204b may include an epitaxial S / D component doped with an n-type dopant and / or a p-type dopant, the epitaxial S / D component sandwiching the transistor channel in the channel region 204a. In some embodiments, for n-type transistors, the S / D regions 204b include epitaxial S / D components having silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming Si:C epitaxial source / drain components, Si:P epitaxial source / drain components, or Si:C:P epitaxial source / drain components). In some embodiments, for p-type transistors, the S / D regions 204b include epitaxial S / D components having silicon germanium or germanium doped with boron, other p-type dopants, or combinations thereof (e.g., forming Si:Ge:B epitaxial source / drain components). In some embodiments, a portion of the epitaxial component closer to the transistor channel in the channel region 204a has a lower doping concentration than a portion of the epitaxial component laterally away from the transistor channel.

[0068] Each of the gate stacks 208 includes a gate electrode above a gate dielectric (not shown), and the gate dielectric is disposed on the channel region 204a. In some embodiments, an interfacial layer (e.g., a silicon oxide layer) is vertically disposed between the channel region 204a and the gate dielectric. The gate dielectric layer includes a high-k dielectric material, such as a material having a dielectric constant greater than silicon oxide (k≈3.9). The gate dielectric layer may include HfO, LaO, ZrO, AlO, TiO, or TaO. The gate electrode includes a suitable conductive material, such as Al, W, Co, TiAl, TiN, or other metal gate materials. For a full-ring gate FET, the gate dielectric layer and the gate electrode may each wrap around a plurality of transistor channels in the channel region 204a. Each transistor device 205 may also include a spacer component, such as a gate spacer and an internal spacer for a full-ring gate FET. The gate spacers may line the sidewalls of the gate stack 208 above the topmost channel, and the inner spacers may be disposed vertically between the transistor channels and laterally between the gate stack 208 and the S / D regions 204 b. The gate spacers and the inner spacers may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material.

[0069] Still reference Fig.10, the method 1000 forms a device-level metal feature 212 electrically coupled to the S / D region 204b and / or the gate stack 208 of the transistor device over the S / D region 204b and / or the gate stack 208 of the transistor device in operation 1004. As previously described, these features can be formed in the ILD layer 211 above the device substrate 202. As part of operation 1004, the method 1000 can form a buried rail 214 buried in the device substrate 202 and extending under the transistor device 205. In addition, as part of operation 1004, the method 1000 can form a feedthrough via 216 extending and penetrating the ILD layer 211 and partially through the device substrate 202. In some embodiments, the bottom surface of the buried rail 214 and the bottom surface of the feedthrough via 216 are substantially coplanar. The device-level metal feature 212, the buried rail 214, and the feedthrough via 216 can be formed by standard FEOL processing techniques. FEOL processing may include: depositing one or more ILD sub-layers; performing one or more patterning processes including photolithography and etching to form patterned trenches in the ILD sub-layers; performing one or more deposition processes such as CVD, PVD, or ALD to form metal features in the patterned trenches; and performing one or more planarization processes such as CMP after depositing the metal features. It should be noted that metals such as Ru, W, or Mo may be used as metal features instead of Cu for device-level metal features 212, buried rails 214, and feedthrough vias 216. This is to withstand high temperatures (e.g., greater than 900 degrees Celsius) during FEOL processing and to prevent electromigration.

[0070] Still reference Fig.10 , the method 1000 forms a front-side interconnect structure 300 over the device-level metal features 212 in operation 1006. The front-side interconnect structure 300 includes electrical metal lines 312, electrical vias 313 vertically coupled between the electrical metal lines 312, and thermal vias 112 electrically isolated from the electrical metal lines 312 and the vias 313. These features are formed in the front-side IMD layer 302.

[0071] In an embodiment, the thermal vias 112 are formed after the electrical metal lines 312 and the electrical vias 313 are formed. In this way, the thermal vias 112 are formed by etching through the entirety (or multiple sub-layers) of the front-side IMD layer 302 in a single etching process, thereby forming a deep trench, and then depositing a metal (e.g., Cu) into the deep trench. In another embodiment, the thermal vias 112 are formed simultaneously with the formation of the electrical metal lines 312 and the electrical vias 313. In this way, the thermal vias 112 are formed in multiple etching and deposition steps, and they are formed at the same time as when different electrical metal lines 312 and vias 313 are formed in the IMD sub-layers of the front-side IMD layer 302.

[0072] It should be noted that the thermal via 112 can be formed as a floating thermal via 112a or a non-floating thermal via 112b. When forming the floating thermal via 112a, a patterned groove is first formed, and then a metal (e.g., Cu) is deposited into the patterned groove. It should be noted that the patterned groove can penetrate multiple IMD sublayers of the front side IMD layer 302. In a first embodiment, the patterned groove can be formed to be laterally adjacent to the location where the transistor device 205 is formed. In a second embodiment, the patterned groove can be formed directly above the location where the transistor device 205 is formed (as with the non-floating thermal via 112b), however, in this case, the patterned groove should only partially penetrate the front side IMD layer 302 without exposing any electrical metal lines 312 and vias 313. When forming non-floating thermal vias 112b, patterned trenches are first formed to expose the top surface of electrical metal line 312, then insulating thermal via material (e.g., diamond nanoparticles, AlN, c-BN, Al2O3, or BeO) is deposited, and then metal (e.g., Cu) is deposited over the insulating thermal via material. Forming thermal vias 112 is compatible with BEOL processes. Therefore, during FEOL processing, the metal (e.g., Cu) deposited to form thermal vias 112 can be deposited by PVD at low temperatures (less than 400 degrees Celsius) as opposed to high temperatures (e.g., greater than 900 degrees Celsius).

[0073] Reference now Fig.11 , the method 1000 bonds a carrier substrate 502 (e.g., a silicon substrate) to a top surface of the front side interconnect structure 300 in operation 1008. Operation 1008 may include depositing a bonding layer 500 over the front side interconnect structure 300 and then depositing the carrier substrate 502 over the bonding layer 500. The bonding layer bonds the carrier substrate 502 to the rest of the IC workpiece.

[0074] Still reference Fig.11, the method 1000 thins down the device substrate 202 from the back side of the device layer 200 in operation 1010. Operation 1010 may be performed before or after flipping the bonded IC structure 100 for further back side processing. Operation 1010 thins down the exposed back side of the device substrate 202 by a suitable process such as a mechanical grinding process and / or a chemical thinning process. In the illustrated embodiment, operation 1014 may also thin down the back side portions of the buried rails 214 and the feed-through vias 216 so that the bottom surfaces of the buried rails 214 and the feed-through vias 216 are coplanar with the bottom surface of the device substrate 202. In the case of partial removal of the device substrate 202, portions of the remaining device substrate 202 still embed portions of the transistor device 205. In the case of substantial or complete removal of the device substrate 202, the thinning down exposes portions of the transistor device 205 (e.g., the S / D region 204b). In either case, the device substrate 202 is no longer able or effective to absorb heat caused by device self-heating due to the partial or complete removal of the device substrate 202. Therefore, the thermal vias 112 and / or the heat sink layer 600 supplement or replace the heat absorbing function of the device substrate 202.

[0075] Still reference Fig.11 , the method 1000 forms a backside interconnect structure 400 on the back side of the device layer 200 in operation 1012. The backside interconnect structure 400 includes backside electrical metal lines 412, backside electrical vias 413 vertically coupled between the backside electrical metal lines 412, and thermal vias 112 electrically isolated from the backside electrical metal lines 412 and the vias 413. These components are formed in the backside IMD layer 402, which may include multiple sub-layers. In the illustrated embodiment, the backside electrical metal lines 412 are formed to directly contact the buried tracks 214 and the feedthrough vias 216. The thermal vias 112 formed in the backside interconnect structure 400 can be formed similar to those formed in the frontside interconnect structure 300.

[0076] Reference now Fig.12 , the method 1000 forms a heat sink layer 600 on the back side of the backside interconnect structure 400 by any suitable deposition process in operation 1014. In an embodiment, a planarization process such as CMP is performed on the back side of the backside interconnect structure 400 before depositing the heat sink layer 600. The planarization process can reduce the surface roughness of the backside interconnect structure 400 to less than 1 nm. It should be noted that in an embodiment where the heat sink layer 600 is formed between the AP layer 602 and the C4 layer 604, the AP layer 602 is deposited on the back side of the backside interconnect structure 400, and the heat sink layer 600 is deposited on the back side of the AP layer 602.

[0077] Still reference Fig.12, method 1000 forms a via 613 in heat spreader layer 600 that is electrically connected to backside electrical metal line 412 and via 413 in operation 1016. As shown, via 613 can be directly bonded to backside electrical metal line 412. It should be noted that in embodiments where heat spreader layer 600 is formed between AP layer 602 and C4 layer 604, via 613 can be directly bonded to an aluminum bonding pad in AP layer 602.

[0078] Reference now Fig.13 , method 1000 forms additional integrated circuit (IC) components to complete the IC chip in operation 1018. These include the TIM layer 504, top cover 506, package substrate 606, BGA structure 608, and PCB 610 described previously.

[0079] For illustration purposes, FIG. 15A to FIG. 15C The thermal improvements that can be achieved with heat sinks and thermal vias are shown. The specific values ​​for temperature, cross-sectional distance, and thermal conductivity k are not intended to be limiting. Other values ​​(or ranges of values) may also demonstrate thermal improvements with heat sinks and thermal vias.

[0080] Fig.15A The circuit diagram of FIG. 6 is shown passing from top to bottom (eg, from cover 506 to PCB 610). Figure 1 The cross section of the IC structure 100 in FIG. 1 and the device layer 200 has 750 W / cm 2 Temperature curve of the hot spot (50μm). Fig.15A An example is shown where there is no heat spreader layer 600 and no thermal vias 112. As shown, the maximum temperature (Tmax) is ~77°C. Fig. 15B Shown for Figure 1 1 , but with the heat spreader layer 600 having k=200 W / m / K and still without the thermal vias 112. As shown, the maximum temperature (Tmax) is ~71°C. Fig. 15C Shown for Figure 1 , wherein the heat spreader layer 600 has k=200 W / m / K, and 20% of the front-side interconnect structure 300 and the back-side interconnect structure 400 are replaced with thermal vias with k=150 W / m / K. As shown, the maximum temperature (Tmax) is ˜69° C. It should be noted that a higher thermal conductivity heat spreader layer 600 (e.g., with k=500 W / m / K) can also be used to further reduce the hot spot temperature.

[0081] Although not limiting, the disclosed embodiments provide advantages for IC semiconductor structures with backside power delivery. One exemplary advantage is incorporating thermal vias in frontside and / or backside interconnect structures. Another exemplary advantage is incorporating a heat sink layer on the backside of the backside interconnect structure. Another exemplary advantage is incorporating thermal vias with insulating portions bonded to metal lines.

[0082] One aspect of the disclosed embodiments relates to an integrated circuit (IC) structure. The IC structure includes: a device layer having a transistor device, the transistor device having a channel region located between a source / drain (S / D) region and a gate stack located above the channel region; a front-side interconnect structure located on the front side of the device layer, wherein the front-side interconnect structure includes a first metal component and a second metal component embedded in an intermetallic dielectric (IMD) layer, the first metal component and the second metal component are isolated from each other by the IMD layer, the first metal component is electrically connected to the S / D region or the gate stack of the transistor device, and the second metal component is electrically isolated from the transistor device; a back-side interconnect structure located on the back side of the device layer. The back-side interconnect structure includes a third metal component and a fourth metal component embedded in the back-side IMD layer, the third metal component and the fourth metal component are isolated from each other by the back-side IMD layer, the third metal component is electrically connected to the S / D region or the gate stack of the transistor device, and the fourth metal component is electrically isolated from the transistor device. The IC structure also includes: a heat sink layer located on the back side of the back-side interconnect structure. The heat sink layer is made of a heat sink material that is thermally conductive and electrically insulating.

[0083] In an embodiment, the first metal component and the third metal component include electrical metal lines and electrical vias, and the electrical vias are vertically disposed between the electrical metal lines. The second metal component and the fourth metal component include thermal vias, and each of the thermal vias has a greater height in a vertical direction than each of the electrical vias.

[0084] In a further embodiment, the electrical metal line extends beyond the side of the electrical via in a first direction or in a second direction perpendicular to the first direction, and the thermal via is a metal pillar having vertical side without extending beyond the vertical side.

[0085] In an embodiment, the second metal component and the fourth metal component are first thermal vias that are completely surrounded by and directly contact the dielectric material, and the IC structure further includes: second thermal vias embedded in the IMD layer, wherein each of the second thermal vias includes a metal portion and a thermal insulation portion, the thermal insulation portion of the second thermal via is directly bonded to the first metal component, and the thermal insulation portion of the second thermal via separates the first metal component from the metal portion of the second thermal via; and third thermal vias embedded in the backside IMD layer, wherein each of the third thermal vias includes a metal portion and a thermal insulation portion, the thermal insulation portion of the third thermal via is directly bonded to the third metal component, and the thermal insulation portion of the third thermal via separates the third metal component from the metal portion of the third thermal via.

[0086] In a further embodiment, the metal portions of the second thermal via and the third thermal via include copper, and the thermal insulation portions of the second thermal via and the third thermal via include diamond, AlN, BN, Al2O3, BeO, or a combination thereof.

[0087] In an embodiment, the fourth metal feature spans from the device layer to the heat spreader layer, and the fourth metal feature is bonded on a top surface of the heat spreader layer.

[0088] In an embodiment, the IC structure further comprises: a redistribution layer (RDL) structure on the back side of the heat spreader layer, the RDL structure comprising an aluminum pad embedded in the passivation layer. The heat spreader layer embeds a via electrically connecting the third metal component to the aluminum pad.

[0089] In an embodiment, the heat sink material has a thermal conductivity between about 10 and about 500 W / m / K.

[0090] In an embodiment, the heat sink material includes diamond, AlN, BN, Al2O3, BeO, or a combination thereof.

[0091] In an embodiment, the transistor device includes a high-power device and a low-power device, and the second metal feature and the fourth metal feature are laterally concentrated closer to the high-power device relative to the low-power device.

[0092] Another aspect of the disclosed embodiments relates to an integrated circuit (IC) structure. The IC structure includes: a device layer having a transistor device, the transistor device having a channel region located between source / drain (S / D) regions and a gate stack located above the channel region; a front-side interconnect structure located on the front side of the device layer, wherein the front-side interconnect structure includes a first metal component and a second metal component embedded in an intermetallic dielectric (IMD) layer, the first metal component and the second metal component are isolated from each other by the IMD layer, the first metal component is electrically connected to the S / D region or the gate stack of the transistor device, and the second metal component is electrically isolated from the transistor device; a bonding oxide layer located above the front-side interconnect structure; and a substrate located above the bonding oxide layer.

[0093] In an embodiment, the first metal component includes electrical metal lines and electrical vias, and the electrical vias are vertically arranged between the electrical metal lines, wherein the second metal component includes thermal vias, and each of the thermal vias has a height in the vertical direction greater than at least the height of the electrical vias plus the height of the electrical metal lines.

[0094] In an embodiment, the second metal component is a floating thermal via that is completely surrounded by and directly contacts the dielectric material, and the IC structure further comprises: non-floating thermal vias embedded in the IMD layer, wherein each of the non-floating thermal vias comprises a metal portion and a thermal insulation portion, the thermal insulation portion is directly bonded to the first metal component, and the thermal insulation portion separates the first metal component from the metal portion.

[0095] In a further embodiment, the metal portion has a greater height in a vertical direction than the thermal insulation portion. In a further embodiment, the floating thermal via has a greater height in a vertical direction than the non-floating thermal via.

[0096] In an embodiment, the IC structure further includes: a backside interconnect structure located on the back side of the device layer, wherein the backside interconnect structure includes a third metal component and a fourth metal component embedded in the backside IMD layer, the third metal component and the fourth metal component are isolated from each other by the backside IMD layer, the third metal component is electrically connected to the S / D region or the gate stack of the transistor device, and the fourth metal component is electrically isolated from the transistor device; and a heat sink layer located on the back side of the backside interconnect structure, wherein the heat sink layer is made of a thermally conductive and electrically insulating heat sink material, and wherein the fourth metal component directly contacts the heat sink layer.

[0097] Another aspect of the disclosed embodiments relates to a method of forming an integrated circuit (IC). The method includes: forming transistor devices in a device layer above a device substrate, each transistor device having a channel region located between source / drain (S / D) regions and a gate stack located above the channel region; forming a device-level contact electrically coupled to the S / D region and the gate stack of the transistor device above the S / D region and the gate stack of the transistor device; forming a front-side interconnect structure above the device-level contact, the front-side interconnect structure having electrical metal lines, electrical vias vertically coupled between the electrical metal lines, and thermal vias electrically isolated from the electrical metal lines and the electrical vias; bonding a substrate to a top surface of the front-side interconnect structure; thinning the device substrate downward from the back side of the device layer; forming a back-side interconnect structure on the back side of the device layer, the back-side interconnect structure having back-side electrical metal lines, back-side electrical vias vertically coupled between the back-side electrical metal lines, and back-side thermal vias electrically isolated from the back-side electrical metal lines and the electrical vias; and forming a heat sink layer on the back side of the back-side interconnect structure, wherein the heat sink layer is made of a heat sink material that is thermally conductive and electrically insulating.

[0098] In an embodiment, the method further includes forming a redistribution layer (RDL) structure on a back side of the heat spreader layer, wherein the RDL structure includes an aluminum bond pad embedded in the passivation layer.

[0099] In a further embodiment, forming the heat spreader layer further includes forming a via in the heat spreader layer, the via electrically coupling the backside electrical metal line to the aluminum bond pad.

[0100] In an embodiment, the thermal vias, backside thermal vias, and heat spreader layer are formed by physical vapor deposition or chemical vapor deposition at a temperature less than 400 degrees Celsius.

[0101] Some embodiments of the present application provide an integrated circuit structure, comprising: a device layer having a transistor device, the transistor device having a channel region located between source / drain regions and a gate stack located above the channel region; a front-side interconnect structure located on the front side of the device layer, wherein the front-side interconnect structure comprises a first metal component and a second metal component embedded in an intermetallic dielectric layer, the first metal component and the second metal component are isolated from each other by the intermetallic dielectric layer, the first metal component is electrically connected to the source / drain region or the gate stack of the transistor device, and the second metal component is electrically connected to the source / drain region or the gate stack of the transistor device, and the second metal component is electrically connected to the source / drain region or the gate stack of the transistor device. a back-side interconnect structure located on the back side of the device layer, wherein the back-side interconnect structure includes a third metal component and a fourth metal component embedded in a back-side intermetallic dielectric layer, the third metal component and the fourth metal component are isolated from each other by the back-side intermetallic dielectric layer, the third metal component is electrically connected to a source / drain region or a gate stack of the transistor device, and the fourth metal component is electrically isolated from the transistor device; and a heat sink layer located on the back side of the back-side interconnect structure, wherein the heat sink layer is made of a heat sink material that is thermally conductive and electrically insulating.

[0102] In some embodiments, the first metal component and the third metal component include electrical metal lines and electrical vias, and the electrical vias are vertically disposed between the electrical metal lines, wherein the second metal component and the fourth metal component include thermal vias, and each of the thermal vias has a height greater than that of each of the electrical vias in a vertical direction. In some embodiments, wherein the electrical metal lines extend beyond the side surfaces of the electrical vias in a first direction or in a second direction perpendicular to the first direction, and the thermal vias are metal pillars having vertical side surfaces without extending beyond the vertical side surfaces. In some embodiments, the second metal component and the fourth metal component are first thermal vias completely surrounded by and directly contacting the dielectric material, and further include: a second thermal via embedded in the intermetallic dielectric layer, wherein each of the second thermal vias includes a metal portion and a thermal insulation portion, the thermal insulation portion of the second thermal via is directly bonded to the first metal component, and the thermal insulation portion of the second thermal via separates the first metal component from the metal portion of the second thermal via; and a third thermal via embedded in the backside intermetallic dielectric layer, wherein each of the third thermal vias includes a metal portion and a thermal insulation portion, the thermal insulation portion of the third thermal via is directly bonded to the third metal component, and the thermal insulation portion of the third thermal via separates the third metal component from the metal portion of the third thermal via. In some embodiments, the metal portions of the second thermal via and the third thermal via include copper, and the thermal insulation portions of the second thermal via and the third thermal via include diamond, AlN, BN, Al2O3, BeO, or a combination thereof. In some embodiments, the fourth metal component spans from the device layer to the heat sink layer, and the fourth metal component is bonded to the top surface of the heat sink layer. In some embodiments, the integrated circuit structure further comprises: a redistribution layer structure located on the back side of the heat sink layer, the redistribution layer structure comprising an aluminum pad embedded in the passivation layer, wherein the heat sink layer embeds a through hole that electrically connects the third metal component to the aluminum pad. In some embodiments, the heat sink material has a thermal conductivity between about 10 and about 500 W / m / K. In some embodiments, the heat sink material comprises diamond, AlN, BN, Al2O3, BeO, or a combination thereof. In some embodiments, the transistor device comprises a high power device and a low power device, and the second metal component and the fourth metal component are laterally concentrated to be closer to the high power device relative to the low power device.

[0103] Still other embodiments of the present application provide an integrated circuit structure, comprising: a device layer having a transistor device, the transistor device having a channel region located between source / drain regions and a gate stack located above the channel region; a front-side interconnect structure located on the front side of the device layer, wherein the front-side interconnect structure comprises a first metal component and a second metal component embedded in an intermetallic dielectric layer, the first metal component and the second metal component being isolated from each other by the intermetallic dielectric layer, the first metal component being electrically connected to the source / drain region or the gate stack of the transistor device, and the second metal component being electrically isolated from the transistor device; a bonding oxide layer located above the front-side interconnect structure; and a substrate located above the bonding oxide layer.

[0104] In some embodiments, the first metal component includes an electrical metal line and an electrical via, and the electrical via is vertically arranged between the electrical metal lines, wherein the second metal component includes a thermal via, and each of the thermal vias has a height in the vertical direction that is greater than at least the height of the electrical via plus the height of the electrical metal line. In some embodiments, the second metal component is a floating thermal via that is completely surrounded by a dielectric material and directly contacts the dielectric material, and further includes: a non-floating thermal via embedded in the inter-metal dielectric layer, wherein each of the non-floating thermal vias includes a metal portion and a thermal insulation portion, the thermal insulation portion is directly bonded to the first metal component, and the thermal insulation portion separates the first metal component from the metal portion. In some embodiments, the metal portion has a height in the vertical direction that is greater than the thermal insulation portion. In some embodiments, the floating thermal via has a height in the vertical direction that is greater than the non-floating thermal via. In some embodiments, the integrated circuit structure further includes: a backside interconnect structure located on the back side of the device layer, wherein the backside interconnect structure includes a third metal component and a fourth metal component embedded in a backside intermetallic dielectric layer, the third metal component and the fourth metal component are isolated from each other by the backside intermetallic dielectric layer, the third metal component is electrically connected to a source / drain region or a gate stack of the transistor device, and the fourth metal component is electrically isolated from the transistor device; and a heat sink layer located on the back side of the backside interconnect structure, wherein the heat sink layer is made of a thermally conductive and electrically insulating heat sink material, and wherein the fourth metal component directly contacts the heat sink layer.

[0105] Some other embodiments of the present application provide a method for forming an integrated circuit structure, comprising: forming transistor devices in a device layer above a device substrate, each transistor device having a channel region located between the source / drain regions and a gate stack located above the channel region; forming a device-level contact electrically coupled to the source / drain region and the gate stack of the transistor device above the source / drain region and the gate stack of the transistor device; forming a front-side interconnect structure above the device-level contact, the front-side interconnect structure having an electrical metal line, a vertically coupled The invention relates to a method of manufacturing a heat sink layer on the back side of the device layer, wherein the heat sink layer is made of a heat conducting and electrically insulating heat sink material. The method comprises the steps of: forming an electrical via between the electrical metal lines and the electrical vias electrically isolated from the electrical metal lines and the electrical vias; bonding a substrate to a top surface of the front-side interconnect structure; thinning the device substrate downward from the back side of the device layer; forming a back-side interconnect structure on the back side of the device layer, the back-side interconnect structure having back-side electrical metal lines, back-side electrical vias vertically coupled between the back-side electrical metal lines, and back-side thermal vias electrically isolated from the back-side electrical metal lines and the electrical vias; and forming a heat sink layer on the back side of the back-side interconnect structure, wherein the heat sink layer is made of a heat conducting and electrically insulating heat sink material.

[0106] In some embodiments, the method further comprises: forming a redistribution layer structure on the back side of the heat sink layer, wherein the redistribution layer structure comprises an aluminum bonding pad embedded in the passivation layer. In some embodiments, forming the heat sink layer further comprises forming a via in the heat sink layer, the via electrically coupling the backside electrical metal line to the aluminum bonding pad. In some embodiments, the thermal via, the backside thermal via, and the heat sink layer are formed by physical vapor deposition or chemical vapor deposition at a temperature of less than 400 degrees Celsius.

[0107] The details of the methods and devices of the embodiments of the present disclosure are described in the accompanying drawings. The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those of ordinary skill in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. An integrated circuit structure, comprising: a device layer having a transistor device having a channel region between source / drain regions and a gate stack over the channel region; a front-side interconnect structure located on the front side of the device layer, wherein the front-side interconnect structure includes a first metal component and a second metal component embedded in an intermetallic dielectric layer, the first metal component and the second metal component are isolated from each other by the intermetallic dielectric layer, the first metal component is electrically connected to a source / drain region or a gate stack of the transistor device, and the second metal component is electrically isolated from the transistor device; a backside interconnect structure located on the back side of the device layer, wherein the backside interconnect structure includes a third metal component and a fourth metal component embedded in a backside intermetallic dielectric layer, the third metal component and the fourth metal component are isolated from each other by the backside intermetallic dielectric layer, the third metal component is electrically connected to a source / drain region or a gate stack of the transistor device, and the fourth metal component is electrically isolated from the transistor device; and A heat sink layer is located on the back side of the back side interconnect structure, wherein the heat sink layer is made of a heat sink material that is thermally conductive and electrically insulating.

2. The integrated circuit structure according to claim 1, in, The first metal component and the third metal component include electrical metal lines and electrical vias, and the electrical vias are vertically disposed between the electrical metal lines, Wherein, the second metal component and the fourth metal component include thermal vias, and each of the thermal vias has a greater height in a vertical direction than each of the electrical vias.

3. The integrated circuit structure according to claim 2, in, The electrical metal line extends beyond the side of the electrical via in a first direction or in a second direction perpendicular to the first direction, and the thermal via is a metal pillar having a vertical side without an extension beyond the vertical side.

4. The integrated circuit structure according to claim 1, wherein: The second metal component and the fourth metal component are first thermal vias that are completely surrounded by and directly contact the dielectric material, and further include: second thermal vias embedded in the intermetal dielectric layer, wherein each of the second thermal vias comprises a metal portion and a thermal insulation portion, the thermal insulation portion of the second thermal via is directly bonded to the first metal component, and the thermal insulation portion of the second thermal via separates the first metal component from the metal portion of the second thermal via; and and a third thermal via embedded in the back-side intermetallic dielectric layer, wherein each of the third thermal vias comprises a metal portion and a thermal insulation portion, the thermal insulation portion of the third thermal via is directly bonded to the third metal component, and the thermal insulation portion of the third thermal via separates the third metal component from the metal portion of the third thermal via.

5. The integrated circuit structure according to claim 4, wherein: The metal portions of the second thermal via and the third thermal via include copper, and the thermal insulation portions of the second thermal via and the third thermal via include diamond, AlN, BN, Al2O3, BeO, or a combination thereof.

6. The integrated circuit structure according to claim 1, wherein: The fourth metal feature spans from the device layer to the heat spreader layer, and the fourth metal feature is bonded on a top surface of the heat spreader layer.

7. The integrated circuit structure according to claim 1, further comprising: a redistribution layer structure located on the back side of the heat sink layer, the redistribution layer structure comprising an aluminum pad embedded in a passivation layer, Wherein, the heat sink layer embeds a through hole that electrically connects the third metal component to the aluminum pad.

8. The integrated circuit structure according to claim 1, wherein: The heat sink material has a thermal conductivity between about 10 and about 500 W / m / K.

9. An integrated circuit structure comprising: a device layer having a transistor device having a channel region between source / drain regions and a gate stack over the channel region; a front-side interconnect structure located on the front side of the device layer, wherein the front-side interconnect structure includes a first metal component and a second metal component embedded in an intermetallic dielectric layer, the first metal component and the second metal component are isolated from each other by the intermetallic dielectric layer, the first metal component is electrically connected to a source / drain region or a gate stack of the transistor device, and the second metal component is electrically isolated from the transistor device; a bonding oxide layer overlying the front-side interconnect structure; and A substrate is located above the bonding oxide layer.

10. A method of forming an integrated circuit structure, comprising: forming transistor devices in a device layer above the device substrate, each transistor device having a channel region between the source / drain regions and a gate stack above the channel region; forming a device-level contact over the source / drain region and the gate stack of the transistor device electrically coupled to the source / drain region and the gate stack of the transistor device; forming a front-side interconnect structure over the device-level contacts, the front-side interconnect structure having electrical metal lines, electrical vias vertically coupled between the electrical metal lines, and thermal vias electrically isolated from the electrical metal lines and the electrical vias; bonding a substrate to a top surface of the front-side interconnect structure; Thinning the device substrate downward from the back side of the device layer; forming a backside interconnect structure on the backside of the device layer, the backside interconnect structure having backside electrical metal lines, backside electrical vias vertically coupled between the backside electrical metal lines, and backside thermal vias electrically isolated from the backside electrical metal lines and the electrical vias; as well as A heat sink layer is formed on the back side of the backside interconnect structure, wherein the heat sink layer is made of a heat sink material that is thermally conductive and electrically insulating.

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