Radio frequency switch structure and preparation method thereof

Abstract

The invention provides a radio frequency switch structure and a preparation method thereof. The radio frequency switch structure comprises an SOI substrate; the transistor chain is arranged on the front surface of the SOI substrate and comprises first to Nth transistors which are cascaded between a head end and a tail end, the head end is connected with radio frequency input, the tail end is grounded, and N is an integer greater than or equal to 4; the dielectric layer covers the SOI substrate and the transistor chain; the first conductive grounding layer to the Nth conductive grounding layer are arranged on the dielectric layer or the back face of the SOI substrate, the first conductive grounding layer to the Nth conductive grounding layer are correspondingly arranged on the front faces or the back faces of the first transistor to the Nth transistor respectively, and the areas, exposed out of the front faces or the back faces of the corresponding transistors, of the first conductive grounding layer to the Nth conductive grounding layer are sequentially increased. According to the invention, the power processing capability of the radio frequency switch structure can be improved by balancing the voltage distribution of each transistor on the radio frequency switch structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a radio frequency switch structure and a preparation method thereof. Background Art

[0002] The RF switch is one of the control devices used to control the transmission path and signal size of RF signals. It is widely used in many fields such as wireless communications, electronic countermeasures, radar systems and electronic measuring instruments.

[0003] In related technologies, such as Figure 1a As shown, the RF switch circuit may include a series branch connected to the antenna and a parallel branch connected to the ground, wherein the parallel branch may be formed by, for example, 12 transistors connected in series, which are, from top to bottom, the first transistor 1, the second transistor 2, the third transistor 3...the eleventh transistor 11 and the twelfth transistor 12. The drain of the first transistor 1 is connected to the RF input as the input end of the RF switch circuit, and its source is connected to the drain of the second transistor 2; the source of the second transistor 2 is connected to the drain of the third transistor 3...the source of the eleventh transistor 11 is connected to the drain of the twelfth transistor 12, and the source of the twelfth transistor 12 is connected to the ground as the output end of the RF switch circuit; the gate of each of the above transistors is connected to the bias voltage Vgn through a high-resistance resistor; a high-resistance resistor is connected to the substrate of each transistor, and is grounded (or uniformly connected to the bias voltage) through a high resistor; a high-resistance resistor is connected between the drain and source of each transistor, and the resistance value of all the above high-resistance resistors is consistent and at least 50K ohms.

[0004] Figure 1b is the actual voltage distribution between the sources and drains of the 12 transistors in the parallel branch, such as Figure 1b As shown, the voltage distribution of the above-mentioned RF switch circuit is unbalanced, which seriously affects the power handling capability and even causes high voltage on the transistor to break down the transistor. Summary of the invention

[0005] The object of the present invention is to provide a radio frequency switch structure and a preparation method thereof, so as to improve the power handling capacity of the radio frequency switch structure by balancing the voltage distribution of each transistor on the radio frequency switch structure.

[0006] In order to solve the above technical problems, the present invention provides a radio frequency switch structure, comprising:

[0007] SOI substrate;

[0008] A transistor chain, arranged on the front side of the SOI substrate, comprising first to Nth transistors cascaded between a head end and a tail end, wherein the head end is connected to a radio frequency input, the tail end is grounded, and N is an integer greater than or equal to 4;

[0009] A dielectric layer covering the SOI substrate and the transistor chain;

[0010] The first to Nth conductive grounding layers are arranged on the dielectric layer or the back side of the SOI substrate, and the first to Nth conductive grounding layers are respectively arranged on the front side or the back side of the first to Nth transistors, and the areas of the first to Nth conductive grounding layers exposed to the front side or the back side of the corresponding transistors increase successively.

[0011] Optionally, the first to Nth conductive ground layers are all connected to a ground terminal of the RF switch structure or a semiconductor device including the RF switch structure.

[0012] Optionally, the first to Nth conductive grounding layers are arranged in the same layer as the grounding end of the radio frequency switch structure and are electrically connected.

[0013] Optionally, the first to Nth conductive grounding layers are located on the dielectric layer, and the first to Nth conductive grounding layers are top metal interconnection layers.

[0014] Optionally, the first to Nth conductive grounding layers are located on the back side of the SOI substrate, and the first to Nth conductive grounding layers are redistribution line layers.

[0015] Optionally, the first to Nth transistors have an interdigitated layout structure of the same size, the gate structures and source-drain structures of the first to Nth transistors extend along a first direction, and the first to Nth conductive ground layers span the gate structures and source-drain structures of the first to Nth transistors along a second direction, and the second direction is orthogonal to the first direction.

[0016] Optionally, the first to Nth conductive grounding layers are all rectangular in shape, and the widths of the first to Nth conductive grounding layers along the first direction increase sequentially.

[0017] According to another aspect of the present invention, a method for preparing a radio frequency switch structure is also provided, comprising:

[0018] Providing an SOI substrate;

[0019] A transistor chain is formed on the front side of the SOI substrate, wherein the transistor chain includes first to Nth transistors cascaded between a head end and a tail end, wherein the head end is connected to a radio frequency input, the tail end is grounded, and N is an integer greater than or equal to 4;

[0020] forming a dielectric layer on the SOI substrate and the transistor chain;

[0021] The first to Nth conductive grounding layers are formed on the surface of the dielectric layer or the back side of the SOI substrate, and the first to Nth conductive grounding layers are respectively arranged on the front side or the back side of the first to Nth transistors, and the areas of the first to Nth conductive grounding layers exposed to the front side or the back side of the corresponding transistor increase successively.

[0022] Optionally, the first to Nth conductive grounding layers are located on the dielectric layer, and the first to Nth conductive grounding layers are formed simultaneously when the top metal interconnection layer of the radio frequency switch structure is formed.

[0023] Optionally, the first to Nth conductive grounding layers are located on the back side of the SOI substrate, and the first to Nth conductive grounding layers are formed simultaneously when the redistribution line layer of the radio frequency switch structure is formed.

[0024] In summary, the RF switch structure provided by the present invention includes an SOI substrate; a transistor chain, which is arranged on the front side of the SOI substrate, and includes first to N-th transistors cascaded between a head end and a tail end, the head end is connected to the RF input, the tail end is grounded, and N is an integer greater than or equal to 4; a dielectric layer, covering the SOI substrate and the transistor chain; first to N-th conductive grounding layers arranged on the back side of the dielectric layer or the SOI substrate, the first to N-th conductive grounding layers are respectively arranged on the front side or back side of the first to N-th transistors, and the areas of the first to N-th conductive grounding layers exposed to the front side or back side of the corresponding transistors increase sequentially. Among them, since the areas of the first to Nth conductive grounding layers exposed to the front or back side of the corresponding transistors increase successively, the parasitic capacitance of the first to Nth conductive grounding layers relative to the first to Nth transistors to the ground increases successively, that is, the impedance of the first to Nth transistors increases successively, and the impedance increase is greater the closer to the tail end, thereby balancing the voltage distribution of each transistor and balancing the processing power of each transistor, thereby improving the power processing capacity of the RF switch structure, and can also reduce the maximum voltage difference distributed between the source and drain of each transistor, so as to reduce the risk of each transistor being broken down by high voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0026] Figure 1a It is a circuit diagram of a radio frequency switch circuit in the related art;

[0027] Figure 1b A schematic diagram of voltage distribution of a radio frequency switch circuit in the related art;

[0028] Figure 2a A schematic cross-sectional view of a single transistor in the radio frequency switch structure provided in Example 1;

[0029] Figure 2b A schematic top view of a transistor chain in a radio frequency switch structure provided in Example 1;

[0030] Figure 2c Schematic diagram of voltage distribution between source and drain before and after optimization of each transistor;

[0031] Figure 3a A schematic cross-sectional view of a single transistor in the radio frequency switch structure provided in the second embodiment;

[0032] Figure 3b A schematic top view of a transistor chain in a radio frequency switch structure provided in Embodiment 2;

[0033] Figure 4a A flow chart of a method for preparing a radio frequency switch structure provided in Example 3;

[0034] Figure 4b A flow chart of a method for preparing a radio frequency switch structure provided in Example 4;

[0035] Figure 5a to Figure 5d It is a structural schematic diagram corresponding to the corresponding steps of the method for preparing the radio frequency switch structure provided in Example 3.

[0036] In the attached figure:

[0037] 10-SOI substrate; 11-silicon base layer; 12-buried oxide layer; 13-top silicon layer; 14-head end; 15-tail end; 20-transistor; 21-gate structure; 22-source-drain structure; 23-source-drain lead structure; 23a-source lead structure; 23b-drain lead structure; 24-dielectric layer; 31-conductive ground layer; X-first direction; Y-second direction; S1-first curve; S2-second curve. DETAILED DESCRIPTION

[0038] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0039] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0040] Embodiment 1

[0041] Embodiment 1 provides a radio frequency switch structure.

[0042] Figure 2a A cross-sectional schematic diagram of a single transistor in the radio frequency switch structure provided in the first embodiment, Figure 2b This is a top view schematic diagram of a transistor chain in the radio frequency switch structure provided in Example 1.

[0043] like Figure 2a and Figure 2b As shown, the RF switch structure provided in this embodiment includes an SOI substrate 10, a transistor chain, a dielectric layer 24, and first to Nth conductive grounding layers 31. The transistor chain is arranged on the front side of the SOI substrate 10, and includes first to Nth transistors 20 cascaded between a head end 14 and a tail end 15, the head end 14 is connected to the RF input, the tail end 15 is grounded, and N is an integer greater than or equal to 4. The dielectric layer 24 covers the SOI substrate 10 and the transistor chain. The first to Nth conductive grounding layers 31 are arranged on the dielectric layer 24, and the first to Nth conductive grounding layers 31 are respectively arranged on the front sides of the first to Nth transistors 20, and the areas (facing areas) of the first to Nth conductive grounding layers 31 exposed to the front sides of the corresponding transistors 20 increase successively.

[0044] Please refer to Figure 2a , the SOI substrate 10 may include a silicon base layer 11, a buried oxide layer 12 and a top silicon layer 13 arranged in sequence, the side where the top silicon layer 13 is located may be the front side of the SOI substrate 10, and the side where the silicon base layer 11 is located may be the back side of the SOI substrate 10. The transistor chain is arranged on the front side of the SOI substrate 10, that is, formed on the top silicon layer 13, and may include a source-drain structure 22, a gate structure 21 and a source-drain lead-out structure 23. The transistor chain uses the top silicon layer 13 as an active area, the gate structure 21 is arranged on the top silicon layer 13, the source-drain structure 22 is located in the active area on both sides of the gate structure 21, the top silicon layer 13 between the source-drain structure 22 is a channel area, and the source-drain lead-out structure 23 is arranged above the gate structure 21 for electrically leading out the source-drain structure 22. As Figure 2b As shown, the gate structure 21 of the transistor 20 may be a first interdigitated structure, which includes a plurality of interdigitated fingers extending along a first direction X, the source-drain structure 22 includes a source terminal and a drain terminal alternately arranged on both sides of the interdigitated fingers along a second direction Y, and the source-drain lead-out structure 23 may include a plug and a first metal interconnection layer on the gate structure 21, which may include a source terminal lead-out structure 23a and a drain terminal lead-out structure 23b in the same layer and alternately arranged to electrically lead out the source terminal and the drain terminal respectively, and the source terminal lead-out structure 23a and the drain terminal lead-out structure 23b may both be second interdigitated structures, and the interdigitated fingers of the second interdigitated structure extend along the first direction X, and the first direction X and the second direction Y are orthogonal.

[0045] Specifically, in this embodiment, the transistor chain may include N transistors 20 (first to Nth transistors 20) connected in series between a head end 14 and a tail end 15, the head end 14 is connected to the RF input, and the tail end 15 is grounded, that is, the first transistor 20 is connected to the RF input, and the Nth transistor 20 is grounded, wherein each transistor 20 may be an nmos transistor with the same setting (same configuration) as described above, that is, the first to Nth transistors 20 have the same or substantially the same layout structure.

[0046] Please continue to refer to Figure 2a , the dielectric layer 24 may be an intermetallic dielectric layer covering the source-drain lead-out structure 23, and the first to Nth conductive grounding layers 31 may be other metal interconnection layers on the first metal interconnection layer (source-drain lead-out structure 23). In a preferred example, the first to Nth conductive grounding layers 31 may be arranged in the same layer (located in the same layer) as the grounding end of the RF switch structure and electrically connected. In this embodiment, the first to Nth conductive grounding layers 31 and the grounding ends of the RF switch structure (or the chip including the RF switch structure) are all arranged in the top metal interconnection layer. Please continue to refer to Figure 2b , the first to Nth conductive grounding layers 31 are respectively arranged above the dielectric layer 24 of the first to Nth transistors 20, and form corresponding parasitic capacitances with the gate structure 21, the source terminal lead structure 23a and the drain terminal lead structure 23b of the corresponding transistor 20. The above-mentioned parasitic capacitances may be parasitic capacitances of each transistor 20 to the ground, which may be respectively recorded as the first to Nth parasitic capacitances to the ground corresponding to the first to Nth transistors 20, and since the areas of the first to Nth conductive grounding layers 31 exposed to the front of the corresponding transistors 20 increase successively, the above-mentioned first to Nth parasitic capacitances to the ground increase successively, and the impedances of the first to Nth transistors 20 may be increased successively, and the impedance increase of the transistors closer to the tail end 15 is greater, so that similar Figure 1b The unbalanced voltage distribution shown is as balanced as possible, thereby balancing the processing power of each transistor 20, thereby improving the power handling capability of the RF switch structure, and also reducing the maximum voltage difference between the source and drain of each transistor 20, so as to reduce the risk of each transistor 20 being broken down by high voltage.

[0047] For details, please continue to refer to Figure 2b , the first to Nth conductive grounding layers 31 may all be rectangular in shape, and may all extend along the second direction Y, the second direction Y being orthogonal to the first direction X, i.e., the first to Nth conductive grounding layers 31 are perpendicular to the fingers of the first and second finger structures, and span all the fingers, so as to uniformly act on all the source-drain lead-out structures 23 and the gate structure 21 of the corresponding transistor 20. In addition to the first to Nth transistors 20, connecting wires are also provided to connect the first to Nth conductive grounding layers 31, which may, for example, extend along the first direction X and be connected to the grounding terminal of the same layer. In particular, under the layout structure in which the first to Nth transistors 20 have the same size as described above, the first to Nth conductive grounding layers 31 have successively increasing widths (along the first direction X) so that the exposed areas of the first to Nth conductive grounding layers 31 on the front of the first to Nth transistors 20 are successively increased, thereby increasing (increasing) the corresponding first to Nth parasitic capacitances to ground. This embodiment does not limit the increment of the width between the first to Nth conductive grounding layers 31 (i.e., the increment of the parasitic capacitance), and can reasonably set the width of the first to Nth conductive grounding layers 31 according to actual debugging experience and in combination with the simulation of the effect of the first to Nth conductive grounding layers 31 on the first to Nth transistors 20, that is, optimize the parasitic capacitance of the first to Nth transistors 20 to the ground. In a preferred example, Figure 2c The schematic diagram of the voltage distribution between the source and drain of each transistor 20 before and after optimization is shown in FIG. Figure 2c As shown, the first curve S1 is the voltage distribution between the source and drain of each transistor 20 in the related art (before optimization), and the second curve S2 is the voltage distribution between the source and drain of each transistor 20 after optimization in this embodiment. After optimization, the voltage distribution between the source and drain of each transistor 20 is basically the same. Of course, the width of the largest conductive ground layer 31 (i.e., the Nth conductive ground layer 31) is usually less than or equal to the width of the active area.

[0048] It can be understood that the above-mentioned N crystals can be parallel branches of the RF switch structure provided in this embodiment (i.e., one end is grounded). The RF switch structure provided in this embodiment may also include a series branch connected to the antenna. The series branch may include multiple transistors cascaded between the head end and the antenna, wherein the multiple transistors of the series branch have no corresponding relationship with the N transistors of the above-mentioned parallel branch, and the above-mentioned setting may not be adopted on the multiple transistors of the series branch.

[0049] Embodiment 2

[0050] Embodiment 2 provides a radio frequency switch structure.

[0051] Figure 3a A schematic cross-sectional view of a single transistor in the radio frequency switch structure provided in the second embodiment; Figure 3bThis is a top view schematic diagram of a transistor chain in a radio frequency switch structure provided in Example 2.

[0052] like Figure 3a and Figure 3b As shown, the RF switch structure provided in this embodiment includes an SOI substrate 10, a transistor chain, a dielectric layer 24, and first to Nth conductive grounding layers 31. The transistor chain is arranged on the front side of the SOI substrate 10, and includes first to Nth transistors 20 cascaded between a head end 14 and a tail end 15, the head end 14 is connected to the RF input, the tail end 15 is grounded, and N is an integer greater than or equal to 4. The dielectric layer 24 covers the SOI substrate 10 and the transistor chain. The first to Nth conductive grounding layers 31 are arranged on the back side of the SOI substrate 10, and the first to Nth conductive grounding layers 31 are respectively arranged on the back side of the first to Nth transistors 20, and the areas of the first to Nth conductive grounding layers 31 exposed to the back side of the corresponding transistors 20 increase sequentially.

[0053] The basic principle of the RF switch structure in the second embodiment is similar to that in the first embodiment, and the only difference is that the first to Nth conductive grounding layers 31 are arranged on the back of the SOI substrate 10, facing away from the first to Nth transistors 20 and forming corresponding first to Nth parasitic capacitances to ground, and the first to Nth parasitic capacitances to ground are increased in sequence by setting the areas (back-to-back areas) of the first to Nth conductive grounding layers 31 to increase the first to Nth parasitic capacitances to ground in sequence, thereby increasing the impedance of the first to Nth transistors 20 in sequence so that the voltage distribution of each transistor 20 (between the source and drain) is as balanced as possible, thereby balancing the processing power of each transistor 20 and improving the power processing capacity of the RF switch structure, and also reducing the maximum voltage difference between the source and drain of each transistor 20, so as to reduce the risk of each transistor 20 being broken down by high voltage. Of course, in this embodiment, the grounding terminal of the RF switch structure or the chip (semiconductor device) including the RF switch structure can also be arranged on the back of the SOI substrate 10 (i.e., arranged on the same layer). In one example, the first to Nth conductive grounding layers 31 and the above-mentioned grounding terminals can be redistribution lines arranged on the back of the SOI substrate 10.

[0054] Embodiment 3

[0055] Embodiment 3 provides a method for preparing a radio frequency switch structure.

[0056] Figure 4a This is a flow chart of a method for preparing a radio frequency switch structure provided in Example 3.

[0057] like Figure 4a As shown, the preparation method of the radio frequency switch structure shown in the first embodiment may include the following steps:

[0058] S01: providing an SOI substrate;

[0059] S02: forming a transistor chain on the front side of the SOI substrate, the transistor chain comprising first to Nth transistors cascaded between a head end and a tail end, the head end being connected to a radio frequency input, the tail end being grounded, and N being an integer greater than or equal to 4;

[0060] S03: forming a dielectric layer on the SOI substrate and the transistor chain;

[0061] S04: forming first to Nth conductive grounding layers on the dielectric layer, wherein the first to Nth conductive grounding layers are respectively arranged on the front sides of the first to Nth transistors, and areas of the first to Nth conductive grounding layers exposed to the front sides of the corresponding transistors increase sequentially.

[0062] Figure 5a to Figure 5d is a schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the radio frequency switch structure provided in Example 3. Next, Figure 5a to Figure 5d The preparation method of the radio frequency switch structure is described in detail.

[0063] First, please refer to Figure 5a , execute step S01 to provide an SOI substrate 10.

[0064] The SOI substrate 10 may include a silicon base layer 11, a buried oxide layer 12 and a top silicon layer 13. In this embodiment, the conductivity type of the top silicon layer 13 of the SOI substrate 10 may be P type to form a plurality of nmos transistors, thereby forming a radio frequency switch structure.

[0065] Next, please refer to Figure 5b , execute step S02, form a transistor chain on the front side of the SOI substrate 10, the transistor chain includes first to Nth transistors 20 cascaded between the head end 14 and the tail end 15, the head end 14 is connected to the RF input, the tail end 15 is grounded, and N is an integer greater than or equal to 4.

[0066] The first to Nth transistors 20 may all be nmos transistors of the same configuration (same size), which may include a source-drain structure 22, a gate structure 21, and a source-drain lead-out structure 23. The transistor chain uses the top silicon layer 13 as an active region, the gate structure 21 is disposed on the top silicon layer 13, the source-drain structure 22 is located in the active region on both sides of the gate structure 21, the top silicon layer 13 between the source-drain structure 22 is a channel region, and the source-drain lead-out structure 23 is disposed above the gate structure 21 for electrically leading out the source-drain structure 22. Among them, the gate structure 21, the source-drain structure 22, and the source-drain lead-out structure 23 may all be in the shape of an interdigitated structure.

[0067] Next, please refer to Figure 5c , executing step S03, forming a dielectric layer 24 on the SOI substrate 10 and the transistor chain.

[0068] The source-drain extraction structure 23 may include a plug on the gate structure 21 and a first metal interconnection layer, and the dielectric layer 24 covering the first to Nth transistors 20 may be an intermetallic dielectric layer in the interconnection structure layer.

[0069] Next, please refer to Figure 5d , execute step S04 to form first to Nth conductive grounding layers 31 on the dielectric layer 24, the first to Nth conductive grounding layers 31 are respectively arranged on the front sides of the first to Nth transistors 20, and the areas of the first to Nth conductive grounding layers 31 exposed to the front sides of the corresponding transistors 20 increase sequentially.

[0070] Among them, the first to Nth conductive grounding layers 31 can be other metal interconnection layers on the first metal interconnection layer (source-drain lead-out structure 23). In a preferred example, the first to Nth conductive grounding layers 31 can be arranged in the same layer (located in the same layer) as the grounding end of the RF switch structure and electrically connected, that is, the first to Nth conductive grounding layers 31 are formed at the same time as the grounding end of the RF switch structure is formed, thereby avoiding the additional increase of mask plates and photolithography times. In this embodiment, the grounding ends of the first to Nth conductive grounding layers 31 and the RF switch structure (or the chip including the RF switch structure) are all arranged in the top metal interconnection layer, that is, when the top metal interconnection layer is formed, the first to Nth conductive grounding layers 31 and the grounding end of the RF switch structure are formed at the same time.

[0071] Embodiment 4

[0072] Embodiment 4 provides a method for preparing a radio frequency switch structure.

[0073] Figure 4b This is a flow chart of a method for preparing a radio frequency switch structure provided in Example 4.

[0074] like Figure 4b As shown, the method for preparing the radio frequency switch structure provided in this embodiment may include the following steps:

[0075] S01: providing an SOI substrate;

[0076] S02: forming a transistor chain on the front side of the SOI substrate, the transistor chain comprising first to Nth transistors cascaded between a head end and a tail end, the head end being connected to a radio frequency input, the tail end being grounded, and N being an integer greater than or equal to 4;

[0077] S03: forming a dielectric layer on the SOI substrate and the transistor chain;

[0078] S04: forming first to Nth conductive grounding layers on the back side of the SOI substrate, wherein the first to Nth conductive grounding layers are respectively arranged on the back sides of the first to Nth transistors, and the areas of the first to Nth conductive grounding layers exposed to the back sides of the corresponding transistors increase sequentially.

[0079] The preparation method provided in the fourth embodiment is used to prepare the RF switch structure of the second embodiment, and its basic principle is similar to that of the preparation method of the third embodiment, and the only difference is that the first to Nth conductive grounding layers are formed on the back of the SOI substrate. In a preferred example, the grounding terminal of the RF switch structure or the chip including the RF switch structure is also provided on the back of the SOI substrate, and the first to Nth conductive grounding layers and the above-mentioned grounding terminals can all be redistribution lines provided on the back of the SOI substrate.

[0080] In summary, the RF switch structure provided by the present invention includes an SOI substrate; a transistor chain, which is arranged on the front side of the SOI substrate, and includes first to N-th transistors cascaded between a head end and a tail end, the head end is connected to the RF input, the tail end is grounded, and N is an integer greater than or equal to 4; a dielectric layer, covering the SOI substrate and the transistor chain; first to N-th conductive grounding layers arranged on the back side of the dielectric layer or the SOI substrate, the first to N-th conductive grounding layers are respectively arranged on the front side or back side of the first to N-th transistors, and the areas of the first to N-th conductive grounding layers exposed to the front side or back side of the corresponding transistors increase sequentially. Among them, since the areas of the first to Nth conductive grounding layers exposed to the front or back side of the corresponding transistors increase successively, the parasitic capacitance of the first to Nth conductive grounding layers relative to the first to Nth transistors to the ground increases successively, that is, the impedance of the first to Nth transistors increases successively, and the impedance increase is greater the closer to the tail end, thereby balancing the voltage distribution of each transistor and balancing the processing power of each transistor, thereby improving the power processing capacity of the RF switch structure, and can also reduce the maximum voltage difference distributed between the source and drain of each transistor, so as to reduce the risk of each transistor being broken down by high voltage.

[0081] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A radio frequency switch structure, characterized in that: include: SOI substrate; A transistor chain, arranged on the front side of the SOI substrate, comprising first to Nth transistors cascaded between a head end and a tail end, wherein the head end is connected to a radio frequency input, the tail end is grounded, and N is an integer greater than or equal to 4; A dielectric layer covering the SOI substrate and the transistor chain; The first to Nth conductive grounding layers are arranged on the dielectric layer or the back side of the SOI substrate, and the first to Nth conductive grounding layers are respectively arranged on the front side or the back side of the first to Nth transistors, and the areas of the first to Nth conductive grounding layers exposed to the front side or the back side of the corresponding transistors increase successively.

2. The radio frequency switch structure according to claim 1, characterized in that: The first to Nth conductive ground layers are all connected to a ground terminal of the radio frequency switch structure or a semiconductor device including the radio frequency switch structure.

3. The radio frequency switch structure according to claim 2, characterized in that: The first to Nth conductive grounding layers are arranged in the same layer as the grounding end of the radio frequency switch structure and are electrically connected.

4. The radio frequency switch structure according to claim 3, characterized in that: The first to Nth conductive grounding layers are located on the dielectric layer, and the first to Nth conductive grounding layers are top metal interconnection layers.

5. The radio frequency switch structure according to claim 3, characterized in that: The first to Nth conductive grounding layers are located on the back side of the SOI substrate, and the first to Nth conductive grounding layers are redistribution line layers.

6. The radio frequency switch structure according to claim 1, characterized in that: The first to Nth transistors have an interdigitated layout structure of the same size, the gate structures and source-drain structures of the first to Nth transistors extend along a first direction, the first to Nth conductive ground layers cross the gate structures and source-drain structures of the first to Nth transistors along a second direction, and the second direction is orthogonal to the first direction.

7. The radio frequency switch structure according to claim 6, characterized in that: The first to Nth conductive grounding layers are all rectangular in shape, and the widths of the first to Nth conductive grounding layers along the first direction increase sequentially.

8. A method for preparing a radio frequency switch structure, characterized in that: include: Providing an SOI substrate; A transistor chain is formed on the front side of the SOI substrate, wherein the transistor chain includes first to Nth transistors cascaded between a head end and a tail end, wherein the head end is connected to a radio frequency input, the tail end is grounded, and N is an integer greater than or equal to 4; forming a dielectric layer on the SOI substrate and the transistor chain; The first to Nth conductive grounding layers are formed on the surface of the dielectric layer or the back side of the SOI substrate, and the first to Nth conductive grounding layers are respectively arranged on the front side or the back side of the first to Nth transistors, and the areas of the first to Nth conductive grounding layers exposed to the front side or the back side of the corresponding transistor increase successively.

9. The method for preparing a radio frequency switch structure according to claim 8, characterized in that: The first to Nth conductive grounding layers are located on the dielectric layer, and the first to Nth conductive grounding layers are formed simultaneously when the top metal interconnection layer of the radio frequency switch structure is formed.

10. The method for preparing a radio frequency switch structure according to claim 8, characterized in that: The first to Nth conductive grounding layers are located on the back side of the SOI substrate, and the first to Nth conductive grounding layers are formed simultaneously when the redistribution line layer of the radio frequency switch structure is formed.

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