Device for interconnection and packaging circuit

Abstract

The embodiment of the invention discloses a device for interconnection and a packaging circuit. The interconnection device includes a first differential transmission line and a second differential transmission line. At least one of the positive line and the negative line of the first differential transmission line is disposed on the first layer of the substrate. The positive line of the second differential transmission line comprises a first part located on the first layer of the substrate and a second part located on the second layer of the substrate, the first part and the second part are connected through a first conductive through hole, and the negative line of the second differential transmission line comprises a third part located on the first layer of the substrate and a fourth part located on the second layer of the substrate. The third portion and the fourth portion are connected through a second conductive via, and the first conductive via and the second conductive via pass through the dielectric material layer between the first layer and the second layer.

Description

Technical Field

[0001] The present invention generally relates to the field of integrated circuits, and more particularly, to an apparatus for interconnecting and a packaged circuit. Background Art

[0002] In advanced packaging technology, multiple integrated circuit dies are located in the same package. The integrated circuit dies are interconnected by D2D (Die to Die). D2D interconnection requires low latency, low power consumption and high reliability. According to some D2D transmission standards, signals are transmitted in a differential form. When differential signal transmission lines transmit signals, electric and magnetic fields are generated. The energy coupling from a pair of differential signal transmission lines to adjacent differential signal transmission lines due to the electric and magnetic fields generated by the signal transmission lines is called crosstalk. As the communication frequency increases and the physical distance between signal transmission lines decreases, the impact of crosstalk on signal transmission becomes more and more serious. Crosstalk restricts the performance of interconnection between integrated circuit dies. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a device for interconnection and a packaging circuit to reduce crosstalk between differential signal transmission lines.

[0004] According to a first aspect of an embodiment of the present invention, a device for interconnection is provided. The device includes a first differential transmission line and a second differential transmission line. The first differential transmission line includes a positive line and a negative line, at least one of the positive line and the negative line is located on the first layer of the substrate. The second differential transmission line includes a positive line and a negative line. The positive line of the second differential transmission line includes a first portion located on the first layer of the substrate and a second portion located on the second layer of the substrate, the first portion and the second portion are connected through a first conductive via, the negative line of the second differential transmission line includes a third portion located on the first layer of the substrate and a fourth portion located on the second layer of the substrate, the third portion and the fourth portion are connected through a second conductive via, and the first conductive via and the second conductive via pass through a dielectric material layer between the first layer and the second layer.

[0005] Optionally, a distance between a first portion of the positive line of the second differential transmission line and the positive line of the first differential transmission line is equal to a distance between a third portion of the negative line of the second differential transmission line and the positive line of the first differential transmission line.

[0006] Optionally, the first portion and the second portion are of equal length, and the third portion and the fourth portion are of equal length.

[0007] Optionally, one of the positive line and the negative line of the first differential transmission line is arranged on a first layer of the substrate, and the other is arranged on a third layer of the substrate, and the first layer is between the second layer and the third layer.

[0008] Optionally, the first differential transmission line is set to multiple, the second differential transmission line is set to multiple, the device also includes a first shielding line and a second shielding line, the first shielding line is set in the third layer, the first shielding line is set between adjacent first differential transmission lines, the second shielding line is set in the second layer, and the second shielding line is set between adjacent second differential transmission lines.

[0009] According to a second aspect of an embodiment of the present invention, a packaged circuit is provided. The packaged circuit includes: a substrate; a first integrated circuit die and a second integrated circuit die located on the substrate; and a first differential transmission line and a second differential transmission line connecting the first integrated circuit die and the second integrated circuit die. The first differential transmission line includes a positive line and a negative line, and at least one of the positive line and the negative line is arranged on the first layer of the substrate. The second differential transmission line includes a positive line and a negative line. The positive line of the second differential transmission line includes a first part located on the first layer of the substrate and a second part located on the second layer of the substrate, and the first part and the second part are connected through a first conductive via, and the negative line of the second differential transmission line includes a third part located on the first layer of the substrate and a fourth part located on the second layer of the substrate, and the third part and the fourth part are connected through a second conductive via, and the first conductive via and the second conductive via pass through a dielectric material layer between the first layer and the second layer.

[0010] Optionally, a distance between a first portion of the positive line of the second differential transmission line and the positive line of the first differential transmission line is equal to a distance between a third portion of the negative line of the second differential transmission line and the positive line of the first differential transmission line.

[0011] Optionally, the first portion and the second portion are of equal length, and the third portion and the fourth portion are of equal length.

[0012] Optionally, one of the positive line and the negative line of the first differential transmission line is arranged on a first layer of the substrate, and the other is arranged on a third layer of the substrate, and the first layer is between the second layer and the third layer.

[0013] Optionally, the first differential transmission line is set to multiple, the second differential transmission line is set to multiple, the packaging circuit also includes a first shielding line and a second shielding line, the first shielding line is set on the third layer, the first shielding line is set between adjacent first differential transmission lines, the second shielding line is set on the second layer, and the second shielding line is set between adjacent second differential transmission lines.

[0014] According to the interconnection device and packaged circuit of the embodiment of the present invention, the first differential transmission line and the second differential transmission line are physically close, the positive line of the second differential transmission line includes a first part and a second part located in two layers, the negative line includes a third part and a fourth part located in two layers, the first part and the second part are connected through a conductive via, and the third part and the fourth part are connected through a conductive via. By adjusting the positions of the positive line and the negative line of the second differential transmission line, the crosstalk between the first differential transmission line and the second differential transmission line is reduced or eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0016] Figure 1 An integrated circuit die for D2D interconnection in an embodiment of the present invention is shown;

[0017] Figure 2 is a schematic block diagram of a packaging circuit according to an embodiment of the present invention;

[0018] Figure 3 is a schematic cross-sectional view of a packaged circuit according to an embodiment of the present invention;

[0019] Figure 4 is a cross-sectional view of a differential transmission line of an interconnect device in the related art;

[0020] Figure 5 is a cross-sectional view of a differential transmission line of an interconnect device according to an embodiment of the present invention;

[0021] Figure 6 is a schematic diagram of a second differential transmission line in an embodiment of the present invention;

[0022] Figure 7 yes Figure 5 A top view of the first layer L00 in FIG.

[0023] Figure 8 A top view showing an exemplary connection of a second differential transmission line;

[0024] Fig. 9 A cross-sectional view showing an exemplary connection of a second differential transmission line;

[0025] Fig.10 is a cross-sectional view of a differential transmission line of an interconnection device in another embodiment of the present invention;

[0026] Fig.11 yes Fig.10 A top view of the first layer L1;

[0027] Fig.12 yes Fig.10A top view of the second layer L2;

[0028] Fig.13 is a cross-sectional view of a differential transmission line of an interconnection device in another embodiment of the present invention;

[0029] Fig.14 A crosstalk simulation method for differential transmission lines of an interconnect device of the present invention is shown;

[0030] Fig.15 is a cross-sectional view of a differential transmission line of an interconnect device for comparison;

[0031] Fig.16 Shows Fig.14 The simulation results of the simulation method are shown. DETAILED DESCRIPTION

[0032] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.

[0033] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0034] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0035] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0036] The package provides protection for the chip and is a bridge for the chip to communicate with the external system. In advanced packaging technology (for example, 2.5D packaging, 3D packaging, Chiplet), multiple integrated circuit dies (also known as bare cores, Die) are packaged together. Multiple integrated circuit dies can be manufactured by different types of processes. In addition to communicating with external systems, the multiple dies communicate with each other. Multiple dies include, for example, logic chips, memory chips, analog circuit chips, sensor chips, etc. The communication between multiple dies is called D2D interconnection. As the communication frequency gets higher and higher, signal integrity becomes a bottleneck that restricts the increase in communication frequency. In order to suppress crosstalk, differential transmission lines are used for signal transmission lines. However, when the density of the signal transmission line is too large and the setting space of the signal transmission line is limited, the differential signal will also face the risk of excessive crosstalk.

[0037] Figure 1 An integrated circuit die 101 and an integrated circuit die 103 interconnected by D2D are shown. The integrated circuit die 101 and the integrated circuit die 103 each include an interface circuit, and a signal transmission line 111 is connected between the interface circuits of the integrated circuit die 101 and the integrated circuit die 103. The interface circuits of the integrated circuit die 101 and the integrated circuit die 103 are, for example, serial interconnect (SERDES) interface circuits, and the integrated circuit die 101 and the integrated circuit die 103 communicate according to the extremely short (XSR) or ultra-short distance (USR) standard. The signal transmission line 111 includes differential transmission lines 202 and 204. Each differential transmission line includes a positive line P and a negative line N, and the phases of the signals carried by the positive line and the negative line differ by 180 degrees. Generally, there is energy coupling between differential transmission lines that are physically close. The energy coupling between the parallel differential transmission lines 202 and 204 varies with the distance between the two and the differential signals carried by the two. Energy coupling causes crosstalk.

[0038] Figure 2 4 is a top view block diagram of a packaging circuit according to an embodiment of the present invention. Figure 3 is a cross-sectional view of the packaged circuit along a first direction. The first direction is Figure 2 The X direction in the second direction is Figure 2 The Y direction in the third direction is Figure 2 The first direction, the second direction and the third direction are perpendicular to each other. It should be understood that the sizes of the components are not necessarily to scale. For the purpose of illustrating the features described, some components may be exaggerated or emphasized in size or position. Figure 2 and Figure 3 As shown, the packaged circuit includes: a first integrated circuit die 101, a second integrated circuit die 103 and an interconnection device 105. The packaged circuit also includes a protection frame (not shown), and the first integrated circuit die 101, the second integrated circuit die 103 and the interconnection device 105 are accommodated in a space defined by the protection frame.

[0039] The packaged circuit includes at least two integrated circuit dies, thereby realizing computing power stacking or heterogeneous integration. The first integrated circuit die 101 and the second integrated circuit die 103 are bare dies. The first integrated circuit die 101 and the second integrated circuit die 103 are arranged on the interconnection device 105. The first integrated circuit die 101 and the second integrated circuit die 103 communicate through the interconnection device 105, and are also connected to an external system through the interconnection device 105.

[0040] The interconnection device 105 includes: a substrate 106, a solder ball 107 located on a first surface of the substrate 106, a solder ball 109 located on a second surface of the substrate 106, and a differential transmission line 111. The first surface and the second surface are opposite. The solder balls 107 and 109 are, for example, C4 solder balls (C4 bump) or C2 micro bumps (micro bump), but are not limited to these two types. The first integrated circuit die 101 and the second integrated circuit die 103 are connected to the interconnection device 105 through corresponding solder balls 107. The interconnection device 105, the first integrated circuit die 101 and the second integrated circuit die 103, for example, have pads, and the solder ball 107 is located between the corresponding pads. One end of the differential transmission line 111 is connected to the solder ball 107 corresponding to the interface circuit of the first integrated circuit die 101, and the other end is connected to the solder ball 107 corresponding to the interface circuit of the second integrated circuit die 103, thereby realizing the interconnection of the first integrated circuit die 101 and the second integrated circuit die 103. The differential transmission lines 111 are usually distributed in multiple layers of the substrate 106. Figure 2 As shown, the differential transmission line 111 includes an extension portion in the XY plane, the extension portion is located below the gap between the first integrated circuit die 101 and the second integrated circuit die 103, one end of the extension portion is connected to the first integrated circuit die 101 through a conductive via, and the other end is connected to the second integrated circuit die 103 through a conductive via. The conductive via is arranged along the third direction Z.

[0041] The interconnection device 105 further includes a signal line 115. The signal line 115 is used to connect the solder ball 107 on the first surface of the substrate 106 and the solder ball 109 on the second surface of the substrate 106. The signal line 115 includes, for example, a plated through-hole or a through silicon via (TSV). The signal line 115 includes, for example, a power line and a ground line. The first integrated circuit die 101 and the second integrated circuit die 103 are connected to power and ground through the signal line 115.

[0042] In some embodiments, the interconnection device 105 is formed on a silicon substrate or a glass substrate to form a differential transmission line 111, a signal line 115, and solder balls 107 and 109. The interconnection device 105 is also called a silicon interposer or a silicon bridge. In some embodiments, the interconnection device 105 is formed on an organic substrate to form a differential transmission line 111, a signal line 115, and solder balls 107 and 109.

[0043] Figure 4 A configuration of a differential transmission line in the related art is shown. Figure 4 is a cross-sectional view of the package substrate along the second direction Y. In this configuration, the positive lines and negative lines of the plurality of differential transmission lines are arranged on the same layer. Figure 4 As shown, the positive line P and the negative line N of the differential transmission lines 202 and 204 are arranged in the same layer, and shielding layers or shielding lines 201 and 203 are also arranged on the upper and lower sides of the layer. The shielding layers 201 and 203 are grounding layers. A dielectric material layer 205 is also arranged between the differential transmission lines 202 and 204 and the shielding layers 201 and 203. The dielectric material layer 205 provides insulation between the differential transmission lines 202 and 204 and between the differential transmission lines 202 and 204 and the shielding layers 201 and 203. Figure 4 In the configuration, the distance between the differential transmission negative line 204N and the differential transmission positive line 202P is smaller than the distance between the differential transmission positive line 204P and the differential transmission positive line 202P, so the crosstalk C1 of the differential transmission negative line 204N to the differential transmission positive line 202P is greater than the crosstalk C2 of the differential transmission positive line 204P to the differential transmission positive line 202P. Although the differential transmission negative line 204N and the differential transmission positive line 204P carry signals with opposite phases, the crosstalk C1 and the crosstalk C2 cannot be completely offset. Similarly, the crosstalk of the differential transmission negative line 204N to the differential transmission negative line 202N is greater than the crosstalk of the differential transmission positive line 204P to the differential transmission negative line 202N. That is, the crosstalk between the positive line P and the negative line N of the differential transmission lines 202 and 204 is large.

[0044] Figure 5 is a cross-sectional view of a differential transmission line of an interconnection device in an embodiment of the present invention. Figure 6 yes Figure 5 Schematic diagram of the connection relationship of the second differential transmission line 204. Figure 7 yes Figure 5 In the embodiment of the present invention, the differential transmission line 111 includes first differential transmission lines 202 and 206, and a second differential transmission line 204. The first differential transmission lines 202 and 206, and the second differential transmission line 204 each include a positive line P and a negative line N. The positive line 202P and the negative line 202N of the first differential transmission line 202, and the positive line 206P and the negative line 206N of the first differential transmission line 206 are both disposed on the first layer L00 of the substrate.

[0045] The positive line 204P of the second differential transmission line 204 includes a first portion 204P1 located on the first layer L00 of the substrate and a second portion 204P2 located on the second layer L01 of the substrate, and the first portion 204P1 and the second portion 204P2 are connected through a first conductive via 2045. Figure 5 In the illustrated embodiment, the second layer L01 is located below the first layer L00. The negative line 204N of the second differential transmission line 204 includes a third portion 204N1 located on the first layer L00 of the substrate and a fourth portion 204N2 located on the second layer L01 of the substrate, and the third portion 204N1 and the fourth portion 204N2 are connected via a second conductive via 2043. That is, the positive line 204P and the negative line 204N of the second differential transmission line 204 both include a portion located on the first layer L00 and a portion located on the second layer L01, and the portion located on the first layer L00 and the portion located on the second layer L01 are connected via conductive vias to achieve layer switching of the transmission line. The first layer L00 and the second layer L01 correspond to the above-mentioned extension portion.

[0046] like Figure 7 As shown in the top view of FIG. 1 , the first portion 204P1 and the third portion 204N1 are both located in the first layer L00 and aligned in the second direction Y. The first portion 204P1 and the third portion 204N1 are separated by a dielectric material. The second portion 204P2 and the fourth portion 204N2 are both located in the second layer L01 and aligned in the second direction Y. The second portion 204P2 and the fourth portion 204N2 are also separated by a dielectric material. The first portion 204P1, the third portion 204N1, the second portion 204P2 and the fourth portion 204N2 are all parallel to the first differential transmission lines 202 and 206. The first portion 204P1 is located above the fourth portion 204N2, and the third portion 204N1 is located above the second portion 204P2.

[0047] Figure 8 and Fig. 9 An exemplary connection manner of the first portion 204P1 and the second portion 204P2 is shown, as well as an exemplary connection manner of the third portion 204N1 and the fourth portion 204N2. Figure 8 It is a top view, which is a view looking at the interconnection device from a third direction Z. Fig. 9 is a cross-sectional view, which is a view looking at the interconnection device from the second direction Y. Figure 8 In the figure, the solid line indicates that it is located in the first layer L00, and the dotted line indicates that it is located in the second layer L01. Figure 8 (A) is a top view of the negative line 204N of the second differential transmission line 204. Figure 8(B) is a top view structure of the positive line 204P of the second differential transmission line 204. The negative line 204N of the second differential transmission line 204 also includes an extension portion 2041 and an extension portion 2042. The extension portion 2041 is disposed on the first layer L00 and extends outward from the third portion 204N1. The extension portion 2041 and the third portion 204N1 are formed integrally. The extension portion 2042 is disposed on the second layer L01 and extends outward from the fourth portion 204N2. The extension portion 2042 and the fourth portion 204N2 are formed integrally. In the third direction Z, the extension portion 2041 and the extension portion 2042 have an overlapping area, and the second conductive through-hole 2043 is disposed in the overlapping area and passes through the dielectric material layer 205 between the first layer L00 and the second layer L01, thereby connecting the extension portion 2041 and the extension portion 2042. The shapes of the extension portion 2041 and the extension portion 2042 are not limited to Figure 8 The first portion 204P1 and the second portion 204P2 have an overlapping region, and the first conductive via 2045 is disposed in the overlapping region and passes through the dielectric material layer 205 between the first layer L00 and the second layer L01.

[0048] In other embodiments, the positive line 204P of the second differential transmission line 204 includes two extensions, the first conductive via 2045 is disposed in the overlapping region of the extensions, the negative line 204N of the second differential transmission line 204 is not provided with an extension, and the second conductive via 2043 is disposed in the overlapping region of the third portion 204N1 and the fourth portion 204N2.

[0049] In some other embodiments, the negative line 204N of the second differential transmission line 204 includes two extensions. Figure 8 The second conductive through hole 2043 is arranged in the overlapping area of ​​the two extensions. The positive line 204P of the second differential transmission line 204 includes two extensions. Figure 8 The first conductive through hole 2045 is arranged in the overlapping area of ​​the two extension parts.

[0050] The above three methods of layer switching of the positive line 204P and the negative line 204N of the second differential transmission line 204 are only examples, and layer switching can also be achieved by other methods.

[0051] like Figure 5-8As shown, the first portion 204P1 and the third portion 204N1 located in the first layer L00 are at the same distance from the negative line 202N of the first differential transmission line 202. Since the first portion 204P1 and the third portion 204N1 carry signals with the same amplitude but opposite phases, the crosstalk generated by the first portion 204P1 and the third portion 204N1 on the first differential transmission negative line 202N is substantially the same, and can be substantially offset, thereby reducing or eliminating the crosstalk of the second differential transmission line 204 on the first differential transmission negative line 202N. Similarly, the crosstalk generated by the first portion 204P1 and the third portion 204N1 on the first differential transmission positive line 202P is substantially the same, but can be offset. The distances between the second portion 204P2 and the fourth portion 204N2 of the second layer L01 and the negative line 202N of the first differential transmission line 202 are the same, and the crosstalk generated by the second portion 204P2 and the fourth portion 204N2 on the first differential transmission negative line 202N can also be offset. In this way, the crosstalk between physically close differential transmission lines is substantially eliminated.

[0052] Preferably, the lengths of the first portion 204P1 and the second portion 204P2 are equal, and the lengths of the third portion 204N1 and the fourth portion 204N2 are equal, so as to ensure that the crosstalk generated by the first portion 204P1 and the third portion 204N1 are offset, and the crosstalk generated by the second portion 204P2 and the fourth portion 204N2 are offset.

[0053] exist Figure 5 In the corresponding embodiment, the first layer L00 is above the second layer L01. In another embodiment, the first layer L00 is below the second layer L01, the first differential transmission lines 202 and 206, the first portion 204P1 of the second differential transmission positive line 204P and the third portion 204N1 of the second differential transmission negative line 204N are all located in the first layer L00, and the second portion 204P2 of the second differential transmission positive line 204P and the fourth portion 204N2 of the second differential transmission negative line 204N are located in the second layer L01 above.

[0054] In the above embodiment, the positive line and the negative line of the first differential transmission line are located in the same layer. In other embodiments, the positive line and the negative line of the first differential transmission line are located in different layers. Fig.10 is a cross-sectional view of a differential transmission line of an interconnection device in another embodiment of the present invention. Fig.11 yes Fig.10 A top view of the first layer L1 in FIG. Fig.12 yes Fig.10 A top view of the second layer L2.

[0055] like Fig.10As shown, the first differential transmission positive lines 202P and 206P, the first portion 204P1 of the second differential transmission positive line 204P, and the third portion 204N1 of the second differential transmission negative line 204N are located in the first layer L1, the second portion 204P2 of the second differential transmission positive line 204P and the fourth portion 204N2 of the second differential transmission negative line 204N are located in the second layer L2, and the first differential transmission negative lines 202N and 206N are located in the third layer L3. The first layer L1 is located between the second layer L2 and the third layer L3. From the perspective of the top view, a plurality of first differential transmission lines and a plurality of second differential transmission lines are alternately arranged.

[0056] The second differential transmission positive line 204P includes a first portion 204P1 located in the first layer L1 and a second portion 204P2 located in the second layer L2, and the first portion 204P1 and the second portion 204P2 are connected through a first conductive via. The second differential transmission negative line 204N includes a third portion 204N1 located in the first layer L1 and a fourth portion 204N2 located in the second layer L2, and the third portion 204N1 and the fourth portion 204N2 are connected through a second conductive via. That is, the second differential transmission positive line 204P and the second differential transmission negative line 204N are both arranged in alternating layers in the first layer L1 and the second layer L2. The arrangement of the first conductive via and the second conductive via can refer to Figure 8 and Fig. 9 .

[0057] The first part 204P1 of the second differential transmission positive line 204P and the third part 204N1 of the second differential transmission negative line 204N are at the same distance from the first differential transmission positive line 202P (206P), and transmit signals with the same amplitude and opposite phases, so the crosstalk of the first part 204P1 and the third part 204N1 to the first differential transmission positive line 202P (206P) can be reduced or offset. In addition, by increasing the number of layers of the signal transmission line, the coupling between the signal transmission lines can be further reduced, and the mutual interference between the signal transmission lines can be reduced.

[0058] The interconnection device also includes a first shielding line 207 and a second shielding line 209. The first shielding line 207 is arranged on the third layer L3. In the third layer L3, the first shield 207 is arranged between adjacent first differential transmission lines 202 and 206. The second shielding line 209 is arranged on the second layer L2. In the second layer L2, the second shield 209 is arranged between adjacent second differential transmission lines 204. The first shielding line 207 and the second shielding line 209 are metal lines and are grounded. The width of the first shielding line 207 and the second shielding line 209 is greater than the width of the differential transmission line. The first shielding line 207 and the second shielding line 209 separate the differential transmission lines, which can further reduce the mutual interference between the signal transmission lines.

[0059] In another embodiment, the first differential transmission negative lines 202N and 206N, the first portion 204P1 of the second differential transmission positive line 204P, and the third portion 204N1 of the second differential transmission negative line 204N are located in the first layer L1, the second portion 204P2 of the second differential transmission positive line 204P and the fourth portion 204N2 of the second differential transmission negative line 204N are located in the second layer L2, and the first differential transmission positive lines 202P and 206P are located in the third layer L3. The first layer L1 is located between the second layer L2 and the third layer L3. Compared to Fig.10 In the embodiment, the arrangement positions of the first differential transmission negative lines 202N and 206N and the arrangement positions of the first differential transmission positive lines 202P and 206P are swapped.

[0060] Fig.13 FIG. 2 is a cross-sectional view of a differential transmission line of an interconnection device in another embodiment of the present invention. In this embodiment, differential transmission lines 202 and 206 are arranged across layers. Fig.13 As shown, the positive line 202P of the differential transmission line 202 includes a first portion 202P1 located at layer L1 and a second portion 202P2 located at layer L3, the first portion 202P1 and the second portion 202P2 are connected through a conductive via, and the negative line 202N of the differential transmission line 202 includes a third portion 202N1 located at layer L1 and a fourth portion 202N2 located at layer L3, the third portion 202N1 and the fourth portion 202N2 are connected through a conductive via. The first portion 202P1 of the differential transmission positive line 202P, the third portion 202N1 of the differential transmission negative line 202N, and the negative line 204N of the differential transmission line 204 are arranged at layer L1, the positive line 204P of the differential transmission line 204 is arranged at layer L2, and the second portion 202P2 of the differential transmission positive line 202P and the fourth portion 202N2 of the differential transmission negative line 202N are arranged at layer L3. At this time, the differential transmission lines 202 and 206 can be understood as the second differential transmission line, the differential transmission line 204 can be understood as the first differential transmission line, the layer L1 is the first layer, the layer L3 is the second layer, and the layer L2 is the third layer.

[0061] In order to verify the anti-crosstalk capability of the interconnection device of the present invention, Fig.10 The interconnect arrangement shown was simulated. Fig.14The crosstalk simulation method of the differential transmission line of the interconnection device of the present invention is shown. A differential signal Sig is input at one end IN of the second differential transmission line 204. The differential signal Sig includes two components with the same amplitude and opposite phases, which are applied to the positive line and the negative line of the second differential transmission line 204 respectively. No signal is applied to the IN end of the first differential transmission line 202. The signal Det is detected at the opposite end OUT of the first differential transmission line 202. The detection signal Det is also a differential signal, and the detection signal Det is obtained based on the signal detected at the opposite end OUT of the positive line and the negative line of the first differential transmission line 202. In this way, the detection signal Det reflects the crosstalk of the signal transmission of the second differential transmission line 204 to the first differential transmission line 202.

[0062] Fig.15 2 is a cross-sectional view of a differential transmission line of an interconnect device for comparison. In this comparative example, the positive line and the negative line of the differential transmission lines 202 and 204 are not arranged across layers. The positive line 202P of the differential transmission line 202 and the negative line 204N of the differential transmission line 204 are arranged on layer L1, the negative line 202N of the differential transmission line 202 is arranged on layer L3, and the positive line 204P of the differential transmission line 204 is arranged on layer L2.

[0063] Fig.16 The simulation results are shown in Fig.16 In the figure, the horizontal axis represents the frequency of the input signal Sig, and the vertical axis represents the crosstalk (in dB). The calculation formula of the vertical axis is b*lg(Sig / Det), where b is the coefficient. Curve 1 is Fig.10 The differential transmission line crosstalk simulation results of the interconnection device of the present invention are shown in FIG. 2 , where curve 2 is Fig.15 The differential transmission line crosstalk simulation results of the interconnect device are shown as a comparison. Fig.16 As shown, curve 1 is substantially below curve 2, and the solution of the present invention reduces the crosstalk between differential transmission lines. For example, when the frequency of the input signal Sig is 28 GHz, Fig.10 The simulation result of the crosstalk between the differential transmission lines is -44dB. Fig.15 The simulation result of crosstalk between differential transmission lines is shown to be -40dB.

[0064] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A device for interconnection, comprising: a first differential transmission line, comprising a positive line and a negative line, wherein at least one of the positive line and the negative line is located on a first layer of the substrate; and The second differential transmission line includes a positive line and a negative line, The positive line of the second differential transmission line includes a first portion located on the first layer of the substrate and a second portion located on the second layer of the substrate, the first portion and the second portion are connected through a first conductive via, the negative line of the second differential transmission line includes a third portion located on the first layer of the substrate and a fourth portion located on the second layer of the substrate, the third portion and the fourth portion are connected through a second conductive via, and the first conductive via and the second conductive via pass through a dielectric material layer between the first layer and the second layer.

2. The device according to claim 1, wherein: The distance between the first portion of the positive line of the second differential transmission line and the positive line of the first differential transmission line is equal to the distance between the third portion of the negative line of the second differential transmission line and the positive line of the first differential transmission line.

3. The device according to claim 1, wherein: The first portion and the second portion have the same length, and the third portion and the fourth portion have the same length.

4. The device according to claim 1, wherein: One of the positive line and the negative line of the first differential transmission line is disposed on a first layer of the substrate, and the other is disposed on a third layer of the substrate, and the first layer is between the second layer and the third layer.

5. The device according to claim 4, wherein: The first differential transmission line is arranged in a plurality, the second differential transmission line is arranged in a plurality, the device further comprises a first shielding line and a second shielding line, the first shielding line is arranged in the third layer, the first shielding line is arranged between adjacent first differential transmission lines, the second shielding line is arranged in the second layer, and the second shielding line is arranged between adjacent second differential transmission lines.

6. A packaged circuit, comprising: substrate; a first integrated circuit die and a second integrated circuit die located on the substrate; as well as a first differential transmission line and a second differential transmission line connecting the first integrated circuit die and the second integrated circuit die, Wherein, the first differential transmission line comprises a positive line and a negative line, and at least one of the positive line and the negative line is located on the first layer of the substrate; The second differential transmission line includes a positive line and a negative line, The positive line of the second differential transmission line includes a first portion located on the first layer of the substrate and a second portion located on the second layer of the substrate, the first portion and the second portion are connected through a first conductive via, the negative line of the second differential transmission line includes a third portion located on the first layer of the substrate and a fourth portion located on the second layer of the substrate, the third portion and the fourth portion are connected through a second conductive via, and the first conductive via and the second conductive via pass through a dielectric material layer between the first layer and the second layer.

7. The packaged circuit according to claim 6, wherein: The distance between the first portion of the positive line of the second differential transmission line and the positive line of the first differential transmission line is equal to the distance between the third portion of the negative line of the second differential transmission line and the positive line of the first differential transmission line.

8. The packaged circuit according to claim 6, wherein: The first portion and the second portion have the same length, and the third portion and the fourth portion have the same length.

9. The packaged circuit according to claim 6, wherein: One of the positive line and the negative line of the first differential transmission line is disposed on a first layer of the substrate, and the other is disposed on a third layer of the substrate, and the first layer is between the second layer and the third layer.

10. The packaged circuit according to claim 9, wherein: The first differential transmission line is arranged in a plurality, the second differential transmission line is arranged in a plurality, the packaged circuit further comprises a first shielding line and a second shielding line, the first shielding line is arranged in the third layer, the first shielding line is arranged between adjacent first differential transmission lines, the second shielding line is arranged in the second layer, and the second shielding line is arranged between adjacent second differential transmission lines.

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