Overvoltage protection circuit applied to step-down DC-DC converter and step-down DC-DC converter

Abstract

The invention provides an overvoltage protection circuit applied to a step-down DC-DC converter and the step-down DC-DC converter. The overvoltage protection circuit comprises a first voltage end used for providing feedback voltage, a second voltage end used for providing reference voltage, a comparator, an upper tube control drive circuit and a lower tube drive control circuit. The step-down DC-DC converter comprises an overvoltage protection circuit, a voltage input end, a high-side power tube, a low-side power tube, an inductor and a capacitor. And when the feedback voltage is greater than the reference voltage, the high-side power tube is controlled to be switched off through the upper tube control driving circuit, and the low-side power tube is controlled to be switched on periodically through the lower tube control driving circuit. Thus, overvoltage protection of the step-down DC-DC converter is realized by controlling turn-off of the high-side power tube and periodic turn-on of the low-side power tube, and meanwhile, compared with a traditional technology of simultaneously controlling turn-off of the high-side power tube and the low-side power tube, release of output-stage energy and recovery of an output overvoltage state of the DC-DC converter are facilitated.

Description

Technical Field

[0001] The present application relates to the technical field of overvoltage protection circuits, and in particular to an overvoltage protection circuit and a step-down DC-DC converter applied to a step-down DC-DC converter. Background Art

[0002] When designing a step-down DC-DC converter, it is necessary to ensure that the load and the converter itself can be protected when the output voltage is over-voltage. To this end, when the output voltage is high, the high-side power tube and the low-side power tube can be controlled to effectively protect the step-down DC-DC converter and its output stage circuit.

[0003] Traditional overvoltage protection circuits used in step-down DC-DC converters are as follows: Figure 1 As shown, it includes a comparator, a LOGIC (logic) module, and a DRIVER (drive) module. Among them, the voltage comparator is used to compare the feedback signal VFB of the output voltage with the reference voltage VREF, and convert the comparison result into an excitation signal and transmit it to the LOGIC module. When it is detected that the feedback signal VFB is greater than the reference voltage VREF, it means that an overvoltage condition occurs, and the LOGIC module and the DRIVER module jointly control the high-side power tube and the low-side power tube to turn off to protect the circuit.

[0004] However, when the voltage of the external power load is too large, the above-mentioned conventional technology takes the measure of simultaneously shutting down the high-side power tube and the low-side power tube of the DC-DC converter, which causes the overvoltage on the external power load to be stored in the external power load, thereby failing to release the output-level energy of the overvoltage. At the same time, since the voltage on the external power load is too large, it means that the output voltage of the DC-DC converter is too large. Therefore, when the high-side power tube and the low-side power tube of the DC-DC converter are both shut down, the output voltage of the DC-DC converter cannot be changed, resulting in the problem that the overvoltage state cannot be restored. Summary of the invention

[0005] The present application provides an overvoltage protection circuit and a step-down DC-DC converter which are intended to facilitate output stage energy release and recovery from an overvoltage state of a DC-DC converter output.

[0006] The present application provides an overvoltage protection circuit applied to a step-down DC-DC converter, which is used to control the on or off of a high-side power tube and a low-side power tube of the step-down DC-DC converter. The overvoltage protection circuit includes: A first voltage terminal for providing a feedback voltage and a second voltage terminal for providing a reference voltage; A comparator, wherein a positive input terminal of the comparator is connected to the first voltage terminal, and a negative input terminal of the comparator is connected to the second voltage terminal; An upper tube control driving circuit, wherein an input end of the upper tube control driving circuit is connected to an output end of the comparator, and an output end is connected to a control end of the high-side power tube; A lower tube control driving circuit, wherein the input end of the lower tube control driving circuit is connected to the output end of the comparator, and the output end is connected to the control end of the low-side power tube; When the feedback voltage is greater than the reference voltage, the high-side power tube is turned off by the upper tube control driving circuit, and the low-side power tube is periodically turned on by the lower tube control driving circuit.

[0007] Optionally, it further includes a current protection control circuit connected to the lower tube control drive circuit, wherein the current protection control circuit includes a zero current control mode and a backflow current control mode; The current protection control circuit switches between the zero current control mode and the backflow current control mode according to a comparison result between the feedback voltage and the reference voltage.

[0008] Optionally, the current protection control circuit is preset with a backflow current detection threshold; when the current protection control circuit is in the backflow current control mode, it is used to detect the current of the inductor in the step-down DC-DC converter, and when the current of the inductor is greater than the backflow current detection threshold, the lower tube control drive circuit turns off the low-side power tube.

[0009] Optionally, the upper tube control driving circuit includes an upper tube opening control circuit and an upper tube driving circuit; the upper tube opening control circuit and the upper tube driving circuit are sequentially connected between the output end of the comparator and the control end of the high-side power tube; When the feedback voltage is greater than the reference voltage, the upper tube opening control circuit is used to generate a first shutoff excitation signal, so that the upper tube driving circuit controls the high-side power tube to shut down; or When the feedback voltage is less than the reference voltage, the upper tube turn-on control circuit is used to generate a first conduction excitation signal, so that the upper tube driving circuit controls the high-side power tube to turn on.

[0010] Optionally, the lower tube control driving circuit includes a lower tube opening control circuit and a lower tube driving circuit; the lower tube opening control circuit and the lower tube driving circuit are sequentially connected between the output end of the comparator and the control end of the low-side power tube; When the feedback voltage is greater than the reference voltage, the lower tube turn-on control circuit is used to generate a second conduction excitation signal, so that the lower tube drive circuit controls the low-side power tube to turn on; or When the feedback voltage is less than the reference voltage, the lower tube opening control circuit is used to generate a second closing excitation signal, so that the lower tube driving circuit controls the low-side power tube to be turned on.

[0011] Optionally, the lower tube opening control circuit is interactively connected with the current protection control circuit; When the feedback voltage is greater than the reference voltage, the lower tube opening control circuit outputs the second conduction excitation signal, so that the current protection control circuit generates an enable signal to detect the current of the inductor in the step-down DC-DC converter.

[0012] Optionally, the overvoltage protection circuit includes a power supply end; the lower tube opening control circuit includes a first inverter, a second inverter, a first current source, a first capacitor, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a third inverter, a first NOR gate, a second current source, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, and a seventh PMOS tube; Among them, the first inverter and the second inverter are connected in series with each other and are connected to the current protection control circuit; one end of the first current source is connected to the power supply end, and the other end is grounded through the first capacitor; the drain of the first NMOS tube is connected to the other end of the first current source, the source is grounded, and the gate is connected between the first inverter and the second inverter; the gate of the second NMOS tube is connected to the gate of the third NMOS tube, and the source of the second NMOS tube and the source of the third NMOS tube are both grounded; the gate of the third NMOS tube is short-circuited with its drain; the gate of the fourth NMOS tube is connected to the gate of the fifth NMOS tube, and the source of the fourth NMOS tube and the source of the fifth NMOS tube are both grounded; the gate of the fourth NMOS tube is short-circuited with its drain; the first input end of the first NOR gate is connected to the first enable signal, and the second input end thereof is connected to the second enable signal; the input end of the third inverter is connected to the output end of the first NOR gate; the gate of the sixth NMOS tube is connected to the output end of the third inverter, and the drain is connected to the fifth NMOS The drain of the tube is connected to the ground; the gate of the first PMOS tube is connected to the third enable signal, the drain is connected to the drain of the second NMOS tube, and the source is connected to the power supply terminal; the second current source is connected to the power supply terminal; the source of the second PMOS tube is connected to the second current source, and the gate is connected to the first enable signal; the source of the third PMOS tube is connected to the drain of the second PMOS tube, the gate is connected to the drain of the first NMOS tube, and the drain is connected to the drain of the third NMOS tube; the source of the fourth PMOS tube is connected to the drain of the second PMOS tube, the gate is connected to the first voltage terminal, and the drain is connected to the drain of the fourth NMOS tube; the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, the source is connected to the power supply terminal, the drain is short-circuited with its gate and connected to the drain of the second NMOS tube; the source of the sixth PMOS tube is connected to the power supply terminal, and the drain is connected to the drain of the fifth NMOS tube; the gate of the seventh PMOS tube is connected to the output terminal of the second inverter, the source is connected to the power supply terminal, and the drain is connected to the lower tube driving circuit and short-circuited with the source.

[0013] Optionally, the lower tube driving circuit includes a plurality of inverters, the number of the plurality of inverters is an even number, and the plurality of inverters are connected in series in sequence, wherein the input end of the first inverter is connected between the drain of the sixth PMOS tube and the drain of the fifth NMOS tube, and the output end is connected to the input end of the next inverter; the input end of the last inverter is connected to the output end of the previous inverter, and the output end is connected to the control end of the low-side power tube and the current protection control circuit; or, The lower tube driving circuit includes at least one phase regulator, the input end of the phase regulator is connected between the drain of the sixth PMOS tube and the drain of the fifth NMOS tube, and the output end is connected to the control end of the low-side power tube and the current protection control circuit.

[0014] Optionally, the lower tube opening control circuit includes a first inverter; the current protection control circuit includes a first trigger, a fourth inverter, a second NOR gate, a first transmission gate, a second transmission gate, a fifth inverter, a sixth inverter, a second trigger and a third NOR gate; Among them, the set end of the first trigger is connected to the output end of the lower tube driving circuit, and the reset end is connected to the signal switching between the zero current control mode and the backflow current control mode, and the switching signal includes a zero current control signal or a backflow current control signal; the input end of the fourth inverter is connected to the reset end of the first trigger; one input end of the second NOR gate is connected to the reset end of the first trigger, and the other input end is connected to the output end of the first trigger; the input end of the first transmission gate is connected to the output end of the fourth inverter, the positive control end of the first transmission gate is connected to the non-control end of the second transmission gate, and the non-control end of the first transmission gate is connected to the first enable signal; the input end of the second transmission gate is connected to the output end of the second NOR gate, and the positive control end of the second transmission gate is connected to the first enable signal; The input end of the fifth inverter is connected to the first enable signal and is connected between the positive control end of the first transmission gate and the non-control end of the second transmission gate, and the output end is connected between the non-control end of the first transmission gate and the positive control end of the second transmission gate; the input end of the sixth inverter is connected to the zero current detection clock signal, and the output end is connected to the reset end of the second trigger; The set end of the second trigger is connected to the output end of the first transmission gate and the output end of the second transmission gate; the first input end of the third NOR gate is connected to the test signal, the second input end is connected to the output end of the second trigger, and the output end is connected to the input end of the first inverter.

[0015] The present application also provides a step-down DC-DC converter, which includes the overvoltage protection circuit as described above, the overvoltage protection circuit includes an upper tube control drive circuit and a lower tube control drive circuit; and a voltage input end, a high-side power tube, a low-side power tube, an inductor and a capacitor; wherein the control end of the high-side power tube is connected to the upper tube control drive circuit, and the source is connected to the voltage input end; the control end of the low-side power tube is connected to the lower tube control drive circuit, and the source is grounded; one end of the inductor is connected to the drain of the high-side power tube and the drain of the low-side power tube, and the other end is connected to the positive electrode of the external power load; one end of the capacitor is connected between the other end of the inductor and the positive electrode of the external power load, and the other end is connected between the negative electrode of the external power load and the ground.

[0016] The beneficial effect of the present invention is: to provide an overvoltage protection circuit and a step-down DC-DC converter for a step-down DC-DC converter. The overvoltage protection circuit includes a first voltage terminal for providing a feedback voltage and a second voltage terminal for providing a reference voltage, and a comparator, an upper tube control drive circuit, and a lower tube drive control circuit. When the feedback voltage is greater than the reference voltage, the high-side power tube is turned off by the upper tube control drive circuit, and the low-side power tube is controlled to be periodically turned on by the lower tube control drive circuit. In this way, by controlling the high-side power tube to be turned off and the low-side power tube to be periodically turned on, overvoltage protection for the step-down DC-DC converter is achieved. At the same time, compared with the traditional technology of simultaneously controlling the high-side and low-side power tubes to be turned off, it is beneficial to the release of output stage energy and the recovery of the DC-DC converter output overvoltage state.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a conventional step-down DC-DC converter.

[0019] Figure 2 A step-down DC-DC converter is provided in accordance with an embodiment of the present application.

[0020] Figure 3 for Figure 2 The illustrated embodiment is a specific circuit diagram of a lower tube control driving circuit in an overvoltage protection circuit of a step-down DC-DC converter.

[0021] Figure 4 for Figure 2 The illustrated embodiment is a specific circuit diagram of a current protection control circuit in an overvoltage protection circuit of a step-down DC-DC converter.

[0022] Figure 5The present application provides a timing waveform diagram of a second enable signal EN2, a lower tube drive signal L_ctrl, a switching signal ZC-EN and a zero current detection clock signal ZC in an overvoltage protection circuit applied to a step-down DC-DC converter. DETAILED DESCRIPTION

[0023] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices consistent with some aspects of the present application as detailed in the appended claims.

[0024] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not indicate a quantitative limit, but indicate that there is at least one. If it only refers to "one", it will be explained separately. "Multiple" or "several" means two or more. Unless otherwise specified, similar words such as "front", "rear", "lower" and / or "upper" are only for the convenience of explanation and are not limited to one position or one spatial orientation. Similar words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" cover the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect. The singular forms "a", "said" and "the" used in this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0025] like Figure 2As shown, the present application provides a step-down DC-DC converter 1, which includes an overvoltage protection circuit 2 and a voltage input terminal VIN, a high-side power tube 3, a low-side power tube 4, an inductor L and a capacitor C. Among them, the overvoltage protection circuit 2 includes an upper tube control drive circuit 5 and a lower tube control drive circuit 6. The control end of the high-side power tube 3 is connected to the output end of the upper tube control drive circuit 5, and the source is connected to the voltage input terminal VIN; the control end of the low-side power tube 4 is connected to the output end of the lower tube control drive circuit 6, and the source is grounded; one end of the inductor L is connected to the drain of the high-side power tube 3 and the drain of the low-side power tube 4, and the other end is connected to the positive electrode of the external power load 7; one end of the capacitor C is connected between the other end of the inductor L and the positive electrode of the external power load 7, and the other end is connected between the negative electrode of the external power load 7 and the ground. In this embodiment, when an overvoltage occurs, the overvoltage protection circuit 2 controls the high-side power tube 3 to turn off through the upper tube control driving circuit 5, and controls the low-side power tube 4 to be periodically turned on through the lower tube control driving circuit 6, thereby realizing overvoltage protection for the step-down DC-DC converter 1. Compared with the prior art of simultaneously controlling the high and low-side power tubes to turn off, the overvoltage protection circuit 1 in this application is conducive to the release of output stage energy and the recovery of the DC-DC converter output overvoltage state. At the same time, the overvoltage protection circuit 1 in this application also has a backflow current detection function, by detecting the current of the inductor L, and comparing the current value of the inductor L with its own preset backflow current detection threshold, when the current value of the inductor L is higher than the backflow current detection threshold, the overvoltage protection circuit 1 can control the low-side power tube 4 to turn off to prevent the low-side power tube 4 from being broken down. In this embodiment, the backflow current detection function of the overvoltage protection circuit 1 is only briefly described. In the following, this application will elaborate on the specific working principle, implementation method and application effect of the backflow current detection function of the overvoltage protection circuit 1.

[0026] In some embodiments, the overvoltage protection circuit 1 further includes a first voltage terminal VFB for providing a feedback voltage and a second voltage terminal VREF for providing a reference voltage, and a comparator 8. The positive input terminal of the comparator 8 is connected to the first voltage terminal VFB, and the negative input terminal is connected to the second voltage terminal VREF. The output terminal of the comparator 8 is connected to the input terminal of the upper tube control drive circuit 5 and the input terminal of the lower tube control drive circuit 6. When the feedback voltage is greater than the reference voltage, that is, when an overvoltage occurs, the comparator 8 outputs a high level, which stimulates the upper tube control drive circuit 5 and the lower tube control drive circuit 6, thereby controlling the high-side power tube 3 to be turned off through the upper tube control drive circuit 5, and controlling the low-side power tube 4 to be periodically turned on through the lower tube control drive circuit 6. In this way, overvoltage protection of the step-down DC-DC converter is achieved. At the same time, compared with the traditional technology of simultaneously controlling the high and low-side power tubes to be turned off, it is conducive to the release of output stage energy and the recovery of the DC-DC converter output overvoltage state.

[0027] In some embodiments, the upper tube control driving circuit 5 includes an upper tube opening control circuit 50 and an upper tube driving circuit 51; the upper tube opening control circuit 50 and the upper tube driving circuit 51 are sequentially connected between the output end of the comparator 8 and the control end of the high-side power tube 3. When the feedback voltage is greater than the reference voltage, it means that the converter is over-voltage, and at this time, the comparator 8 outputs a high level, and the upper tube opening control circuit 50 is used to generate a first shutdown excitation signal, so that the upper tube driving circuit 51 controls the high-side power tube 3 to turn off; or, when the feedback voltage is less than the reference voltage, it means that the converter is not over-voltage, and the upper tube opening control circuit 50 is used to generate a first conduction excitation signal, so that the upper tube driving circuit 51 controls the high-side power tube 3 to turn on. In this embodiment, when the feedback voltage is greater than the reference voltage, the upper tube opening control circuit 50 is used to generate a first shutdown excitation signal according to the high level output by the comparator 8, so as to transmit it to the upper tube driving circuit 51, so that the upper tube driving circuit 51 controls the high-side power tube 3 to turn off. When the feedback voltage is less than the reference voltage, the upper tube opening control circuit 50 is used to generate a first conduction excitation signal according to the low level output by the comparator 8, so as to transmit the first conduction excitation signal to the upper tube driving circuit 51, so that the upper tube driving circuit 51 controls the high-side power tube 3 to conduct. In this embodiment, the upper tube control driving circuit 5 adopts the existing technology, so its specific circuit is not described in detail.

[0028] In some embodiments, the lower tube control driving circuit 6 includes a lower tube opening control circuit 60 and a lower tube driving circuit 61; the lower tube opening control circuit 60 and the lower tube driving circuit 61 are sequentially connected between the output end of the comparator 8 and the control end of the low-side power tube 4; when the feedback voltage is greater than the reference voltage, the lower tube opening control circuit 60 is used to generate a second conduction excitation signal, so that the lower tube driving circuit 61 controls the low-side power tube 4 to be turned on; or when the feedback voltage is less than the reference voltage, the lower tube opening control circuit 60 is used to generate a second shutdown excitation signal, so that the lower tube driving circuit 61 controls the low-side power tube 4 to be turned on. In this embodiment, when the feedback voltage is greater than the reference voltage, the lower tube opening control circuit 60 is used to generate a second conduction excitation signal according to the high level output by the comparator 8, so as to transmit it to the lower tube driving circuit 61, so that the lower tube driving circuit 61 controls the low-side power tube 4 to be turned on periodically. When the feedback voltage is less than the reference voltage, the lower tube opening control circuit 60 is used to generate a second shutdown excitation signal according to the low level output by the comparator 8, and transmit it to the lower tube driving circuit 61, so that the lower tube driving circuit 61 controls the low-side power tube 4 to shut down.

[0029] like Figure 3As shown, in some embodiments, the overvoltage protection circuit 1 also includes a power supply terminal VCC for providing a circuit voltage; the lower tube opening control circuit 60 includes a first inverter INV1, a second inverter INV2, a first current source I1, a first capacitor C1, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a third inverter INV3, a first NOR gate NOR1, a second current source I2, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, and a seventh PMOS tube PM7. Among them, the first inverter INV1 and the second inverter INV2 are connected in series with each other and connected to the current protection control circuit 9, and are used to receive the zero current shutdown signal ZC_SHUT of the current protection control circuit 9; one end of the first current source I1 is connected to the power supply end VCC, and the other end is grounded through the first capacitor C1, which is used to provide a stable current for the components in the circuit; the drain of the first NMOS tube NM1 is connected to the other end of the first current source I1, the source is grounded, and the gate is connected between the first inverter INV1 and the second inverter INV2; the second NMOS tube NM2 and the third NMOS tube NM3 form a current mirror structure, and the gates of the two are connected to each other. The source of the second NMOS tube NM2 and the source of the third NMOS tube NM3 are both grounded. The gate of the third NMOS tube NM3 is short-circuited with its drain. The fourth NMOS tube NM4 and the fifth NMOS tube NM5 form a current mirror structure, and the gates of the two are connected to each other. The source of the fourth NMOS transistor NM4 and the source of the fifth NMOS transistor NM5 are both grounded. The gate of the fourth NMOS transistor NM4 is short-circuited with its drain. The first input end of the first NOR gate NOR1 is connected to the first enable signal EN1, and the second input end thereof is connected to the second enable signal EN2. The input end of the third inverter INV3 is connected to the output end of the first NOR gate NOR1.The gate of the sixth NMOS tube NM6 is connected to the output end of the third inverter INV3, the drain is connected to the drain of the fifth NMOS tube NM5, and the source is grounded; the gate of the first PMOS tube PM1 is connected to the third enable signal EN3, the drain is connected to the drain of the second NMOS tube NM2, and the source is connected to the power supply terminal VCC; the second current source I2 is connected to the power supply terminal VCC; the source of the second PMOS tube PM2 is connected to the second current source I2, and the gate is connected to the first enable signal EN1; the source of the third PMOS tube PM3 is connected to the drain of the second PMOS tube PM2, the gate is connected to the drain of the first NMOS tube NM1, and the drain is connected to the drain of the third NMOS tube NM3; the source of the fourth PMOS tube PM4 is connected to the drain of the second PMOS tube PM2, the gate is connected to the first voltage terminal VREF, and the drain is connected to the drain of the fourth NMOS tube NM4. The fifth PMOS tube PM5 and the sixth PMOS tube PM6 form a current mirror structure, the gates of the two are connected to each other, the source is connected to the power supply terminal VCC, the drain is short-circuited with its gate and connected to the drain of the second NMOS tube NM2; the source of the sixth PMOS tube PM6 is connected to the power supply terminal VCC, and the drain is connected to the drain of the fifth NMOS tube NM5; the gate of the seventh PMOS tube PM7 is connected to the output end of the second inverter INV2, the source is connected to the power supply terminal VCC, and the drain is connected to the lower tube driving circuit 61 and short-circuited with the source.

[0030] In this embodiment, the first enable signal EN1, the second enable signal EN2, and the third enable signal EN3 are all enable signals in the lower tube opening control circuit 60. Among them, the first enable signal EN1 and the second enable signal EN2 are low level effective, and the enablement of the lower tube opening control circuit 60 is controlled by the sixth NMOS tube NM6. When the first enable signal EN1 is high level, the second PMOS tube PM2 is turned off, and no current passes through the third PMOS tube PM3 and the fourth PMOS tube PM4 at this time, and the circuit cannot work. Therefore, if the lower tube opening control circuit 60 is to maintain normal enablement, the first enable signal EN1 should be low level effective. When the second enable signal EN2 is high level, the output of the first NOR gate NOR1 is low level, and the output of the third inverter INV5 is high level. At this time, the sixth NMOS tube NM6 is turned on, and the fourth NMOS tube NM4 and the fifth NMOS tube NM5 cannot form a current mirror. Therefore, if the lower tube opening control circuit 60 is to maintain normal enablement, the second enable signal EN2 should be low level effective.

[0031] In addition, the first enable signal EN1 is also used to control the on or off of the second PMOS transistor PM2. When the first enable signal EN1 is at a low level, the second PMOS transistor PM2 is turned on, and the second current source I2 starts to provide current to the third PMOS transistor PM3 and the fourth PMOS transistor PM4; when the first enable signal EN1 is at a high level, the second PMOS transistor PM2 is turned off.

[0032] The third enable signal EN3 is high level effective, and the first PMOS transistor PM1 controls the enablement of the lower tube opening control circuit 60. When the third enable signal EN3 is low level, the first PMOS transistor PM1 is turned on, and the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 cannot form a current mirror. Therefore, if the lower tube opening control circuit 60 is to maintain normal enablement, the third enable signal EN3 should be high level effective.

[0033] When the feedback voltage is greater than the reference voltage, the lower tube opening control circuit 60 is turned on and generates a second conduction excitation signal. While providing an excitation signal to the lower tube driving circuit 61, an excitation signal is also provided to the current protection control circuit 9, so that the current protection control circuit 9 enters the enable mode to drive the lower tube opening control circuit 60 to be normally enabled. When the zero current shutdown signal ZC_SHUT is at a high level, the first NMOS tube NM1 is turned off, and the first current source I1 charges the first capacitor C1. When the voltage across the first capacitor C1 is greater than the reference voltage VREF, the current flowing through the fourth PMOS tube PM4 increases, and the fourth NMOS tube NM4 and the fifth NMOS tube NM5 form a current mirror circuit, so the current flowing through the fifth NMOS tube NM5 also increases. At this time, the drain voltage of the fifth NMOS tube NM5 is a low level, so when the lower tube opening control circuit 60 is normally enabled, the lower tube driving circuit 61 outputs a low level accordingly, thereby controlling the low-side power tube 4 to be turned off. When the zero current shutdown signal ZC_SHUT is at a low level, the first NMOS tube NM1 is turned on, and the first current source I1 does not charge the first capacitor C1 at this time, so that the gate voltage of the third PMOS tube PM3 becomes low level, so the current flowing through the third PMOS tube PM3 increases, and the current flowing through the fourth PMOS tube PM4 decreases. At the same time, the fourth NMOS tube NM4 and the fifth NMOS tube NM5 form a current mirror circuit, so the current on the fifth NMOS tube NM5 decreases, so that the drain voltage of the fifth NMOS tube NM5 is high level, so when the lower tube opening control circuit 60 is normally enabled, the lower tube driving circuit 61 outputs a high level accordingly, thereby controlling the low-side power tube 4 to be turned on. In addition, the zero current shutdown signal ZC_SHUT is sequentially inverted by the first inverter INV1 and the second inverter INV2, and the output signal ZC_SHUT1 is used to control the conduction and shutdown of the seventh PMOS tube PM7. When the signal ZC_SHUT1 outputs a high level, the seventh PMOS transistor PM7 is turned off; when the signal ZC_SHUT1 outputs a low level, the seventh PMOS transistor PM7 is turned on and serves as a decoupling capacitor of the power supply terminal VCC to reduce noise on the power supply terminal VCC.

[0034] In this embodiment, a lower tube opening control circuit 60 is formed by a first inverter INV1, a second inverter INV2, a first current source I1, a first capacitor C1, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a third inverter INV3, a first NOR gate NOR1, a second current source I2, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, and a seventh PMOS tube PM7, and three enable signals are used to control the switching states of the NMOS tubes and the PMOS tubes in the circuit to achieve precise control of the current in the circuit, thereby controlling the lower tube driving circuit 61 to output a high level or a low level.

[0035] In some embodiments, the lower tube drive circuit 61 includes a plurality of inverters. The working principle of the inverter is that the output level is opposite to the input level. Taking the plurality of inverters as a whole, if the final output level is required to be the same as the input low level, then the number of the plurality of inverters is required to be an even number, i.e., 2 or 4 or 6. For example, when the drain of the fifth NMOS tube NM5 outputs a high level, it means that the low-side power tube 4 needs to be turned on, that is, the lower tube drive circuit 61 needs to output a high level, so when the number of the plurality of inverters is an even number, it can be ensured that the level output by the lower tube drive circuit 61 is consistent with the level output by the drain of the fifth NMOS tube NM5. In this embodiment, taking into account that the small circuit area is conducive to circuit miniaturization, and the more the number of inverters, the greater the driving current, the number of the plurality of inverters is preferably 4, i.e., the seventh inverter INV7, the eighth inverter INV8, the ninth inverter INV9, and the tenth inverter INV10. The four inverters are connected in series in sequence, wherein the input end of the first inverter is connected between the drain of the sixth PMOS tube and the drain of the fifth NMOS tube, and the output end is connected to the input end of the next inverter; the input end of the last inverter is connected to the output end of the previous inverter, and the output end is connected to the control end of the low-side power tube and the current protection control circuit. In some embodiments, the seventh inverter INV7 and the eighth inverter INV8 are respectively composed of two MOS tubes. Among them, the seventh inverter INV7 includes the eighth PMOS tube PM8 and the ninth NMOS tube NM9. The eighth inverter INV8 includes the ninth PMOS tube PM9 and the tenth NMOS tube NM10. The gate of the eighth PMOS tube PM8 is connected to the drain of the fifth NMOS tube NM5, the source is connected to the power supply terminal VCC, and the drain is connected to the drain of the ninth NMOS tube NM9. The gate of the ninth NMOS tube NM9 is connected to the drain of the fifth NMOS tube NM5, and the source is grounded. The gate of the ninth PMOS tube PM9 is connected to the drain of the eighth PMOS tube PM8 and the drain of the ninth NMOS tube NM9, the source is connected to the power supply terminal VCC, and the drain is connected to the drain of the tenth NMOS tube NM10. The gate of the tenth NMOS tube NM10 is connected to the drain of the eighth PMOS tube PM8 and the drain of the ninth NMOS tube NM9, and the source is grounded. The input end of the ninth inverter INV9 is connected between the drain of the ninth PMOS tube PM9 and the drain of the tenth NMOS tube NM10, and the output end is connected to the input end of the tenth inverter IVN10. The output end of the tenth inverter IVN10 is connected to the low-side power tube 4 and the current protection control circuit 9.

[0036] In this embodiment, by cascading multiple inverters, the current driving capability can be significantly improved, so that the speed of turning on or off the low-side power tube 4 can be accelerated, which is beneficial to improving the efficiency of the entire circuit.

[0037] According to the inverter principle, an even number of inverters is equivalent to a phase co-inverter. Therefore, in some embodiments, the lower tube driving circuit 61 may also include at least one phase co-inverter (not shown in the figure). The input end of the phase co-inverter is connected between the drain of the sixth PMOS tube PM6 and the drain of the fifth NMOS tube NM5, and the output end is connected to the control end of the low-side power tube and the current protection control circuit. In this embodiment, the phase co-inverter has a simpler circuit design than an even number of inverters.

[0038] In addition, it should be noted that although the phase converter is simpler than the cascade inverter, the cascade inverter is still necessary in some specific cases, especially when the circuit design needs to utilize other characteristics of the inverter, such as logic inversion, buffering or signal shaping. Those skilled in the art need to select the most appropriate solution according to specific application requirements and design goals.

[0039] In some embodiments, the overvoltage protection circuit 1 also includes a current protection control circuit 9 connected to the lower tube control drive circuit 6, and the current protection control circuit 9 includes a zero current control mode and a backflow current control mode; the current protection control circuit 9 switches between the zero current control mode and the backflow current control mode according to the comparison result between the feedback voltage and the reference voltage. In this embodiment, when the feedback voltage is less than the reference voltage, the current protection control circuit 9 is in the zero current control mode, and zero current detection is performed, and the overvoltage protection circuit 1 is in a non-working state, which effectively reduces the circuit power consumption. When the feedback voltage is greater than the reference voltage, the current protection control circuit 9 switches from the zero current control mode to the backflow current control mode, and backflow current detection is performed, and the overvoltage protection circuit 1 is in a working state.

[0040] In some embodiments, the current protection control circuit 9 is preset with a backflow current detection threshold; when the current protection control circuit 9 is in the backflow current control mode, it is used to detect the current of the inductor L in the step-down DC-DC converter 1, and when the current of the inductor L is greater than the backflow current detection threshold, the lower tube control drive circuit 6 turns off the low-side power tube 4. In this embodiment, when the feedback voltage is greater than the reference voltage, the current protection control circuit 9 performs backflow current detection. When it is detected that the current of the inductor L is greater than the preset backflow current detection threshold, the current protection control circuit 9 provides an enable signal to the lower tube control drive circuit 6, so that the lower tube control drive circuit 6 turns off the low-side power tube 4 to avoid the low-side power tube 4 from being broken down.

[0041] In some embodiments, the lower tube opening control circuit 60 is interactively connected with the current protection control circuit 9. When the feedback voltage is greater than the reference voltage, the lower tube opening control circuit 60 outputs the second conduction excitation signal, so that the current protection control circuit 60 generates an enable signal to detect the current of the inductor L in the step-down DC-DC converter 1. In this embodiment, through the interaction between the lower tube opening control circuit 60 and the current protection control circuit 9, when an overvoltage occurs, the lower tube opening control circuit 60 provides the second conduction excitation signal to the lower tube drive circuit 61, and can also provide an excitation signal to the current protection control circuit 9, so that the current protection control circuit 9 enters the enable mode and detects the current of the inductor L, thereby comparing the current value of the inductor L with the size of the backflow current detection threshold preset in the current protection control circuit 9, and when the current value of the inductor L is greater than the backflow current detection threshold, the lower tube opening control circuit 60 and the lower tube drive circuit 61 turn off the low-side power tube 4 to prevent the low-side power tube 4 from being broken down.

[0042] like Figure 4As shown, in some embodiments, the current protection control circuit 9 includes a first trigger RS1, a fourth inverter INV4, a second NOR gate NOR2, a first transmission gate TG1, a second transmission gate TG2, a fifth inverter INV5, a sixth inverter INV6, a second trigger RS2 and a third NOR gate NOR3. Among them, the set end S1 of the first trigger RS1 is connected to the output end of the lower tube drive circuit 61, and the reset end R1 is connected to the signal ZC-EN switched between the zero current control mode and the backflow current control mode, and the switched signal ZC-EN includes a zero current control signal or a backflow current control signal. When the feedback signal VFB is lower than the reference voltage VREF, the switched signal ZC_EN is a high level signal, that is, a zero current control signal, and the current protection control circuit 9 operates in the zero current control mode. When the feedback signal VFB is higher than the reference voltage VREF, the switched signal ZC_EN is a low level signal, that is, a backflow current control signal, and the current protection control circuit 9 operates in the backflow current control mode. The input end of the fourth inverter INV4 is connected to the reset end R1 of the first trigger RS1; one input end of the second NOR gate NOR2 is connected to the reset end R1 of the first trigger RS1, and the other input end is connected to the output end of the first trigger RS1; the input end of the first transmission gate TG1 is connected to the output end of the fourth inverter INV4, the positive control end of the first transmission gate TG1 is connected to the non-control end of the second transmission gate TG2, and the non-control end of the first transmission gate TG1 is connected to the first enable signal EN1; the input end of the second transmission gate TG2 is connected to the output end of the second NOR gate NOR2, and the positive control end of the second transmission gate TG2 is connected to the first enable signal EN1. The input end of the fifth inverter INV5 is connected to the first enable signal EN1, and is connected between the positive control end of the first transmission gate TG1 and the non-control end of the second transmission gate TG2, and the output end is connected between the non-control end of the first transmission gate TG1 and the positive control end of the second transmission gate TG2; the input end of the sixth inverter INV6 is connected to the zero current detection clock signal ZC, and the output end is connected to the reset end of the second trigger RS2. The set end S2 of the second trigger RS2 is connected to the output end of the first transmission gate TG1 and the output end of the second transmission gate TG2; the first input end of the third NOR gate NOR3 is connected to the test signal TEST, which is valid at a high level, the second input end is connected to the output end of the second trigger RS2, and the output end is connected to the input end of the first inverter INV1.

[0043] In this embodiment, the working principle of the current protection control circuit 9 is specifically as follows: when the feedback signal VFB is less than the reference voltage VREF, the switched signal ZC_EN is a high-level signal, at which time the working mode of the current protection control circuit 9 is the zero current control mode, and the overvoltage protection circuit does not need to work. When the feedback signal VFB is greater than the reference voltage VREF, the switched signal ZC_EN is a low-level signal, at which time the working mode of the current protection control circuit 9 is the backflow current control mode, and the current of the inductor L is detected. When the current of the inductor L is less than the backflow current detection threshold, the low-side power tube 4 will be periodically turned on with the zero current detection clock signal ZC, thereby realizing the release of output stage energy; when the current of the inductor L is greater than the backflow current detection threshold, the second enable signal EN2 connected to the lower tube opening control circuit 60 is a high-level signal, at which time no matter how the zero current detection clock signal ZC changes, the low-side power tube 4 is in the off state, thereby avoiding the breakdown damage of the low-side power tube 4.

[0044] like Figure 5 As shown, it is a timing waveform diagram of the second enable signal EN2 connected to the lower tube opening control circuit 60, the lower tube driving signal L_ctrl outputted from the output end of the lower tube driving circuit 61, the switching signal ZC-EN, and the zero current detection clock signal ZC, so as to illustrate the specific situation of the output voltage of the step-down DC-DC converter.

[0045] The timing waveform is divided into three states of output voltage by dotted lines, namely, the state of output not over-voltage, the state of output over-voltage and small output current, and the state of output over-voltage and excessive output current. Specifically, when the feedback signal VFB is less than the reference voltage VREF, the signal ZC_EN switched by the working mode of the current protection control circuit 9 is high level, and the current protection control circuit 9 works in the zero current control mode, which means that the output voltage of the step-down DC-DC converter is in the state of output not over-voltage, and the overvoltage protection circuit does not need to work; when the feedback signal VFB is greater than the reference voltage VREF, the switched signal ZC_EN is low level, and the current protection control circuit 9 works in the reverse current control mode, and detects the current of the inductor L. If the current of the inductor L does not exceed the reverse current detection threshold, the second enable signal EN2 remains low level, and the lower tube opening control circuit 60 is normally enabled, then the lower tube drive signal L_ctrl output by the lower tube opening control circuit 60 is high level, so that the low-side power tube 4 is controlled by the zero current detection clock signal ZC is periodically turned on to release the energy of the output stage, which means that the output voltage of the step-down DC-DC converter is in an output overvoltage and a small output current state; when the output voltage of the step-down DC-DC converter continues to be overvoltage and the output current continues to increase, it means that the output voltage of the step-down DC-DC converter is in an output overvoltage and an output current is too large, and the switched signal ZC_EN continues to be maintained at a low level. At this time, the current protection control circuit 9 continues to operate in the backflow current control mode. However, if the detected current of the inductor L exceeds the backflow current detection threshold, the second enable signal EN2 signal will switch to a high level. At this time, the lower tube opening control circuit 60 cannot be enabled, and the lower tube drive signal L_ctrl output by the lower tube opening control circuit 60 is low, so that the low-side power tube 4 is turned off, thereby preventing the low-side power tube 4 from being broken down.

[0046] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An overvoltage protection circuit applied to a step-down DC-DC converter, used to control the on or off of a high-side power tube and a low-side power tube of the step-down DC-DC converter, characterized in that: The overvoltage protection circuit comprises: A first voltage terminal for providing a feedback voltage and a second voltage terminal for providing a reference voltage; A comparator, wherein a positive input terminal of the comparator is connected to the first voltage terminal, and a negative input terminal of the comparator is connected to the second voltage terminal; An upper tube control driving circuit, wherein an input end of the upper tube control driving circuit is connected to an output end of the comparator, and an output end is connected to a control end of the high-side power tube; A lower tube control driving circuit, wherein the input end of the lower tube control driving circuit is connected to the output end of the comparator, and the output end is connected to the control end of the low-side power tube; When the feedback voltage is greater than the reference voltage, the high-side power tube is turned off by the upper tube control driving circuit, and the low-side power tube is periodically turned on by the lower tube control driving circuit.

2. The overvoltage protection circuit according to claim 1, characterized in that: It also includes a current protection control circuit connected to the lower tube control drive circuit, and the current protection control circuit includes a zero current control mode and a backflow current control mode; The current protection control circuit switches between the zero current control mode and the backflow current control mode according to a comparison result between the feedback voltage and the reference voltage.

3. The overvoltage protection circuit according to claim 2, characterized in that: The current protection control circuit is preset with a backflow current detection threshold; when the current protection control circuit is in the backflow current control mode, it is used to detect the current of the inductor in the step-down DC-DC converter, and when the current of the inductor is greater than the backflow current detection threshold, the lower tube control drive circuit turns off the low-side power tube.

4. The overvoltage protection circuit according to claim 1, characterized in that: The upper tube control driving circuit comprises an upper tube opening control circuit and an upper tube driving circuit; the upper tube opening control circuit and the upper tube driving circuit are sequentially connected between the output end of the comparator and the control end of the high-side power tube; When the feedback voltage is greater than the reference voltage, the upper tube opening control circuit is used to generate a first shut-down excitation signal, so that the upper tube driving circuit controls the high-side power tube to shut down; or When the feedback voltage is less than the reference voltage, the upper tube turn-on control circuit is used to generate a first conduction excitation signal, so that the upper tube driving circuit controls the high-side power tube to turn on.

5. The overvoltage protection circuit according to claim 2, characterized in that: The lower tube control driving circuit comprises a lower tube opening control circuit and a lower tube driving circuit; the lower tube opening control circuit and the lower tube driving circuit are sequentially connected between the output end of the comparator and the control end of the low-side power tube; When the feedback voltage is greater than the reference voltage, the lower tube turn-on control circuit is used to generate a second conduction excitation signal, so that the lower tube drive circuit controls the low-side power tube to turn on; or When the feedback voltage is less than the reference voltage, the lower tube opening control circuit is used to generate a second closing excitation signal, so that the lower tube driving circuit controls the low-side power tube to be turned on.

6. The overvoltage protection circuit according to claim 5, characterized in that: The lower tube opening control circuit is interactively connected with the current protection control circuit; When the feedback voltage is greater than the reference voltage, the lower tube opening control circuit outputs the second conduction excitation signal, so that the current protection control circuit generates an enable signal to detect the current of the inductor in the step-down DC-DC converter.

7. The overvoltage protection circuit according to claim 5, characterized in that: The overvoltage protection circuit includes a power supply end; the lower tube opening control circuit includes a first inverter, a second inverter, a first current source, a first capacitor, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a third inverter, a first NOR gate, a second current source, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, and a seventh PMOS tube; Among them, the first inverter and the second inverter are connected in series with each other and are connected to the current protection control circuit; one end of the first current source is connected to the power supply end, and the other end is grounded through the first capacitor; the drain of the first NMOS tube is connected to the other end of the first current source, the source is grounded, and the gate is connected between the first inverter and the second inverter; the gate of the second NMOS tube is connected to the gate of the third NMOS tube, and the source of the second NMOS tube and the source of the third NMOS tube are both grounded; the gate of the third NMOS tube is short-circuited with its drain; the gate of the fourth NMOS tube is connected to the gate of the fifth NMOS tube, and the source of the fourth NMOS tube and the source of the fifth NMOS tube are both grounded; the gate of the fourth NMOS tube is short-circuited with its drain; the first input end of the first NOR gate is connected to the first enable signal, and the second input end thereof is connected to the second enable signal; the input end of the third inverter is connected to the output end of the first NOR gate; the gate of the sixth NMOS tube is connected to the output end of the third inverter, and the drain is connected to the fifth NMOS The drain of the tube is connected to the ground; the gate of the first PMOS tube is connected to the third enable signal, the drain is connected to the drain of the second NMOS tube, and the source is connected to the power supply terminal; the second current source is connected to the power supply terminal; the source of the second PMOS tube is connected to the second current source, and the gate is connected to the first enable signal; the source of the third PMOS tube is connected to the drain of the second PMOS tube, the gate is connected to the drain of the first NMOS tube, and the drain is connected to the drain of the third NMOS tube; the source of the fourth PMOS tube is connected to the drain of the second PMOS tube, the gate is connected to the first voltage terminal, and the drain is connected to the drain of the fourth NMOS tube; the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, the source is connected to the power supply terminal, the drain is short-circuited with its gate and connected to the drain of the second NMOS tube; the source of the sixth PMOS tube is connected to the power supply terminal, and the drain is connected to the drain of the fifth NMOS tube; the gate of the seventh PMOS tube is connected to the output terminal of the second inverter, the source is connected to the power supply terminal, and the drain is connected to the lower tube driving circuit and short-circuited with the source.

8. The overvoltage protection circuit according to claim 7, characterized in that: The lower tube driving circuit comprises a plurality of inverters, the number of the plurality of inverters is an even number, and the plurality of inverters are connected in series in sequence, wherein the input end of the first inverter is connected between the drain of the sixth PMOS tube and the drain of the fifth NMOS tube, and the output end is connected to the input end of the next inverter; the input end of the last inverter is connected to the output end of the previous inverter, and the output end is connected to the control end of the low-side power tube and the current protection control circuit; or, The lower tube driving circuit includes at least one phase regulator, the input end of the phase regulator is connected between the drain of the sixth PMOS tube and the drain of the fifth NMOS tube, and the output end is connected to the control end of the low-side power tube and the current protection control circuit.

9. The overvoltage protection circuit according to claim 3, characterized in that: The lower tube opening control circuit includes a first inverter; the current protection control circuit includes a first trigger, a fourth inverter, a second NOR gate, a first transmission gate, a second transmission gate, a fifth inverter, a sixth inverter, a second trigger and a third NOR gate; Among them, the set end of the first trigger is connected to the output end of the lower tube driving circuit, and the reset end is connected to the signal switching between the zero current control mode and the backflow current control mode, and the switching signal includes a zero current control signal or a backflow current control signal; the input end of the fourth inverter is connected to the reset end of the first trigger; one input end of the second NOR gate is connected to the reset end of the first trigger, and the other input end is connected to the output end of the first trigger; the input end of the first transmission gate is connected to the output end of the fourth inverter, the positive control end of the first transmission gate is connected to the non-control end of the second transmission gate, and the non-control end of the first transmission gate is connected to the first enable signal; the input end of the second transmission gate is connected to the output end of the second NOR gate, and the positive control end of the second transmission gate is connected to the first enable signal; The input end of the fifth inverter is connected to the first enable signal and is connected between the positive control end of the first transmission gate and the non-control end of the second transmission gate, and the output end is connected between the non-control end of the first transmission gate and the positive control end of the second transmission gate; the input end of the sixth inverter is connected to the zero current detection clock signal, and the output end is connected to the reset end of the second trigger; The set end of the second trigger is connected to the output end of the first transmission gate and the output end of the second transmission gate; the first input end of the third NOR gate is connected to the test signal, the second input end is connected to the output end of the second trigger, and the output end is connected to the input end of the first inverter.

10. A step-down DC-DC converter, characterized in that: It includes an overvoltage protection circuit as described in any one of claims 1 to 9 above, the overvoltage protection circuit includes an upper tube control drive circuit and a lower tube control drive circuit; and a voltage input terminal, a high-side power tube, a low-side power tube, an inductor and a capacitor; wherein the control terminal of the high-side power tube is connected to the upper tube control drive circuit, and the source is connected to the voltage input terminal; the control terminal of the low-side power tube is connected to the lower tube control drive circuit, and the source is grounded; one end of the inductor is connected to the drain of the high-side power tube and the drain of the low-side power tube, and the other end is connected to the positive electrode of an external power load; one end of the capacitor is connected between the other end of the inductor and the positive electrode of the external power load, and the other end is connected between the negative electrode of the external power load and the ground.

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