Bevel drive compensation

Abstract

The invention relates to oblique angle driver compensation. Systems and methods for skew compensation in push-pull drivers are described herein. A device may include a first circuit configured for skew measurement of an output driver stage in an output driver circuit. The device may also include a second circuit configured to determine a first skew parameter based on the skew measurement and apply a first bias dependent on the skew measurement to drive a high side transistor in the output driver stage. The device may also include a third circuit configured to determine a second skew parameter based on the skew measurement and apply a second bias dependent on the skew measurement to drive a low-side transistor in the output driver stage. The first bias and the second bias may be complementary.

Description

Technical Field

[0001] The present disclosure relates to data signal drivers, and more particularly, to skew compensation in push-pull drivers. Background Art

[0002] A data signal driver, such as a push-pull driver, can output a signal that controls two power transistors (a high-side switch and a low-side switch) to switch a DC input voltage in alternating half-cycles to generate an output signal. Each power transistor can be responsible for both the positive and negative half-cycles of the output signal's waveform. In operation, one power transistor can be turned on at a time. The output signal can supply current to the load (e.g., push) or sink current from the load (e.g., pull). Summary of the Invention

[0003] In one embodiment, a semiconductor device that can implement skew driver compensation is generally described. The semiconductor device may include a first circuit configured to measure a skew of an output driver stage in an output driver circuit. The semiconductor device may also include a second circuit configured to determine a first skew parameter based on the skew measurement and apply a first bias that depends on the skew measurement to drive a high-side transistor in the output driver stage. The semiconductor device may also include a third circuit configured to determine a second skew parameter based on the skew measurement and apply a second bias that may depend on the skew measurement to drive a low-side transistor in the output driver stage. The first bias and the second bias may be complementary.

[0004] In one embodiment, a device that can implement skew driver compensation is generally described. The device may include a controller configured to receive an input signal. The device may also include an output driver stage that may include a high-side transistor and a low-side transistor. The output driver stage may be configured to switch the high-side transistor and the low-side transistor to output an output voltage representative of the input signal. The device may also include circuitry configured to determine a skew measurement of the output driver stage. The device may also include circuitry configured to determine a first skew parameter based on the skew measurement. The device may also include circuitry configured to apply a first bias that may depend on the skew measurement to drive the high-side transistor. The device may also include circuitry configured to determine a second skew parameter based on the skew measurement. The device may also include circuitry configured to apply a second bias that depends on the skew measurement to drive the low-side transistor. The first bias and the second bias may be complementary.

[0005] In one embodiment, a method for operating a driver circuit may include determining a skew measurement of an output driver stage of the driver circuit. The method may include determining a first skew parameter based on the skew measurement. The method may also include applying a first bias that may depend on the skew measurement to drive a high-side transistor of the output driver stage. The method may also include determining a second skew parameter based on the skew measurement. The method may also include applying a second bias that depends on the skew measurement to drive a low-side transistor of the output driver stage. The first bias and the second bias may be complementary.

[0006] The foregoing summary is illustrative only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the accompanying drawings and the following detailed description. In the accompanying drawings, the same reference numerals indicate the same or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram illustrating an apparatus in which bevel drive compensation may be implemented in one embodiment.

[0008] Figure 2 It shows Figure 1 Figure 2 shows additional details of the device.

[0009] Figure 3 is a diagram illustrating an exemplary skew determination circuit that may be used to implement bevel driver compensation in one embodiment.

[0010] Figure 4 is a diagram illustrating an exemplary implementation of a drive correction circuit that may be used for bevel drive compensation in one embodiment.

[0011] Figure 5 is a diagram illustrating another exemplary implementation of a drive correction circuit that may be used for bevel drive compensation in one embodiment.

[0012] Figure 6 is a flow chart of an exemplary process by which bevel drive compensation may be implemented in one embodiment. DETAILED DESCRIPTION

[0013] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be understood by those skilled in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0014] Figure 1is a diagram illustrating an apparatus in which bevel drive compensation may be implemented in one embodiment. Figure 1 The apparatus shown can be a semiconductor device that implements the driver circuit 100. In one embodiment, the driver circuit 100 can be a multi-branch push-pull data driver. The driver circuit 100 can include multiple branches, such as N branches from branch-1 to branch-N. A branch can be a portion that can be configured to perform a specific task. For example, one branch can provide data and commands (e.g., in the form of voltage) to control one load of the device, and another branch can provide data or commands to control another load of the device. The driver circuit 100 can be a current mode driver or a voltage mode driver.

[0015] Using branch-1 as an example, each branch may include at least a data interface 102, a controller 103, a deskew circuit 110, and an output driver stage 108. The controller 103 may be, for example, a microcontroller including various types of hardware and circuit elements, such as logic gates and other specialized circuits. Figure 1 In the example shown, the controller 103 may include at least a NAND gate 104 and a NOR gate 106. The output driver stage 108 may include a pair of power transistors, the pair of power transistors including a high-side (HS) transistor and a low-side (LS) transistor. The output driver stage 108 may also include a driver circuit system configured to drive the HS transistor and the LS transistor. The HS transistor may be a P-type metal oxide semiconductor (PMOS) device, such as a P-type metal oxide semiconductor field effect transistor (MOSFET). The LS transistor may be an N-type metal oxide semiconductor (NMOS) device, such as an N-type MOSFET.

[0016] The data interface 102 can be configured to receive input data 101 intended for a load 109. Branch-1 can be configured to provide data to the load 109 in the form of an output voltage Vout. The driver circuit 100 can receive an input voltage Vin from, for example, a power supply, and the output driver stage 108 can switch the HS transistor and the LS transistor to convert Vin to Vout. The NAND gate 104 in the controller 103 can receive an enable signal EN to turn on the HS transistor, and the NOR gate 106 in the controller 103 can receive an enable signal EN_n to turn on the LS transistor. The enable signals EN and EN_n can be complementary so that only one of the HS transistor and the LS transistor is turned on at a time.

[0017] The output driver stage 108 can be configured to drive the HS transistor on and off based on the output from the NAND gate 104. The output driver stage 108 can be configured to drive the LS transistor on and off based on the output from the NOR gate 106. During the push phase, the NAND gate 104 can output a low logic voltage level (e.g., representing a logic 0), and the HS transistor can be activated (e.g., closed) or turned on. Current can flow from Vin to Vout through the activated HS transistor. During the push phase, the LS transistor remains inactive (e.g., open) and non-conductive, so that no current flows through the LS transistor. During the pull phase, the NOR gate 106 can output a high logic voltage level (e.g., representing a logic 1), and the LS transistor can be activated (e.g., closed) or turned on. Current can flow from Vout to ground (GND) through the activated LS transistor. During the pull phase, the HS transistor remains inactive (e.g., open) and non-conductive, so that no current flows through the HS transistor.

[0018] In one aspect, the drive signal used by a push-pull driver can be a pull-up signal or a pull-down signal. The pull-up signal can drive the output voltage to a high level (e.g., Vin), and the pull-down signal can drive the input voltage to a low level (e.g., GND). When the pull-up signal pulls the output voltage from low to high, the rate at which the output voltage rises can be called the rising slew rate. When the pull-down signal pulls the output voltage from high to low, the rate at which the output voltage falls can be called the falling slew rate.

[0019] The rising slew rate and the falling slew rate can be controlled by the controller to maintain symmetry between the rising waveform and the falling waveform of the output voltage. The symmetry between the rising waveform and the falling waveform can be based on the relationship between the rising slew rate and the falling slew rate. The symmetry of the rising waveform and the falling waveform can affect the duty cycle (e.g., the ratio of the on state to the total period of the output signal). Therefore, it is necessary to control the symmetry in order to maintain the output signal at the desired duty cycle. Different data signaling systems and applications may have different desired duty cycles. For example, applications such as double data rate (DDR) memory interface devices may require a 50% duty cycle.

[0020] However, the slew rate can change and deviate from its predefined value based on operating conditions (e.g., data rate) and process corners (e.g., skew corners). On the one hand, process variations can cause PMOS and NMOS devices to be unbalanced and operate at different switching speeds. This imbalance can lead to asymmetry in the rising and falling slew rates and asymmetric push-pull characteristics. For example, if the PMOS device responds more strongly to the drive signal than the NMOS device, the PMOS device can switch faster than the NMOS device, and the rising slew rate can be faster than the falling slew rate. This causes asymmetry in the switching state and has a negative impact on the duty cycle and data integrity. In addition, the severity of the unbalanced push-pull driver increases at process corners where MOSFET skew is more common. For example, at the SLOW / FAST (SF) and FAST / SLOW (FS) corners, the strengths of the PMOS and NMOS move in opposite directions. In addition to the asymmetric output signal duty cycle, the skew of the MOSFET can also reduce yield.

[0021] To address the imbalance between the HS and LS transistors in driver circuit 100, skew correction circuit 110 can be configured to provide HS skew parameters 112 and LS skew parameters 114 to shape the waveform of output voltage Vout. HS skew parameters 112 and LS skew parameters 114 can be bias currents or bias voltages that can provide separate skew bias corrections for the HS and LS transistors. Furthermore, HS skew parameters 112 and LS skew parameters 122 can be complementary to offset output skew and achieve balanced pull-up and pull-down behavior. Because each PMOS and NMOS device in each branch of branch-1 through branch-N is susceptible to unique skew bias, each HS and LS transistor in each branch of driver circuit 100 can be individually biased. The individual biases provided to individual HS and LS transistors can provide skew compensation for a variety of applications. For example, DDR memory interface transmitter designs and other devices utilizing push-pull drivers can use the skew compensation techniques described herein to address imbalances between power transistor pairs.

[0022] Figure 2 It shows Figure 1 Figure 2 shows additional details of the device. Figure 2 The description can be found in Figure 1 The components shown in Figure 2In the example shown, the skew correction circuit 110 may include a skew determination circuit 202, a HS drive correction circuit 204, and a LS drive correction circuit 206. The skew determination circuit 202 may be configured to determine the skew generated by the output driver stage 108. In one embodiment, the skew determination circuit 202 may include replicas of the HS transistor and the LS transistor that may be used to measure or estimate the skew generated by the output driver stage 108. The skew determination circuit 202 may output a skew measurement structure 210 to the HS drive correction circuit 204 and the LS drive correction circuit 206.

[0023] The HS drive correction circuit 204 can use the skew measurement 210 to generate a bias current or bias voltage that can be applied to control the strength of the drive current provided by the controller 103 (or by the NAND gate 104). The drive current with the applied bias current or bias voltage generated by the HS drive correction circuit 204 can be used to drive the HS transistor. The LS drive correction circuit 206 can use the skew measurement 210 to generate a bias current or bias voltage that can be applied to control the strength of the drive current provided by the controller 103 (or by the NOR gate 106). The drive current with the applied bias current or bias voltage generated by the LS drive correction circuit 206 can be used to drive the LS transistor.

[0024] Figure 3 is a diagram illustrating an exemplary skew determination circuit that may be used to implement bevel driver compensation in one embodiment. Figure 3 The description can be found in Figure 1 and Figure 2 The components shown in Figure 3 In the illustrated embodiment, skew determination circuit 202 may include a reference transistor Mref, an HS replica 302, and an LS replica 304. Reference transistor Mref may be a P-type MOSFET. HS replica 302 may be a P-type MOSFET that replicates the HS transistor in output driver stage 108. HS replica 302 may have the same process behavior, including corner conditions, as the HS transistor in output driver stage 108. LS replica 304 may be an N-type MOSFET that replicates the LS transistor in output driver stage 108. LS replica 304 may have the same process behavior, including corner conditions, as the LS transistor in output driver stage 108. Reference transistor Mref, HS replica 302, and LS replica 304 may form a current mirror.

[0025] The MOSFET skew of the HS replica 302 and the LS replica 304 can be used to generate a current division and provide a measurement of the skewness, which can be represented by the skew current Isk. In one embodiment, the controller (e.g., Figure 1 The controller 103 in FIG. 2 can apply an arbitrary voltage, such as a reference voltage Vref, and each of the reference transistor Mref, the HS replica 302, and the LS replica 304 can draw a current Iref from Vref. The current Iref flowing through Mref can become the current Im, the current Irref flowing through the HS replica 302 can become the current Ip, and the current Iref flowing through the LS replica 304 can become the current In. Since the reference transistor Mref, the HS replica 302, and the LS replica 304 are arranged as a current mirror, the current Im can be a replica of Ip. In the ideal case where the HS replica 302 and the LS replica 304 have the same process behavior and corner conditions, the currents Ip and In are equivalent, and the output current of the skew determination circuit 202 (i.e., the skew current Isk) can be net zero.

[0026] When HS replica 302 and LS replica 304 are unbalanced, such as when they have different process behaviors and corner conditions, currents Ip and In will not be equivalent, and current 2I will not be evenly divided into Ip and In. Furthermore, skew current Isk may be non-zero. The value of Isk may reflect whether HS replica 302 or LS replica 304 is the more dominant device. For example, if HS replica 302 is more dominant than LS replica 304, Ip may be greater than I and In may be less than I, but the sum of Ip and In may still be 2I. Since Ip is greater than I and I draws current I through the path of Mref, Isk then becomes Ip – I (or I – In), and skew determination circuit 202 may infer the current as skew current Isk. A positive Isk (e.g., indicating a driver by skew determination circuit 202) may indicate that HS replica 302 is more dominant than LS replica 304 by a factor of Isk. Furthermore, if the HS replica 302 is more dominant than the LS replica 304, then the HS transistor is also more dominant than the LS transistor by the same dominance factor.

[0027] If HS replica 302 is less dominant than LS replica 304, Ip can be less than I and In can be greater than I, but the sum of Ip and In can still be 2I. Since Ip is less than I, and I draws current I through the path of Mref, Isk then becomes I–Ip (or In–I), and skew determination circuit 202 can pull Isk toward GND in an attempt to fill I. A negative Isk (e.g., indicating a pull by skew determination circuit 202) can indicate that HS replica 302 is less dominant than LS replica 304 by a factor of Isk. Furthermore, if HS replica 302 is less dominant than LS replica 304, the HS transistor is also less dominant than the LS transistor by the same factor. The skew current Isk can be output as skew measurement 210 to HS drive correction circuit 204 and LS drive correction circuit 206 for use in generating a bias current or bias voltage that can be used to correct the drive current used to drive the HS and LS transistors in output driver stage 108.

[0028] Figure 4 FIG is a diagram illustrating an exemplary implementation of a drive correction circuit that may be used for bevel drive compensation in one embodiment. Figure 4 In the embodiment shown, the HS driver correction circuit 204 may include a circuit 402, wherein the circuit 402 may be configured to receive the skew current Isk and generate a Figure 1 The HS skew parameters of the circuit 112 are shown. Figure 4 In the example shown, the circuit 402 can generate the HS skew parameters 112, which include bias currents such as the complementary correction current I HS + and I HS -. Complementary correction current I HS + and I HS - may be applied to the current mode pre-driver 406 to control the strength of the pre-driver current sources 408, 409. The output of the current mode pre-driver 406 may depend on the data_in signal, which may be determined by, for example Figure 1 The NAND gate 104 in the controller 103 is shown as providing a voltage drop. Changing the strength of the pre-driver current sources 408, 409 can change the drive strength of the current mode pre-driver 406. Changing the drive strength of the current mode pre-driver 406 can change the speed at which the HS transistor is turned on and off, thereby changing the rising slew rate of Vout.

[0029] Similarly, in Figure 4 In the illustrated embodiment, the LS driver correction circuit 206 may include a circuit 412, wherein the circuit 412 may be configured to receive the skew current Isk and generate a Figure 1 The LS skew parameters of the circuit 114 are shown. Figure 4 In the example shown, the circuit 412 can generate the LS skew parameters 114, which include a bias current, such as the complementary correction current I LS + and I LS -. Complementary correction current I LS + and I LS - may be applied to the current mode pre-driver 416 to control the strength of the pre-driver current sources 418, 419. Changing the strength of the pre-driver current sources 418, 419 may change the drive strength of the current mode pre-driver 416. The output of the current mode pre-driver 416 may depend on the data_in_n signal, which may be determined by, for example Figure 1 The NOR gate 106 in the controller 103 is shown as providing the signals data_in and data_in_n. The signals data_in and data_in_n may be complementary. Changing the drive strength of the current mode pre-driver 416 may change the speed at which the LS transistor is turned on and off, thereby changing the falling slew rate of Vout.

[0030] For example, if the HS replica 302 is more dominant than the LS replica 304 (or the HS transistor is more dominant than the LS transistor), the skew determination circuit 202 may push the skew current Isk to the circuit 402, and the circuit 402 may receive or see Isk having a positive value. In response to Isk having a positive value, the circuit 402 may set the complementary correction current I HS + and I HS -, to adjust the pre-driver current sources 408, 409 to reduce the transition speed of the HS transistor from the off state to the on state by a factor Isk. With respect to the LS transistor, the skew determination circuit 202 may push the skew current Isk to the circuit 412, and the circuit 412 may receive or see Isk having a positive value. In response to Isk having a positive value, the circuit 412 may set the complementary correction current I LS + and I LS −, to adjust the pre-driver current sources 418, 419 to increase the transition speed of the LS transistor from the on state to the off state by a factor Isk.

[0031] If the HS replica 302 is less dominant than the LS replica 304 (or the HS transistor is less dominant than the LS transistor), the skew determination circuit 202 may pull the skew current Isk from the circuit 402, and the circuit 402 may receive or see Isk having a negative value. In response to Isk having a negative value, the circuit 402 may set the complementary correction current I HS + and I HS- to adjust the pre-driver current sources 408, 409 to increase the transition speed of the HS transistor from the off state to the on state by a factor Isk. With respect to the LS transistor, the skew determination circuit 202 may pull the skew current Isk from the circuit 412, and the circuit 412 may receive or see Isk having a negative value. In response to Isk having a negative value, the circuit 412 may set the complementary correction current I LS + and I LS −, to adjust the pre-driver current sources 418, 419 to reduce the transition speed of the LS transistor from the on state to the off state by a factor Isk.

[0032] Therefore, when the HS transistors are more dominant, the rising slew rate of the output driver stage 108 can be reduced, and the falling slew rate of the output driver stage 108 can be increased by the same factor Isk to achieve the desired duty cycle (e.g., 50% for DDR memory applications). When the HS transistors are less dominant, the rising slew rate of the output driver stage 108 can be increased, and the falling slew rate of the output driver stage 108 can be reduced by the same factor Isk to achieve the desired duty cycle.

[0033] Figure 5 FIG is a diagram illustrating another exemplary implementation of a drive correction circuit that may be used for bevel drive compensation in one embodiment. Figure 5 In the illustrated embodiment, the HS drive correction circuit 204 may include a voltage control circuit 502 ("circuit 502"). The voltage control circuit 502 may be a circuit configured to control the voltage level of the voltage-mode pre-driver 506. The circuit 502 may receive the skew current Isk and use Isk to determine Figure 1 The HS skew parameter 112 is shown. Figure 5 In the example shown, the HS skew parameters 112 may include parameters for adjusting the drive voltage level for driving the HS transistors, such as the bias voltage V HSbias .exist Figure 5 In the embodiment shown, circuit 502 may use Isk to change the output of complementary metal oxide semiconductor (CMOS) inverter 508 in voltage mode pre-driver 506. The output of CMOS inverter 508 may depend on data_in signal, which may be determined by, for example, Figure 1 The NAND gate 104 in the controller 103 is shown as providing.

[0034] If the circuit 502 is disabled and data_in is a high voltage (e.g., a voltage representing a logic one or high logic), the CMOS inverter 508 will register a low voltage output (e.g., a voltage representing a logic zero or low logic, 0V). If the circuit 502 is enabled and data_in is a high voltage, the CMOS inverter 508 will output a low voltage, which in this embodiment may be V Hsbias Output level V Hsbias It can be adjusted by Isk via circuit 502. Adjusting the output level of CMOS inverter 508 can adjust the driving strength of the HS transistor, thereby affecting the rising slew rate of Vout.

[0035] In addition, Figure 5 In the illustrated embodiment, the LS driver correction circuit 206 may include a voltage control circuit 512 ("circuit 512"). The voltage control circuit 512 may be a circuit configured to control the voltage level of the voltage-mode pre-driver 516. The circuit 512 may receive the skew current Isk and use Isk to determine Figure 1 The LS skew parameter 114 is shown. Figure 5 In the example shown, the LS bias parameters 114 may include parameters for adjusting the driving voltage level for driving the LS transistor, such as the bias voltage V Lsbias .exist Figure 5 In the embodiment shown, circuit 512 may use Isk to change the output of CMOS inverter 518 in voltage-mode pre-driver 516. The output of CMOS inverter 518 may depend on data_in_n signal, which may be provided by, for example, Figure 1 A NOR gate 106 is shown in the controller 103 to provide.

[0036] If the circuit 512 is disabled and data_in_n is a low voltage, the CMOS inverter 518 will output a high voltage (e.g., a voltage representing a logic one or high logic). If the circuit 512 is enabled and data_in_n is a low voltage, the CMOS inverter 518 will output a high voltage, which in this embodiment may be V Lsbias Output level V Lsbias It can be adjusted by Isk via circuit 512. Adjusting the output level of CMOS inverter 518 can adjust the drive strength of the LS transistor, thereby affecting the falling slew rate of Vout.

[0037] If Isk indicates that the HS transistor is more dominant, circuit 502 may remain disabled, but circuit 512 may be enabled to increase the falling slew rate of output driver stage 108. If Isk indicates that the HS transistor is less dominant, circuit 512 may remain disabled, but circuit 502 may be enabled to increase the rising slew rate of output driver stage 108. The adjustments to both the rising and falling slew rates may be based on the same factor, Isk.

[0038] Figure 6 is a flow chart of an exemplary process by which bevel drive compensation may be implemented in one embodiment. Figure 6 The process 600 in FIG. 5 can be implemented using, for example, the apparatus 100 discussed above. The process 600 may include one or more operations, actions, or functions, as shown by one or more of blocks 602, 604, 606, 608, and / or 610. Although shown as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, performed in a different order, or performed in parallel, depending on the desired implementation.

[0039] Process 600 can be performed by a driver circuit, such as a push-pull driver (driver circuit 100 described herein). Process 600 can begin at block 602, where the driver circuit can determine a skew measurement of an output driver stage of the driver circuit. Process 600 can continue from block 602 to block 604. At block 604, the driver circuit can determine a first skew parameter based on the skew measurement. Process 600 can continue from block 604 to block 606. At block 606, the driver circuit can apply a first bias that can depend on the skew measurement to drive the high-side transistor of the output driver stage. Process 600 can continue from block 606 to block 608. At block 608, the driver circuit can determine a second skew parameter based on the skew measurement. Process 600 can continue from block 608 to block 610. At block 610, the driver circuit can apply a second bias that can depend on the skew measurement to drive the low-side transistor of the output driver stage. The first bias and the second bias can be complementary.

[0040] In one embodiment, the skew measurement can indicate an imbalance between the replica of the high-side transistor and the replica of the low-side transistor. In another embodiment, the driver circuit 100 can determine the skew measurement by applying a reference current to a current mirror formed by at least a replica of the high-side transistor and a replica of the low-side transistor. The driver circuit can also obtain an output of the current mirror representing the skew measurement. In another embodiment, the driver circuit can apply a first bias to a first pre-driver configured to drive the high-side transistor, and can also apply a second bias to a second pre-driver configured to drive the low-side transistor. In another embodiment, the driver circuit can apply a first bias by applying a first bias current to adjust the current source of the first current-mode pre-driver configured to drive the high-side transistor. The driver circuit can also apply a second bias by applying a second bias current to adjust the current source of the second current-mode pre-driver configured to drive the low-side transistor. In another example, the driver circuit can apply a first bias by applying a first bias voltage to adjust the drive voltage output by the first current-mode pre-driver configured to drive the high-side transistor. The driver circuit may also apply a second bias by applying a second bias voltage to adjust a driving voltage output by a second voltage-mode pre-driver configured to drive the low-side transistor.

[0041] The flowcharts and block diagrams in the figures illustrate the architecture, functionality and operation of possible specific implementations of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions annotated in the box may not appear in the order annotated in the figure. For example, depending on the functions involved, two boxes shown in succession may actually be implemented substantially simultaneously, or sometimes the boxes may be implemented in the opposite order. It should also be noted that each block in the block diagram and / or flowchart illustration, as well as the combination of blocks in the block diagram and / or flowchart illustration, may be implemented by a dedicated hardware-based system that can perform the specified function or behavior, or a combination of dedicated hardware and computer instructions.

[0042] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a," "an," and "the" also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when used in this specification, the terms "comprises" and "comprising" explicitly indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0043] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements (if any) in the appended claims are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The disclosed embodiments of the invention are presented for purposes of illustration and description and are not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, and to enable those skilled in the art to understand the invention for various embodiments with various modifications suitable for the particular use contemplated.

Claims

1. A semiconductor device, comprising: A first circuit configured for skew measurement of an output driver stage in an output driver circuit; The second circuit is configured as follows: determining a first skew parameter based on the skew measurement; and applying a first bias dependent on the skew measurement to drive a high-side transistor in the output driver stage; The third circuit is configured as: determining a second skew parameter based on the skew measurement; and A second bias dependent on the skew measurement is applied to drive a low-side transistor in the output driver stage, wherein the first bias and the second bias are complementary.

2. The semiconductor device according to claim 1, wherein: The first circuit includes a copy of the high-side transistor and a copy of the low-side transistor; and The skew measurement indicates an imbalance between the copy of the high-side transistor and the copy of the low-side transistor.

3. The semiconductor device according to claim 1, wherein: The first circuit includes a current mirror formed by at least a copy of the high-side transistor and a copy of the low-side transistor; and The skew measurement is representative of the output current of the current mirror.

4. The semiconductor device according to claim 1, further comprising: a first pre-driver configured to drive the high-side transistor; a second pre-driver configured to drive the low-side transistor; The second circuit is configured to apply the first bias to the first pre-driver; and The third circuit is configured to apply the second bias to the second pre-driver.

5. The semiconductor device according to claim 4, wherein: The first pre-driver is a first current mode pre-driver; The second pre-driver is a second current mode pre-driver; The first bias is a first bias current; The second bias is a second bias current; The second circuit is configured to apply the first bias current to adjust a current source of the first current-mode pre-driver; and The third circuit is configured to apply the second bias current to adjust a current source of the second current-mode pre-driver.

6. The semiconductor device according to claim 4, wherein: The first pre-driver is a first voltage mode pre-driver; The second pre-driver is a second voltage mode pre-driver; The first bias is a first bias voltage; The second bias is a second bias voltage; The second circuit is configured to apply the first bias voltage to adjust a drive voltage output by the first voltage-mode pre-driver; and The third circuit is configured to apply the second bias voltage to adjust a driving voltage output by the second voltage-mode pre-driver.

7. The semiconductor device according to claim 1, wherein the drive circuit is a push-pull driver.

8. An apparatus comprising: a controller configured to receive an input signal; an output driver stage, the output driver stage comprising a high-side transistor and a low-side transistor, the output driver stage configured to switch the high-side transistor and the low-side transistor to output an output voltage representative of the input signal; The circuit is configured as: determining a skew measurement of the output driver stage; determining a first skew parameter based on the skew measurement; applying a first bias dependent upon the skew measurement to drive the high-side transistor; determining a second skew parameter based on the skew measurement; and A second bias dependent on the skew measurement is applied to drive the low-side transistor, wherein the first bias and the second bias are complementary.

9. The device according to claim 8, wherein: The circuit includes a copy of the high-side transistor and a copy of the low-side transistor; and The skew measurement indicates an imbalance between the copy of the high-side transistor and the copy of the low-side transistor.

10. The device according to claim 8, wherein: The circuit includes a current mirror formed by at least a copy of the high-side transistor and a copy of the low-side transistor; and The skew measurement is representative of the output current of the current mirror.

11. The apparatus according to claim 8, further comprising: a first pre-driver configured to drive the high-side transistor; a second pre-driver configured to drive the low-side transistor; The circuit is configured as: applying the first bias to the first pre-driver; and The second bias is applied to the second pre-driver.

12. The device according to claim 11, wherein: The first pre-driver is a first current mode pre-driver configured to drive the high-side transistor; The second pre-driver is a second current mode pre-driver configured to drive the low-side transistor; The first bias is a first bias current; The second bias is a second bias current; The circuit is configured as: applying the first bias current to adjust a current source of the first current mode pre-driver; and The second bias current is applied to adjust a current source of the second current mode pre-driver.

13. The device according to claim 11, wherein: The first pre-driver is a first voltage-mode pre-driver configured to drive the high-side transistor; The second pre-driver is a second voltage mode pre-driver configured to drive the low-side transistor; The first bias is a first bias voltage; The second bias is a second bias voltage; The circuit is configured as: applying the first bias voltage to adjust a drive voltage output by the first voltage-mode pre-driver; and The second bias voltage is applied to adjust a driving voltage output by the second voltage-mode pre-driver.

14. The apparatus of claim 8, wherein the controller, the output driver stage, and the circuit are parts of a push-pull driver.

15. A method for operating a driver circuit, the method comprising: determining a skew measurement of an output driver stage of a driver circuit; determining a first skew parameter based on the skew measurement; applying a first bias dependent upon the skew measurement to drive a high-side transistor of the output driver stage; determining a second skew parameter based on the skew measurement; and A second bias dependent on the skew measurement is applied to drive a low-side transistor of the output driver stage, wherein the first bias and the second bias are complementary.

16. The method of claim 15, wherein: The skew measurement indicates an imbalance between the copy of the high-side transistor and the copy of the low-side transistor.

17. The method of claim 15, wherein determining the skew measurement comprises: applying a reference current to a current mirror formed by at least a copy of the high-side transistor and a copy of the low-side transistor; and An output of the current mirror is obtained that represents the deflection measurement.

18. The method according to claim 15, further comprising: applying the first bias to a first pre-driver configured to drive the high-side transistor; and The second bias is applied to a second pre-driver configured to drive the low-side transistor.

19. The method of claim 15, wherein: Applying the first bias includes: applying a first bias current to adjust a current source of a first current mode pre-driver configured to drive the high-side transistor; and Applying the second bias includes applying a second bias current to adjust a current source of a second current mode pre-driver configured to drive the low-side transistor.

20. The method of claim 15, wherein: Applying the first bias includes: applying a first bias voltage to adjust a drive voltage output by a first current mode pre-driver configured to drive the high-side transistor; and Applying the second bias includes applying a second bias voltage to adjust a driving voltage output by a second voltage-mode pre-driver configured to drive the low-side transistor.

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