Driving circuit, inverter, circuit board and electronic equipment

Abstract

The embodiment of the invention discloses a driving circuit, an inverter, a circuit board and electronic equipment. A comparator receives inductive current and reference current of the inverter, and the output end of the comparator is connected with the first input end of a trigger; the second input end of the trigger is connected with the first end of the first filter, and the output end of the trigger is connected with the first input end of the latch; the second input end of the latch is connected with the output end of the first timer, the output end of the latch is connected with the input end of the NOT gate module and the first end of the second filter, and the output end of the NOT gate module is used for controlling the on-off of the auxiliary switching tube; the second end of the second filter is connected with the first input end of the AND gate module, the output end of the AND gate module is connected with the second end of the first filter, the second input end of the AND gate module is used for receiving a logic value corresponding to preset pulse time, and the output end of the AND gate module is used for controlling on and off of a main switching tube. Total harmonic distortion is reduced, and output current quality is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of current control technology, and in particular to a drive circuit, an inverter, a circuit board and an electronic device. Background Art

[0002] An inverter is a converter that converts DC power into constant frequency and voltage or frequency and voltage-regulated AC power. It consists of an inverter bridge, control logic, and filter circuits. Inverters are widely used in people's daily lives, such as air conditioners, home theaters, computers, televisions, fans, refrigerators, and so on.

[0003] Inverter main circuit Figure 1 As shown, existing inverters are usually controlled in the form of soft switching. The use of soft switching helps to increase the switching frequency, reduce the size of the inverter and reduce electromagnetic interference. Currently, the critical current mode can be used to achieve soft switching. In order to have sufficient time to achieve soft switching control, the control switch tube of the critical current mode delays a period of dead time after the inductor current drops to zero and then resets the cycle. The resonance of the inductor current during the dead time is used to charge and discharge the junction capacitance of the switch tube to achieve zero voltage switching. Although this method can use the resonance of the inductor current to achieve zero voltage switching of the switch tube, it will cause the overall waveform of the inductor current to be deformed, affecting the quality of the output current. Summary of the invention

[0004] The embodiments of the present application provide a drive circuit, an inverter, a circuit board and an electronic device, which can solve the problem of poor output current quality during the inverter control process, reduce total harmonic distortion, and improve the quality of the output current.

[0005] In a first aspect, an embodiment of the present application provides a driving circuit for an inverter, comprising a comparator, a trigger, a latch, a first filter, a second filter, a first timer, a NOT gate module, and an AND gate module;

[0006] The output end of the comparator is connected to the first input end of the trigger, and the input end of the comparator is used to receive the inductor current and the reference current of the inverter;

[0007] The second input terminal of the trigger is connected to the first terminal of the first filter, and the output terminal of the trigger is connected to the first input terminal of the latch;

[0008] The second input end of the latch is connected to the output end of the first timer, the output end of the latch is connected to the input end of the NOT gate module and the first end of the second filter, the first timer is used to determine the input value of the second input end of the latch according to the dead time of the main switch tube or the auxiliary switch tube of the inverter, and the output end of the NOT gate module is used to control the on and off of the auxiliary switch tube of the inverter;

[0009] The second end of the second filter is connected to the first input end of the AND gate module, the output end of the AND gate module is connected to the second end of the first filter, the second input end of the AND gate module is used to receive a logic value obtained according to a preset pulse time of the main switch tube of the inverter, and the output end of the AND gate module is used to control the on and off of the main switch tube of the inverter.

[0010] In a second aspect, an embodiment of the present application provides an inverter, including a main circuit and the above-mentioned drive circuit, the main circuit including a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a resonance module;

[0011] The source of the first switch tube is connected to the drain of the second switch tube and the first end of the resonance module, the drain of the first switch tube and the drain of the third switch tube are used to connect to the positive end of the power supply, and the source of the second switch tube and the source of the fourth switch tube are used to connect to the negative end of the power supply;

[0012] The source of the third switch tube is connected to the drain of the fourth switch tube and the second end of the resonance module, and the second end of the resonance module and the third end of the resonance module are used to connect to the electrical device;

[0013] The gate of the first switch tube and the gate of the fourth switch tube are connected to the output end of the AND gate module of the driving circuit;

[0014] The gate of the second switch tube and the gate of the third switch are connected to the output end of the NOT gate module of the driving circuit.

[0015] In a third aspect, an embodiment of the present application provides a circuit board, comprising the drive circuit described in the first aspect or the inverter described in the second aspect.

[0016] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising the drive circuit described in the first aspect or the inverter described in the second aspect or the circuit board described in the third aspect.

[0017] The embodiment of the present application is driven by hardware devices such as a comparator, a trigger, a latch, a first filter, a second filter, a first timer, a NOT gate module and an AND gate module, and does not need to be processed by a controller, thereby avoiding the delay caused by sampling processing and affecting the quality of the output current, thereby solving the problem of poor output current quality in the existing inverter control process, reducing total harmonic distortion, and improving the quality of the output current. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of an inverter main circuit provided in an embodiment of the present application;

[0019] Figure 2 is a schematic diagram of a driving circuit provided in an embodiment of the present application;

[0020] Figure 3 is a first schematic diagram of an inductor current waveform corresponding to a driving circuit provided in an embodiment of the present application;

[0021] Figure 4 This is a second schematic diagram of an inductor current waveform corresponding to a driving circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and advantages of the present application clearer, the specific embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. It is understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for the convenience of description, only the part related to the present application but not all the contents are shown in the accompanying drawings. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow chart describes each operation (or step) as a sequential process, many of the operations therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of each operation can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0023] The current control in the main circuit of the traditional inverter generally chooses to control the output current, and adopts the conventional sinusoidal pulse width modulation method for regulation. The drive signal of each power switch tube is obtained by the intersection of the sinusoidal modulation wave and the triangular carrier. In this control mode of the sinusoidal pulse width modulation method, the inductor current in the main circuit of the inverter works in the continuous current mode. If no additional auxiliary circuit is added, the switch tube cannot achieve soft switching, and when the switch tube is turned off, the reverse recovery loss on its body diode is serious, and the overall working efficiency is low. It is less applicable to high-efficiency application fields such as micro inverters.

[0024] Inverter main circuit Figure 1 As shown, existing inverters are usually controlled in the form of soft switching. The use of soft switching helps to increase the switching frequency, reduce the size of the inverter and reduce electromagnetic interference. Currently, critical current mode or discontinuous current mode can be used to achieve soft switching. There may be inductor current distortion under discontinuous current, which affects the quality of the output current. In order to have sufficient time to achieve soft switching control, the control switch tube of the critical current mode delays a dead time after the inductor current drops to zero and then performs a periodic reset. The resonance of the inductor current during the dead time is used to charge and discharge the junction capacitance of the switch tube to achieve zero voltage switching. Although this method can use the resonance of the inductor current to achieve zero voltage switching of the switch tube, it will cause the overall waveform of the inductor current to be deformed, which also affects the quality of the output current.

[0025] Based on the above, in the critical current mode, the reset value of the inductor current is reduced from zero to a smaller negative value to ensure soft switching. The inductor current is controlled to drop to the preset lower limit value (-i min ) is reset periodically so that it flows bidirectionally in each cycle. The negative current is used to ensure that the charge and discharge process of the switch tube junction capacitance can be completed within a shorter dead time, thereby ensuring the zero voltage turn-on of the switch tube. However, the analog-to-digital conversion performed in this mode during the digital signal processing will cause a time delay in the sampling signal, which will affect the calculation of the corresponding parameters of the switch tube, and further affect the output current, causing the output grid-connected current to be skewed and the total harmonic distortion to be high. In order to eliminate this effect, the sampling loop influence speed and the analog-to-digital conversion speed can be increased, but this will increase the cost relatively.

[0026] The drive circuit, inverter, circuit board and electronic device provided in the present application are intended to be driven by hardware devices such as comparators, triggers, latches, first filters, second filters, first timers, NOT gate modules and AND gate modules during inverter drive control, without the need for processing by a controller, so as to avoid the time delay caused by sampling processing affecting the quality of the output current, thereby reducing the total harmonic distortion and improving the quality of the output current. Compared with the traditional driving method under the critical current mode, it usually causes the overall waveform of the inductor current to be deformed, affecting the quality of the output current. Based on this, a drive circuit of an embodiment of the present application is provided to solve the problem of poor output current quality in the existing inverter control process.

[0027] Figure 2 is a schematic diagram of a driving circuit provided in an embodiment of the present application, referring to Figure 2 , the driving circuit is used for an inverter, and specifically includes a comparator 10, a trigger 11, a latch 12, a first filter 13, a second filter 14, a first timer 15, a NOT gate module 16 and an AND gate module 17. The output end of the comparator 10 is connected to the first input end of the trigger 11, and the input end of the comparator 10 is used to receive the inductor current and the reference current of the inverter. The comparator 10 is used to compare the received current sampling value of the inductor current in the main circuit of the inverter with the received current reference value of the reference current to obtain a comparison result, and input the comparison result to the first input end of the trigger 11. The second input end of the trigger 11 is connected to the first end of the first filter 13, and the output end of the trigger 11 is connected to the first input end of the latch 12 (for example, the S end of the RS latch). The trigger 11 is used to generate a current sampling value (i ) of the inductor current in the main circuit of the inverter according to the current sampling value (i L ) and the preset current reference value (i min) or according to the comparison result of the driving current of the main switch tube of the inverter, the first input value of the latch 12 is determined. The second input end of the latch 12 (for example, the R end of the RS latch) is connected to the output end of the first timer 15, and the output end of the latch 12 is connected to the input end of the NOT gate module 16 and the first end of the second filter 14. The first timer 15 is used to determine the input value of the second input end of the latch 12 according to the dead time of the main switch tube or the auxiliary switch tube of the inverter. It should be noted that the first timer 15 pre-stores the corresponding dead time of the main switch tube and the dead time of the auxiliary switch tube. The output end of the NOT gate module 16 is used to control the on and off of the auxiliary switch tube of the inverter. The second end of the second filter 14 is connected to the first input end of the AND gate module 17, and the output end of the AND gate module 17 is connected to the second end of the first filter 13. The second input end of the AND gate module 17 is used to receive the logic value obtained according to the preset pulse time of the main switch tube of the inverter, and the output end of the AND gate module 17 is used to control the on and off of the main switch tube of the inverter. The latch 12 is used to output a corresponding output value according to the first input value, the second input value and the preset first comparison relationship. The NOT gate module 16 is used to control the on and off of the auxiliary switch tube of the inverter according to the output value of the latch 12. The AND gate module 17 is used to control the on and off of the main switch tube of the inverter according to the output value of the latch 12 and the logic value obtained according to the preset pulse time of the main switch tube of the inverter.

[0028] It should be noted that the first end of the first filter 13 can be understood as the output end of the first filter 13, and the second end can be understood as the input end of the first filter 13. The first end of the second filter 14 can be understood as the input end of the second filter 14, and the second end can be understood as the output end of the second filter 14.

[0029] Figure 3 is a first schematic diagram of an inductor current waveform corresponding to a driving circuit provided in an embodiment of the present application, referring to Figure 3 Through the setting of the aforementioned driving circuit, the comparator 10, the trigger 11, the latch 12, the first filter 13, the second filter 14, the first timer 15, the NOT gate module 16 and the AND gate module 17 and other hardware devices are driven, and there is no need to process through the controller, so as to avoid the delay caused by the sampling process affecting the quality of the output current. The total harmonic distortion of the inductor current waveform is small, and the quality of the output current is improved.

[0030] In one embodiment, the first filter 13 includes a first capacitor C1 and a first resistor R1. The first end of the first capacitor C1 is connected to the second input end of the trigger 11 and the first end of the first resistor R1, and the second end of the first capacitor C1 is grounded. The second end of the first resistor R1 is connected to the output end of the AND gate module 17. The first filter 13 is provided to provide sufficient time for the inductor current to achieve zero voltage switching within the dead time, thereby improving the device utilization and extending the device service life.

[0031] In one embodiment, the second filter 14 includes a second resistor R2 and a second capacitor C2. The first end of the second resistor R2 is connected to the output end of the latch 12, and the second end of the second resistor R2 is connected to the first end of the second capacitor C2 and the first input end of the AND gate module 17; the second end of the second capacitor C2 is grounded. The second filter 14 plays a role in preventing direct-through, thereby protecting the circuit and extending the service life of the device.

[0032] In one embodiment, the latch 12 is an RS latch, the first input terminal of the latch 12 is the S terminal, and the second input terminal of the latch 12 is the R terminal. A first comparison relationship can be preset, that is, a truth table of the RS latch can be preset, and the corresponding output value Q can be obtained according to the input values ​​of the S terminal and the R terminal and the preset first comparison relationship. The truth table of the preset RS latch is shown in the following table:

[0033] R S Q 0 0 Unstable 0 1 0 1 0 1 1 1 Keep

[0034] In one embodiment, the trigger 11 is a rising falling edge trigger, which is used to output a high level signal when receiving a falling edge signal, and output a low level signal when receiving a rising edge signal.

[0035] In one embodiment, the driving circuit further includes a second timer 18 or a control module (which can be arranged at the position of the reference numeral 18 in the figure). The output end of the second timer 18 is connected to the second input end of the AND gate module 17, and the second timer 18 is used to determine the input value of the second end of the AND gate module 17 according to the preset pulse time of the main switch tube of the inverter. The output end of the control module is connected to the second input end of the AND gate module 17, and the control module is used to determine the input value of the second end of the AND gate module 17 according to the preset pulse time of the main switch tube of the inverter.

[0036] In one embodiment, the inverter includes a main circuit and the aforementioned drive circuit. Figure 1 As shown, the main circuit includes a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4 and a resonance module 19. The source of the first switch tube Q1 is connected to the drain of the second switch tube Q2 and the first end of the resonance module 19, and the drain of the first switch tube Q1 and the drain of the third switch tube Q3 are used to connect to the power supply (U bus), the source of the second switch tube Q2 and the source of the fourth switch tube Q4 are used to connect the power supply (U bus The source of the third switch tube Q3 is connected to the drain of the fourth switch tube Q4 and the second end of the resonance module 19. The second end of the resonance module 19 and the third end of the resonance module 19 are used to connect to an electrical device, that is, to output a voltage (U grid The gate of the first switch tube Q1 (g s1 ) and the gate of the fourth switch tube Q4 (g s4 ) is connected to the output end of the AND gate module 17 of the driving circuit. The gate of the second switch tube Q2 (g s2 ) and the gate of the third switch tube Q3 (g s3 ) is connected to the output end of the NOT gate module 16 of the driving circuit.

[0037] In one embodiment, the resonance module 19 includes a first inductor L s , the second inductor L f and the third capacitor C f The first inductor L s The first end of the first inductor L is connected to the source of the first switch tube Q1 and the drain of the second switch tube Q2. s The second end of the second inductor L f The first end and the third capacitor C f The first end of the third capacitor C f The second end of the third capacitor C is connected to the source of the third switch tube Q3 and the drain of the fourth switch tube Q4. f The second end of the second inductor L f The second end is used to connect the electrical device, that is, to output voltage (U grid ).

[0038] In one embodiment, the main switch tubes are the first switch tube Q1 and the fourth switch tube Q4, the auxiliary switch tubes are the second switch tube Q2 and the third switch tube Q3, the latch 12 is an RS latch, and the trigger 11 is a rising and falling edge trigger. The current sampling value of the inductor current in the main circuit of the inverter is i L , the current reference value of the reference current is i min It should be noted that the current reference value can be understood as the preset current lower limit value. L min Change to i L >i min When the falling edge triggers, the output terminal of the trigger 11 outputs a high level signal, that is, the input value of the S terminal of the latch 12 is S=1. When the current sampling value of the inductor current changes from i L >i min Change to i​L min When , it is a rising edge trigger, and the output end of the trigger 11 outputs a low level signal, that is, the input value of the S end of the latch 12 is S=0. The output end of the trigger 11 is connected to the S end of the RS latch, and the input value of the R end of the latch 12 is determined by the dead time of the main switch tube or the auxiliary switch tube. That is, the input value of the R end of the latch 12 is determined by the first timer 15 according to the dead time of the main switch tube (that is, the first switch tube Q1 and the fourth switch tube Q4) or the dead time of the auxiliary switch tube (that is, the second switch tube Q2 and the third switch tube Q3). According to the input value of the R end and the input value of the S end and the aforementioned preset RS latch truth table, the output value Q of the output end of the latch 12 can be obtained. Based on the output end of the latch 12 being connected to the NOT gate module 16, the output end of the NOT gate module 16 is used to control the conduction of the auxiliary switch tubes (i.e., the second switch tube Q2 and the third switch tube Q3). Therefore, when Q=0, the auxiliary switch tubes (i.e., the second switch tube Q2 and the third switch tube Q3) are turned on.

[0039] When the main switch tube (i.e., the first switch tube Q1 and the fourth switch tube Q4) is turned on, the inductor current increases; when the auxiliary switch tube (i.e., the second switch tube Q2 and the third switch tube Q3) is turned on, the inductor current decreases; the preset peak inductor current is i peak .

[0040] By formula Calculate the main switch tube main opening time t up , where i peak Represents the preset peak inductor current, i min Represents the current reference value, U bus Represents the input voltage value, that is, the voltage value of the input main circuit; U grid Represents the output voltage value, that is, the voltage value output by the main circuit; L s represents the inductance value of the first inductor Ls.

[0041] By formula Calculate the auxiliary switch tube auxiliary turn-on time t down , where i peak Represents the preset peak inductor current, i min Represents the current reference value, U bus Represents the input voltage value, that is, the voltage value of the input main circuit; U grid Represents the output voltage value, that is, the voltage value output by the main circuit; L s represents the inductance value of the first inductor Ls.

[0042] By formula Calculate the dead time t of the main switch 14 , where C mos ​Represents the capacitance value of the switch junction capacitance. It should be noted that C mos It may be the capacitance value of the junction capacitance of the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the first switch tube Q4. The capacitance value of the junction capacitance of the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the first switch tube Q4 is the same.

[0043] By formula Calculate the dead time t of the auxiliary switch tube 23 , where C mos Represents the capacitance value of the switch junction capacitance. It should be noted that C mos It may be the capacitance value of the junction capacitance of the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the first switch tube Q4. The capacitance value of the junction capacitance of the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the fourth switch tube Q4 is the same.

[0044] By the formula T = t up +t down +t 14 +t 23 , calculate the switching cycle T. According to the switching cycle T, determine a lower limit value T of time min , set the switching period T greater than the lower limit T min .

[0045] The dead time t of the main switch tube is pre-stored in the first timer 15. 14 and the auxiliary switch dead time t 23 , used to determine the dead time t of the main switch 14 and the auxiliary switch dead time t 23 The corresponding logic value is output to the R terminal of the RS latch. The main on time t of the main switch tube is pre-stored in the second timer 18 or the control module. up , auxiliary switch tube auxiliary turn-on time t down and the switching cycle T, which is used to calculate the main on-time t of the pre-stored main switch tube. up , auxiliary switch tube auxiliary turn-on time t down The logic value corresponding to the switching cycle T output is given to the second input terminal of the AND gate module 17.

[0046] Reference Figure 1 and Figure 2, assuming that the initial state is that the auxiliary switch is in the off state, that is, the second switch Q2 and the third switch Q3 are not turned on, at this time, the input value of the S end of the RS latch is S=0, the input value of the R end is R=1, and the output value of the RS latch is Q=1. The auxiliary switch (i.e., the second switch Q2 and the third switch Q3) is controlled to be in the off state through the NOT gate module 16. When the timing in the second timer 18 or the control module reaches the switching cycle T, the second timer 18 or the control module outputs a high-level signal to the second input end of the AND gate module 17. Based on the output value Q=1 of the RS latch, the first input end of the AND gate module 17 also receives a high-level signal, and the output end of the AND gate module 17 outputs a high-level signal to the main switch (i.e., the first switch Q1 and the fourth switch Q4) to control the main switch (i.e., the first switch Q1 and the fourth switch Q4) to turn on.

[0047] It should be noted that after the timing in the second timer 18 or the control module reaches the switching cycle T, the second timer 18 or the control module restarts the timing, that is, the timing of the switching cycle T is restarted.

[0048] After the main switch tubes (i.e., the first switch tube Q1 and the fourth switch tube Q4) are turned on, S=0 and R=1. Figure 3 and Figure 4 , based on the main switch tube (i.e., the first switch tube Q1 and the fourth switch tube Q4) being turned on, the inductor current continues to rise. At this time, the current sampling value i of the inductor current L >i min When the second timer 18 or the timing in the control module reaches the main opening time t of the main switch tube up , the second timer 18 or the control module outputs a low-level signal to the second input terminal of the AND gate module 17. Based on the high-level signal at the first input terminal of the AND gate module 17, the output terminal of the AND gate module 17 outputs a low-level signal to control the main switch tubes (i.e., the first switch tube Q1 and the fourth switch tube Q4) to be disconnected. At this time, the first timer 15 starts timing, i.e., the dead time t 23 The output of the AND gate module 17 is connected to the second input of the rising and falling edge trigger (trigger 11) through the first filter 13. At this time, since the main switch tube (i.e., the first switch tube Q1 and the fourth switch tube Q4) are disconnected, the second input of the rising and falling edge trigger (trigger 11) detects the falling edge trigger and outputs a high level signal to the S end of the RS latch. At this time, S=1. The first timer 15 counts the dead time t of the auxiliary switch tube. 23 After that, the first timer 15 outputs a low level signal to the R terminal of the RS latch, that is, R=0. According to the truth table of the RS latch mentioned above, the output value Q=0 of the RS latch is obtained. At this time, a high level is output after passing through the NOT gate module 16, that is, the auxiliary switch tubes (that is, the second switch tube Q2 and the third switch tube Q3) are controlled to be turned on.

[0049] When the auxiliary switch tube (i.e., the second switch tube Q2 and the third switch tube Q3) are in the on state, the input of the RS latch is S=1, R=0, and the current sampling value of the inductor current i L >i min , based on the conduction of the auxiliary switch tube, such as Figure 3 and Figure 4 As shown, the inductor current continues to decrease until the current sampling value i of the inductor current reaches L <i min When the rising falling edge trigger (trigger 11) detects the falling edge trigger, it outputs a low level signal to the S terminal of the RS latch, that is, S=0. The first timer 15 counts the dead time t of the main switch tube. 14 After that, the first timer 15 outputs a high-level signal to the R terminal of the RS latch, that is, R=1. Based on S=0, R=1, according to the aforementioned truth table of the RS latch, the output value Q=1 of the RS latch is obtained. At this time, the auxiliary switch tube (i.e., the second switch tube Q2 and the third switch tube Q3) is controlled to be disconnected through the NOT gate module 16. When the timing in the second timer 18 or the control module reaches the switching cycle T, the second timer 18 or the control module outputs a high-level signal to the second input terminal of the AND gate module 17. Based on the output value Q=1 of the RS latch, the first input terminal of the AND gate module 17 also receives a high-level signal, and the output terminal of the AND gate module 17 outputs a high-level signal to the main switch tube (i.e., the first switch tube Q1 and the fourth switch tube Q4) to control the main switch tube (i.e., the first switch tube Q1 and the fourth switch tube Q4) to be turned on.

[0050] As described above, through the cooperation of hardware devices such as the comparator 10, the trigger 11, the latch 12, the first filter 13, the second filter 14, the first timer 15, the NOT gate module 16 and the AND gate module 17, the zero voltage opening of the inverter main circuit is realized, avoiding the use of an independent control chip for processing, saving cost investment. In addition, by driving the hardware devices such as the comparator 10, the trigger 11, the latch 12, the first filter 13, the second filter 14, the first timer 15, the NOT gate module 16 and the AND gate module 17, there is no need to process through the controller, avoiding the delay caused by the sampling process to affect the quality of the output current, reducing the total harmonic distortion, and improving the quality of the output current.

[0051] Based on the above embodiment, the embodiment of the present application further provides an inverter, including a main circuit and the above-mentioned drive circuit. Figure 1As shown, the main circuit includes a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4 and a resonance module 19. The source of the first switch tube Q1 is connected to the drain of the second switch tube Q2 and the first end of the resonance module 19, and the drain of the first switch tube Q1 and the drain of the third switch tube Q3 are used to connect to the power supply (U bus ), the source of the second switch tube Q2 and the source of the fourth switch tube Q4 are used to connect the power supply (U bus The source of the third switch tube Q3 is connected to the drain of the fourth switch tube Q4 and the second end of the resonance module 19. The second end of the resonance module 19 and the third end of the resonance module 19 are used to connect to an electrical device, that is, to output a voltage (U grid The gate of the first switch tube Q1 (g s1 ) and the gate of the fourth switch tube Q4 (g s4 ) is connected to the output end of the AND gate module 17 of the driving circuit. The gate of the second switch tube Q2 (g s2 ) and the gate of the third switch tube Q3 (g s3 ) is connected to the output end of the NOT gate module 16 of the driving circuit.

[0052] In one embodiment, the resonance module 19 includes a first inductor L s , the second inductor L f and the third capacitor C f .

[0053] The first inductor L s The first end is connected to the source of the first switch tube Q1 and the drain of the second switch tube Q2.

[0054] The first inductor L s The second end of the second inductor Lf and the first end of the third capacitor C f The first end of the third capacitor C f The second end of the third capacitor C is connected to the source of the third switch tube Q3 and the drain of the fourth switch tube Q4. f The second end of the second inductor L f The second end is used to connect the electrical device, that is, to output voltage (U grid ).

[0055] Based on the above embodiments, an embodiment of the present application further provides a circuit board, including the above-mentioned drive circuit or inverter.

[0056] On the basis of the above embodiments, an embodiment of the present application further provides an electronic device, comprising the above-mentioned drive circuit or inverter or circuit board.

[0057] In the above, the comparator 10, the trigger 11, the latch 12, the first filter 13, the second filter 14, the first timer 15, the NOT gate module 16 and the AND gate module 17 and other hardware devices are driven, avoiding the use of an independent control chip for processing, saving cost investment. In addition, the comparator 10, the trigger 11, the latch 12, the first filter 13, the second filter 14, the first timer 15, the NOT gate module 16 and the AND gate module 17 and other hardware devices are driven, and there is no need to process through the controller, so as to avoid the delay caused by the sampling process affecting the quality of the output current, reduce the total harmonic distortion, and improve the quality of the output current.

[0058] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0059] In this application, unless otherwise clearly specified and limited, the terms "set", "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0060] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0061] It should be noted that, in the present application, unless otherwise clearly specified and limited, the first feature being “above” or “below” the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being “above”, “above” and “above” the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the horizontal surface height of the first feature is higher than that of the second feature. The first feature being “below”, “below” and “below” the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the horizontal surface height of the first feature is lower than that of the second feature.

[0062] The above is only a preferred specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can make equivalent substitutions or changes within the technical scope disclosed in the present application according to the technical solution and application concept of the present application, which should be covered by the protection scope of the present application.

Claims

1. A driving circuit, characterized in that: Used in an inverter, comprising a comparator, a trigger, a latch, a first filter, a second filter, a first timer, a NOT gate module and an AND gate module; The output end of the comparator is connected to the first input end of the trigger, and the input end of the comparator is used to receive the inductor current and the reference current of the inverter; The second input terminal of the trigger is connected to the first terminal of the first filter, and the output terminal of the trigger is connected to the first input terminal of the latch; The second input end of the latch is connected to the output end of the first timer, the output end of the latch is connected to the input end of the NOT gate module and the first end of the second filter, the first timer is used to determine the input value of the second input end of the latch according to the dead time of the main switch tube or the auxiliary switch tube of the inverter, and the output end of the NOT gate module is used to control the on and off of the auxiliary switch tube of the inverter; The second end of the second filter is connected to the first input end of the AND gate module, the output end of the AND gate module is connected to the second end of the first filter, the second input end of the AND gate module is used to receive a logic value obtained according to a preset pulse time of the main switch tube of the inverter, and the output end of the AND gate module is used to control the on and off of the main switch tube of the inverter.

2. The driving circuit according to claim 1, characterized in that: The first filter includes a first capacitor and a first resistor; The first end of the first capacitor is connected to the second input end of the trigger and the first end of the first resistor, and the second end of the first capacitor is grounded; The second end of the first resistor is connected to the output end of the AND gate module.

3. The driving circuit according to claim 1, characterized in that: The second filter includes a second resistor and a second capacitor; The first end of the second resistor is connected to the output end of the latch, and the second end of the second resistor is connected to the first end of the second capacitor and the first input end of the AND gate module; The second terminal of the second capacitor is grounded.

4. The driving circuit according to any one of claims 1 to 3, characterized in that: The latch is an RS latch.

5. The driving circuit according to claim 4, characterized in that: The trigger is a rising and falling edge trigger, which is used to output a high level signal when receiving a falling edge signal, and output a low level signal when receiving a rising edge signal.

6. The driving circuit according to claim 1, characterized in that: The driving circuit also includes a second timer; The output end of the second timer is connected to the second input end of the AND gate module, and the second timer is used to determine the input value of the second end of the AND gate module according to the preset pulse time of the main switch tube of the inverter.

7. The driving circuit according to claim 1, characterized in that: The driving circuit also includes a control module; The output end of the control module is connected to the second input end of the AND gate module, and the control module is used to determine the input value of the second end of the AND gate module according to the preset pulse time of the main switch tube of the inverter.

8. An inverter, characterized in that: It comprises a main circuit and a driving circuit according to any one of claims 1 to 7, wherein the main circuit comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a resonance module; The source of the first switch tube is connected to the drain of the second switch tube and the first end of the resonance module, the drain of the first switch tube and the drain of the third switch tube are used to connect to the positive end of the power supply, and the source of the second switch tube and the source of the fourth switch tube are used to connect to the negative end of the power supply; The source of the third switch tube is connected to the drain of the fourth switch tube and the second end of the resonance module, and the second end of the resonance module and the third end of the resonance module are used to connect an electrical device; The gate of the first switch tube and the gate of the fourth switch tube are connected to the output end of the AND gate module of the driving circuit; The gate of the second switch tube and the gate of the third switch are connected to the output end of the NOT gate module of the driving circuit.

9. The inverter according to claim 8, characterized in that: The resonance module includes a first inductor, a second inductor and a third capacitor; The first end of the first inductor is connected to the source of the first switch tube and the drain of the second switch tube; The second end of the first inductor is connected to the first end of the second inductor and the first end of the first capacitor; The second end of the first capacitor is connected to the source of the third switch tube and the drain of the fourth switch tube, and the second end of the second capacitor and the second end of the second inductor are used to connect to an electrical device.

10. A circuit board, characterized in that: It comprises the drive circuit described in any one of claims 1-7 or the inverter described in any one of claims 8-9.

11. An electronic device, characterized in that: It comprises the drive circuit described in any one of claims 1 to 7, the inverter described in any one of claims 8 to 9, or the circuit board described in claim 10.

Images