A power distribution network (PDN) system, an electronic device, and a board-level network module

Abstract

A power distribution network (PDN) system, an electronic device, and a board-level network module. The PDN system includes a voltage regulation module (VRM), a board-level network module, and a load; the VRM includes a power supply, the board-level network module includes a first sampling resistor R1, a second sampling resistor R2, and a first capacitor C1, and the power supply supplies power to the load through the board-level network module; the power output terminal of the VRM is connected to the first end of R1 and the first end of R2; the second end of R1 and the second end of R2 are connected to the first end of C1 and the power input terminal of the load, and the second end of C1 is grounded. The embodiments of the present application can effectively suppress the PDN impedance and save the integration space.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and particularly to a power distribution network (PDN) system, an electronic device, and a board-level network module. Background Art

[0002] A power distribution network (PDN) system can transmit power to a load. To ensure the stability of the power supply, reduce voltage fluctuations, and ensure the normal operation of the system, the PDN system needs to set a target impedance Ztarget so that within a specific frequency range, the PDN reaches the corresponding impedance value. To make the PDN system reach the target impedance, capacitors can be connected across the power plane and the ground plane of the PDN system. However, capacitors significantly occupy the integration space of the printed circuit board (PCB), reducing the competitiveness of the product in terms of size. Summary of the Invention

[0003] Embodiments of this application provide a power distribution network (PDN) system, an electronic device, and a board-level network module, which can suppress the PDN impedance while saving the PCB integration space.

[0004] In a first aspect, embodiments of this application provide a method, which is applied to an electronic device. The method includes: The PDN system includes a voltage regulation module (VRM), a board-level network module, and a load; the VRM includes a power supply, the board-level network module includes a first sampling resistor R1, a second sampling resistor R2, and a first capacitor C1, and the power supply supplies power to the load through the board-level network module; the power output terminal of the VRM is connected to the first ends of the R1 and the R2; the second ends of the R1 and the R2 are connected to the first end of the C1 and the power input terminal of the load, and the second end of the C1 is grounded.

[0005] In the embodiment of this application, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0006] In a possible implementation, the PDN system includes a PCB board, the PCB board includes a power plane and a ground plane, the first end of the R1 is connected to the first power pin of the PCB; the first end of the R2 is connected to the second power pin of the PCB; both the first power pin and the second power pin are connected to the first end of the power plane; the second end of the R1 is connected to the third power pin of the PCB; the second end of the R2 is connected to the fourth power pin of the PCB; both the third power pin and the fourth power pin are connected to the second end of the power plane. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0007] In a possible implementation, the first end of the C1 is connected to the fifth power pin; the fifth power pin is connected to the second end of the power plane; the second end of the C1 is connected to the first ground pin. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0008] In a possible implementation, the power supply is a power management integrated circuit (PMIC) module. The power output terminal of the PMIC is connected to the sixth power pin of the printed circuit board (PCB), and the sixth power pin is connected to the first end of the power plane; the ground terminal of the PMIC is connected to the second ground pin of the PCB. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0009] In a possible implementation, the load is a first chip. The power input terminal of the first chip is connected to the seventh power pin of the PCB, and the seventh power pin is connected to the second end of the power plane; the ground terminal of the first chip is connected to the third ground pin of the PCB. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0010] In a possible implementation, the resistance values of both the R1 and the R2 are less than 20 mΩ. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0011] In a possible implementation, the equivalent series inductance (ESL) of the parallel structure of the R1 and the R2 is less than the ESL of the R1; the ESL of the parallel structure of the R1 and the R2 is less than the ESL of the R2. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0012] In a second aspect, an embodiment of the present application provides a board-level network module. The board-level network module is applied to a PDN system. The board-level network module includes a first sampling resistor R1, a second sampling resistor R2, and a first capacitor C1; wherein, the first ends of the R1 and the R2 are used to connect to the power output terminal of a voltage regulator module (VRM) in the PDN system; the second ends of the R1 and the R2 are used to connect to the first end of the C1 and the power input terminal of a load in the PDN system, and the second end of the C1 is grounded.

[0013] In the embodiments of the present application, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0014] In a possible embodiment, the board-level network module includes a PCB board, the PCB board includes a power plane and a ground plane, the first end of the R1 is connected to the first power pin of the PCB; the first end of the R2 is connected to the second power pin of the PCB; both the first power pin and the second power pin are connected to the first end of the power plane; the second end of the R1 is connected to the third power pin of the PCB; the second end of the R2 is connected to the fourth power pin of the PCB; both the third power pin and the fourth power pin are connected to the second end of the power plane. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0015] In a possible embodiment, the first end of the C1 is connected to the fifth power pin; the fifth power pin is connected to the second end of the power plane; the second end of the C1 is connected to the first ground pin. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0016] In a possible embodiment, the power input end of the board-level network module is connected to the power output end of the VRM; the VRM includes a power supply, the power supply is a power management chip PMIC module, the power output end of the PMIC is connected to the sixth power pin of the PCB, and the sixth power pin is connected to the first end of the power plane; the ground end of the PMIC is connected to the second ground pin of the PCB. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0017] In a possible embodiment, the power output end of the board-level network module is connected to the power input end of the load; the load is a first chip, the power input end of the first chip is connected to the seventh power pin of the PCB, and the seventh power pin is connected to the second end of the power plane; the ground end of the first chip is connected to the third ground pin of the PCB. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0018] In a possible embodiment, the resistance values of both the R1 and the R2 are less than 20 mΩ. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0019] In a possible implementation manner, the equivalent inductance ESL of the parallel structure of R1 and R2 is less than the equivalent inductance of R1; the equivalent inductance ESL of the parallel structure of R1 and R2 is less than the equivalent inductance of R2. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save the space integration area, and improve the PDN impedance suppression effect.

[0020] In a third aspect, an embodiment of the present application provides an electronic device, and the electronic device includes a power distribution network PDN system as described in the first aspect or any one of the possible implementation manners of the first aspect.

[0021] In a fourth aspect, an embodiment of the present application provides a printed circuit board assembly (Printed Circuit Board Assembly, PCBA), and the printed circuit board assembly includes a power distribution network PDN system as described in the first aspect or any one of the possible implementation manners of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A is a schematic structural diagram of a power distribution network system provided by an embodiment of the present application;

[0023] Figure 1B is a simplified cross-sectional schematic structural diagram of a power distribution network system provided by an embodiment of the present application;

[0024] Figure 1C is a schematic equivalent circuit structure diagram of a power distribution network provided by an embodiment of the present application;

[0025] Figure 2 is a PDN impedance curve diagram proposed by an embodiment of the present application;

[0026] Figure 3 is a schematic diagram of Z-parameter curves of multiple capacitors proposed by an embodiment of the present application;

[0027] Figure 4 is a schematic diagram of impedance curves of a PDN system at different frequencies proposed by an embodiment of the present application;

[0028] Figure 5A is a schematic structural diagram of another power distribution network system provided by an embodiment of the present application;

[0029] Figure 5B is a schematic equivalent circuit structure diagram of a PDN system provided by an embodiment of the present application;

[0030] Figure 5C is a simplified cross-sectional schematic diagram of a board-level network module and a load in a PDN system provided by an embodiment of the present application;

[0031] Figure 6A It is a schematic structural diagram of a power distribution network system provided by an embodiment of the present application;

[0032] Figure 6B It is a schematic simplified cross-sectional diagram of the structure of a power distribution network system provided by an embodiment of the present application;

[0033] Figure 6C It is a schematic diagram of the equivalent circuit structure of a power distribution network provided by an embodiment of the present application;

[0034] Figures 7A - 7C It is a set of curve graphs showing the relationship between frequency and impedance with different numbers of sampling resistors provided by an embodiment of the present application;

[0035] Figure 8 It is a set of schematic diagrams of the circuit structure of a PCB board provided by an embodiment of the present application;

[0036] Figure 9 It is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0037] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. As used in the specification and appended claims of the present application, the singular forms "a", "an", "the", "above", "said", "this" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in the present application refers to and includes any or all possible combinations of one or more of the listed items.

[0038] First, the terms related to the embodiments of the present application will be introduced below.

[0039] A power distribution network (PDN) refers to the circuit path that delivers power from the power source to the load. The current flows from the power source to the load through the power plane of the PDN, and then flows back from the load to the power source through the ground plane of the PDN. The main function of the PDN is to provide a stable voltage for the load, quickly respond to changes in the load current, reduce noise, and ensure the quality of the power waveform.

[0040] The impedance of an ideal power supply system is zero. However, there are various noises in reality. For example, the noise in the output voltage of the power management chip; the voltage drop caused by the inability of the load current to respond quickly; the voltage fluctuations formed by the impedance in the power path and the ground loop, etc. The circuit power supply operates under a certain noise tolerance. If the power supply noise exceeds the range allowed by the system, the system cannot operate normally.

[0041] The PDN may include a voltage regulator module (VRM), filter capacitors, bypass / decoupling capacitors, vias, interconnects, printed circuit board (PCB) plane capacitors, package solder balls / pins, capacitors in device packages, bond wires, and load devices, etc. The PCB can connect each load device of the voltage regulator module and decoupling capacitors, etc. The PCB may include a power plane, a ground plane, connections, cables, interfaces, etc. The power supply path of the power supply is the path from the VRM output voltage to the load through the PCB.

[0042] The following will specifically describe the system structure of the PDN in combination with Figures 1A - 1C specific examples.

[0043] Figure 1A FIG. [X] is a schematic structural diagram of a power distribution network system exemplarily provided by an embodiment of the present application. As Figure 1A shown, the power distribution network may include a VRM, a board-level network module, and a load. Among them, the voltage regulator module includes a power supply. For example, the power supply is a power management integrated circuit (PMIC) module. The PMIC can supply power to each load through the PDN network. The board-level network module is an intermediate power supply network connecting the VRM and the load, and has the function of suppressing the impedance of the PDN. The board-level network module includes decoupling capacitors, that is, the board-level network module connects decoupling capacitors between the power plane and the ground plane. The voltage regulator module connects the power input end of the board-level network module through the power output end. The power output end of the board-level network module is connected to the load. The ground wires of the VRM, the board-level network module, and the load are connected, that is, the VRM, the board-level network module, and the load are all connected to the ground plane of the PCB.

[0044] Combined with Figure 1A the power distribution network system shown in Figure 1B a simplified cross-sectional schematic diagram of the structure of a power distribution network system is specifically provided for the power distribution network system. As Figure 1B shown, the PDN system includes a VRM, a large capacitor C1, a small capacitor C2, a chip, and a part of the PCB. Each component of the PDN system is packaged on the PCB. The chip is the load of the PDN system. The PCB includes a power line and a ground line. The power line is Figure 1B the solid line in Figure 1BThe dashed line in [it] can also be referred to as the ground plane. Among them, the VRM is connected to the PCB board through the power supply pin and the ground pin. The board-level network module includes large capacitors and small capacitors. The two ends of the large capacitors and small capacitors are respectively connected to the power supply line and the ground line of the PCB. Among them, both the large capacitors and small capacitors can be connected to the power supply line of the PCB through the power supply pin, and both the large capacitors and small capacitors can be connected to the ground line of the PCB through the ground pin. The small capacitor can be a ceramic capacitor, and both the large capacitors and small capacitors are decoupling capacitors. In addition, it should be noted that the large capacitors and small capacitors are capacitors formed by multiple capacitors connected at both ends of the power supply line and the ground line. The large capacitors can suppress the PDN impedance of higher frequencies, and the small capacitors can suppress the PDN impedance of lower frequencies. Figure 1B In the power distribution network of [it], the load is a chip, and the chip can be connected to the power supply line and the ground line of the PCB through different package solder balls respectively. Optionally, multiple pairs of package solder balls of the chip can be connected to the power supply line and the ground line of the PCB board, and the present application does not limit the number of connections.

[0045] Figure 1C It is a schematic diagram of the equivalent circuit structure of a power distribution network exemplarily provided by an embodiment of the present application. As Figure 1C shown, the power distribution network can include a VRM, a board-level network module, and a package power layer.

[0046] The VRM includes a power supply, the board-level network module includes a large capacitor C1 and a small capacitor C2, and the package power layer includes a package capacitor C3 and an on-chip capacitor C4. Among them, the board-level network module can also be referred to as the PCB power layer. The large capacitor C1 can be a large-capacity capacitor, and the small capacitor C2 can be a ceramic capacitor. The large capacitor C1 can be equivalent to a series structure of a resistor Rc1, a capacitor Cc1, and an inductor Lc1; the small capacitor C2 can be equivalent to a series structure of a resistor Rc2, a capacitor Cc2, and an inductor Lc2; the package capacitor C3 can be equivalent to a series structure of a resistor Rc3, a capacitor Cc3, and an inductor Lc3; the on-chip capacitor C4 can be equivalent to a series structure of a resistor Rc4, a capacitor Cc4, and an inductor Lc4. The plane and vias of the board-level network module of the PCB are equivalent to an inductor L1. One ball and via of the package power layer can be equivalent to a parasitic inductor L2, and the bump can be equivalent to an inductor L3.

[0047] The positive output terminal of the power supply is connected to the first terminal of Rc1, the first terminal of Rc2, and the first terminal of L1. The second terminal of Rc1 is connected to the first terminal of Cc1, and the second terminal of Cc1 is connected to the first terminal of Lc1; the second terminal of Rc2 is connected to the first terminal of Cc2, and the second terminal of Cc2 is connected to the first terminal of Lc2; the second terminal of L1 is connected to the first terminal of L2; the second terminal of L2 is connected to the first terminal of Rc3 and the first terminal of L3. The second terminal of Rc3 is connected to the first terminal of Cc3, and the second terminal of Cc3 is connected to the first terminal of Lc3; the second terminal of L3 is connected to the first terminal of Rc4 and the power input terminal of the load. The second terminal of Rc4 is connected to the first terminal of Cc4, and the second terminal of Cc4 is connected to the first terminal of Lc4. The second terminals of Lc1, Lc2, Lc3, Lc4, the ground terminal of the power supply, and the ground terminal of the load are all grounded.

[0048] Since the impedance of the PDN network is related to frequency, the voltage consumed on the PDN changes with frequency. To reduce the voltage fluctuation of the integrated circuit, it is necessary to control the impedance of the PDN within a certain range. The following combines Figure 2 and Figure 3 to illustrate the impedance change of the PDN system and the method of suppressing impedance.

[0049] Figure 2 is a PDN impedance curve graph exemplarily disclosed in an embodiment of the present application. As Figure 2 shown, the impedance value of the PDN circuit changes at different frequencies. Among them, the abscissa is the frequency, and the ordinate is the impedance value. Combining Figure 1B of several modules, the frequency of the power distribution network can be divided into the following sections. In the frequency range from DC to 10 kHz, the VRM can determine the impedance value of the PDN. In the frequency range from 10 kHz to several hundred kHz, the large capacitor can determine the impedance value of the PDN. In the range from several hundred kHz to several tens of MHz, the small capacitor can determine the impedance value of the PDN. In the range greater than one hundred MHz, the capacitance adjustment circuit inside the load can determine the impedance value of the PDN. For example, the on-chip capacitor, that is, the on-chip capacitor determines the impedance of the power distribution network at the highest frequency band. Among them, the large capacitor can be a bulk cap, for example, a body capacitor; the small capacitor can be SMT caps, for example, ceramic decoupling capacitors.

[0050] As Figure 2As shown, there are parasitic inductances during the connection process of circuits and chips. For example, parasitic inductances in packaging, package leads, vias, and the connection of vias to the power / ground plane, etc. Parasitic inductances increase the impedance of high-frequency circuits. This makes it impossible to reduce the impedance of the power distribution network below the package pins regardless of the board-level power supply design. Therefore, high frequencies are limited by the parasitic parameters of the chip package. It is difficult to suppress the impedance of the PDN through board-level decoupling capacitors, and large capacitors are required to suppress the impedance in the high-frequency band of the PDN. In addition, suppressing the impedance of the high-frequency PDN requires arranging multiple capacitors, and multiple capacitors will occupy more space on the PCB board.

[0051] Figure 3 is a schematic diagram of the Z-parameters curves of multiple capacitors publicly disclosed exemplarily in the embodiments of the present application. Figure 3 The types of capacitors included are: 1uF 0201, 22uF 0603, 4.7uF 0402, 10uF 0402, 10uF Tri, and 4.3uF Tri. Among them, the resonant frequency of the actual capacitance of 4.7uF 0402 is 70MHz; the resonant frequencies of the actual capacitances of 1uF 0201 and 4.3uF Tri are 10MHz; the resonant frequency of the actual capacitance of 10uF Tri is 8MHz; the resonant frequency of the actual capacitance of 10uF 0402 is 5MHz; the resonant frequency of the actual capacitance of 22uF 0603 is 2MHz. It can be seen from this that in order to meet the impedance requirements of the PDN system, multiple capacitors need to be connected in parallel at both ends of the power line and the ground line, so as to effectively suppress the impedance.

[0052] Figure 4 is a schematic diagram of the impedance curves of different frequency bands in different situations of the PDN network with an increased sampling resistor in the embodiments of the present application. As Figure 4 shown is a schematic diagram of the impedance curves of the PDN system at different frequencies. Assuming that the standard impedance is 0.2Ω, the standard impedance is the impedance critical value that controls the impedance of all frequency bands not to exceed, that is, the target impedance set for the PDN system. Without connecting capacitors, the impedance exceeds the standard impedance at about 10MHz, resulting in unqualified suppression of the PDN impedance. When two capacitors are connected, the impedance exceeds the standard impedance at about 60MHz. The imaginary part of the impedance exceeds the standard impedance at about 100MHz. When only a 100nF capacitor is connected, the impedance drops again at 5MHz and exceeds the standard impedance at about 100MHz. Combining Figure 4 the curve changes, it can be seen that different capacitors have different effects on the PDN impedance, and large capacitors need to be packaged on the PDN system in the end product. Facing the impedance increase brought by inductance and IC load packaging, it is further necessary to add multiple large capacitors to suppress the PDN curve in the medium and high frequency bands in order to meet the target of impedance suppression.

[0053] Combined with the above Figures 1A - 1CFor the PDN system shown, in order to protect the load, the board-level network module of the PDN needs to have the ability to detect current. The function of detecting current can prevent the circuit from being burned due to excessive current or voltage, or read the current data for other functions of the electronic device to call, etc. Therefore, a sampling resistor needs to be connected in series in the power plane of the board-level network module of the PDN. The voltage across the sampling resistor can be measured, so that the magnitude of the current flowing through the power line can be determined, that is, the ratio of the voltage across the sampling resistor to the resistance value of the sampling resistor. Among them, the sampling resistor is also called a current-sensing resistor. The sampling resistor is a resistor device with high precision and low resistance. Therefore, when connected in series to the power line, it has little impact on the impedance at low frequencies and almost no impact on the impedance at high frequencies.

[0054] The following combines Figures 5A - 5C to illustrate the PDN system formed by connecting a sampling resistor in series.

[0055] Figure 5A is a schematic diagram of another PDN system structure provided by an embodiment of the present application. As Figure 5A shown, the board-level network module includes a sampling resistor R1, a first capacitor C1, and a second capacitor C2. The electronic device can connect both ends of R1 to the power line. The power output terminal of the VRM is connected to the first end of R1, and the second end of R1 is connected to the first end of the first capacitor C1 and the first end of the second capacitor C2. The second ends of the first capacitor C1 and the second capacitor C2 are both grounded. Among them, the first capacitor C1 and the second capacitor C2 can be multiple capacitors connected between the power plane and the ground plane, and the number is not limited. Among them, due to the significant increase in ESL, the curve of the PDN in the high-frequency band rises. The decoupling capacitors in parallel can be increased to increase the total capacitance value of the decoupling capacitors, so that the PDN impedance above 25 MHz can be suppressed to meet the constraint conditions of the target impedance.

[0056] In the high-frequency band, the spreading inductance of the power-ground plane pair will also affect the PDN impedance. Using a larger planar capacitor can provide a higher capacitance value, so as to maintain a lower impedance at high frequencies. In the high-frequency band, the suppression of the PDN impedance mainly depends on the selection and configuration of capacitors. Multiple large-capacitance capacitors need to be used to effectively provide energy compensation in the high-frequency band, reduce power supply noise and voltage fluctuations.

[0057] Figure 5B is Figure 5A the equivalent circuit diagram of the board-level network module in the PDN system. As Figure 5B shown, the sampling resistor R1 can be equivalent to the series connection of a resistor Rb and an inductor Lb, and C1 is equivalent to the series connection of a capacitor C c1 , a resistor R c1 and an inductor L c1 in series; C2 is equivalent to a capacitor Cc2 and resistor R c2 and inductor L c2 in series. The power input terminal of the equivalent circuit of the board-level network module is connected to the first end of Rb, the second end of Rb is connected to the first end of Lb, and the second end of Lb is connected to the first end of C c1 and the first end of C c2 The first end of C c1 The second end of C is connected to the first end of R c1 The first end of R c1 The second end of R is connected to the first end of L c1 The first end of L c1 The second end of L is grounded. The second end of Lb, the first end of C c2 The second end of C is connected to the first end of R c2 The first end of R c2 The second end of R is connected to the first end of L c2 The first end of L c2 The second end of L is grounded. The second end of Lb, the first end of C c1 and the first end of C c2 The first end of C are used as the power output terminal of the board-level network module and are connected to the power input terminal of the load. In addition, for other connections and content of the VRM, load, and board-level network module, reference can be made to Figure 1A and Figure 5A for the relevant descriptions, which will not be elaborated here.

[0058] Combined with Figure 5A and Figure 5B the schematic structural diagram of the board-level network module shown, Figure 5C a simplified cross-sectional view of the board-level network module and the load in the PDN system is provided. As Figure 5C shown, the solid lines in the PCB board are power lines, and the dashed lines are ground lines. Among them, both ends of the first resistor R1 are connected to the power lines through two power pins, and the first capacitor C1 and the second capacitor C2 are respectively connected to the power pin and the ground pin. The chip device can be connected to the power line and the ground line of the PCB board through a pair of package solder balls. Optionally, the chip can be connected to the power line and the ground line through multiple pairs of package solder balls, and the number of connections in this application is not limited.

[0059] Combined with Figures 5A - 5C the PDN system shown, the sampling resistor R1 is connected into the power line to detect the current value of the power path. However, due to the non-ideal characteristic of the resistor that is not a pure resistance value, that is, the resistor contains an equivalent series inductance ESL, such as Figure 5B Lb in, the addition of the sampling resistor causes an increase in the overall impedance of the PDN system, and further causes the PDN to fail to meet the constraint conditions of impedance suppression.

[0060] Specifically, the impedance of the power network Z = R + jwL + 1 / jwC, where R is the equivalent resistance in the PDN network, L is the equivalent inductance in the PDN network, and C is the equivalent capacitance in the PDN network. Since the sampling resistor R1 is added, both R and L increase, resulting in an increase in the overall impedance of the power network. The increase in L will affect the voltage in the corresponding high-frequency band, causing problems in charging. To solve the above problems, on the basis of Figures 1A - 1C continue to connect capacitors of corresponding frequency bands at both ends of the power plane and the ground plane. For example, in Figure 5A a third capacitor C3 is connected in parallel with C2, and so on. Among them, Figure 5A C3 is not shown in

[0061] It can be seen from this that due to the sampling resistor introducing an equivalent capacitance, the electronic device needs to additionally connect two inductors to effectively suppress the impedance. For example, in the high-frequency band PDN of limited PCB layout space, multiple 0603 capacitors are usually required to suppress the PDN. The 0603 capacitor occupies a board area of 1.28 mm 2 , and the 0201 sampling resistor occupies a board area of 0.18 mm 2 . High-frequency band PDN suppression usually requires multiple 0603 capacitors to suppress the PDN. Therefore, a single sampling branch will bring at least 2 * 1.28 mm 2 = 2.56 mm 2 of area consumption. Generally speaking, the larger the volume of the capacitor, the larger the capacitance value of the corresponding capacitor. It can be seen from this that the higher the frequency of PDN suppression, the larger the parameters of the required capacitor, the larger the volume of the capacitor, and the more integrated space it occupies. Therefore, the PCB layout space is consumed seriously. The branch of a single sampling resistor will occupy more PCB area, and the competitiveness of high-density PCBs for terminals will be sharply weakened.

[0062] In view of the above problems, the embodiments of the present application propose a PDN system and an electronic device. The board-level network module of the PDN system may include at least two sampling resistors. That is, on the basis of connecting a first sampling resistor to the power line, a second sampling resistor is connected in parallel with the existing first sampling resistor. The parallel structure of the first sampling resistor and the second sampling resistor reduces both the equivalent inductance and resistance, so that the PDN impedance can be suppressed, the number of capacitors used can be reduced, and the integration space of general resistors is smaller than that of capacitors, thereby saving the space of the PCB board and improving the space density of the PCB board.

[0063] The following combines Figures 6A - 6C to illustrate the PDN system proposed in the present application.

[0064] Figure 6A is a schematic diagram of the structure of a PDN system exemplarily disclosed in the embodiments of the present application. As shown in Figure 6AAs shown, the board-level network module of the PDN may include a first sampling resistor R1, a second sampling resistor R2, and a first capacitor C1. Among them, the first capacitor C1 may be a large-capacity capacitor. The power input terminal of the board-level network module is connected to the first ends of R1 and R2. The second ends of R1 and R2 are connected to the first end of the first capacitor C1 and serve as the power output terminal of the board-level network module. The second end of C1 is grounded. In the embodiment of the present application, the impedance of the PDN can be effectively suppressed by adding a second sampling resistor in parallel with the first sampling resistor. The number of connections of the first capacitor C1 is not a single capacitor and can be multiple capacitors. The present application does not limit the number of capacitors connected. In addition, Figure 6A adding the second sampling resistor R2 in Figure 5A the solution reduces the number of connections of capacitors in the first capacitor C1, that is, reduces one or more capacitors, which can save the integration space of the PCB board.

[0065] Optionally, the range of R1 and R2 is 0 to 20 mΩ, that is, both R1 and R2 are less than 20 mΩ. The inductive reactance value of the parasitic inductance increases with the increase of frequency. Exemplarily, generally, the inductive reactance at 1 MHz is only about 0.4 mΩ, the inductive reactance value of ESL at 24 MHz is about 58 mΩ, and the inductive reactance value of ESL at 200 MHz is about 209 mΩ. Generally, in the case of large current, small-value resistors are used for R1 and R2 to avoid using too large resistors, because large resistors will cause the PDN to rise, which will instead affect the PDN suppression effect.

[0066] It should be noted that the number of sampling resistors of the board-level network module can be further increased, that is, the PDN system may include a third sampling resistor R3. The connection method of R3 is in parallel with R2 and R1. The connection method of R2 can be referred to and will not be elaborated. In this way, the impedance can be further reduced. The maximum number of sampling resistors in the PDN system is 3. On the one hand, although increasing the sampling resistor can suppress the PDN impedance, the circuit integration area will also increase; on the other hand, the effect of increasing the sampling resistor on suppressing the PDN impedance will decrease, and the benefit of increasing the sampling resistor will be reduced. Therefore, the number of parallel sampling resistors should be 2 or 3 for the best benefit. Among them, R3 is Figure 6A not shown in

[0067] Combined with Figure 6A the PDN system shown, Figure 6B a simplified cross-sectional schematic diagram of the board-level network module and the load of the PDN system structure is disclosed. As Figure 6B shown, the solid lines in the PCB board are power lines, and the dotted lines are ground lines. Among them, both ends of the first sampling resistor R1 and the second sampling resistor R2 are connected to the power line through two power pins, and the first capacitor C1 is connected to the power pin and the ground pin respectively. The chip device can be connected to the power line and the ground line of the PCB board through a pair of package solder balls.

[0068] Exemplarily, as Figure 6B shown, the PDN system includes a PCB board, the PCB board includes a power plane and a ground plane, the first end of R1 is connected to the first power pin of the PCB; the first end of R2 is connected to the second power pin of the PCB; both the first power pin and the second power pin are connected to the first end of the power plane; the second end of R1 is connected to the third power pin of the PCB; the second end of R2 is connected to the fourth power pin of the PCB; both the third power pin and the fourth power pin are connected to the second end of the power plane. The first end of C1 is connected to the fifth power pin; the fifth power pin is connected to the second end of the power plane; the second end of C1 is connected to the first ground pin. The power supply can be a power management chip PMIC module, the power output end of the PMIC is connected to the sixth power pin of the PCB, and the sixth power pin is connected to the first end of the power plane; the ground end of the PMIC is connected to the second ground pin of the PCB. The load can be a first chip, the power input end of the first chip is connected to the seventh power pin of the PCB, and the seventh power pin is connected to the second end of the power plane; the ground end of the first chip is connected to the third ground pin of the PCB.

[0069] Combined with Figure 6A and Figure 6B the PDN system shown, Figure 6C is an equivalent circuit schematic diagram of a PDN structure provided by an embodiment of the present application. As Figure 6C shown, R1 is equivalent to a series structure of a resistor Rb1 and an inductor Lb1, R2 is equivalent to a series structure of a resistor Rb2 and an inductor Lb2, and C1 is equivalent to a series structure of a capacitor C c1 , a resistor R c1 and an inductor L c1 . After the above equivalence, the power input end of the board-level network module is connected to the first end of resistor Rb1 and the first end of resistor Rb2. The second end of Rb1 is connected to the first end of Lb1, and the second end of resistor Rb2 is connected to the first end of Lb2. The second end of Lb1 is connected to the second end of Lb2 and the first end of Cc1. The second end of Cc1 is connected to the first end of Rc1, the second end of Rc1 is connected to the first end of Lc1, and the second end of Lc1 is grounded. The second end of Lb1, the second end of Lb2 and the first end of Cc1 serve as the power output end of the board-level network module.

[0070] It should be noted that, combined with the impedance of the power network Z = R + jwL + 1 / jwC, the real part impedance affects the low-frequency signal, and the imaginary part impedance affects the high-frequency signal. Therefore, the parallel sampling resistor can reduce the magnitude of the equivalent inductance. Exemplarily, assume Figure 6CIn R1 and R2, they are respectively equivalent to inductor Lb1 and inductor Lb2. The two inductors are connected in parallel, so that the inductance drop decreases rapidly. That is, the equivalent inductance after parallel connection is Lb = (Lb1 × Lb1) / (Lb1 + Lb1). If the two equal inductors are equal, the inductance after parallel connection is reduced to half of the original. In this way, the PDN impedance suppression effect can be significantly improved.

[0071] Figures 7A - 7C It is a curve graph showing the relationship between frequency and impedance with different numbers of sampling resistors, which is exemplarily disclosed in the embodiments of the present application. Figure 7A It is a curve graph of the PDN impedance frequency corresponding to a single 5mΩ resistor and a scheme of two 5mΩ resistors in the embodiments of the present application. Among them, the solid line is the curve graph when a 5mΩ resistor is connected in series on the PDN power line, and the dashed line is the curve graph when two parallel 5mΩ resistors are connected in series on the PDN power line. Through comparison, it can be seen that in the frequency range of 1KHz to 500MHz, the PDN impedance in the scheme of two 5mΩ resistors is much smaller than that in the scheme of a single 5mΩ resistor. Therefore, Figures 6A - 6C the embodiments can effectively suppress the impedance of the PDN.

[0072] Figure 7B It is a curve graph of the impedance frequency of the real part, imaginary part and Z value corresponding to the PDN system of a scheme of two 5mΩ resistors disclosed in the embodiments of the present application. Figure 7C It is a curve graph of the impedance frequency of the real part, imaginary part and Z value corresponding to the PDN system of a scheme of a single 5mΩ resistor disclosed in the embodiments of the present application. After Figure 7B and Figure 7C comparison, it can be found that compared with a single 5mΩ resistor, the equivalent resistance ESL of the imaginary part in the scheme of two 5mΩ resistors will be greatly reduced in the high-frequency band. Therefore, Figures 6A - 6C the scheme can effectively suppress the high-frequency PDN impedance.

[0073] After Figures 7A - 7C comparison, it is found that in the range of 25MHz to 1GHz, adding a second sampling resistor in parallel with the first sampling resistor can significantly reduce the PDN impedance.

[0074] If in the way shown in Figures 5A - 5C , adding capacitors to suppress the PDN impedance. For example, in the high-frequency band of limited PCB layout space, the PDN usually requires multiple 0603 capacitors to suppress the PDN. Therefore, a single sampling resistor will bring at least 2 * 1.28mm 2 = 2.56mm 2 area consumption. In the present application, by packaging and connecting 0201 sampling resistors, the board-level area consumption is 0.36mm 2。The branch with a single sampling resistor will occupy more PCB area. Therefore, multiple sampling resistors do not occupy more PCB area, do not add multiple large-package capacitance Decaps, and can significantly suppress the PDN impedance, which can significantly improve the competitiveness of high-density PCBs for terminal devices.

[0075] Exemplarily, Figure 8 is a schematic diagram of a set of PCB board line structures publicly disclosed in an exemplary embodiment of the present application. Figure 8 In (a), it is a partial structure of a PCB board where two 10 mΩ parallel sampling resistors are connected to the power supply line. Figure 8 Exemplarily shown in (a) are 3 pairs of 10 mΩ parallel sampling resistors. Figure 8 In (b), it is a PCB board line structure where a 5 mΩ sampling resistor is connected in series to the power supply line. Figure 8 Exemplarily shown in (b) is one 5 mΩ sampling resistor. Figure 8 The sampling resistors in (a) and (b) are the framed parts. Figure 8 The PCB circuit structure shown in (a) corresponds to Figure 6A the PDN system. Through simulation, it is obtained that at a frequency of 24 MHz, the impedance is 47.46 mΩ; at a frequency of 200 MHz, the impedance is 366 mΩ. Figure 8 The PCB circuit structure shown in (b) corresponds to Figure 5A the PDN system. Through simulation, it is obtained that at a frequency of 24 MHz, the impedance is 50.96 mΩ; at a frequency of 200 MHz, the impedance is 383.3 mΩ. At this time, the target impedance of the current PDN design is Zspec(f = 24 MHz) = 48.1 mΩ, Zspec(f = 200 MHz) = 377 mΩ. Through Figure 8 actual simulation tests, it can be seen that when the PCB layout area is limited, reducing the method of using large-package capacitors to suppress the PDN impedance can reduce the occupation of large-area PCBs, and can use a smaller PCB occupation area to complete the ESL suppression in the high-frequency band of the PDN, and meet the suppression requirements of the target impedance PDNspec, improving the competitiveness of the product.

[0076] The electronic device in the embodiment of the present application can be a tablet computer, mobile phone, desktop computer, laptop computer, handheld computer, smart bracelet, ultra-mobile personal computer, netbook, personal phone, personal digital assistant, touch-screen device such as augmented reality (AR) / virtual reality (VR), etc. The present application does not limit the specific form of the electronic device.

[0077] Next, the device involved in the embodiment of the present application will be introduced.

[0078] Figure 9Schematic diagram of the hardware structure of an electronic device provided by an embodiment of this application.

[0079] The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0080] It can be understood that the structure illustrated in the embodiment of this application does not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than those illustrated, or combine certain components, or split certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0081] The processor 110 may include one or more processing units. For example: the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors.

[0082] A memory can also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can hold the instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to use the instruction or data again, it can directly call it from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0083] It can be understood that the interface connection relationships illustrated among the modules in the embodiments of the present application are only illustrative and do not constitute a structural limitation on the electronic device. In other embodiments of the present application, the electronic device can also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0084] The power management module 141 is used to connect to the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives inputs from the battery 142 and / or the charging management module 140 and supplies power to the processor 110, the internal memory 121, the external memory, the display screen 194, the wireless communication module 160, etc. The power management module 141 can also be used to monitor parameters such as the battery capacity, the number of battery charge cycles, and the battery health status. In some other embodiments, the power management module 141 can also be provided in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be provided in the same device. In the embodiments of the present application, the power management module 141 can include a VRM.

[0085] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired or wireless manner. The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium, an optical medium, or a semiconductor medium, etc.

[0086] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by relevant hardware instructed by a computer program. This program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. The aforementioned storage medium includes various media that can store program codes, such as ROM, random access memory (RAM), magnetic disks, or optical discs.

Claims

1. A power distribution network (PDN) system, characterized in that, The PDN system includes a voltage regulation module (VRM), a board-level network module, and a load; The VRM includes a power supply. The board-level network module includes a first sampling resistor R1, a second sampling resistor R2, and a first capacitor C1. The power supply supplies power to the load through the board-level network module; The power output terminal of the VRM is connected to the first end of the R1 and the first end of the R2; the second end of the R1 and the second end of the R2 are connected to the first end of the C1 and the power input terminal of the load, and the second end of the C1 is grounded; Wherein, the equivalent series inductance (ESL) of the parallel structure of the R1 and the R2 is less than the equivalent inductance of the R1; the equivalent series inductance (ESL) of the parallel structure of the R1 and the R2 is less than the equivalent inductance of the R2.

2. The system according to claim 1, wherein The PDN system includes a printed circuit board (PCB). The PCB includes a power plane and a ground plane. The first end of the R1 is connected to the first power pin of the PCB; the first end of the R2 is connected to the second power pin of the PCB; both the first power pin and the second power pin are connected to the first end of the power plane; the second end of the R1 is connected to the third power pin of the PCB; the second end of the R2 is connected to the fourth power pin of the PCB; both the third power pin and the fourth power pin are connected to the second end of the power plane.

3. The system according to claim 2, characterized in that The first end of the C1 is connected to a fifth power pin; the fifth power pin is connected to the second end of the power plane; the second end of the C1 is connected to a first ground pin.

4. The system according to claim 2 or 3, characterized in that, The power supply is a power management integrated circuit (PMIC) module. The power output terminal of the PMIC is connected to the sixth power pin of the PCB, and the sixth power pin is connected to the first end of the power plane; the ground terminal of the PMIC is connected to the second ground pin of the PCB.

5. The system according to claim 2 or 3, characterized in that, The load is a first chip. The power input terminal of the first chip is connected to the seventh power pin of the PCB, and the seventh power pin is connected to the second end of the power plane; the ground terminal of the first chip is connected to the third ground pin of the PCB.

6. The system according to any one of claims 1-3, characterized in that, The resistance values of both the R1 and the R2 are less than 20 mΩ.

7. An electronic device, characterized in that, Including the PDN system according to any one of claims 1-6.

8. A board-level network module, characterized in that The board-level network module is applied to a PDN system. The board-level network module includes a first sampling resistor R1, a second sampling resistor R2, and a first capacitor C1; Wherein, the first end of the R1 and the first end of the R2 are used to connect to the power output terminal of the VRM in the PDN system; the second end of the R1 and the second end of the R2 are used to connect to the first end of the C1 and the power input terminal of the load in the PDN system, and the second end of the C1 is grounded; Wherein, the equivalent series inductance (ESL) of the parallel structure of the R1 and the R2 is less than the equivalent inductance of the R1; the equivalent series inductance (ESL) of the parallel structure of the R1 and the R2 is less than the equivalent inductance of the R2.

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