Amplifier circuit and analog closed loop circuit

Abstract

The application discloses an amplifier circuit and an analog closed loop circuit. The amplifier circuit comprises an amplifying unit, a first mirror branch, a second mirror branch, an upper pull switch, a lower pull switch and a control unit. The upper pull switch is configured to pull up the output voltage when closed. The lower pull switch is configured to pull down the output voltage when closed. The control unit is configured to control the opening and closing of the upper pull switch and the lower pull switch according to a third reference voltage and a fourth reference voltage, so that the response speed of the upper pull switch and the lower pull switch when opened is higher than the response speed of the output voltage, and the response speed of the upper pull switch and the lower pull switch when closed is lower than the response speed of the output voltage. Since the response speed of the upper pull switch and the lower pull switch when closed is lower than the response speed of the output voltage, and the response speed of the upper pull switch and the lower pull switch when opened is higher than the response speed of the output voltage, it can be ensured that the upper pull switch and the lower pull switch are opened for a period of time when the amplifying unit just recovers to a steady state, thereby avoiding large signal oscillation.

Description

Technical Field

[0001] This application relates to the field of amplifier technology, and more specifically, to an amplifier circuit and a switching power supply. Background Technology

[0002] Slew rate (SR) is one of the most important specifications of an amplifier. In most cases, it is limited by the amplifier's charging and discharging speed of capacitors, and the capacitors that need to be charged and discharged are determined by the specific external application and cannot be changed. To optimize the amplifier's slew rate, the common approach is to increase the amplifier's saturation pull-up and pull-down currents. The most direct way to increase the slew rate is to increase the op-amp's static bias current, but this will increase the amplifier's static power consumption. Therefore, slew rate enhancement techniques were developed.

[0003] In related technologies, the slew rate enhancement effect of an amplifier is limited by the pull-up and pull-down switches connected to the output terminal. When the input voltage difference detected by the amplifier is small, the pull-up and pull-down switches connected to the output terminal are closed. When the input voltage difference detected by the amplifier is large, the pull-up or pull-down switch is opened, activating the corresponding feedback loop to increase the effective slew rate.

[0004] However, when the pull-up switch is turned on, the feedback loop increases the rate of decrease and reversal of the input signal. Just as the pull-up switch is turned off, the input voltage difference detected by the amplifier triggers the pull-down switch to turn on again, resulting in large signal oscillations in the loop. Summary of the Invention

[0005] This application provides an amplifier circuit and an analog closed-loop circuit.

[0006] The application provides an amplifier circuit, which comprises an amplification unit, a first mirror branch, a second mirror branch, an upper pull switch, a lower pull switch and a control unit. The amplification unit comprises a first branch and a second branch. The first branch is configured to generate a first reference voltage according to a voltage difference between a first input voltage and a second input voltage. The second branch is configured to generate a second reference voltage according to the voltage difference between the first input voltage and the second input voltage. The amplification unit is configured to provide an output voltage according to the first reference voltage and the second reference voltage. The first mirror branch is configured to generate a third reference voltage according to the first input voltage. The upper pull speed of the third reference voltage is higher than that of the first reference voltage. The lower pull speed of the third reference voltage is lower than that of the first reference voltage. The second mirror branch is configured to generate a fourth reference voltage according to the second input voltage. The upper pull speed of the fourth reference voltage is higher than that of the second reference voltage. The lower pull speed of the fourth reference voltage is lower than that of the second reference voltage. The upper pull switch is configured to pull up the output voltage when closed. The lower pull switch is configured to pull down the output voltage when closed. The control unit is configured to control the opening and closing of the upper pull switch and the lower pull switch according to the third reference voltage and the fourth reference voltage, so that the response speed of the upper pull switch and the lower pull switch when opened is higher than that of the output voltage, and the response speed of the upper pull switch and the lower pull switch when closed is lower than that of the output voltage.

[0007] In the amplifier circuit of the application, the response speed of the upper pull switch and the lower pull switch when closed is lower than that of the output voltage, and the response speed of the upper pull switch and the lower pull switch when opened is higher than that of the output voltage, so that the upper pull switch and the lower pull switch can be kept open for a period of time when the amplification unit just recovers to a steady state, thereby avoiding large signal oscillation of the main loop.

[0008] In some embodiments, the first branch is configured to generate a first current according to the first input voltage and generate the first reference voltage according to the first current. The second branch is configured to generate a second current according to the second input voltage and generate the second reference voltage according to the second current. The amplification unit is configured to provide the output voltage according to the first reference voltage and the second reference voltage. The first mirror branch is configured to copy the first current to obtain a first mirror current and provide the third reference voltage according to the first mirror current. The second mirror branch is configured to copy the second current to obtain a second mirror current and provide the fourth reference voltage according to the second mirror current.

[0009] In some embodiments, the output voltage is positively correlated with the voltage difference between the first input voltage and the second input voltage. When the first input voltage is consistent with the second input voltage, the output voltage reaches a steady state value.

[0010] In some embodiments, the control unit is configured to control the pull-up switch and the pull-down switch to be open when the voltage difference is less than or equal to a dead-zone voltage threshold. The control unit is configured to control the pull-up switch to be closed or the pull-down switch to be closed to adjust the output voltage to the steady state value when the voltage difference is greater than the dead-zone voltage threshold.

[0011] In some embodiments, the dead-zone voltage threshold is positively correlated to pull-up speed of the third reference voltage and the fourth reference voltage, and is negatively correlated to pull-down speed of the third reference voltage and the fourth reference voltage.

[0012] In some embodiments, the third reference voltage is lower than a first voltage threshold when the voltage difference is greater than the dead-zone voltage threshold and the first input voltage is higher than the second input voltage, and the control unit is configured to control the pull-down switch to be open and the pull-up switch to be closed. The fourth reference voltage is lower than a second voltage threshold when the voltage difference is greater than the dead-zone voltage threshold and the first input voltage is lower than the second input voltage, and the control unit is configured to control the pull-up switch to be open and the pull-down switch to be closed. The third reference voltage is higher than or equal to the first voltage threshold and the fourth reference voltage is higher than or equal to the second voltage threshold when the voltage difference is less than or equal to a dead-zone voltage threshold, and the control unit is configured to control the pull-up switch and the pull-down switch to be open.

[0013] In some embodiments, the first branch includes a first transistor and a second transistor, a voltage source of the amplifier circuit is grounded through the first transistor and the second transistor, a control electrode of the first transistor is configured to access the first input voltage, a current flowing through the first transistor and the second transistor is the first current, the first transistor and the second transistor are connected to a first node, and a voltage written to the first node is the first reference voltage. The first mirror branch includes a first mirror transistor and a second mirror transistor, the voltage source is grounded through the first mirror transistor and the second mirror transistor, a control electrode of the first mirror transistor is connected to the control electrode of the first transistor, a control electrode of the second mirror transistor is connected to the control electrode of the second transistor, a current flowing through the first mirror transistor and the second mirror transistor is the first mirror current, the first mirror transistor and the second mirror transistor are connected to a third node, and a voltage written to the third node is the third reference voltage. A width-length ratio of the first mirror transistor is greater than that of the first transistor, and a width-length ratio of the second mirror transistor is less than that of the second transistor.

[0014] In some embodiments, the second branch includes a third transistor and a fourth transistor, a voltage source of the amplifier circuit is connected to ground through the third transistor and the fourth transistor, a control electrode of the third transistor is configured to be connected to the second input voltage, a current flowing through the third transistor and the fourth transistor is the second current, the third transistor and the fourth transistor are connected to a second node, and a voltage written to the second node is the second reference voltage. The second mirror branch includes a third mirror transistor and a fourth mirror transistor, the voltage source is connected to ground through the third mirror transistor and the fourth mirror transistor, a control electrode of the third mirror transistor is connected to the control electrode of the third transistor, a control electrode of the fourth mirror transistor is connected to the control electrode of the fourth transistor, a current flowing through the third mirror transistor and the fourth mirror transistor is the second mirror current, the third mirror transistor and the fourth mirror transistor are connected to a fourth node, and a voltage written to the fourth node is the fourth reference voltage. A width-length ratio of the third mirror transistor is greater than that of the third transistor, and a width-length ratio of the fourth mirror transistor is less than that of the fourth transistor.

[0015] In some embodiments, the amplification unit includes a third branch and a fourth branch, the third branch is configured to generate a third current according to the first reference voltage, the fourth branch is configured to generate a fourth current according to the second reference voltage, and the amplification unit is configured to provide the output voltage according to a current difference between the third current and the fourth current.

[0016] In some embodiments, the third branch includes a first input transistor and a first load, a first node of the first branch is written to the first reference voltage, and the first node is connected to a voltage source of the amplifier circuit through the first input transistor and the first load. The fourth branch includes a second input transistor and a second load, a second node of the second branch is written to the second reference voltage, and the second node is connected to the voltage source of the amplifier circuit through the second input transistor and the second load, and an output end of the amplification unit is connected between the second input transistor and the second load.

[0017] In some embodiments, the amplifier circuit includes a bias transistor, a first electrode of the bias transistor is connected to a voltage source of the amplifier circuit, and a second electrode of the bias transistor is connected to the first branch, the second branch, the first mirror branch, and the second mirror branch. A bias voltage provided by the second electrode of the bias transistor is less than a voltage of the first electrode of the bias transistor, and the first reference voltage, the second reference voltage, the third reference voltage, and the fourth reference voltage are all less than the bias voltage.

[0018] In some embodiments, the output terminal of the amplifier circuit includes a single-ended output terminal configured to output a single-ended amplified signal and a differential output terminal configured to output a differential amplified signal.

[0019] The analog closed-loop circuit provided by the embodiments of the present application includes the amplifier circuit of any of the above embodiments.

[0020] The embodiments of the present application provide an amplifier circuit and an analog closed-loop circuit. The amplifier circuit includes an amplification unit, a first mirror branch, a second mirror branch, a pull-up switch, a pull-down switch, and a control unit. The amplification unit includes a first branch and a second branch. The first branch is configured to generate a first reference voltage according to a voltage difference between a first input voltage and a second input voltage. The second branch is configured to generate a second reference voltage according to the voltage difference between the first input voltage and the second input voltage. The amplification unit is configured to provide an output voltage according to the first reference voltage and the second reference voltage. The first mirror branch is configured to generate a third reference voltage according to the first input voltage. The pull-up speed of the third reference voltage is higher than the pull-up speed of the first reference voltage. The pull-down speed of the third reference voltage is lower than the pull-down speed of the first reference voltage. The second mirror branch is configured to generate a fourth reference voltage according to the second input voltage. The pull-up speed of the fourth reference voltage is higher than the pull-up speed of the second reference voltage. The pull-down speed of the fourth reference voltage is lower than the pull-down speed of the second reference voltage. The pull-up switch is configured to pull up the output voltage when closed. The pull-down switch is configured to pull down the output voltage when closed. The control unit is configured to control the opening and closing of the pull-up switch and the pull-down switch according to the third reference voltage and the fourth reference voltage, so that the response speed of the pull-up switch and the pull-down switch when opened is higher than the response speed of the output voltage, and the response speed of the pull-up switch and the pull-down switch when closed is lower than the response speed of the output voltage.

[0021] In the amplifier circuit of the embodiments of the present application, the response speed of the pull-up switch and the pull-down switch when closed is lower than the response speed of the output voltage, and the response speed of the pull-up switch and the pull-down switch when opened is higher than the response speed of the output voltage, which can ensure that the pull-up switch and the pull-down switch are opened for a period of time when the amplification unit just recovers to a steady state, thereby avoiding large signal oscillation of the main loop.

[0022] Additional aspects and advantages of the present application will be made apparent by the following description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood by considering the following detailed description, including the accompanying drawings, in which:

[0024] Figure 1 is a schematic diagram of an amplifier circuit according to some embodiments of the present application;

[0025] Figure 2 is a schematic diagram of an amplifier circuit according to some embodiments of the present application;

[0026] Figure 3 is a schematic diagram of an amplifier circuit according to some embodiments of the present application;

[0027] Figure 4 is a schematic diagram of an amplifier circuit according to some embodiments of the present application;

[0028] Figure 5 is a schematic diagram of an amplifier circuit according to some embodiments of the present application;

[0029] Figure 6 is a schematic diagram of an amplifier circuit according to some embodiments of the present application;

[0030] Figure 7 is a schematic diagram of an amplifier circuit according to some embodiments of the present application;

[0031] Figure 8 is a schematic diagram of an amplifier circuit according to some embodiments of the present application.

[0032] Reference signs: amplifier circuit 100, amplification unit 10, first branch 11, second branch 12, first mirror branch 13, second mirror branch 14, third branch 15, fourth branch 16, pull-up switch 20, pull-down switch 30, control unit 40, bias transistor 17, first transistor 111, second transistor 112, third transistor 121, fourth transistor 122, first mirror transistor 131, second mirror transistor 132, third mirror transistor 141, fourth mirror transistor 142, first input transistor 151, first load 152, second input transistor 161, second load 162. DETAILED DESCRIPTION

[0033] Embodiments of the present application are described in detail below with reference to the attached drawing figures, wherein the same or like reference numerals and letters indicate the same or functionally similar elements throughout the figures. The embodiments described below are merely exemplary for the purpose of explanation and are not to be understood as limiting the present application.

[0034] Reference Figure 1 and Figure 2This application provides an amplifier circuit 100, including an amplification unit 10, a first mirror branch 13, a second mirror branch 14, a pull-up switch 20, a pull-down switch 30, and a control unit 40. The amplification unit 10 includes a first branch 11 and a second branch 12. The first branch 11 is configured to generate a first reference voltage based on the voltage difference between a first input voltage and a second input voltage. The second branch 12 is configured to generate a second reference voltage based on the voltage difference between the first and second input voltages. The amplification unit 10 is configured to provide an output voltage based on the first and second reference voltages. The first mirror branch 13 is configured to generate a third reference voltage based on the first input voltage. The pull-up speed of the third reference voltage is higher than the pull-up speed of the first reference voltage, and the pull-down speed of the third reference voltage is lower than the pull-down speed of the first reference voltage. The second mirror branch 14 is configured to generate a fourth reference voltage based on the second input voltage. The pull-up speed of the fourth reference voltage is higher than the pull-up speed of the second reference voltage, and the pull-down speed of the fourth reference voltage is lower than the pull-down speed of the second reference voltage. Pull-up switch 20 is configured to pull up the output voltage when closed. Pull-down switch 30 is configured to pull down the output voltage when closed. Control unit 40 is configured to control the on / off state of pull-up switch 20 and pull-down switch 30 according to a third reference voltage and a fourth reference voltage, such that the response speed of pull-up switch 20 and pull-down switch 30 opening is higher than the response speed of the output voltage, and the response speed of pull-up switch 20 and pull-down switch 30 closing is lower than the response speed of the output voltage.

[0035] In related technologies, the slew rate enhancement effect of the amplifier is limited by the pull-up switch 20 and pull-down switch 30 connected to the output terminal. When the input voltage difference detected by the amplifier is small, the pull-up switch 20 and pull-down switch 30 connected to the output terminal are closed. When the input voltage difference detected by the amplifier is large, the pull-up switch 20 or pull-down switch 30 is opened, activating the corresponding feedback loop to increase the effective slew rate. However, when the pull-up switch 20 is open, the feedback loop increases the falling and flipping speed of the input signal. Just as the pull-up switch 20 is opened, the input voltage difference detected by the amplifier triggers the pull-down switch 30 to open, resulting in large signal oscillations in the loop.

[0036] by Figure 3 For example, an upper comparator and a lower comparator can be configured. The upper comparator controls transistor M12, and the lower comparator controls transistor M11. When the voltage difference between the INP and INN terminals is small, transistors M11 and M12 connected to the OUT terminal are turned off. When the voltage difference between the INP and INN terminals is large, either transistor M11 or transistor M12 connected to the OUT terminal is turned on, increasing the effective slew rate.

[0037] Suppose that the voltage difference between the INP and INN terminals exceeds the dead-time threshold of the upper comparator, causing transistor M12 to turn on. The voltage output at the OUT terminal is pulled up, and the feedback loop causes the voltage connected to the INN terminal to be pulled down. If the upper comparator has a slow response speed, when transistor M12 turns off, the voltage difference between the INP and INN terminals is already less than the dead-time threshold of the lower comparator, causing transistor M11 to turn on. This cycle repeats, with transistors M12 and M11 turning on intermittently, resulting in large signal oscillations in the loop, which negatively impacts the stability of the main loop.

[0038] In related technologies, there are other solutions to enhance the slew rate of amplifiers, but these solutions still suffer from insufficient main loop stability.

[0039] by Figure 4 For example, when the voltage difference between INP and INN is small, the voltage difference between node A and node C is also small. Transistors M15 and M16 still operate near their static bias points, and the average current flowing through them will not deviate too much from the current flowing through transistor M14. This ensures that transistor M19 is turned off, and the first-stage bias current of the amplifier is determined by the current flowing through transistor M0. When the voltage difference between INP and INN is large, the voltage difference between node A and node C is also large. Transistors M15 and M16 deviate from their static bias points, causing transistor M19 to turn on and increasing the first-stage bias current of the amplifier, thereby increasing the transient slew rate of the amplifier. This scheme requires the amplifier to have a load connection structure, which consumes additional power. Moreover, because it is embedded in the amplifier body, it has a negative impact on the stability of the main loop.

[0040] by Figure 5 For example, the RFC (Reused Folded Cascode) structure can be used to simultaneously improve bandwidth and slew rate. Compared to traditional folded cascode operational amplifiers, the RFC structure has higher gain bandwidth, low-frequency gain, and slew rate, without increasing power consumption or design area. However, this approach increases the complexity of the signal path, introducing more poles in the main loop, increasing system complexity, and negatively impacting main loop stability. Furthermore, the RFC amplifies current through multiple NMOS current mirrors, therefore it cannot be directly applied to fully differential amplifiers.

[0041] Compared to the aforementioned related technologies, the amplifier circuit 100 of this application embodiment can ensure that when the amplification unit 10 just returns to a steady state, the pull-up switch 20 and the pull-down switch 30 are disconnected for a period of time, thus avoiding large signal oscillations in the main loop.

[0042] Specifically, the voltage source VDD is a voltage source of the amplifier circuit 100, the amplifier circuit 100 can include an INP terminal and an INN terminal, the first input voltage can be a voltage accessed by the INP terminal, the second input voltage can be a voltage accessed by the INN terminal, and the OUT terminal can be an output terminal of the amplification unit 10.

[0043] The first branch 11 can include a node N1, the first mirror branch 13 can include a node N3, the second branch 12 can include a node N2, and the second mirror branch 14 can include a node N4. The voltage written to the node N1 can be a first reference voltage, the voltage written to the node N2 can be a second reference voltage, the voltage written to the node N3 can be a third reference voltage, and the voltage written to the node N4 can be a fourth reference voltage.

[0044] In the case where the first input voltage and the second input voltage are the same, the first branch 11, the second branch 12, the first mirror branch 13, and the second mirror branch 14 work in a steady state. In the case where the first input voltage is greater than the second input voltage, the greater the voltage difference between the first input voltage and the second input voltage, the lower the voltage written to the nodes N1 and N3 is pulled than the voltage value in the steady state. In the case where the second input voltage is greater than the first input voltage, the greater the voltage difference between the first input voltage and the second input voltage, the lower the voltage written to the nodes N2 and N4 is pulled than the voltage value in the steady state.

[0045] In the case where the voltage written to the node N1 is pulled up, the voltage written to the node N3 follows the voltage written to the node N1 to be pulled up, and in the case where the voltage written to the node N1 is pulled down, the voltage written to the node N3 follows the voltage written to the node N1 to be pulled down. The speed of pulling up the voltage written to the node N3 is higher than the speed of pulling up the voltage written to the node N1, and the speed of pulling down the voltage written to the node N3 is lower than the speed of pulling down the voltage written to the node N1.

[0046] In the case where the voltage written to the node N2 is pulled up, the voltage written to the node N4 follows the voltage written to the node N2 to be pulled up, and in the case where the voltage written to the node N2 is pulled down, the voltage written to the node N4 follows the voltage written to the node N2 to be pulled down. The speed of pulling up the voltage written to the node N4 is higher than the speed of pulling up the voltage written to the node N2, and the speed of pulling down the voltage written to the node N4 is lower than the speed of pulling down the voltage written to the node N2.

[0047] The pull-up switch 20 can be a transistor M12, and the pull-down switch 30 can be a transistor M11. The amplification unit 10 provides an output voltage at the OUT terminal according to the voltage written to the nodes N1 and N2, and the control unit 40 controls the on-off of the transistor M11 and the transistor M12 according to the voltage written to the nodes N3 and N4.

[0048] Since the pull-up speed of the third reference voltage is higher than the pull-up speed of the first reference voltage, the pull-down speed of the third reference voltage is lower than the pull-down speed of the first reference voltage, the response speed of the pull-up switch 20 corresponding to the closing is lower than the response speed of the output voltage, and the response speed of the opening is higher than the response speed of the output voltage.

[0049] Since the pull-up speed of the fourth reference voltage is higher than the pull-up speed of the second reference voltage, the pull-down speed of the fourth reference voltage is lower than the pull-down speed of the second reference voltage, the response speed of the pull-up switch 20 corresponding to the closing is lower than the response speed of the output voltage, and the response speed of the opening is higher than the response speed of the output voltage.

[0050] The response speed of the pull-up switch 20 and the pull-down switch 30 corresponding to the closing is lower than the response speed of the output voltage, and the response speed of the pull-up switch 20 and the pull-down switch 30 corresponding to the opening is higher than the response speed of the output voltage, which can ensure that the pull-up switch 20 and the pull-down switch 30 are opened for a period of time when the amplification unit 10 just recovers to the steady state, thereby avoiding large signal oscillation of the main loop.

[0051] In addition, the amplifier circuit 100 provided by the embodiment of the present application also has the following technical effects: the improvement of the circuit structure is based on the comparator, and has little effect on the main loop after stabilization; the swing rate enhancement effect is only limited to the pull-up and pull-down switch 30 connected to OUT; the single-channel comparator is adopted, and the dead zone function is integrated at the same time, so that the increased power consumption is reduced to the minimum; the comparator output swing is reduced, and the comparator speed is indirectly improved; at the same time, through current multiplexing, when a large signal is input, the comparator improves the flip speed by occupying the differential pair current of the amplifier; the single-channel comparator has asymmetric rising / falling flip speed by nature, and naturally avoids the risk of large signal oscillation.

[0052] In some embodiments, the first branch 11 is configured to generate a first current according to the first input voltage and generate a first reference voltage according to the first current, the second branch 12 is configured to generate a second current according to the second input voltage and generate a second reference voltage according to the second current, and the amplification unit 10 is configured to provide an output voltage according to the first reference voltage and the second reference voltage. The first mirror branch 13 is configured to copy the first current to obtain a first mirror current and provide a third reference voltage according to the first mirror current. The second mirror branch 14 is configured to copy the second current to obtain a second mirror current and provide a fourth reference voltage according to the second mirror current.

[0053] Specifically, the first mirror branch 13 is a current mirror branch of the first branch 11, if the current flowing through the first branch 11 is I1, the current flowing through the first mirror branch 13 is I1, (K1 is determined according to the electronic device parameters of the first mirror branch 13 and the first branch 11). The second mirror branch 14 is a current mirror branch of the second branch 12, if the current flowing through the second branch 12 is I2, the current flowing through the second mirror branch 14 is K2*I2, (K2 is determined according to the electronic device parameters of the second mirror branch 14 and the second branch 12).

[0054] The speed of the first mirror current increasing is higher than the speed of the first current increasing, the speed of the first mirror current decreasing is lower than the speed of the first current decreasing, thereby causing the speed of the third reference voltage pulling up to be higher than the speed of the first reference voltage pulling up, and the speed of the third reference voltage pulling down to be lower than the speed of the first reference voltage pulling down.

[0055] The speed of the second mirror current increasing is higher than the speed of the second current increasing, the speed of the second mirror current decreasing is lower than the speed of the second current decreasing, thereby causing the speed of the fourth reference voltage pulling up to be higher than the speed of the second reference voltage pulling up, and the speed of the fourth reference voltage pulling down to be lower than the speed of the second reference voltage pulling down.

[0056] The improvement of the first mirror branch 13 and the second mirror branch 14 is based on the comparator, which has little effect on the main loop after stabilization. In addition, through current multiplexing, when a large signal is input, the comparator improves the pull-up speed of the third reference voltage and the fourth reference voltage by preoccupying the differential pair current of the amplifier, thereby indirectly improving the response speed of the control unit 40. The rising / falling flip speed of the third reference voltage and the fourth reference voltage is asymmetric, so that the single comparator naturally avoids the risk of large signal oscillation.

[0057] In some embodiments, the output voltage is positively related to the voltage difference between the first input voltage and the second input voltage, and the output voltage reaches a steady state value when the first input voltage and the second input voltage are consistent.

[0058] Specifically, the amplifier unit 10 is a differential amplifier, and the greater the voltage difference between the first input voltage and the second input voltage, the greater the output voltage at the OUT terminal. When the first input voltage and the second input voltage are substantially consistent, the output voltage is substantially close to zero, at which time the output voltage reaches a steady state value, and the loop of the amplifier circuit 100 is maintained in a steady state.

[0059] In some embodiments, when the voltage difference is less than or equal to the dead-zone voltage threshold, the control unit 40 is configured to control the pull-up switch 20 and the pull-down switch 30 to be open. When the voltage difference is greater than the dead-zone voltage threshold, the control unit 40 is configured to control the pull-up switch 20 to be closed, or the pull-down switch 30 to be closed, to adjust the output voltage to reach a steady state value.

[0060] Specifically, the amplification unit 10 is provided with a corresponding dead-zone voltage threshold. When the voltage difference between the first input voltage and the second input voltage is less than or equal to the dead-zone voltage threshold, it can be considered that the first input voltage and the second input voltage are substantially consistent at this time, and the transistor M11 and the transistor M12 are maintained in an off state at this time. At this time, the feedback loop is disconnected, and there is no impact on the main loop.

[0061] When the voltage difference between the first input voltage and the second input voltage is greater than the dead-zone voltage threshold, it can be considered that the corresponding feedback loop needs to be started at this time to pull up the output voltage of the OUT terminal or pull down the output voltage of the OUT terminal, so that the output voltage of the OUT terminal can be restored to a steady state. In the case where the first input voltage is greater than the second input voltage and the voltage difference is greater than the dead-zone voltage threshold, the pull-down switch 30 is closed and the pull-up switch 20 is opened to pull up the output voltage of the OUT terminal. In the case where the first input voltage is less than the second input voltage and the voltage difference is greater than the dead-zone voltage threshold, the pull-up switch 20 is closed and the pull-down switch 30 is opened to pull down the output voltage of the OUT terminal.

[0062] In some embodiments, when the voltage difference is greater than the dead-zone voltage threshold and the first input voltage is higher than the second input voltage, the third reference voltage is lower than the first voltage threshold, and the control unit 40 is configured to control the pull-down switch 30 to be open and the pull-up switch 20 to be closed. When the voltage difference is greater than the dead-zone voltage threshold and the first input voltage is lower than the second input voltage, the fourth reference voltage is lower than the second voltage threshold, and the control unit 40 is configured to control the pull-up switch 20 to be open and the pull-down switch 30 to be closed. When the voltage difference is less than or equal to the dead-zone voltage threshold, the third reference voltage is higher than or equal to the first voltage threshold, and the fourth reference voltage is higher than or equal to the second voltage threshold, the control unit 40 is configured to control the pull-up switch 20 and the pull-down switch 30 to be open.

[0063] Specifically, the control unit 40 can determine the on-off of the pull-down switch 30 according to the size of the third reference voltage (the voltage written to the node N3), and determine the on-off of the pull-down switch 30 according to the size of the fourth reference voltage (the voltage written to the node N4).

[0064] In the case that the first input voltage is greater than the second input voltage and the voltage difference is greater than the dead zone voltage threshold, the third reference voltage is lower than the first voltage threshold, and the control unit 40 controls the pull-down switch 30 to be closed and the pull-up switch 20 to be opened to pull up the output voltage of the OUT terminal. In the case that the first input voltage is less than the second input voltage and the voltage difference is greater than the dead zone voltage threshold, the fourth reference voltage is lower than the first voltage threshold, and the control unit 40 controls the pull-up switch 20 to be closed and the pull-down switch 30 to be opened to pull down the output voltage of the OUT terminal.

[0065] The control unit 40 can be a single comparator (the first voltage threshold is compared with the third reference voltage or the first voltage threshold is compared with the fourth reference voltage) integrated with the dead zone function, which is beneficial to reduce power consumption.

[0066] In some embodiments, the dead zone voltage threshold is positively correlated with the pull-up speed of the third reference voltage and the fourth reference voltage, and is negatively correlated with the pull-down speed of the third reference voltage and the fourth reference voltage.

[0067] Specifically, the faster the third reference voltage and the fourth reference voltage pull up, the easier the third reference voltage and the fourth reference voltage reach a level higher than the first voltage threshold, and the control unit 40 is less likely to trigger the control of the pull-up switch 20 to be closed or the control of the pull-down switch 30 to be closed, that is, the corresponding dead zone voltage threshold is larger.

[0068] The faster the third reference voltage and the fourth reference voltage pull down, the easier the third reference voltage and the fourth reference voltage reach a level lower than the first voltage threshold, and the control unit 40 is more likely to trigger the control of the pull-up switch 20 to be closed or the control of the pull-down switch 30 to be closed, that is, the corresponding dead zone voltage threshold is smaller.

[0069] Reference Figure 6In some embodiments, the first branch 11 includes a first transistor 111 and a second transistor 112, a voltage source of the amplifier circuit 100 is grounded through the first transistor 111 and the second transistor 112, a control electrode of the first transistor 111 is configured to access a first input voltage, a current flowing through the first transistor 111 and the second transistor 112 is a first current, the first transistor 111 and the second transistor 112 are connected to a first node, a voltage written to the first node is a first reference voltage. The first mirror branch 13 includes a first mirror transistor 131 and a second mirror transistor 132, the voltage source is grounded through the first mirror transistor 131 and the second mirror transistor 132, a control electrode of the first mirror transistor 131 is connected to the control electrode of the first transistor 111, a control electrode of the second mirror transistor 132 is connected to the control electrode of the second transistor 112, a current flowing through the first mirror transistor 131 and the second mirror transistor 132 is a first mirror current, the first mirror transistor 131 and the second mirror transistor 132 are connected to a third node, a voltage written to the third node is a third reference voltage. A width-length ratio of the first mirror transistor 131 is greater than that of the first transistor 111, and a width-length ratio of the second mirror transistor 132 is less than that of the second transistor 112.

[0070] Specifically, the first transistor 111 can be a transistor M1, the second transistor 112 can be a transistor M2, the first mirror transistor 131 can be a transistor M1_cmp, and the second mirror transistor 132 can be a transistor M2_cmp. The transistor M2 and the transistor M2_cmp are in a constant-on state. Control electrodes of the transistor M1 and the transistor M1_cmp are connected to an INP terminal.

[0071] A first electrode of the transistor M1 can be connected to a voltage source VDD, a second electrode of the transistor M1 can be connected to a second electrode of the transistor M2 at a node N1, and a first electrode of the transistor M2 can be grounded. A first electrode of the transistor M1_cmp can be connected to the voltage source VDD, a second electrode of the transistor M1_cmp can be connected to the second electrode of the transistor M2 at a node N2, and a first electrode of the transistor M2_cmp can be grounded.

[0072] Since the width-length ratio of the first mirror transistor 131 is greater than that of the first transistor 111, the speed of the first mirror current increasing is higher than that of the first current increasing, thereby causing the speed of the third reference voltage pulling up to be higher than that of the first reference voltage pulling up. Since the width-length ratio of the first mirror transistor 131 is greater than that of the first transistor 111, the speed of the first mirror current decreasing is lower than that of the first current decreasing, thereby causing the speed of the third reference voltage pulling down to be higher than that of the first reference voltage pulling down.

[0073] Reference Figure 6In some embodiments, the second branch 12 includes a third transistor 121 and a fourth transistor 122, a voltage source of the amplifier circuit 100 is grounded through the third transistor 121 and the fourth transistor 122, a control electrode of the third transistor 121 is configured to access a second input voltage, a current flowing through the third transistor 121 and the fourth transistor 122 is a second current, the third transistor 121 and the fourth transistor 122 are connected to a second node, and a voltage written to the second node is a second reference voltage. The second mirror branch 14 includes a third mirror transistor 141 and a fourth mirror transistor 142, the voltage source is grounded through the third mirror transistor 141 and the fourth mirror transistor 142, a control electrode of the third mirror transistor 141 is connected to the control electrode of the third transistor 121, a control electrode of the fourth mirror transistor 142 is connected to the control electrode of the fourth transistor 122, a current flowing through the third mirror transistor 141 and the fourth mirror transistor 142 is a second mirror current, the third mirror transistor 141 and the fourth mirror transistor 142 are connected to a fourth node, and a voltage written to the fourth node is a fourth reference voltage. A width-length ratio of the third mirror transistor 141 is greater than that of the third transistor 121, and a width-length ratio of the fourth mirror transistor 142 is less than that of the fourth transistor 122.

[0074] Specifically, the third transistor 121 can be a transistor M3, the fourth transistor 122 can be a transistor M4, the third mirror transistor 141 can be a transistor M3_cmp, and the fourth mirror transistor 142 can be a transistor M4_cmp. The transistor M4 and the transistor M4_cmp are in a constant-on state. Control electrodes of the transistor M3 and the transistor M3_cmp are connected to the INN terminal.

[0075] A first electrode of the transistor M3 can be connected to a voltage source VDD, a second electrode of the transistor M3 can be connected to a second electrode of the transistor M4 at a node N3, and a first electrode of the transistor M4 can be grounded. A first electrode of the transistor M3_cmp can be connected to the voltage source VDD, a second electrode of the transistor M3_cmp can be connected to the second electrode of the transistor M4 at a node N4, and a first electrode of the transistor M4_cmp can be grounded.

[0076] Since the width-length ratio of the second mirror transistor 132 is greater than that of the second transistor 112, the second mirror current increases at a higher speed than the second current, thereby causing the fourth reference voltage to be pulled up at a higher speed than the second reference voltage. Since the width-length ratio of the second mirror transistor 132 is greater than that of the second transistor 112, the second mirror current decreases at a lower speed than the second current, thereby causing the fourth reference voltage to be pulled down at a higher speed than the second reference voltage.

[0077] Reference Figure 6In some embodiments, the amplifier circuit 100 comprises a bias transistor 17, a voltage source of the amplifier circuit 100 is connected to a first pole of the bias transistor 17, and a second pole of the bias transistor 17 is connected to the first branch 11, the second branch 12, the first mirror branch 13 and the second mirror branch 14. The bias voltage provided by the second pole of the bias transistor 17 is less than the voltage of the first pole of the bias transistor 17, and the first reference voltage, the second reference voltage, the third reference voltage and the fourth reference voltage are all less than the bias voltage.

[0078] Specifically, the bias transistor 17 can be a transistor M0, which can be in a constant-on state. The first pole of the transistor M0 is connected to the voltage source VDD, and the second pole of the transistor can be connected to the first branch 11, the second branch 12, the first mirror branch 13 and the second mirror branch 14, and the bias voltage is provided through the node vs. The voltage of the second pole of the transistor M0 is lower than that of the first pole, and the bias voltage is lower than the voltage provided by the voltage source VDD. Since the voltages of the second poles of the transistors M1, M1_cmp, M3 and M3_cmp are lower than those of the first poles, the first reference voltage, the second reference voltage, the third reference voltage and the fourth reference voltage are all less than the bias voltage.

[0079] The output swing of the first reference voltage, the second reference voltage, the third reference voltage and the fourth reference voltage is from 0 to the bias voltage, which is conducive to increasing the flip speed of the amplifier

[0080] Referring to Figure 1 In some embodiments, the amplifier circuit 100 can comprise a transistor M13, a voltage source VDD is connected to a first pole of the transistor M13, a control pole of the transistor M13 is connected to the node vs, a second pole of the transistor M13 is grounded through a capacitor C1, and the transistor M13 provides a voltage Vdd-f to the control unit 40, which can serve as a first voltage threshold. The voltage of the second pole of the transistor M13 is lower than that of the first pole, i.e., the first voltage threshold is lower than the bias voltage.

[0081] The first voltage threshold is lower than the bias voltage, the output swing of the first reference voltage, the second reference voltage, the third reference voltage and the fourth reference voltage is from 0 to the bias voltage, in the case that the voltage value of the third reference voltage is less than the first voltage threshold, the control unit 40 controls the pull-down switch 30 to be closed, and in the case that the voltage value of the third reference voltage is greater than the first voltage threshold, the control unit 40 controls the pull-down switch 30 to be opened. In the case that the voltage value of the fourth reference voltage is less than the first voltage threshold, the control unit 40 controls the pull-up switch 20 to be closed, and in the case that the voltage value of the fourth reference voltage is greater than the first voltage threshold, the control unit 40 controls the pull-up switch 20 to be opened.

[0082] Referring to Figure 2In some embodiments, the amplification unit 10 comprises a third branch 15 configured to generate a third current according to a first reference voltage and a fourth branch 16 configured to generate a fourth current according to a second reference voltage, and the amplification unit 10 is configured to provide an output voltage according to a current difference between the third current and the fourth current.

[0083] Specifically, the third branch 15 is connected to the node N1 with the first branch 11 and generates the third current according to the first reference voltage written in the node N1, and the third current can be the current flowing through the transistor M5, the transistor M7 and the transistor M9. The fourth branch 16 is connected to the node N2 with the second branch 12 and generates the fourth current according to the second reference voltage written in the node N2, and the fourth current can be the current flowing through the transistor M6, the transistor M8 and the transistor M10.

[0084] When the voltage value of the first input voltage is substantially the same as the voltage value of the second input voltage, the voltage value of the first reference voltage is substantially the same as the voltage value of the second reference voltage, the current value of the third current is substantially the same as the current value of the fourth current, and the output voltage provided by the OUT terminal is close to zero.

[0085] The greater the voltage difference between the first input voltage and the second input voltage, the greater the voltage difference between the first reference voltage and the second reference voltage, the greater the current difference between the third current and the fourth current, and the greater the amplitude of the output voltage provided by the OUT terminal.

[0086] In some embodiments, when the first input voltage is greater than the second input voltage, the value of the output voltage is positive, and when the first input voltage is less than the second input voltage, the value of the output voltage is negative.

[0087] Reference Figure 7 In some embodiments, the third branch 15 comprises a first input transistor 151 and a first load 152, the voltage written in the first node of the first branch 11 is the first reference voltage, and the first node is connected to the voltage source of the amplifier circuit 100 through the first input transistor 151 and the first load 152. The fourth branch 16 comprises a second input transistor 161 and a second load 162, the voltage written in the second node of the second branch 12 is the second reference voltage, and the second node is connected to the voltage source of the amplifier circuit 100 through the second input transistor 161 and the second load 162, and the output terminal of the amplification unit 10 is connected between the second input transistor 161 and the second load 162.

[0088] Specifically, the first input transistor 151 can be the transistor M5, the first load 152 can comprise the transistor M7 and the transistor M9, and the transistor M5, the transistor M7 and the transistor M9 can be in a constant-on state.

[0089] The first terminal of transistor M5 can be connected to node N1. The second terminal of transistor M5 can be connected to the second terminal of transistor M7 and the control terminal of transistor M9. The first terminal of transistor M7 can be connected to the second terminal of transistor M9. The first terminal of transistor M9 can be connected to the voltage source VDD. The first terminal of transistor M6 can be connected to node N2. The second terminal of transistor M6 can be connected to the second terminal of transistor M8 and the OUT terminal. The first terminal of transistor M8 can be connected to the second terminal of transistor M10. The first terminal of transistor M10 can be connected to the voltage source VDD.

[0090] In some embodiments, the output of amplifier circuit 100 includes a single-ended output and a differential output, wherein the single-ended output is configured to output a single-ended amplified signal and the differential output is configured to output a differential amplified signal.

[0091] In addition to being used in the example single-ended amplifier, the amplifier circuit 100 can also be used in a fully differential amplifier. For specific implementation details, please refer to the implementation details of the example single-ended amplifier, which will not be elaborated here.

[0092] by Figure 1 For example, amplifier circuit 100 can be applied to a single-ended amplifier, with the OUT terminal serving as the single-ended output terminal.

[0093] by Figure 8 For example, amplifier circuit 100 can be applied to a differential amplifier, with OUTA and OUTB terminals serving as differential output terminals.

[0094] This application also provides an analog closed-loop circuit, which includes the amplifier circuit 100 described in the above embodiments.

[0095] Specifically, the amplifier circuit 100 provided in this application embodiment can be applied to the analog closed-loop circuit of devices such as low dropout linear regulators (LDOs) and DC-DC amplifiers, which can improve the amplifier slew rate while effectively avoiding large signal oscillations in the loop and improving the stability of the loop.

[0096] In the description of this specification, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, without contradiction, those skilled in the art can combine and integrate different embodiments or examples described in this specification, as well as features of different embodiments or examples.

[0097] In addition, the term "connection" should be interpreted broadly, for example, can include fixed connection, but also can include detachable connection, or integrally connected; can include direct connection, but also can be indirectly connected through intermediate media, but also can include the communication inside two elements. For those skilled in the art, the specific meaning of the above-mentioned terms in the present application can be understood according to the specific circumstances.

[0098] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0099] Any process or method descriptions in flow charts or otherwise described herein, represent embodiments of examples that can be implemented as code (e.g., instructions for execution by a processor or other machine) for performing a certain task or implementing a certain aspect of the present application. The preferred embodiments of this application include additional steps performed by the code and those steps can not be shown or described herein. However, such steps will be readily apparent to one of ordinary skill in the art given the task at hand and the descriptions provided above.

[0100] Although the embodiments of the present application have been shown and described above, it should be understood that the above-mentioned embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present application.

Claims

1. An amplifier circuit, characterized by The application relates to an amplifier circuit. The amplifier circuit comprises: an amplification unit, comprising a first branch and a second branch, the first branch is configured to generate a first reference voltage according to a voltage difference between a first input voltage and a second input voltage, the second branch is configured to generate a second reference voltage according to the voltage difference between the first input voltage and the second input voltage, the amplification unit is configured to provide an output voltage according to the first reference voltage and the second reference voltage; a first mirror branch, configured to generate a third reference voltage according to the first input voltage, the pull-up speed of the third reference voltage is higher than that of the first reference voltage, and the pull-down speed of the third reference voltage is lower than that of the first reference voltage; a second mirror branch, configured to generate a fourth reference voltage according to the second input voltage, the pull-up speed of the fourth reference voltage is higher than that of the second reference voltage, and the pull-down speed of the fourth reference voltage is lower than that of the second reference voltage; a pull-up switch, configured to pull up the output voltage when closed; a pull-down switch, configured to pull down the output voltage when closed; 2. The amplifier circuit of claim 1, wherein a control unit, configured to control the opening and closing of the pull-up switch and the pull-down switch according to the third reference voltage and the fourth reference voltage, so that the response speed of the pull-up switch and the pull-down switch when being opened is higher than that of the output voltage, and the response speed of the pull-up switch and the pull-down switch when being closed is lower than that of the output voltage. The first branch is configured to generate a first current according to the first input voltage and a first reference voltage according to the first current, the second branch is configured to generate a second current according to the second input voltage and a second reference voltage according to the second current, and the amplification unit is configured to provide an output voltage according to the first reference voltage and the second reference voltage; the first mirror branch is configured to copy the first current to obtain a first mirror current and provide a third reference voltage according to the first mirror current; 3. The amplifier circuit of claim 2, wherein, the second mirror branch is configured to copy the second current to obtain a second mirror current and provide a fourth reference voltage according to the second mirror current.

4. The amplifier circuit of claim 3, wherein The output voltage is positively related to the voltage difference between the first input voltage and the second input voltage, and the output voltage reaches a steady state value when the first input voltage is consistent with the second input voltage. When the voltage difference is less than or equal to a dead zone voltage threshold, the control unit is configured to control the pull-up switch and the pull-down switch to be opened; 5. The amplifier circuit of claim 4, wherein, When the voltage difference is greater than the dead zone voltage threshold, the control unit is configured to control the pull-up switch to be closed or control the pull-down switch to be closed to adjust the output voltage to reach the steady state value. The dead zone voltage threshold is positively related to the pull-up speed of the third reference voltage and the fourth reference voltage, and is negatively related to the pull-down speed of the third reference voltage and the fourth reference voltage.

6. The amplifier circuit of claim 4, wherein, when the voltage difference is greater than the dead-zone voltage threshold and the first input voltage is higher than the second input voltage, the third reference voltage is lower than a first voltage threshold, and the control unit is configured to control the pull-down switch to be open and the pull-up switch to be closed; when the voltage difference is greater than the dead-zone voltage threshold and the first input voltage is lower than the second input voltage, the fourth reference voltage is lower than a second voltage threshold, and the control unit is configured to control the pull-up switch to be open and the pull-down switch to be closed; when the voltage difference is less than or equal to the dead-zone voltage threshold, the third reference voltage is higher than or equal to the first voltage threshold, and the fourth reference voltage is higher than or equal to the second voltage threshold, the control unit is configured to control the pull-up switch and the pull-down switch to be open.

7. The amplifier circuit of claim 2, wherein, The first branch includes a first transistor and a second transistor, a voltage source of the amplifier circuit is grounded through the first transistor and the second transistor, a control electrode of the first transistor is configured to access the first input voltage, a current flowing through the first transistor and the second transistor is the first current, the first transistor and the second transistor are connected to a first node, and a voltage written to the first node is the first reference voltage; The first mirror branch includes a first mirror transistor and a second mirror transistor, the voltage source is grounded through the first mirror transistor and the second mirror transistor, a control electrode of the first mirror transistor is connected to a control electrode of the first transistor, a control electrode of the second mirror transistor is connected to a control electrode of the second transistor, a current flowing through the first mirror transistor and the second mirror transistor is the first mirror current, the first mirror transistor and the second mirror transistor are connected to a third node, and a voltage written to the third node is the third reference voltage; A width-length ratio of the first mirror transistor is greater than that of the first transistor, and a width-length ratio of the second mirror transistor is less than that of the second transistor.

8. The amplifier circuit of claim 2, wherein, The second branch includes a third transistor and a fourth transistor, a voltage source of the amplifier circuit is grounded through the third transistor and the fourth transistor, a control electrode of the third transistor is configured to access the second input voltage, a current flowing through the third transistor and the fourth transistor is the second current, the third transistor and the fourth transistor are connected to a second node, and a voltage written to the second node is the second reference voltage; The second mirror branch comprises a third mirror transistor and a fourth mirror transistor, the voltage source is connected to ground through the third mirror transistor and the fourth mirror transistor, a control electrode of the third mirror transistor is connected to a control electrode of the third transistor, a control electrode of the fourth mirror transistor is connected to a control electrode of the fourth transistor, a current flowing through the third mirror transistor and the fourth mirror transistor is the second mirror current, the third mirror transistor and the fourth mirror transistor are connected to a fourth node, and a voltage written to the fourth node is the fourth reference voltage. A width-length ratio of the third mirror transistor is greater than that of the third transistor, and a width-length ratio of the fourth mirror transistor is less than that of the fourth transistor.

9. The amplifier circuit of claim 2, wherein, The amplification unit comprises a third branch and a fourth branch, the third branch is configured to generate a third current according to the first reference voltage, the fourth branch is configured to generate a fourth current according to the second reference voltage, and the amplification unit is configured to provide the output voltage according to a current difference between the third current and the fourth current.

10. The amplifier circuit of claim 9, wherein, The third branch comprises a first input transistor and a first load, a first node of the first branch is written with the first reference voltage, and the first node is connected to a voltage source of the amplifier circuit through the first input transistor and the first load. The fourth branch comprises a second input transistor and a second load, a second node of the second branch is written with the second reference voltage, and the second node is connected to the voltage source of the amplifier circuit through the second input transistor and the second load, and an output end of the amplification unit is connected between the second input transistor and the second load.

11. The amplifier circuit of claim 1, wherein, The amplifier circuit comprises a bias transistor, a first electrode of the bias transistor is connected to the voltage source of the amplifier circuit, and a second electrode of the bias transistor is connected to the first branch, the second branch, the first mirror branch and the second mirror branch. A bias voltage provided by the second electrode of the bias transistor is less than a voltage of the first electrode of the bias transistor, and the first reference voltage, the second reference voltage, the third reference voltage and the fourth reference voltage are all less than the bias voltage.

12. The amplifier circuit of claim 1, wherein, The output end of the amplifier circuit comprises a single-ended output end and a differential output end, the single-ended output end is configured to output a single-ended amplified signal, and the differential output end is configured to output a differential amplified signal.

13. An analog closed loop circuit, characterized by The analog closed-loop circuit comprises the amplifier circuit of any one of claims 1-12.

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