Four-stage common-mode loop fully differential amplifier and application method

Abstract

The invention relates to the technical field of differential amplifiers, and discloses a four-stage common-mode loop fully differential amplifier and an application method. The four-stage common-mode loop fully-differential amplifier comprises a two-stage fully-differential main amplifier for receiving a differential-mode signal, performing two-stage amplification on the differential-mode signal and then outputting a differential signal; the common-mode level sensing unit is used for capturing a common-mode level output by the two-stage fully-differential main amplifier; and the two-stage common-mode feedback amplifier receives the common-mode level and the common-mode reference signal at the same time, and is used for amplifying an error signal between the common-mode level and the common-mode reference signal and outputting the amplified error signal to a grid electrode of a current source load of the input stage of the two-stage fully differential main amplifier. According to the four-stage common-mode loop provided by the invention, the numerical value of the CMRR is remarkably increased, meanwhile, good isolation of the common-mode feedback loop and the differential loop is realized, and the gain of the main amplifier is not constrained.

Description

Technical Field

[0001] The present invention relates to the technical field of differential amplifiers, and in particular to a four-stage common-mode loop fully differential amplifier and an application method thereof. Background Art

[0002] Common-mode negative feedback (CMFB) is a classic and widely used technology in the design of fully differential amplifiers. The output common-mode level in high-gain amplifiers is quite sensitive to changes in input voltage, device characteristics and mismatch, and cannot be stabilized by differential feedback. Therefore, a common-mode feedback (CMFB) network must be added to stabilize the common-mode level and static operating point of the circuit. Based on this, it can prevent the device from deviating from the saturated operating state and losing the amplification effect on the signal. CMFB is essentially a negative feedback network that detects the common-mode level of the two output terminals and adjusts the bias current of the amplifier accordingly, thereby achieving the purpose of stabilizing the output DC voltage. This ability can be measured by the common-mode rejection ratio (CMRR). The larger the CMRR, the stronger the amplifier's ability to suppress common-mode interference, the more stable the output DC operating point, and the better the amplifier performance.

[0003] At present, the common CMFB technology structure is to track the output common-mode level through an output common-mode level sensing circuit, compare it with the reference level, and feed the comparison result back to a bias current of the amplifier to stabilize the DC operating point of the amplifier and improve the common-mode rejection ratio.

[0004] In the above process, the comparison process between the common-mode level and the reference level is involved, which can be achieved through a feedback amplifier. At present, feedback amplifiers are mostly designed using single-stage amplifiers, and there is a mutual restriction between CMRR and the gain of the main amplifier. The reason is that the feedback amplifier and the main amplifier form a closed loop under the common-mode signal path. In order to obtain high gain and high common-mode rejection ratio, the main amplifier and the feedback amplifier theoretically need to adopt a multi-stage structure (generally two stages), but the multi-stage structure will cause the common-mode loop to form a ring oscillator, resulting in common-mode loop oscillation and instability. Therefore, the existing technologies currently use single-stage main amplifiers or single-stage feedback amplifiers, or other complex structures. The former creates a compromise relationship between CMRR and amplifier gain, limiting the further simultaneous improvement of these two indicators; the latter is difficult to promote and design. Summary of the invention

[0005] The purpose of the present invention is to provide a four-stage common-mode loop fully differential amplifier and an application method thereof, aiming to solve the restrictive relationship between common-mode rejection ratio and gain. The fully differential amplifier adopts the architecture of a two-stage main amplifier and a two-stage feedback amplifier, and frequency compensation is applied at the same time to ensure the stability of the output. The four-stage common-mode loop provided by the present invention significantly improves the value of CMRR, and at the same time achieves good isolation between the common-mode feedback loop and the differential loop, and the gain of the main amplifier is not constrained.

[0006] In order to achieve the above object, the present invention adopts the following technical scheme:

[0007] In a first aspect, the present invention provides a four-stage common-mode loop fully differential amplifier, comprising:

[0008] A two-stage fully differential main amplifier receives a differential signal and outputs a differential signal after performing two-stage amplification on the differential signal;

[0009] A common-mode level sensing unit, used to capture the common-mode level output by the two-stage fully differential main amplifier;

[0010] And a two-stage common-mode feedback amplifier receives the common-mode level and the common-mode reference signal at the same time, is used to amplify the error signal between the common-mode level and the common-mode reference signal, and outputs the amplified error signal to the gate of the current source load of the input stage of the two-stage fully differential main amplifier.

[0011] As a possible implementation, the two-stage common-mode feedback amplifier includes a first bias circuit, a first-stage common-mode error amplifier circuit, a coupling circuit, a second-stage common-mode error amplifier circuit and a first frequency compensation circuit; wherein the first bias circuit provides a bias voltage for the first-stage common-mode error amplifier circuit and the second-stage common-mode error amplifier circuit; the first-stage common-mode error amplifier circuit receives an error signal and pre-amplifies it; the pre-amplified error signal is coupled to the second-stage common-mode error amplifier circuit via the coupling circuit, and is amplified by the second-stage common-mode error amplifier circuit and then output; the first frequency compensation circuit is connected across the input and output ends of the second-stage common-mode error amplifier circuit, and is used to perform frequency compensation on the two-stage common-mode feedback amplifier.

[0012] As a possible implementation, the first-stage common-mode error amplifier circuit adopts an input rail-to-rail structure; and the second-stage common-mode error amplifier circuit adopts an output class AB rail-to-rail structure.

[0013] As a possible implementation, the first frequency compensation circuit is a Miller frequency compensation circuit containing a zero adjustment resistor, which is composed of a resistor and an NMOS tube connected in series, wherein one end of the resistor is connected to the output end of the first-stage common-mode error amplifier circuit, and the other end of the resistor is connected to the gate of the NMOS tube, and the source, drain and substrate of the NMOS tube are connected to the input end of the second-stage common-mode error amplifier circuit.

[0014] As a possible implementation, the two-stage fully differential main amplifier includes a second bias circuit, a first-stage main amplifier circuit, a second-stage main amplifier circuit, a second frequency compensation circuit, and a third frequency compensation circuit; wherein the second bias circuit provides a bias voltage for the first-stage main amplifier circuit and the second-stage main amplifier circuit; the input tube of the first-stage main amplifier circuit receives a differential signal, the gate of the current source load of the input stage of the first-stage main amplifier circuit receives an error signal, and pre-amplifies the differential signal before inputting it into the second-stage main amplifier circuit, and the second-stage main amplifier circuit performs secondary amplification on the pre-amplified differential signal and outputs a differential signal; the second frequency compensation circuit has two paths, and each path of the second frequency compensation circuit is connected between the input end and the output end of the second-stage main amplifier circuit; the third frequency compensation circuit is connected between the output end of the second-stage common-mode error amplifier circuit and the output end of the first-stage main amplifier circuit.

[0015] As a possible implementation, the first bias circuit and the second bias circuit are both full MOSFET low-voltage bandgap reference circuits, outputting temperature-independent current output ports of 1uA and 200uA.

[0016] As a possible implementation, the first-stage main amplifier circuit is composed of an NMOS tube (0), an NMOS tube (1), a PMOS tube (1), and a PMOS tube (2); wherein the gates of the NMOS tube (0) and the NMOS tube (1) are connected, the drains of the NMOS tube (1) and the PMOS tube (1) are connected, the sources of the PMOS tube (1) and the PMOS tube (2) are connected, and the drains of the PMOS tube (2) and the NMOS tube (0) are connected; and the second-stage main amplifier circuit is a two-way circuit of the same type, wherein one way The circuit is composed of an NMOS tube (3) and a PMOS tube (3); wherein the drains of the NMOS tube (3) and the PMOS tube (3) are connected, the source of the NMOS tube (3) is grounded, and the gate of the NMOS tube (3) is connected to the output of the first-stage main amplifier circuit; and another circuit is composed of an NMOS tube (4) and a PMOS tube (4); wherein the drains of the NMOS tube (4) and the PMOS tube (4) are connected, the source of the NMOS tube (4) is grounded, and the gate of the NMOS tube (4) is connected to the output of the first-stage main amplifier circuit.

[0017] As a possible implementation, the second frequency compensation circuits are each composed of a resistor and a capacitor connected in series, that is, capacitor C(1) and resistor R(2) constitute one of the second frequency compensation circuits, and capacitor C(0) and resistor R(3) constitute another second frequency compensation circuit.

[0018] As a possible implementation, the third frequency compensation circuit is composed of a capacitor C (14), an NMOS (4), an NMOS (9), and a capacitor C (14) connected in series in sequence.

[0019] In a second aspect, the present invention further provides an application method of a four-stage common-mode loop fully differential amplifier, wherein a first-stage main amplifier circuit receives a differential-mode signal under the control of a second bias circuit and pre-amplifies the differential-mode signal;

[0020] The second-stage main amplifier circuit receives the pre-amplified differential mode signal under the control of the second bias circuit, performs secondary amplification on the differential mode signal, and uses the second frequency compensation circuit to perform primary frequency compensation on the secondary amplified differential mode signal and then outputs a differential signal;

[0021] The common mode level sensing unit receives the common mode initial signal, averages it, and outputs the common mode level;

[0022] The first-stage common-mode error amplifier circuit receives the common-mode level and the common-mode reference signal simultaneously under the control of the first bias circuit, and pre-amplifies the error signal;

[0023] The coupling circuit receives the pre-amplified error signal and couples it to the second common-mode error amplifier circuit;

[0024] The second common-mode error amplifier circuit amplifies the error signal twice, and applies the first frequency compensation circuit to perform frequency compensation on the two-stage common-mode feedback amplifier to output the error signal. The error signal after the second amplification is input to the gate of the current source load of the input stage of the first-stage main amplifier circuit, and is subjected to a third frequency compensation by the third frequency compensation circuit before input.

[0025] Compared with the prior art, the beneficial effects of the present invention are:

[0026] 1. In the traditional solution, since the number of common-mode loop stages is generally no more than 3, one of the main amplifier or the feedback amplifier must be a single-stage structure. The main amplifier determines the gain, and the feedback amplifier determines the CMRR, so there is a mutual constraint between the gain and the CMRR. The present invention successfully achieves four-stage loop stability, so the main amplifier and the auxiliary amplifier are both implemented in two stages, which means that compared with the prior art, higher CMRR and main amplifier gain can be achieved at the same time.

[0027] 2. The four-stage common-mode loop fully differential amplifier provided by the present invention uses a two-stage common-mode feedback amplifier and a two-stage fully differential main amplifier in combination, and adopts a three-stage Miller compensation to stabilize the four-stage common-mode loop, thereby achieving an ultra-high common-mode rejection ratio of 198.75dB. At the same time, since the output of the common-mode feedback amplifier acts on the input stage of the main amplifier, the output power can be kept constant with the change of the output common-mode level.

[0028] 3. The four-stage common-mode loop fully differential amplifier provided by the present invention also includes a common-mode level sensing unit, which is used to block the differential mode path (two-stage fully differential main amplifier) ​​and the common mode loop (two-stage common mode feedback amplifier), while reducing the influence of the common mode loop on the differential loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0030] Figure 1 A schematic diagram of the structure of a four-stage common-mode loop fully differential amplifier provided in an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of the structure of a two-stage common-mode feedback amplifier circuit provided by an embodiment of the present invention;

[0032] Figure 3 A diagram showing the common mode rejection ratio simulation verification result of a four-stage common mode loop fully differential amplifier provided in an embodiment of the present invention;

[0033] Figure 4 A diagram showing simulation results of three process angles (tt, ss, ff) of the common mode rejection ratio of a four-stage common mode loop fully differential amplifier provided in an embodiment of the present invention;

[0034] Figure 5 The waveform diagram of the STB loop stability simulation of the four-stage common-mode loop fully differential amplifier provided in the embodiment of the present invention;

[0035] Figure 6 A summary diagram of the STB loop stability simulation of the four-stage common-mode loop fully differential amplifier provided in an embodiment of the present invention.

[0036] Reference numerals

[0037] A0-first bias circuit, A1-first common mode error amplifier circuit, A2-coupling circuit, A3-second common mode error amplifier circuit, A4-first frequency compensation circuit;

[0038] B- common mode level sensing unit;

[0039] D0-second bias circuit, D1-first stage main amplifier circuit, D2-second stage main amplifier circuit, D3-second frequency compensation circuit, D4-third frequency compensation circuit. DETAILED DESCRIPTION

[0040] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0041] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0042] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. The following at least one item (items) or similar expressions thereof refer to any combination of these items, including any combination of single items (items) or plural items (items). For example, at least one item (items) of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0043] The present invention provides a four-stage common-mode loop fully differential amplifier with an ultra-high common-mode rejection ratio, which further improves the common-mode rejection ratio of a traditional fully differential amplifier and ensures the stability of the four-stage common-mode loop. That is, firstly, a low-power two-stage rail-to-rail amplifier is designed as a feedback amplifier in a common-mode negative feedback, and at the same time, in order to stabilize the four-stage common-mode loop, a Miller capacitor compensation technology with a zeroing resistor is used between the two stages of the fully differential amplifier, between the two stages of the feedback amplifier, and between the feedback output end of the feedback amplifier and the first-stage output end of the fully differential amplifier, so as to achieve stability of the common-mode loop.

[0044] In a traditional two-stage fully differential amplifier with common-mode negative feedback, in order to improve the common-mode rejection ratio of the amplifier and determine the output common-mode level, and reduce the abnormal working of the active load caused by mismatch, a feedback amplifier is needed. This structure is simple in principle and easy to implement, but the gain of the single-stage feedback amplifier is limited, and it cannot guarantee a sufficiently high DC common-mode rejection capability and the ability to stabilize the output common-mode level, which will cause the output common-mode level to shift, and the circuit indicator is that the DC common-mode rejection ratio (CMRR) value is low; the use of a multi-stage feedback amplifier can effectively improve the loop common-mode rejection ratio and the output common-mode level stability, but the multi-stage common-mode loop may cause the common-mode loop to oscillate. A fully differential amplifier with an ultra-high common-mode rejection ratio provided by the present invention proposes a frequency compensation technology suitable for stabilizing the four-stage common-mode loop for the four-stage common-mode loop generated during the design process, and significantly improves the stability of the multi-stage common-mode loop by using a two-stage feedback amplifier and a two-stage fully differential amplifier, while providing a higher DC common-mode rejection capability, and significantly improving the common-mode rejection ratio of the amplifier. In addition, the output of the feedback amplifier is fed back to the first stage of the two-stage fully differential amplifier, and the output stage is biased separately by a current mirror, so the output power does not change with the change of the output common-mode level and remains constant.

[0045] See also Figure 1 and Figure 2 The embodiment of the present invention provides a four-stage common-mode loop fully differential amplifier, including: a two-stage fully differential main amplifier, receiving a differential signal, and outputting a differential signal after performing two-stage amplification on the differential signal. A common-mode level sensing unit B, used to capture the common-mode level output by the two-stage fully differential main amplifier. And a two-stage common-mode feedback amplifier, which simultaneously receives a common-mode level and a common-mode reference signal, is used to amplify an error signal between the common-mode level and the common-mode reference signal, and outputs the amplified error signal to the gate of a current source load of the input stage of the two-stage fully differential main amplifier.

[0046] The number of common-mode loops provided by the prior art generally does not exceed three levels. Therefore, one of the main amplifier or the feedback amplifier must be a single-stage structure. The main amplifier determines the gain, and the feedback amplifier determines the CMRR. Therefore, there is a mutual constraint between the gain and the CMRR. The four-stage common-mode loop fully differential amplifier provided by the present invention combines two-stage common-mode feedback amplifiers and two-stage fully differential main amplifiers for the first time. Compared with the prior art, it can simultaneously achieve higher CMRR and main amplifier gain. Specifically, it achieves an ultra-high common-mode rejection ratio of 198.75dB. In addition, since the common-mode feedback output acts on the input stage of the main amplifier, the output power can be kept unchanged by the change of the output common-mode level.

[0047] The two-stage common-mode feedback amplifier provided by the present invention comprises a first bias circuit A0, a first-stage common-mode error amplifier circuit A1, a coupling circuit A2, a second-stage common-mode error amplifier circuit A3 and a first frequency compensation circuit A4. The first bias circuit A0 provides a bias voltage for the first-stage common-mode error amplifier circuit A1 and the second-stage common-mode error amplifier circuit A3; the first-stage common-mode error amplifier circuit A1 receives an error signal and pre-amplifies it; the pre-amplified error signal is coupled to the second-stage common-mode error amplifier circuit A3 via the coupling circuit A2, and is amplified by the second-stage common-mode error amplifier circuit A3 and then output; the first frequency compensation circuit A4 is connected across the input end and the output end of the second-stage common-mode error amplifier circuit A3, and is used to perform frequency compensation on the two-stage common-mode feedback amplifier.

[0048] The first-stage common-mode error amplifier circuit A1 adopts an input rail-to-rail structure, which can receive all possible common-mode levels from 0 to VDD and pre-amplify the differential signal input. The second-stage common-mode error amplifier circuit A3 adopts an output class AB rail-to-rail structure, which further amplifies the output of the input rail-to-rail structure and provides an output voltage range from 0 to VDD.

[0049] The first frequency compensation circuit A4 has two paths, each of which is a Miller frequency compensation circuit containing a zero adjustment resistor. One of the paths is composed of a resistor R4 and an NMOS tube 10 connected in series, wherein one end of the resistor R4 is connected to the output end of the first-stage common-mode error amplifier circuit A1, and the other end of the resistor R4 is connected to the gate of the NMOS tube 10, and the source, drain and substrate of the NMOS tube 10 are connected to the input end of the second-stage common-mode error amplifier circuit A3. The other path is composed of a resistor R5 and an NMOS tube 11 in series. The NMOS tubes 10 and 11 replace capacitors, which is conducive to improving the compensation accuracy.

[0050] The two-stage common-mode feedback amplifier used in the present invention can realize common-mode negative feedback, determine the output common-mode level, and also improve the common-mode rejection ratio of the amplifier.

[0051] The two-stage fully differential main amplifier includes a second bias circuit D0, a first-stage main amplifier circuit D1, a second-stage main amplifier circuit D2, a second frequency compensation circuit D3, and a third frequency compensation circuit D4. The second bias circuit D0 provides a bias voltage for the first-stage main amplifier circuit D1 and the second-stage main amplifier circuit D2. The input tube of the first-stage main amplifier circuit D1 receives a differential signal, and the gate of the current source load of the input stage of the first-stage main amplifier circuit D1 receives an error signal, and pre-amplifies the differential signal and inputs it to the second-stage main amplifier circuit D2. The second-stage main amplifier circuit D2 performs secondary amplification on the pre-amplified differential signal and outputs a differential signal. The second frequency compensation circuit D3 is two-way, and each of the second frequency compensation circuits D3 is connected between the input end and the output end of the second-stage main amplifier circuit D2. The third frequency compensation circuit D4 is connected between the output end of the second-stage common-mode error amplifier circuit A3 and the output end of the first-stage main amplifier circuit D1. The present invention adopts a three-stage Miller compensation stabilized four-stage common mode loop, which can not only achieve an ultra-high common mode rejection ratio, but also prevent the common mode loop from oscillating to ensure the stability of the common mode feedback.

[0052] The first bias circuit A0 and the second bias circuit D0 are all-MOSFET low-voltage bandgap reference circuits, outputting temperature-independent current output ports of 1uA and 200uA.

[0053] The first-stage main amplifier circuit D1 is composed of NMOS tube 0, NMOS tube 1, PMOS tube 1, and PMOS tube 2. The gates of NMOS tube 0 and NMOS tube 1 are connected, the drains of NMOS tube 1 and PMOS tube 1 are connected, the sources of PMOS tube 1 and PMOS tube 2 are connected, and the drains of PMOS tube 2 and NMOS tube 0 are connected.

[0054] The second-stage main amplifier circuit D2 is a two-way circuit, one of which is composed of an NMOS tube 3 and a PMOS tube 3; wherein the drains of the NMOS tube 3 and the PMOS tube 3 are connected, the source of the NMOS tube 3 is grounded, and the gate of the NMOS tube 3 is connected to the output of the first-stage main amplifier circuit D1;

[0055] The other path is composed of an NMOS tube 4 and a PMOS tube 4 , wherein the drains of the NMOS tube 4 and the PMOS tube 4 are connected, the source of the NMOS tube 4 is grounded, and the gate of the NMOS tube 4 is connected to the output of the first stage main amplifier circuit D1 .

[0056] The second frequency compensation circuit D3 is composed of a resistor and a capacitor connected in series, that is, the capacitor C1 and the resistor R2 constitute one of the second frequency compensation circuits D3, and the capacitor C0 and the resistor R3 constitute the other second frequency compensation circuit D3.

[0057] The third frequency compensation circuit D4 is composed of a capacitor C14, an NMOS transistor 4, an NMOS transistor 9, and a capacitor C15 connected in series in sequence. In the third frequency compensation circuit D4, NMOS transistors (4, 9) are used instead of resistors to reduce the area.

[0058] As an example, see Figure 1 , NMOS tube 4 and NMOS tube 9 are used to realize the zeroing resistor in the third compensation of the common mode loop; opar2r1 is a two-stage low-power feedback amplifier; PMOS tube 4, NMOS tube 2, PMOS tube 3, NMOS tube 3 form the main amplifier output stage. NMOS tube 0, NMOS tube 1, PMOS tube 1, PMOS tube 2 constitute the main amplifier input stage; R2, C1 and R3, C0 constitute the Miller compensation unit containing the zeroing resistor of the main amplifier, which and the compensation unit of the feedback amplifier (see Figure 3 ), NMOS 4, NMOS 9, C0, and C1 together form the third-level compensation of the four-level common-mode loop. PMOS 5 and PMOS 0 are bias MOSFETs. Vcc represents the power supply, gnd represents the ground, ib1 represents the bias of the two-level common-mode feedback amplifier, and vcm represents the common-mode reference signal.

[0059] The common-mode level sensing unit B includes two matched large-value resistors (R0 and R1), and includes two input ports and one output port. The two input ports are respectively connected to the output terminals of the second-stage main amplifier circuit D2 of the two fully differential amplifiers, and the output port is connected to an input terminal of the two-stage common-mode feedback amplifier. The common-mode level sensing unit B is used to block the differential mode path (two-stage fully differential main amplifier) ​​and the common mode loop (two-stage common mode feedback amplifier), and at the same time reduce the influence of the common mode loop on the differential loop.

[0060] Figure 3 The common mode rejection ratio verification result based on the Cadence Virtuoso simulation tool is shown. The common mode rejection ratio simulation result of the present invention under the Cadence Virtuoso simulation tool is shown. The process library used is the SMIC 180nm CMOS process. The simulation results show that the DC common mode rejection ratio (CMRR) is 198.75dB.

[0061] Figure 4 The simulation results of three process angles (tt, ss, ff) of the CMRR of the fully differential amplifier show that the common-mode rejection ratio of the present invention changes little with the process angle. The minimum value among the three process angles is 190.42dB, which is obtained under the ss process angle. The fluctuation of CMRR does not exceed 10dB. Therefore, the above simulation results show that the present invention has excellent PVT characteristics.

[0062] Figure 5Stb loop stability simulation waveform based on Cadence Virtuoso, Figure 5 The loop gain curve in the figure represents the gain-frequency variation of the common-mode loop, and the loop phase curve represents the phase-frequency variation of the common-mode loop. The necessary condition for loop stability is that when the loop gain drops to 0dB with frequency, the phase shift of the loop cannot reach -180 degrees. The difference between the actual phase margin and -180 degrees is called the phase margin. The larger the phase margin, the more stable the loop. Based on the above principles, Figure 5 The phase margin is read out from the simulation curve to determine whether the common mode loop of the present invention is stable. The Cadence Virtuoso tool provides a convenient phase margin display method for the above simulation curve. The phase margin result based on this display method is as follows: Figure 6 ,Right now Figure 6 The simulation results are presented in numerical form, and the simulation results show that the four-stage common-mode loop has sufficient phase margin and gain margin, so the four-stage common-mode loop is stable, proving the effectiveness of the invention.

[0063] For comparison, the results of the present invention are compared with the related products of the world-leading company Texas Instruments. The CMRR of the OPA1637 fully differential amplifier of Texas Instruments is 140dB, the CMRR of the OPA862 amplifier is 120dB, the CMRR of the THS4567 fully differential amplifier is 80dB, and the CMRR of the THP210 is 140dB. Therefore, the common mode rejection ratio achieved by the present invention is at the leading level in the industry.

[0064] Table 1 Comparison of core indicators of the present invention and products from Texas Instruments

[0065]

[0066] In a second aspect, the present invention further provides an application method of a four-stage common-mode loop fully differential amplifier, wherein a first-stage main amplifier circuit receives a differential-mode signal under the control of a second bias circuit and pre-amplifies the differential-mode signal;

[0067] The second-stage main amplifier circuit receives the pre-amplified differential mode signal under the control of the second bias circuit, performs secondary amplification on the differential mode signal, and uses the second frequency compensation circuit to perform primary frequency compensation on the secondary amplified differential mode signal and then outputs a differential signal;

[0068] The common mode level sensing unit receives the common mode initial signal, averages it, and outputs the common mode level;

[0069] The first-stage common-mode error amplifier circuit receives the common-mode level and the common-mode reference signal simultaneously under the control of the first bias circuit, and pre-amplifies the error signal;

[0070] The coupling circuit receives the pre-amplified error signal and couples it to the second common-mode error amplifier circuit;

[0071] The second common-mode error amplifier circuit amplifies the error signal twice, and applies the first frequency compensation circuit to perform frequency compensation on the two-stage common-mode feedback amplifier to output the error signal. The error signal after the second amplification is input to the gate of the current source load of the input stage of the first-stage main amplifier circuit, and is subjected to a third frequency compensation by the third frequency compensation circuit before input.

[0072] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the drawings, etc. In the specification, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the specification. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0073] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the present invention and its equivalents.

Claims

1. A four-stage common-mode loop fully differential amplifier, characterized in that: include: A two-stage fully differential main amplifier receives a differential signal and outputs a differential signal after performing two-stage amplification on the differential signal; A common-mode level sensing unit, used to capture the common-mode level output by the two-stage fully differential main amplifier; And a two-stage common-mode feedback amplifier receives the common-mode level and the common-mode reference signal at the same time, is used to amplify the error signal between the common-mode level and the common-mode reference signal, and outputs the amplified error signal to the gate of the current source load of the input stage of the two-stage fully differential main amplifier.

2. The four-stage common-mode loop fully differential amplifier according to claim 1, characterized in that: The two-stage common-mode feedback amplifier includes a first bias circuit, a first-stage common-mode error amplifier circuit, a coupling circuit, a second-stage common-mode error amplifier circuit and a first frequency compensation circuit; Among them, the first bias circuit provides a bias voltage for the first-stage common-mode error amplifier circuit and the second-stage common-mode error amplifier circuit; the first-stage common-mode error amplifier circuit receives an error signal and pre-amplifies it; the pre-amplified error signal is coupled to the second-stage common-mode error amplifier circuit through a coupling circuit, and is output after being amplified by the second-stage common-mode error amplifier circuit; the first frequency compensation circuit is connected across the input and output ends of the second-stage common-mode error amplifier circuit, and is used to perform frequency compensation on the two-stage common-mode feedback amplifier.

3. The four-stage common-mode loop fully differential amplifier according to claim 2, characterized in that: The first-stage common-mode error amplifier circuit adopts an input rail-to-rail structure; the second-stage common-mode error amplifier circuit adopts an output class AB rail-to-rail structure.

4. The four-stage common-mode loop fully differential amplifier according to claim 2, characterized in that: The first frequency compensation circuit is a Miller frequency compensation circuit containing a zero adjustment resistor, which is composed of a resistor and an NMOS tube connected in series, wherein one end of the resistor is connected to the output end of the first-stage common-mode error amplifier circuit, and the other end of the resistor is connected to the gate of the NMOS tube, and the source, drain and substrate of the NMOS tube are connected to the input end of the second-stage common-mode error amplifier circuit.

5. The four-stage common-mode loop fully differential amplifier according to claim 2, characterized in that: The two-stage fully differential main amplifier includes a second bias circuit, a first-stage main amplifier circuit, a second-stage main amplifier circuit, a second frequency compensation circuit, and a third frequency compensation circuit; Wherein, the second bias circuit provides a bias voltage for the first-stage main amplifier circuit and the second-stage main amplifier circuit; The input tube of the first-stage main amplifier circuit receives a differential signal, the gate of the current source load of the input stage of the first-stage main amplifier circuit receives an error signal, and pre-amplifies the differential signal before inputting it into the second-stage main amplifier circuit, and the second-stage main amplifier circuit performs secondary amplification on the pre-amplified differential signal before outputting a differential signal; The second frequency compensation circuit has two paths, and each path of the second frequency compensation circuit is connected between the input and output ends of the second-stage main amplifier circuit; the third frequency compensation circuit is connected between the output end of the second-stage common-mode error amplifier circuit and the output end of the first-stage main amplifier circuit.

6. The four-stage common-mode loop fully differential amplifier according to claim 5, characterized in that: The first bias circuit and the second bias circuit are all full MOSFET low voltage bandgap reference circuits, outputting temperature-independent current output ports of 1uA and 200uA.

7. The four-stage common-mode loop fully differential amplifier according to claim 5, characterized in that: The first-stage main amplifier circuit is composed of an NMOS tube (0), an NMOS tube (1), a PMOS tube (1), and a PMOS tube (2); wherein the gate electrodes of the NMOS tube (0) and the NMOS tube (1) are connected, the drain electrodes of the NMOS tube (1) and the PMOS tube (1) are connected, the source electrodes of the PMOS tube (1) and the PMOS tube (2) are connected, and the drain electrodes of the PMOS tube (2) and the NMOS tube (0) are connected; The second-stage main amplifier circuit is a two-way circuit of the same type, one of which is composed of an NMOS tube (3) and a PMOS tube (3); wherein the drains of the NMOS tube (3) and the PMOS tube (3) are connected, the source of the NMOS tube (3) is grounded, and the gate of the NMOS tube (3) is connected to the output of the first-stage main amplifier circuit; The other circuit is composed of an NMOS tube (4) and a PMOS tube (4); wherein the drains of the NMOS tube (4) and the PMOS tube (4) are connected, the source of the NMOS tube (4) is grounded, and the gate of the NMOS tube (4) is connected to the output of the first-stage main amplifier circuit.

8. The four-stage common-mode loop fully differential amplifier according to claim 5, characterized in that: The second frequency compensation circuits are composed of a resistor and a capacitor connected in series, that is, capacitor C(1) and resistor R(2) constitute one of the second frequency compensation circuits, and capacitor C(0) and resistor R(3) constitute another second frequency compensation circuit.

9. The four-stage common-mode loop fully differential amplifier according to claim 5, characterized in that: The third frequency compensation circuit is composed of a capacitor C (14), an NMOS transistor (4), an NMOS transistor (9), and a capacitor C (15) which are connected in series in sequence.

10. An application method of a four-stage common-mode loop fully differential amplifier, characterized in that: The steps include: The first stage main amplifier circuit receives the differential mode signal under the control of the second bias circuit and pre-amplifies the differential mode signal; The second-stage main amplifier circuit receives the pre-amplified differential mode signal under the control of the second bias circuit, performs secondary amplification on the differential mode signal, and uses the second frequency compensation circuit to perform primary frequency compensation on the secondary amplified differential mode signal and then outputs a differential signal; The common mode level sensing unit receives the common mode initial signal, averages it, and outputs the common mode level; The first-stage common-mode error amplifier circuit receives the common-mode level and the common-mode reference signal simultaneously under the control of the first bias circuit, and pre-amplifies the error signal; The coupling circuit receives the pre-amplified error signal and couples it to the second common-mode error amplifier circuit; The second common-mode error amplifier circuit amplifies the error signal twice, and applies the first frequency compensation circuit to perform frequency compensation on the two-stage common-mode feedback amplifier to output the error signal. The error signal after the second amplification is input to the gate of the current source load of the input stage of the first-stage main amplifier circuit, and is subjected to a third frequency compensation by the third frequency compensation circuit before input.

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