Noise self-blocking high-voltage level shift circuit and method, and gate drive circuit

Abstract

The invention discloses a noise self-blocking high-voltage level shift circuit and method and a gate drive circuit, relates to the technical field of high-voltage drive circuits, and provides a technical scheme capable of effectively blocking common-mode noise transmission. The noise self-blocking high-voltage level shift circuit comprises a high-voltage level shift module, an operation module, a first noise self-blocking module and a second noise self-blocking module. When the high-voltage level shifting module is influenced by common-mode noise, the first output end of the high-voltage level shifting module outputs a first low-level signal, the second output end of the high-voltage level shifting module outputs a second low-level signal to the operation module, and the operation module outputs the first low-level signal according to the first low-level signal. And outputting a third low-level signal to the enabling control end of the first noise self-blocking module and the enabling control end of the second noise self-blocking module according to the first low-level signal and the second low-level signal, wherein the third low-level signal is used for controlling the first noise self-blocking module and the second noise self-blocking module to block the common-mode noise signal.

Description

Technical Field

[0001] The present invention relates to the technical field of high-voltage drive circuits, and in particular to a high-voltage level shift circuit and method for self-blocking noise, and a gate drive circuit. Background Art

[0002] With the development of power electronics technology, intelligent power integrated circuits have been developed that can integrate power devices and control logic circuits in the same circuit. They are generally composed of high-voltage power devices, low-voltage signal processing circuits, level shift circuits, and various protection modules. Power devices are the core unit of intelligent power integrated circuits SPIC, and are the key to SPIC modules being able to withstand high voltage tests. With the gradual development and maturity of SPIC technology, its application scope is also expanding step by step, including power management, aerospace, automotive electronics, medical and other aspects of production and life.

[0003] Intelligent power integrated circuits mainly include high-voltage side gate drive modules and low-voltage side gate drive modules. The high-voltage level shift circuit is the core circuit of the entire high-voltage side gate drive module, and its performance will directly affect the normal operation of the entire intelligent power module.

[0004] The current high-voltage level shift circuit includes two LDMOS tubes: LD1 and LD2, and two load resistors: R1 and R2. Since the high-voltage side voltage of the high-voltage level shift circuit will rise rapidly between 0V and high voltage, dV / dt noise will be generated in the circuit. The dV / dt noise can generate a displacement current through the drain-source parasitic capacitance of the two LDMOS tubes, and the current will generate a voltage drop through the load resistors R1 and R2, thereby generating a false trigger signal in the form of a negative pulse at the drain end of the two LDMOS tubes. For these two falsely triggered common-mode noise signals, as long as the noise amplitude is large enough, they can reach the RS latch through the filtering circuit. When the common-mode noise signal reaches the RS latch at the same time, it will put it in an uncertain working state, resulting in an erroneous output signal HO, which will cause the power tube to be turned on incorrectly. Common-mode noise will seriously threaten the reliability of the high-voltage level shift circuit, causing the power tube to be directly connected up and down, and in severe cases, it may burn out the power device. Summary of the invention

[0005] The object of the present invention is to provide a high-voltage level shift circuit and method for self-blocking noise, and a gate drive circuit, so as to provide a technical solution that can effectively block the transmission of common-mode noise.

[0006] In a first aspect, the present invention discloses a high-voltage level shift circuit with noise self-blocking, comprising a high-voltage level shift module, a calculation module, a first noise self-blocking module and a second noise self-blocking module.

[0007] The first output end of the high-voltage level shift module is electrically connected to the input ends of the operation module and the first noise self-blocking module, respectively; the second output end of the high-voltage level shift module is electrically connected to the input ends of the operation module and the second noise self-blocking module, respectively; the output end of the operation module is electrically connected to the enable control end of the first noise self-blocking module and the enable control end of the second noise self-blocking module, respectively.

[0008] When the high-voltage level shift module is affected by a common-mode noise signal, the first output end of the high-voltage level shift module outputs a first low-level signal, and the second output end of the high-voltage level shift module outputs a second low-level signal to the operation module. The operation module outputs a third low-level signal to the enable control end of the first noise self-blocking module and the enable control end of the second noise self-blocking module according to the first low-level signal and the second low-level signal. The third low-level signal is used to control the first noise self-blocking module and the second noise self-blocking module to block the common-mode noise signal.

[0009] In the case of adopting the above technical solution, the noise self-blocking high-voltage level shift circuit provided by the present invention includes an operation module, a first noise self-blocking module and a second noise self-blocking module. When the high-voltage level shift module has a common-mode noise signal, the first output end of the high-voltage level shift module outputs a first low-level signal, and the second output end of the high-voltage level shift module outputs a second low-level signal to the operation module. The operation module outputs a third low-level signal to the enable control end of the first noise self-blocking module and the enable control end of the second noise self-blocking module according to the first low-level signal and the second low-level signal. The first noise self-blocking module and the second noise self-blocking module block both output low-level signals. In the high-voltage side gate drive module, the low-level signals output by the first noise self-blocking module and the second noise self-blocking module are filtered by the filtering circuit, and the output signal of the RS latch circuit maintains the original transmission state. Based on this, the present invention can effectively block the transmission path of the common-mode noise, so that it will not allow the RS latch to enter an unstable state, thereby effectively suppressing the common-mode noise.

[0010] Furthermore, the operation module includes an OR gate; a first input end of the OR gate is electrically connected to a first output end of the high-voltage level shift module, a second input end of the OR gate is electrically connected to a second output end of the high-voltage level shift module, and an output end of the OR gate is electrically connected to an enable control end of the first noise self-blocking module and an enable control end of the second noise self-blocking module, respectively.

[0011] Furthermore, the noise self-blocking high-voltage level shift circuit further includes a first buffer module and a second buffer module;

[0012] The first buffer module is disposed between the high-voltage level shift module and the first noise self-blocking module, and is used for delaying the level signal output by the high-voltage level shift module and then outputting a first delayed signal to the first noise self-blocking module;

[0013] The second buffer module is disposed between the high-voltage level shift module and the second noise self-blocking module, and is used to delay the level signal output by the high-voltage level shift module and then output a second noise signal to the second noise self-blocking module.

[0014] Furthermore, the first noise self-blocking module includes a first PMOS tube, a first NMOS tube and a third resistor; the output end of the first buffer module is electrically connected to the input ends of the first PMOS tube and the first NMOS tube, the output end of the OR gate is electrically connected to the enable control end of the first PMOS tube, the output end of the first PMOS tube is electrically connected to the output end of the first NMOS tube, the output end of the first NMOS tube is connected to the high-voltage floating ground end, one end of the third resistor is connected to the output ends of the first PMOS tube and the first NMOS tube, and the other end is connected to the high-voltage floating ground end.

[0015] The second noise self-blocking module includes a second PMOS tube, a second NMOS tube and a fourth resistor; the output end of the second buffer module is electrically connected to the input ends of the second PMOS tube and the second NMOS tube, the output ends of the OR gate are electrically connected to the enable control ends of the second PMOS tube, the output end of the second PMOS tube is electrically connected to the output end of the second NMOS tube, the output end of the second NMOS tube is connected to the high-voltage floating ground end, one end of the fourth resistor is connected to the output ends of the second PMOS tube and the second NMOS tube, and the other end is connected to the high-voltage floating ground end.

[0016] Further, the high-voltage level shift module includes a first LDMOS tube, a second LDMOS tube, a first voltage regulator diode, a second voltage regulator diode, a first resistor and a second resistor; the first end of the first resistor is electrically connected to the high-voltage floating ground end, and the second end is grounded after passing through the first LDMOS tube; the first end of the second resistor is electrically connected to the high-voltage floating ground end, and the second end is grounded after passing through the second LDMOS tube; there is a first parasitic capacitor between the drain and source of the first LDMOS, and there is a second parasitic capacitor between the drain and source of the second LDMOS; the first voltage regulator diode is connected to both ends of the first resistor, and the second voltage regulator diode is connected to both ends of the second resistor; wherein the control end of the first LDMOS tube is used to access the first pulse signal, the control end of the second LDMOS tube is used to access the second pulse signal, and the rising edge of the first pulse signal is different from the rising edge of the second pulse signal.

[0017] Furthermore, when the first pulse signal is at a low level, the second pulse signal is at a high level or a low level; and when the first pulse signal is at a high level, the second pulse signal is at a low level.

[0018] In a second aspect, the present invention further provides a noise self-blocking method, which is applied to a noise self-blocking high-voltage level shifting circuit, and the noise self-blocking method comprises the following steps:

[0019] When a common mode noise signal exists in the high voltage level shift module, the high voltage level shift module outputs a first low level signal and a second low level signal to the operation module respectively.

[0020] After the operation module is used to operate the first low-level signal and the second low-level signal, a third low-level signal is output to the first noise self-blocking module and the second noise self-blocking module for blocking.

[0021] The third low level signal is used to control the first noise self-blocking module and the second noise self-blocking module to block common mode noise signals.

[0022] In a third aspect, the present invention further provides a high-voltage gate drive circuit, including a filter circuit, an RS latch circuit, an output drive circuit, and the noise self-blocking high-voltage level shift circuit.

[0023] The noise self-blocking high-voltage level shift circuit, the filter circuit, the RS latch circuit, and the output drive circuit are electrically connected in sequence.

[0024] Furthermore, the noise self-blocking high-voltage level shift circuit is electrically connected to the pulse generating circuit, and is used to access the first pulse signal and the second pulse signal generated by the pulse generating circuit, and the rising edge of the first pulse signal is different from the rising edge of the second pulse signal.

[0025] Furthermore, when a common-mode noise signal exists in the noise self-blocking high-voltage level shift circuit, the noise self-blocking high-voltage level shift circuit outputs two low-level signals to the filtering circuit. After filtering, the filtering circuit sends the filtered signal to the RS latch circuit, and the output signal of the RS latch circuit maintains the original transmission state.

[0026] Compared with the prior art, the beneficial effects of the second and third aspects of the present invention are the same as the beneficial effects of the noise self-blocking high-voltage level shift circuit of the above technical solution, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0028] Figure 1 A structural principle diagram of a high voltage level shift circuit in the prior art is shown;

[0029] Figure 2 A structural principle diagram of a high-voltage level shift circuit of a noise self-blocking circuit provided by an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of an application of a high-voltage level shift circuit with self-noise blocking provided by an embodiment of the present invention;

[0031] Figure 4 A waveform diagram of a signal normally transmitted when there is no common mode noise provided by an embodiment of the present invention;

[0032] Figure 5 A noise transmission waveform diagram for suppressing noise when there is common mode noise provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0034] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0035] With the development of power electronics technology, intelligent power integrated circuits that can integrate power devices and control logic circuits in the same circuit are generally composed of high-voltage power devices, low-voltage signal processing circuits, level shift circuits, and various protection modules. Power devices are the core unit of smart power integrated circuits SPIC (Smart Power IC) and are the key to SPIC modules being able to withstand high voltage tests. With the gradual development and maturity of SPIC technology, its application scope is also expanding step by step, including power management, aerospace, automotive electronics, medical and other aspects of production and life.

[0036] The intelligent power integrated circuit mainly includes a high-voltage side gate drive module and a low-voltage side gate drive module. In the intelligent power module, the high-voltage side gate drive module is responsible for converting the 3.3V / 5V PWM control signal into a high-voltage side gate control signal relative to the high-voltage floating ground voltage VS. It contains an interface circuit, a narrow-band pulse generation circuit, a 600V high-voltage level shift circuit, a filter circuit, a pulse recovery circuit, and an output drive module for increasing the output current. The high-voltage level shift circuit is the core circuit of the entire high-voltage side gate drive module, and its performance will directly affect the normal operation of the entire intelligent power module. The function of this circuit is to convert the PWM input signal relative to the common ground GND in the high-voltage side drive module into a gate control signal relative to the high-voltage side floating ground VS after level shifting, so that when the high-voltage side floating ground voltage VS is 600V, it can also drive the high-voltage side power tube to work normally.

[0037] The traditional high-voltage side gate drive circuit includes a high-voltage level shift circuit, a filter circuit, an RS latch circuit, and an output drive circuit. The pulse generation circuit converts the rising and falling edges of the input square wave signal into two pulse signals, which are added to the gates of LD1 and LD2 to control the normal operation of the high-voltage level shift circuit. The function of the pulse generation circuit is to reduce the conduction loss of the LDMOS tube.

[0038] Conventional high voltage level shift circuits such as Figure 1As shown, it includes two LDMOS tubes: LD1 and LD2, two load resistors: R1 and R2, and two voltage regulator diodes: DZ1 and DZ2. CN1 and CN2 are the parasitic capacitances of LD1 and LD2 respectively. The LDMOS tube is used to withstand the 615V high voltage. When the pulse signal is added to the gate of LD1, LD1 is turned on, and the current flows through R1, generating a negative pulse voltage at the drain of LD1. When LD2 is driven by the pulse signal, it outputs a negative pulse voltage. DZ1 and DZ2 limit the voltage drop on R1 and R2 to never exceed the voltage regulation value VDZ of the diode, that is, the amplitude of the negative pulse S and R will not exceed VDZ, and generally VDZ = VCC. After passing through the noise filtering circuit, S and R are restored to square wave signals by the RS latch, and after passing through the output drive module, they drive the high-side power tube T1 to turn on.

[0039] In a traditional level shift circuit, the high-voltage floating ground terminal VS will rise very quickly between 0V and high voltage, thereby generating dV / dt noise in the circuit. The dV / dt noise can generate a displacement current through the drain-source parasitic capacitance of the two LDMOS tubes. This current generates a voltage drop across the load resistors R1 and R2, thereby generating a false trigger signal in the form of a negative pulse at the drain end of the two LDMOS tubes. For these two falsely triggered common-mode noise signals, as long as the noise amplitude is large enough, they can reach the RS latch through the filtering circuit. When the common-mode noise signal reaches the RS latch at the same time, it will put it in an uncertain working state, resulting in an erroneous output signal HO, which will cause the power tube to be turned on incorrectly. Common-mode noise will seriously threaten the reliability of the high-voltage level shift circuit, causing the power tube to be directly connected up and down, and in severe cases, it may burn out the power device.

[0040] Based on this, refer to Figure 2 An embodiment of the present invention provides a high-voltage level shift circuit with noise self-blocking, including a high-voltage level shift module, a calculation module, a first noise self-blocking module and a second noise self-blocking module.

[0041] Wherein, the first output end of the high-voltage level shift module is electrically connected to the input end of the operation module and the first noise self-blocking module respectively, and the second output end of the high-voltage level shift module is electrically connected to the input end of the operation module and the second noise self-blocking module respectively; the output end of the operation module is electrically connected to the enable control end of the first noise self-blocking module and the enable control end of the second noise self-blocking module respectively;

[0042] When the high-voltage level shift module is affected by a common-mode noise signal, the first output end of the high-voltage level shift module outputs a first low-level signal, and the second output end of the high-voltage level shift module outputs a second low-level signal to the operation module. The operation module outputs a third low-level signal to the enable control end of the first noise self-blocking module and the enable control end of the second noise self-blocking module according to the first low-level signal and the second low-level signal. The third low-level signal is used to control the first noise self-blocking module and the second noise self-blocking module to block the common-mode noise signal.

[0043] Specifically, the noise self-blocking high-voltage level shift circuit provided by the embodiment of the present invention includes an operation module, a first noise self-blocking module and a second noise self-blocking module. When the high-voltage level shift module has a common-mode noise signal, the first output end of the high-voltage level shift module outputs a first low-level signal, and the second output end of the high-voltage level shift module outputs a second low-level signal to the operation module. The operation module outputs a third low-level signal to the enable control end of the first noise self-blocking module and the enable control end of the second noise self-blocking module according to the first low-level signal and the second low-level signal. The first noise self-blocking module and the second noise self-blocking module block both output low-level signals. In the high-voltage side gate drive module, the low-level signals output by the first noise self-blocking module and the second noise self-blocking module are filtered by the filtering circuit, and the output signal of the RS latch circuit maintains the original transmission state. Based on this, the present invention can effectively block the transmission path of the common-mode noise, so that it will not allow the RS latch to enter an unstable state, thereby effectively suppressing the common-mode noise.

[0044] In some examples, reference Figure 2 The above-mentioned high-voltage level shift circuit with self-noise blocking also includes a first buffer module and a second buffer module. The first buffer module is arranged between the high-voltage level shift module and the first self-noise blocking module, and is used to delay the level signal output by the high-voltage level shift module and then output a first delayed signal to the first self-noise blocking module.

[0045] The first buffer module and the second buffer module are used to delay the signal output by the high-voltage level shift module. In practice, the delay time of the first buffer module and the second buffer module is at the nanosecond level.

[0046] In an embodiment of the present invention, the above-mentioned operation module can be an OR gate, a first input end of the OR gate is electrically connected to the first output end of the high-voltage level shift module, a second input end of the OR gate is electrically connected to the second output end of the high-voltage level shift module, and an output end of the OR gate is electrically connected to an enable control end of the first noise self-blocking module and an enable control end of the second noise self-blocking module, respectively.

[0047] In practical applications, only when the signal input to the OR gate is low level "0" and low level "0", the EN output by the OR gate is low level "0", and at other times, the EN output by the OR gate is high level "1". Based on this, not only can the first noise self-blocking module and the second noise self-blocking module be controlled to block the common mode noise signal, but also the first noise self-blocking module and the second noise self-blocking module can be guaranteed to transmit signals backward normally.

[0048] Specifically, refer to Figure 2 The first noise self-blocking module includes a first PMOS tube MP1, a first NMOS tube MN1 and a third resistor R3; the output end of the first buffer module is electrically connected to the input ends of the first PMOS tube MP1 and the first NMOS tube MN1, the output end of the OR gate is electrically connected to the enable control end of the first PMOS tube MP1, the output end of the first PMOS tube MP1 is electrically connected to the output end of the first NMOS tube MN1, the source of the first NMOS tube MN1 is connected to the high-voltage floating ground end, one end of the third resistor R3 is connected to the output end of the first PMOS tube MP1 and the output end of the first NMOS tube MN1, and the other end is connected to the high-voltage floating ground end.

[0049] Reference Figure 2 The second noise self-blocking module includes a second PMOS tube MP2, a second NMOS tube MN2 and a fourth resistor R4; the output end of the second buffer module is electrically connected to the input ends of the second PMOS tube MP2 and the second NMOS tube MN2, the output ends of the OR gate are electrically connected to the enable control end of the second PMOS tube MP2, the output end of the second PMOS tube MP2 is electrically connected to the output end of the second NMOS tube MN2, the source of the second NMOS tube MN2 is connected to the high-voltage floating ground, one end of the fourth resistor R4 is connected to the output end of the second PMOS tube MP2 and the output end of the second NMOS tube MN2, and the other end is connected to the high-voltage floating ground.

[0050] Reference Figure 2The high-voltage level shift module includes a first LDMOS transistor LD1, a second LDMOS transistor LD2, a first voltage zener diode DZ1, a second voltage zener diode DZ2, a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is electrically connected to the high-voltage floating power supply VB, and the second end is grounded after passing through the first LDMOS transistor LD1; the first end of the second resistor R2 is electrically connected to the high-voltage floating power supply VB, and the second end is grounded after passing through the second LDMOS transistor LD2; a first parasitic capacitor C is provided between the source and the drain of the first LDMOS transistor LD1 N1 There is a second parasitic capacitor C between the source and drain of the second LDMOS tube LD2. N2 The first voltage zener diode DZ1 is connected to both ends of the first resistor R1, and the second voltage zener diode DZ2 is connected to both ends of the second resistor R2.

[0051] The control end of the first LDMOS tube is used to access a first pulse signal, and the control end of the first LDMOS tube is used to access a second pulse signal. The rising edge of the first pulse signal is different from the rising edge of the second pulse signal.

[0052] When the first pulse signal is at a low level, the second pulse signal is at a high level or a low level; when the first pulse signal is at a high level, the second pulse signal is at a low level.

[0053] Specifically, refer to Figure 2 and Figure 3 The high-voltage level shift circuit of the noise self-blocking includes two LDMOS: LD1 and LD2, two load resistors: R1 and R2; two voltage stabilizing diodes: DZ1 and DZ2; an OR gate; two module buffers, and two noise self-blocking modules. The first noise self-blocking module is composed of a PMOS tube MP1, an NMOS tube MN1, and a resistor R3. The second noise self-blocking module is composed of a PMOS tube MP2, an NMOS tube MN2, and a resistor R4.

[0054] LDMOS is used to withstand 615V high voltage. When a pulse signal is added to the gate of LD1, LD1 is turned on, and current flows through R1, generating a corresponding signal 1 at the drain of LD1. Similarly, the drain of LD2 will also generate a corresponding signal 2. These two signals output the enable control signal EN through the OR gate. EN controls whether the two self-blocking structures can transmit signals backward. Signal 1 outputs S1 through BUFFER1, and signal 2 outputs R1 through BUFFER2. S1 and R1 are input to the input of BLOCK1 and the input of BLOCK2 respectively. BLOCK1 and BLOCK2 output S_OUT and R_OUT respectively. S_OUT and R_OUT output S and R after passing through the noise filtering circuit. S and R are restored to square wave signals by the RS latch. After passing through the output drive module, they drive the high-side power tube T1 to turn on.

[0055] Reference Figure 2-Figure 4 , when there is no common mode noise signal and the signal is transmitted normally, SET is high level "1" and RESET is low level "0": LD1 drain outputs low level "0", LD2 drain outputs high level "1", OR gate OR outputs EN as high level "1", S1 is low level "0", R1 is high level "1", EN controls BLOCK1 and BLOCK2 to transmit signals normally backward, so S_OUT is high level "1" and R_OUT is low level "0". After passing through the filtering circuit, the output signal of the RS latch flips from low level to high level.

[0056] When SET is low level "0" and RESET is high level "1": LD1 drain outputs high level "1", LD2 drain outputs low level "0", OR gate OR outputs EN as high level "1", S1 as high level "1", R1 as low level "0", EN controls BLOCK1 and BLOCK2 to transmit signals backward normally, so S_OUT is low level "0", R_OUT is high level "1". After passing through the filtering circuit, the output signal of the RS latch flips from high level to low level.

[0057] When SET is low level "0" and RESET is low level "0": LD1 drain outputs high level "1", LD2 drain outputs high level "1", OR gate OR outputs EN as high level "1", S1 is high level "1", R1 is high level "1", EN controls BLOCK1 and BLOCK2 to transmit signals backward normally, so S_OUT is low level "0", and R_OUT is low level "0". After passing through the filtering circuit, the output signal of the RS latch maintains the original transmission state.

[0058] When there is common mode noise, the noise self-blocking structure suppresses the common mode noise. Figure 5 As shown:

[0059] The common mode noise signal generates a voltage drop V across R1 and R2. drop1 、V drop2 .LD1 drain outputs low level "0", LD2 drain outputs low level "0", OR gate OR outputs EN as low level "0", S1 as low level "0", R1 as low level "0", EN controls BLOCK1 and BLOCK2 to block common mode noise signals, R3 and R4 make S_OUT as low level "0", and R_OUT as low level "0". After passing through the filtering circuit, the output signal of the RS latch maintains the original transmission state. That is, the present invention can effectively suppress common mode noise signals.

[0060] Based on the above description, the embodiments of the present invention can effectively block the transmission path of common-mode noise, thereby avoiding the influence of common-mode noise on false triggering of the circuit without affecting the transmission of normal signals.

[0061] Furthermore, the present invention only includes two LDMOS tubes, so the circuit structure is simple, the chip area occupied is small, the process difficulty is low, and the reliability and practical value are high.

[0062] In a second aspect, an embodiment of the present invention further provides a noise self-blocking method, which is applied to the noise self-blocking high-voltage level shifting circuit, and the noise self-blocking method comprises the following steps:

[0063] When a common mode noise signal exists in the high voltage level shift module, the high voltage level shift module outputs a first low level signal and a second low level signal to the operation module respectively.

[0064] After the operation module is used to operate the first low-level signal and the second low-level signal, a third low-level signal is output to the first noise self-blocking module and the second noise self-blocking module for blocking.

[0065] The third low level signal is used to control the first noise self-blocking module and the second noise self-blocking module to block common mode noise signals.

[0066] In the case of adopting the technical solution, the operation module outputs a third low-level signal to the enable control end of the first noise self-blocking module and the enable control end of the second noise self-blocking module according to the first low-level signal and the second low-level signal, and the first noise self-blocking module and the second noise self-blocking module block both output low-level signals, and in the high-voltage side gate drive module, the low-level signals output by the first noise self-blocking module and the second noise self-blocking module are filtered by the filter circuit, and the output signal of the RS latch circuit maintains the original transmission state. Based on this, the present invention can effectively block the transmission path of common-mode noise, so that it will not let the RS latch enter an unstable state, thereby effectively suppressing common-mode noise.

[0067] In a third aspect, the present invention provides a high-voltage gate drive circuit, including a filter circuit, an RS latch circuit, an output drive circuit, and the noise self-blocking high-voltage level shift circuit described in the first aspect.

[0068] The noise self-blocking high-voltage level shift circuit, the filter circuit, the RS latch circuit, and the output drive circuit are electrically connected in sequence.

[0069] In the intelligent power module, the high-voltage gate drive circuit is responsible for converting the 3.3V / 5V PWM control signal into a high-voltage side gate control signal relative to the high-side floating ground voltage VS. It contains an interface circuit, a narrow-band pulse generation circuit, a 600V high-voltage level shift circuit, a filter circuit, a pulse recovery circuit, and an output drive module that increases the output current.

[0070] In practice, the noise self-blocking high-voltage level shift circuit is electrically connected to a pulse generating circuit, and is used to access a first pulse signal and a second pulse signal generated by the pulse generating circuit, wherein the rising edge of the first pulse signal is different from the rising edge of the second pulse signal.

[0071] When a common-mode noise signal exists in the noise self-blocking high-voltage level shift circuit, the noise self-blocking high-voltage level shift circuit outputs two low-level signals to the filtering circuit. After filtering, the filtering circuit sends the filtered signal to the RS latch circuit, and the output signal of the RS latch circuit maintains the original transmission state.

[0072] Based on the above description, since the high-voltage gate drive circuit in the embodiment of the present invention envelops the high-voltage level shift circuit of the noise self-blocking in the first aspect, in practice, the operation module can be used to operate the first low-level signal and the second low-level signal, and then output a third low-level signal to the enable control end of the first noise self-blocking module and the enable control end of the second noise self-blocking module. The first noise self-blocking module and the second noise self-blocking module block both output low-level signals. In the high-voltage side gate drive module, the low-level signals output by the first noise self-blocking module and the second noise self-blocking module are filtered by the filter circuit, and the output signal of the RS latch circuit maintains the original transmission state. Based on this, the embodiment of the present invention can effectively block the transmission path of the common-mode noise, so that it will not let the RS latch enter an unstable state, thereby effectively suppressing the common-mode noise.

[0073] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0074] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A noise self-blocking high-voltage level shift circuit, characterized in that: The noise self-blocking high-voltage level shifting circuit comprises a high-voltage level shifting module, a calculation module, a first noise self-blocking module and a second noise self-blocking module; The first output end of the high-voltage level shift module is electrically connected to the input end of the operation module and the first noise self-blocking module respectively, and the second output end of the high-voltage level shift module is electrically connected to the input end of the operation module and the second noise self-blocking module respectively; the output end of the operation module is electrically connected to the enable control end of the first noise self-blocking module and the enable control end of the second noise self-blocking module respectively; When the high-voltage level shift module is affected by a common-mode noise signal, the first output end of the high-voltage level shift module outputs a first low-level signal, and the second output end of the high-voltage level shift module outputs a second low-level signal to the operation module. The operation module outputs a third low-level signal to the enable control end of the first noise self-blocking module and the enable control end of the second noise self-blocking module according to the first low-level signal and the second low-level signal. The third low-level signal is used to control the first noise self-blocking module and the second noise self-blocking module to block the common-mode noise signal.

2. The high-voltage level shift circuit with self-noise blocking according to claim 1, characterized in that: The operation module includes an OR gate; a first input end of the OR gate is electrically connected to a first output end of the high-voltage level shift module, a second input end of the OR gate is electrically connected to a second output end of the high-voltage level shift module, and an output end of the OR gate is electrically connected to an enable control end of the first noise self-blocking module and an enable control end of the second noise self-blocking module, respectively.

3. The high-voltage level shift circuit with self-noise blocking according to claim 1, characterized in that: The noise self-blocking high-voltage level shift circuit also includes a first buffer module and a second buffer module; The first buffer module is disposed between the high-voltage level shift module and the first noise self-blocking module, and is used for delaying the level signal output by the high-voltage level shift module and then outputting a first delayed signal to the first noise self-blocking module; The second buffer module is disposed between the high-voltage level shift module and the second noise self-blocking module, and is used to delay the level signal output by the high-voltage level shift module and then output a second noise signal to the second noise self-blocking module.

4. The high-voltage level shift circuit with self-noise blocking according to claim 3, characterized in that: The first noise self-blocking module includes a first PMOS tube, a first NMOS tube and a third resistor; the output end of the first buffer module is electrically connected to the input ends of the first PMOS tube and the first NMOS tube, the output end of the OR gate is electrically connected to the enable control end of the first PMOS tube, the output end of the first PMOS tube is electrically connected to the output end of the first NMOS tube, the source of the first NMOS tube is connected to the high-voltage floating ground end, one end of the third resistor is connected to the output end of the first PMOS tube and the output end of the first NMOS tube, and the other end is connected to the high-voltage floating ground end; The second noise self-blocking module includes a second PMOS tube, a second NMOS tube and a fourth resistor; the output end of the second buffer module is electrically connected to the input ends of the second PMOS tube and the second NMOS tube, the output ends of the OR gate are electrically connected to the enable control ends of the second PMOS tube, the output end of the second PMOS tube is electrically connected to the output end of the second NMOS tube, the source of the second NMOS tube is connected to the high-voltage floating ground end, one end of the fourth resistor is connected to the output end of the second PMOS tube and the output end of the second NMOS tube, and the other end is connected to the high-voltage floating ground end.

5. The high-voltage level shift circuit with self-noise blocking according to claim 1, characterized in that: The high-voltage level shift module includes a first LDMOS tube, a second LDMOS tube, a first voltage-stabilizing diode, a second voltage-stabilizing diode, a first resistor and a second resistor; the first end of the first resistor is electrically connected to the high-voltage floating ground end, and the second end is grounded after passing through the first LDMOS tube; the first end of the second resistor is electrically connected to the high-voltage floating ground end, and the second end is grounded after passing through the second LDMOS tube; a first parasitic capacitor is provided between the drain and source of the first LDMOS, and a second parasitic capacitor is provided between the drain and source of the second LDMOS; the first voltage-stabilizing diode is connected to both ends of the first resistor, and the second voltage-stabilizing diode is connected to both ends of the second resistor; wherein the control end of the first LDMOS tube is used to access a first pulse signal, and the control end of the second LDMOS tube is used to access a second pulse signal, and the rising edge of the first pulse signal is different from the rising edge of the second pulse signal.

6. The high-voltage level shift circuit with self-noise blocking according to claim 5, characterized in that: When the first pulse signal is at a low level, the second pulse signal is at a high level or a low level; when the first pulse signal is at a high level, the second pulse signal is at a low level.

7. A noise self-blocking method, characterized in that: Applicable to the high-voltage level shift circuit with self-noise blocking according to any one of claims 1 to 6, the self-noise blocking method comprises the following steps: When the high-voltage level shift module is affected by common-mode noise, the high-voltage level shift module outputs a first low-level signal and a second low-level signal to the operation module respectively; After using the operation module to operate the first low-level signal and the second low-level signal, a third low-level signal is output to the first noise self-blocking module and the second noise self-blocking module for blocking; The third low level signal is used to control the first noise self-blocking module and the second noise self-blocking module to block common mode noise signals.

8. A high voltage gate drive circuit, characterized in that: It comprises a filtering circuit, an RS latch circuit, an output driving circuit and a high-voltage level shift circuit with self-noise blocking as claimed in any one of claims 1 to 6; The noise self-blocking high-voltage level shift circuit, the filter circuit, the RS latch circuit, and the output drive circuit are electrically connected in sequence.

9. The high voltage gate drive circuit according to claim 8, characterized in that: The noise self-blocking high-voltage level shift circuit is electrically connected to a pulse generating circuit and is used to access a first pulse signal and a second pulse signal generated by the pulse generating circuit, wherein a rising edge of the first pulse signal is different from a rising edge of the second pulse signal.

10. The high voltage gate drive circuit according to claim 9, characterized in that: When the noise self-blocking high-voltage level shift circuit is affected by common-mode noise, the noise self-blocking high-voltage level shift circuit outputs two low-level signals to the filtering circuit. After filtering, the filtering circuit sends the filtered signal to the RS latch circuit, and the output signal of the RS latch circuit maintains the original transmission state.

Images