Clock signal quadrature phase error calibration device and method and chip

Abstract

The embodiment of the invention discloses a clock signal quadrature phase error calibration device, a clock signal quadrature phase error calibration method and a chip, relates to the technical field of clock circuits, and facilitates calibration of clock signal quadrature phase errors. The apparatus comprises: a DLL loop configured to generate a plurality of sets of quadrature phase clock signals; the phase error detection module is used for comparing phase differences of two adjacent groups of orthogonal phase clock signals and outputting phase error information; the phase calibration module comprises a delay link and a digital state machine, the delay link is located in the DLL loop and comprises a plurality of cascaded delay units, a first pin of the digital state machine is connected with the phase error detection module, and a second pin of the digital state machine is connected with the DLL loop. And a second pin of the digital state machine is connected with each delay unit of the delay link and is configured to control at least one delay unit in the delay link according to the phase error information so as to calibrate the phase error of the quadrature phase clock signal. The method is suitable for application scenes such as clock signal transmission and control.

Description

Technical Field

[0001] The present invention relates to the technical field of clock circuits, and in particular to a clock signal quadrature phase error calibration device, method and chip. Background Art

[0002] In modern digital circuit design, multi-phase clock signals are increasingly used, especially in high-performance and high-frequency systems. These systems usually rely on technologies such as phase-locked loops (PLLs) or delay-locked loops (DLLs) to generate orthogonal phase clock signals (same frequency, 90-degree phase difference) to achieve data transmission and processing. However, due to factors such as process deviations and mismatches in physical implementation, phase errors will occur between the generated multi-phase signals, and the ideal 90-degree phase shift (also called phase difference) is often not achieved. This non-ideal factor may affect the timing stability of the system in high-speed signal transmission. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a clock signal quadrature phase error calibration device, method and chip, which are convenient for calibrating the clock signal quadrature phase error.

[0004] In a first aspect, an embodiment of the present invention provides a clock signal quadrature phase error calibration device, the device comprising: a DLL (Delay Lock Loop) loop, configured to generate a plurality of groups of quadrature phase clock signals; A phase error detection module, used to compare the phase difference between two adjacent groups of orthogonal phase clock signals and output phase error information; The phase calibration module comprises: a delay link and a digital state machine, wherein the delay link is located inside the DLL loop, the delay link comprises a plurality of cascaded delay units, a first pin of the digital state machine is connected to the phase error detection module, a second pin of the digital state machine is connected to each delay unit of the delay link, and is configured to control at least one delay unit in the delay link according to the phase error information to calibrate the phase error of the orthogonal phase clock signal.

[0005] According to an embodiment of the present invention, the phase error detection module includes: a phase error detector and a phase error comparator connected to the phase error detector; The phase error detector is configured to monitor the phase relationship between the input quadrature phase clock signals and output phase difference information of each group of quadrature phase clock signals; The phase error comparator is configured to generate a logic value representing the phase error information of two adjacent groups of orthogonal phase clock signals according to the comparison of the phase difference information of two adjacent groups; The first pin of the digital state machine is connected to the phase error comparator in the phase error detection module, and is specifically configured to control at least one delay unit in the delay link according to the logic value to calibrate the phase error of the orthogonal phase clock signal.

[0006] According to an embodiment of the present invention, the phase error detector comprises: a phase skew generation module, a phase skew selection module and a clock control switch connected in sequence; The phase skew generation module is configured to receive and output the multiple groups of quadrature phase clock signals; the multiple groups of quadrature phase clock signals include: a first group of quadrature phase clock signals, a second group of quadrature phase clock signals, a third group of quadrature phase clock signals and a fourth group of quadrature phase clock signals; The phase skew selection module is configured to select two adjacent groups of orthogonal phase clock signals and output them via a low-pass filter; The clock control switch is configured to control the state of the switch to selectively conduct according to the input selection signal, and output the selected two adjacent groups of orthogonal phase clock signals to the phase error comparator in a predetermined phase error comparison order.

[0007] According to an embodiment of the present invention, the predetermined phase error comparison order is: the first group of orthogonal phase clock signals are compared with the second group of orthogonal phase clock signals, the third group of orthogonal phase clock signals are compared with the fourth group of orthogonal phase clock signals, the second group of orthogonal phase clock signals are compared with the third group of orthogonal phase clock signals, and the fourth group of orthogonal phase clock signals are compared with the first group of orthogonal phase clock signals.

[0008] According to an embodiment of the present invention, the order in which the first group of quadrature phase clock signals are compared with the second group of quadrature phase clock signals and the order in which the third group of quadrature phase clock signals are compared with the fourth group of quadrature phase clock signals can be interchanged; The order of comparing the second group of quadrature phase clock signals with the third group of quadrature phase clock signals and the order of comparing the fourth group of quadrature phase clock signals with the first group of quadrature phase clock signals can be interchanged; The first group of orthogonal phase clock signals are compared with the second group of orthogonal phase clock signals and the third group of orthogonal phase clock signals are compared with the fourth group of orthogonal phase clock signals, and are overall prior to or after the second group of orthogonal phase clock signals are compared with the third group of orthogonal phase clock signals and the fourth group of orthogonal phase clock signals are compared with the first group of orthogonal phase clock signals.

[0009] According to an embodiment of the present invention, the phase error comparator includes an automatic zeroing comparator and a state holder. The automatic zeroing comparator is configured to compare the output voltage information of the orthogonal phase clock signals of two adjacent groups and output the comparison result to the state holder; The state holder is configured to temporarily hold and output the comparison result when no input signal is switched; The digital state machine controls the corresponding delay unit in the delay link according to the comparison result, and controls the respective phase differences of the two adjacent groups of orthogonal phase clock signals until the phase error of the two adjacent groups of orthogonal phase clock signals reaches the expected value.

[0010] In a second aspect, the present invention also provides a clock signal quadrature phase error calibration method, the method comprising: generating a plurality of sets of quadrature phase clock signals; Compare the phase differences of two adjacent groups of quadrature-phase clock signals and output phase error information; At least one delay unit in a delay link is controlled according to the phase error information to calibrate the phase error of the quadrature phase clock signal.

[0011] According to an embodiment of the present invention, the method of comparing the phase difference between two adjacent groups of orthogonal phase clock signals and outputting phase error information includes: monitoring the phase relationship between the input orthogonal phase clock signals and outputting phase difference information of each group of orthogonal phase clock signals; comparing the phase difference information of two adjacent groups and generating a logic value representing the phase error information of two adjacent groups of orthogonal phase clock signals; and controlling at least one delay unit in the delay link according to the logic value to calibrate the phase error of the orthogonal phase clock signal.

[0012] According to an embodiment of the present invention, the outputting of phase error information based on the comparison of the phase difference between two adjacent groups of orthogonal phase clock signals includes: receiving and outputting the multiple groups of orthogonal phase clock signals; the multiple groups of orthogonal phase clock signals include: a first group of orthogonal phase clock signals, a second group of orthogonal phase clock signals, a third group of orthogonal phase clock signals and a fourth group of orthogonal phase clock signals; selecting two adjacent groups of orthogonal phase clock signals and outputting them through a low-pass filter; according to an input selection signal, controlling the state of the switch to selectively turn on, and outputting the selected two adjacent groups of orthogonal phase clock signals to the phase error comparator in a predetermined phase error comparison order.

[0013] According to an embodiment of the present invention, the predetermined phase error comparison order is: the first group of quadrature phase clock signals are compared with the second group of quadrature phase clock signals, the third group of quadrature phase clock signals are compared with the fourth group of quadrature phase clock signals, the second group of quadrature phase clock signals are compared with the third group of quadrature phase clock signals, and the fourth group of quadrature phase clock signals are compared with the first group of quadrature phase clock signals; wherein the order of comparing the first group of quadrature phase clock signals with the second group of quadrature phase clock signals and the order of comparing the third group of quadrature phase clock signals with the fourth group of quadrature phase clock signals are interchangeable; the order of comparing the second group of quadrature phase clock signals with the third group of quadrature phase clock signals and the order of comparing the fourth group of quadrature phase clock signals with the first group of quadrature phase clock signals are interchangeable; the first group of quadrature phase clock signals are compared with the second group of quadrature phase clock signals and the third group of quadrature phase clock signals are compared with the fourth group of quadrature phase clock signals, which are overall prior to or after the second group of quadrature phase clock signals are compared with the third group of quadrature phase clock signals and the fourth group of quadrature phase clock signals are compared with the first group of quadrature phase clock signals.

[0014] According to one embodiment of the present invention, after outputting two adjacent groups of selected orthogonal phase clock signals to the phase error comparator in a predetermined phase error comparison order, the method further includes: comparing the output voltage information of the two adjacent groups of orthogonal phase clock signals, and outputting the comparison result to the state holder, so that the state holder temporarily holds and outputs the comparison result when the input signal is not switched; controlling at least one delay unit in the delay link according to the phase error information to calibrate the phase error of the orthogonal phase clock signal includes: controlling the corresponding delay unit in the delay link according to the comparison result, and controlling the respective phase differences of the two adjacent groups of orthogonal phase clock signals until the phase error of the two adjacent groups of orthogonal phase clock signals reaches a desired value.

[0015] The clock signal orthogonal phase error calibration device, method and chip provided by the embodiments of the present invention set a delay link inside the DLL loop, and the DLL loop and the phase calibration module share the delay link. There is no need to introduce an additional phase calibration loop or mechanism. Under the coordinated cooperation of the digital state machine, the orthogonal phase clock signal is calibrated by controlling the delay link inside the DLL loop, which facilitates the calibration of the clock signal orthogonal phase error in a low-power form. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 This is a schematic block diagram of the structure of an embodiment of a clock signal quadrature phase error calibration device of the present invention; Figure 2 This is a schematic block diagram of the structure of an embodiment of a clock signal quadrature phase error calibration device of the present invention; Figure 3 This is a schematic block diagram of an embodiment of the clock signal quadrature phase error calibration device of the present invention, mainly showing the circuit structure of a phase error detection module; Figure 4 A phase timing diagram of four sets of orthogonal phase clock signals generated for calibration in one embodiment of the present invention; Figure 5 In one embodiment of the present invention, Figure 4 A schematic diagram of the sequence of steps for comparing and calibrating the phases of four sets of orthogonal phase clock signals generated in FIG. Figure 6 A schematic diagram of a phase shift and duty cycle timing in which the first group of orthogonal phase clock signals is greater than the second group of orthogonal phase clock signals (for example, the phase shift between phase0 and phase9 is greater than the phase shift between phase90 and phase180) in step 1 in an embodiment of the present invention; Figure 7 It is a schematic diagram of the principle of alternately turning on the clock control switch in step 1 when the first group of quadrature-phase clock signals is greater than the second group of quadrature-phase clock signals in one embodiment of the present invention; Figure 8 The phase shift and duty cycle timing diagram for executing step 1 in which the first set of orthogonal phase clock signals is smaller than the second set of orthogonal phase clock signals (for example, the phase shift between phase 0 and phase 9 is smaller than the phase shift between phase 90 and phase 180); Fig. 9 It is a schematic diagram of the principle of alternately turning on the clock control switch in step 1 when the first group of quadrature-phase clock signals is smaller than the second group of quadrature-phase clock signals in one embodiment of the present invention; Fig.10 The figure is a flow chart of a method for calibrating a clock signal quadrature phase error according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0019] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] In the related art, a phase-locked loop (PLL) is usually used to generate an orthogonal phase clock signal, and an XOR operation is performed through current mode logic (CML), and then the output differential result is sent to a low-pass filter and a differential comparator for phase error comparison. However, due to the offset of the current mode logic and the comparator itself, additional errors are introduced in the phase calibration process. Therefore, the existing solution needs to introduce an additional calibration loop to calibrate the XOR current mode logic and the comparator to improve the matching accuracy between the orthogonal phases.

[0021] In addition, although the phase interpolator (PI) introduced in the orthogonal clock loop can effectively adjust the phase error, it also significantly increases the power consumption of the system, which is contrary to the low power consumption requirements of modern electronic systems.

[0022] To this end, the clock signal orthogonal phase error calibration device provided in the embodiment of the present application optimizes the circuit design and control strategy, adjusts the delay link in the orthogonal phase generator, cooperates with the digital state machine to form a phase calibration module, and places some core circuit units of the phase calibration module inside the orthogonal phase generator, so as to facilitate the calibration of the orthogonal phase error of the clock signal in a low-power form.

[0023] See also Figure 1 As shown, the embodiment of the present application provides a clock signal quadrature phase error calibration device 100, which can effectively generate and calibrate a quadrature phase clock signal to ensure signal integrity and system performance in various application scenarios, and is suitable for application scenarios such as clock signal transmission and control. The device 100 includes: The delay lock loop (DLL) circuit 110 is configured to generate a plurality of sets of quadrature phase clock signals. Figure 2Specifically, the DLL loop includes: a delay line 111, a phase detector 112, a digital filter 113, a reference voltage generating module 114 and a voltage adjusting module 115, wherein the output voltage value of the voltage adjusting module is continuously adjusted through the feedback mechanism formed by the above components inside the DLL loop to ensure that the output clock signal and the reference signal have a phase difference of one clock cycle, thereby generating an orthogonal phase clock signal. Among them, a set of orthogonal phase clock signals is composed of two clock signals, and the phase difference or phase shift angle between the two clock signals is 90°. For a 360° clock cycle, the constructed orthogonal phase clock signals are generally 0° / 90° / 180° / 270° / 360° clock signals.

[0024] Of course, since the orthogonal phase clock signal is affected by the process and physical implementation, the generated orthogonal clocks are not an ideal 90-degree phase shift (phase difference), so it is necessary to calibrate the error between the orthogonal clock phase signals.

[0025] The phase error detection module 120 is used to compare the phase difference between two adjacent groups of quadrature phase clock signals and output phase error information. For example, the clock signals of 0° and 90° constitute the first group of quadrature phase clock signals, and the clock signals of 90° and 180° constitute the second group of quadrature phase clock signals. The phase difference between the first group of quadrature phase clock signals and the second group of quadrature phase clock signals are compared to output phase error information. In an ideal state, the phase difference between the two is equal, that is, the error is 0°, but based on the reasons described above, there is generally a phase error between the two.

[0026] The phase calibration module 130 includes a delay link 111 and a finite state machine (FSM) 131. The delay link 111 is located inside the DLL loop, and the delay link 111 includes a plurality of cascaded delay units; a first pin of the digital state machine 131 is connected to the phase error detection module 120, and a second pin of the digital state machine 131 is connected to each delay unit of the delay link 111. The digital state machine 131 is configured to control at least one delay unit in the delay link 111 according to the phase error information to calibrate the phase error of the orthogonal phase clock signal.

[0027] In this embodiment, by setting the delay link 111 inside the DLL loop 110 and sharing the delay link 111 with the phase calibration module 130, there is no need to introduce an additional phase calibration loop or mechanism. Under the coordination of the digital state machine 131, the orthogonal phase clock signal is calibrated by controlling the delay link 111 inside the DLL loop 110, which facilitates the calibration of the orthogonal phase error of the clock signal in a low-power form.

[0028] refer to Figure 2 Specifically, when the DLL loop 110 starts to work, the output initial voltage of the reference voltage generating module 114 is set to a higher value, so that the total delay of the delay link 111 is less than one input clock cycle, that is, the delay difference between the clock signals p360 and p0 is less than one input clock clk in cycle to prevent the DLL loop 110 from entering the multi-harmonic locking range. Wherein, one input clock cycle = 1 / input clock frequency.

[0029] Input clock clk in The delay link 111 generates the delay0 / delay90 / delay180 / delay270 / dealy360 clock signals, and these signals are sent to the duty cycle calibration module 116. The output clock signals p0 and p360 are sent to the phase detector 112. The phase detector 112 detects that the phase of p360 lags behind the phase of p0, and outputs the lag late signal equal to 1. After the late signal passes through the digital filter 113, a control code ctrl code is generated to increase the current source cur source current or increase the adjustment resistor R, so that the reference voltage generation module 114 outputs the voltage vreg ref Decrease, vreg ref As the input terminal of the DLL voltage adjustment module 115, vreg ref The output voltage VDD of the DLL voltage adjustment module 115 is reduced. DLL As it decreases, the total delay of the DLL delay link 111 increases, which reduces the phase difference between the clock signals p360 and p0. This process is repeated and the DLL link delay increases until the phase difference between p360 and p0 is greater than an input clk in In the clock cycle, the phase detector 112 detects that the phase p360 is ahead of the phase p0, and outputs the early signal equal to 0. After the early signal passes through the digital filter 113, a control code ctrl code is generated to reduce the current source cur source current or reduce the adjustment resistor R, so that the reference voltage generation module 114 outputs the voltage vreg ref Increase, vreg refAs the input of the DLL voltage drive adjustment module, vreg ref Increase, DLL voltage drive adjustment module output voltage VDD DLL As it increases, the total delay of the DLL delay link 111 is reduced. The amount of total delay reduction and increase depends on the voltage adjustment accuracy of the voltage adjustment module 115. The higher the accuracy, the smaller the delay amount of each step adjustment. The above process is repeated over and over again to achieve dynamic stability of the DLL loop 110, so as to output multiple sets of stable orthogonal phase clock signals.

[0030] After the DLL loop 110 is stable, it outputs multiple sets of orthogonal phase clock signals delay0 / delay90 / delay180 / delay270, passes through the duty cycle adjustment module 116, and then passes through the multi-stage clock driver (Clock buffer) 140 to be sent to the remote application end to generate phase0 / phase90 / phase180 / phase270 orthogonal signals for use by the transmitter or receiver.

[0031] Since the orthogonal phase clock signal is affected by the process and physical implementation, the phase shift between the orthogonal clocks is not ideally 90 degrees, and the duty cycle also deviates from the ideal value of 50%. Therefore, the duty cycle and orthogonal phase error need to be calibrated before normal application.

[0032] Among them, in order to achieve orthogonal phase calibration, the duty cycle needs to be calibrated before the phase calibration. The duty cycle calibration method can adopt the traditional calibration method, that is, the output clock is compared with half of the power supply voltage after passing through the low-pass filter, and the comparison result is used to adjust the ratio of PMOS or NMOS in the drive link, and finally achieve 50% duty cycle output. Since the calibration of the duty cycle is not the focus of this application, it will not be described in detail.

[0033] After the phase0 / phase90 / phase180 / phase270 orthogonal phase clock signals are generated, they are sent to the phase error detection module 120. The phase error detection module 120 compares the input phase difference information and outputs phase error information. The phase error information is sent to the digital state machine 131. The digital state machine 131 outputs a control signal to control the driving strength of the delay cell delay cell1 / delay cell2 / delay cell3 / delay cell4 in the delay link 111 in the DLL or the load connected to the output end of the delay cell to achieve the purpose of phase calibration.

[0034] See also Figure 3As shown, in some embodiments, the phase error detection module 120 includes: a phase error detector (Phase error detector) 121 and a phase error comparator (Phase error comparator) 122 connected to the phase error detector.

[0035] The phase error detector 121 is configured to monitor the phase relationship between the input orthogonal phase clock signals and output the phase difference information of each group of orthogonal phase clock signals; specifically, the phase error detector calculates the phase difference between each group of signals by sampling the input signal and analyzing its waveform, and passes the result to the phase error comparator.

[0036] The phase error comparator 122 is configured to compare the phase difference information of two adjacent groups and generate a logic value representing the phase error information of two adjacent groups of orthogonal phase clock signals; the logic value is used to indicate whether the delay link 111 needs to be adjusted to calibrate the phase of the clock signal.

[0037] The first pin of the digital state machine 131 is connected to the phase error comparator 122 in the phase error detection module 120, and is specifically configured to control at least one delay unit in the delay link 111 according to the logic value to calibrate the phase error of the orthogonal phase clock signal. The first pin of the digital state machine 131 is connected to the phase error comparator 122, and the second pin is connected to each delay unit in the delay link 111, and each delay unit is configured to independently adjust its delay time, thereby realizing the calibration of different orthogonal phase clock signals.

[0038] Specifically, after two groups of orthogonal phase clock signals phase0 / phase90 / phase180 / phase270 are generated, they are sent to the phase error detector, and the phase error detector outputs VIP and VIN signals as inputs of the phase error comparator 122, which are compared according to the input phase difference information and output phase error information. Specifically, a comparison is performed based on the input phase difference to be compared to determine whether the phases of two adjacent groups of orthogonal phase clock signals are equal, and the phase error information is sent to the digital state machine 131. The digital state machine 131 outputs a control signal to control the driving strength of the delay cells delaycell1 / delay cell2 / delay cell3 / delay cell4 in the delay link 111 in the DLL or the load connected to the output end of the delay cell, so as to achieve the purpose of phase calibration.

[0039] It can be understood that the comparator represents the phase error information by outputting a logic value of 0 or 1, and the digital state machine 131 controls at least one delay unit according to the logic value from the comparator to achieve dynamic calibration of the orthogonal phase clock signal.

[0040] In specific implementation, when the digital state machine 131 receives a logical value indicating the existence of a phase error, it sends a control signal to activate the corresponding delay unit, and adjusts the phase of the output signal by increasing or decreasing its delay time, thereby eliminating the error, thereby ensuring that the clock signal output to the application end always maintains high precision under various working conditions.

[0041] Continue to view Figure 3 and Figure 4 As shown, in some embodiments, the phase error detector 121 includes: a phase skew generator module 1211, a phase skew select module 1212 and a clock control switch 1213 which are connected in sequence.

[0042] The phase skew generating module 1211 is configured to receive and output the multiple groups of orthogonal phase clock signals; the multiple groups of orthogonal phase clock signals include: a first group of orthogonal phase clock signals, a second group of orthogonal phase clock signals, a third group of orthogonal phase clock signals and a fourth group of orthogonal phase clock signals.

[0043] Exemplarily, the first group of quadrature phase clock signals consists of phase0 and phase90, the second group of quadrature phase clock signals consists of phase90 and phase180, the third group of quadrature phase clock signals consists of phase180 and phase270, and the fourth group of quadrature phase clock signals consists of phase270 and phase0.

[0044] A phase skew selection module 1212 is configured to select two adjacent groups of orthogonal phase clock signals and output them via a low-pass filter 1214; The clock control switch is configured to control the state of the switch to selectively conduct according to the input selection signal, and output the selected two adjacent groups of orthogonal phase clock signals to the phase error comparator 122 according to a predetermined phase error comparison sequence.

[0045] The main function of the phase skew generation module 1211 is to receive and output multiple groups of orthogonal phase clock signals. The module includes multiple input ports, which respectively receive the first group, the second group, the third group and the fourth group of orthogonal phase clock signals generated by the DLL loop 110. The phase relationship of each group of signals is 90 degrees, ensuring that they are in an orthogonal state on the time axis.

[0046] Specifically, the phase skew generation module 1211 includes a clock signal generation circuit, which can generate the required multiple sets of orthogonal phase skew clock signals according to the input reference clock signal. Ideally, the duty cycle of each set of orthogonal phase skew clock signals is 25%, and they are sent to the subsequent circuit for processing after low-pass filtering.

[0047] The phase skew selection module 1212 is responsible for selecting two adjacent groups of orthogonal phase skew clock signals and outputting them through the low-pass filter 1214. The phase skew selection module 1212 includes a plurality of selection switches, allowing the system to select two specific groups of orthogonal phase clock signals for output for comparison as needed.

[0048] In a specific implementation, the phase skew selection module 1212 adopts a multiplexer (MUX) structure, and can select any pair of adjacent orthogonal phase skew clock signals between the first group and the second group, the second group and the third group, or the third group and the fourth group according to the control signal. The selected signal is processed by the low-pass filter 1214 and sent to the subsequent comparator for processing.

[0049] The clock control switch is used to control the switch state according to the input selection signal to selectively conduct and output the selected two adjacent groups of orthogonal phase clock skew signals to the phase error comparator 122 in a predetermined phase error comparison order. The switch is driven by a clock control circuit and can quickly respond to the selection instruction from the system.

[0050] In the specific implementation, the clock control switch is implemented with a transmission gate structure. After receiving the control signal from the phase skew selection module 1212, the clock control switch will quickly switch states and send the selected two sets of orthogonal phase clock skew signals to the phase error comparator 122 for subsequent processing.

[0051] like Figure 3 and Figure 4 As shown, in some practical applications, when the system is started, the phase skew generation module 1211 first generates multiple groups of orthogonal phase skew clock signals, such as Figure 4 As shown, the phase skew selection module 1212 outputs the phase skew selection module 1212. The system issues a selection instruction through the control logic as needed to activate the corresponding multiplexer, thereby selecting two groups of orthogonal phase clock signals to be compared.

[0052] Subsequently, these selected signals are processed by low-pass filter 1214 and then introduced into phase error comparator 122 for comparison through clock control switch. The comparator will analyze the phase relationship between the two sets of signals and output corresponding error information for subsequent phase calibration module 130 to use.

[0053] In this embodiment, through the above-mentioned structure and workflow, an efficient, flexible and reliable phase error detection scheme is provided, which cooperates with the phase calibration module 130 to monitor and calibrate multiple groups of orthogonal phase clock signals in real time, which is beneficial to improving the system's response capability to the clock signal accuracy requirements and enhancing the overall system performance. It can be widely used in various high-precision electronic equipment and communication systems.

[0054] See also Figure 5 As shown, in some embodiments, the predetermined phase error comparison sequence is: step1, step2, step3 to step4, specifically: the first group of orthogonal phase clock signals are compared with the second group of orthogonal phase clock signals, the third group of orthogonal phase clock signals are compared with the fourth group of orthogonal phase clock signals, the second group of orthogonal phase clock signals are compared with the third group of orthogonal phase clock signals, and the fourth group of orthogonal phase clock signals are compared with the first group of orthogonal phase clock signals.

[0055] Among them, the order in which the first group of orthogonal phase clock signals are compared with the second group of orthogonal phase clock signals and the order in which the third group of orthogonal phase clock signals are compared with the fourth group of orthogonal phase clock signals can be interchanged; the order in which the second group of orthogonal phase clock signals are compared with the third group of orthogonal phase clock signals and the order in which the fourth group of orthogonal phase clock signals are compared with the first group of orthogonal phase clock signals can be interchanged; the first group of orthogonal phase clock signals are compared with the second group of orthogonal phase clock signals and the third group of orthogonal phase clock signals are compared with the fourth group of orthogonal phase clock signals, which are overall before or after the second group of orthogonal phase clock signals are compared with the third group of orthogonal phase clock signals and the fourth group of orthogonal phase clock signals are compared with the first group of orthogonal phase clock signals.

[0056] For example, the comparison order may be Figure 4 The process shown is: step1, step2, step3 to step 4. It can also be the following process: 1. step1, step2, step4 to step3, or, 2. step2, step1, step3 to step4, or, 3. step2, step1, step4 to step3, or, 4. step3, step4, step1 to step2, or, 5. step3, step4, step2, step1, or, 6. step4, step3, step1 to step2, or, 7. step4, step3, step2 to step1.

[0057] High-precision clock systems require precise control of the phase relationship of orthogonal phase clock signals. However, due to factors such as device mismatch, the actually generated orthogonal phase clock signals often have phase errors, which will affect the overall performance of the system.

[0058] See also Figure 3 As shown, in some embodiments, the phase error comparator (Phase error comparator) 122 includes an auto-zero comparator 1221 (Auto-zero comparator) and a state holder (Latch) 1222 .

[0059] The automatic zeroing comparator 1221 is configured to compare the output voltage information of the orthogonal phase clock signals of two adjacent groups and output the comparison result to the state holder 1222; the state holder 1222 is configured to temporarily hold and output the comparison result when the input signal is not switched; the digital state machine 131 controls the corresponding delay unit in the delay link 111 according to the comparison result, and controls the respective phase difference of the orthogonal phase clock signals of the two adjacent groups until the phase error of the orthogonal phase clock signals of the two adjacent groups reaches the expected value.

[0060] In this embodiment, the orthogonal phase clock signal is a square wave, and its phase difference represents the phase error that needs to be corrected. The automatic zeroing comparator 1221 determines whether the phase difference between the two sets of signals is leading or lagging by comparing these voltage information. If it is leading, the logic value of the output Early signal is 1, and the result is output to the state holder 1222 in the form of a digital signal. The state holder 1222 plays a buffering role. When there is no new comparison result input, the previous comparison result is maintained to prevent the influence of transient interference and ensure the stability of the output.

[0061] The digital state machine 131 controls the delay unit in the delay link 111 according to the comparison result output by the state holder 1222. The delay unit may be a capacitor array or a programmable delay device. The digital state machine 131 selectively adjusts the delay value of the corresponding delay unit in the delay link 111 according to the magnitude and direction of the phase error, thereby changing the phase of one of the orthogonal phase clock signals, thereby being able to quickly and accurately correct the phase error of the orthogonal phase clock signal.

[0062] It should be noted that the phase adjustment process is a closed-loop control process that is continuously iterated until the phase error between two adjacent sets of orthogonal phase clock signals reaches a preset expected value. This expected value can be set according to system requirements, for example, requiring the two sets of signals to accurately maintain a phase difference of 90°, or a range of values ​​around 90°.

[0063] In a specific implementation, the automatic zeroing comparator 1221 can be implemented using a high-speed comparator circuit. The state holder 1222 can be implemented using a simple latch or a trigger. The digital state machine 131 can be implemented using a microcontroller. The delay link 111 can use various programmable delay devices, and the accuracy of the delay link 111 of the selected device affects the final phase correction accuracy to a certain extent.

[0064] For example, assuming that the expected phase difference is 90 degrees. If the automatic zeroing comparator 1221 detects that one group of signals leads another group of signals, the state machine will control the corresponding delay unit of the delay link 111 according to the preset control algorithm to reduce the phase difference. This process will continue until the phase difference is close to 90 degrees.

[0065] In order to help understand the technical solution provided by the embodiment of the present invention, the following Figure 3 ,by Figure 4 The process shown is as follows: step 1, step 2, step 3 to step 4, which details the four-step phase calibration scheme in the present application, specifically step 1, calibrating the phases of two groups of orthogonal phase clock signals, phase0 / phase90 and phase180 / phase270, step 2, calibrating the phases of two groups of orthogonal phase clock signals, phase180 / phase270 and phase270 / phase0, step 3, calibrating the phases of two groups of orthogonal phase clock signals, phase90 / phase180 and phase180 / phase270, and step 4, calibrating the phases of two groups of orthogonal phase clock signals, phase270 / phase0 and phase0 / phase90.

[0066] Two adjacent phases of phase0 / phase90 / phase180 / phase270 form a group of orthogonal phase clock signals that are input into the phase skew generation module 1211 to generate four groups of orthogonal phase clock signals: the output of phase0 and phase90 is clk1, the output of phase90 and phase180 is clk2, the output of phase180 and phase270 is clk3, and the output of phase270 and phase0 is clk4. Ideally, the duty cycle of the outputs clk1, clk2, clk3 and clk4 is an ideal 25%.

[0067] clk1, clk2, clk3 and clk4 are sent to the phase skew selection module 1212. The phase selection module first enters the step1 stage according to the above-mentioned comparison and calibration sequence, and sends clk1, clk2, clk2 and clk1 to the selection switches Mux0, Mux1, Mux2 and Mux3 through the selection signal step sel. Mux0, Mux1, Mux2 and Mux3 output clkp0, clkn0, clkp1 and clkn1 respectively and send them to the low-pass filter 1214. V0, V1, V2 and V3 are output through the low-pass filter 1214, and then VIP0 and VIN0 are output through the non-overlapping clock control switches SW0 / SW1 and SW2 / SW3.

[0068] In step 1, compare whether the phase shift from phase 0 to phase 90 is equal to the phase shift from phase 90 to phase 180. If the phase shift from phase 0 to phase 90 is greater than the phase shift from phase 90 to phase 180, Figure 6 As shown, the duty cycle of clk1 is less than the duty cycle of clk2. After passing through the low-pass filter 1214, the output voltage V0 is VDD / 4-deltav (also represented by "δv" in this article and the figure), V1 is VDD / 4+deltav, V2 is VDD / 4+deltav, and V3 is VDD / 4-deltav.

[0069] like Figure 7 As shown, because the clock control switches SW0 / SW1 and SW2 / SW3 are non-overlapping clocks, that is, SW0 / SW1 and SW2 / SW3 do not have a simultaneous on-time interval, SW2 / SW3 will only be turned on after SW0 / SW1 is completely turned off; vice versa, SW0 / SW1 will only be turned on after SW2 / SW3 is completely turned off.

[0070] During the period when the non-overlapping clock switch signal clock reset is 1, SW0 / SW1 and SW4 / SW5 are turned on at the same time, and SW2 / SW3 is turned off. At this time, the VIP0 voltage is VDD / 4-δv, and the VIN0 voltage is VDD / 4+δv; at this time, the output terminal VOUTP / VOUTN of the automatic zeroing comparator 1221 is connected to the input terminal VIP / VIN, so that the voltages of the differential input terminals of the comparator are equal, both equal to Volcm+offset / 2, where Volcm represents the common mode voltage of the differential input, offset is the offset voltage of the comparator, and δv is the voltage offset caused by asymmetry or noise in the circuit. Specifically, δv represents the small offset caused by asymmetry or noise in the actual circuit on the basis that the VIP0 and VIN0 voltages should be VDD / 4 in an ideal situation (that is, when there is no offset or noise). In the actual circuit, due to factors such as manufacturing process, temperature changes, and power supply voltage fluctuations, the voltage may have a small offset. These offsets will cause the voltages of VIP0 and VIN0 to be not completely equal, thereby introducing δv. By considering δv, the actual working state of the circuit can be described more accurately, and corresponding corrections and optimizations can be made during the design and testing process. The voltage difference between capacitors C0 and C1 is: VC0 = Volcm+offset / 2-(VDD / 4-δv); VC1 = Volcm+offset / 2-(VDD / 4+δv).

[0071] At this time, the state holder 1222 (Latch) holds the result 1 of the previous phase error comparator 122 output. When the non-overlapping clock signal clock reset becomes 0 and the clock latch becomes 1, the VIP0 voltage switches from VDD / 4-δv to VDD / 4+δv, and the VIN0 voltage switches from VDD / 4+δv to VDD / 4-δv. Because the voltages across capacitors C0 and C1 cannot change suddenly, the voltages of VIP and VIN are: VIP = Volcm + offset / 2 + 2 × δv; VIN= Volcm+offset / 2-2×δv; At this time, the comparator is in the comparison stage. Since VIP is greater than VIN, the output result is 1. Latch sends the output result of the phase error comparator 122 to the digital state machine 131. The digital state machine 131 outputs a load reduction of the delay cell 1 in the DLL loop 110, so that the phase difference between phase 0 and phase 90 is reduced, and the phase difference between phase 90 and phase 180 is increased.

[0072] In step 1, if the phase shift between phase 0 and phase 9 is smaller than the phase shift between phase 90 and phase 180, such as Figure 8 As shown, the duty cycle of clk1 is greater than the duty cycle of clk2. After passing through the low-pass filter 1214, the output voltage V0 is VDD / 4+deltav, V1 is VDD / 4-deltav, V2 is VDD / 4-deltav, and V3 is VDD / 4+deltav.

[0073] When the non-overlapping clock signal clock reset is 1, SW0 / SW1 and SW4 / SW5 are turned on at the same time, and SW2 / SW3 is turned off. At this time, the voltage information of VIP0 / VIN0 and VIP / VIN is as follows: Figure 8 As shown, the VIP0 voltage is VDD / 4+δv, and the VIN0 voltage is VDD / 4-δv; at this time, the output terminal VOUTP / VOUTN of the automatic zeroing comparator 1221 is connected to the input terminal VIP / VIN, and the differential input terminal voltage is equal, which is equal to Volcm+offset / 2. The voltage difference between the two ends of the capacitors C0 and C1 is: VC0 = Volcm+offset / 2-(VDD / 4+δv); VC1 = Volcm+offset / 2-(VDD / 4-δv).

[0074] At this time, the state holder 1222 holds the result of the previous comparator output 0. When the non-overlapping clock signal clockreset becomes 0 and the clock latch becomes 1, the VIP0 voltage switches from VDD / 4+δv to VDD / 4-δv, and the VIN0 voltage switches from VDD / 4-δv to VDD / 4+δv. Because the voltages across capacitors C0 and C1 cannot change suddenly, the voltages of VIP and VIN are: VIP = Volcm + offset / 2-2×δv; VIN= Volcm+offset / 2+2×δv.

[0075] At this time, the phase error comparator 122 is in the comparison stage. Since VIP is less than VIN, the output result is 0. The state holder 1222 sends the output result of the phase error comparator 122 to the digital state machine 131. The digital state machine 131 outputs a control signal to increase the load of the delay cell delay cell1 of the DLL loop 110, thereby increasing the phase difference between phase0 and phase90 and reducing the phase difference between phase90 and phase180.

[0076] Through the above process, the load size of the delay cell 1 is continuously adjusted, and finally the phase difference between phase 0 and phase 90 is equal to the phase difference between phase 90 and phase 180, and the calibration of step 1 is completed.

[0077] After the calibration of step 1 is completed, step 2 is entered. At this time, the phase shift from phase 180 to phase 270 is compared with the phase shift from phase 270 to phase 0. If the phase shift from phase 180 to phase 270 is greater than the phase shift from phase 270 to phase 0, the process is consistent with step 1. Then the duty cycle of clk2 is less than the duty cycle of clk3. After passing through the low-pass filter 1214, the output voltage V0 is VDD / 4-deltav, V1 is VDD / 4+deltav, V2 is VDD / 4+deltav, and V3 is VDD / 4-deltav.

[0078] During the period when the non-overlapping clock signal clock reset is 1, SW0 / SW1 and SW4 / SW5 are turned on at the same time, and SW2 / SW3 is turned off. At this time, the VIP0 voltage is VDD / 4-deltav, and the VIN0 voltage is VDD / 4+deltav; the comparator output terminal VOUTP / VOUTN is connected to the input terminal VIP / VIN, so that the voltage of the differential input terminal of the comparator is equal, which is equal to Volcm+offset / 2. The voltage difference between the two ends of capacitors C0 and C1 is: VC0 = Volcm+offset / 2-(VDD / 4-deltav); VC1 = Volcm+offset / 2-(VDD / 4+deltav).

[0079] At this time, the state holder 1222 holds the result 1 of the previous comparator output. When the clock reset signal of the non-overlapping clock becomes 0 and the clock latch becomes 1, the VIP0 voltage switches from VDD / 4-deltav to VDD / 4+deltav, and the VIN0 voltage switches from VDD / 4+deltav to VDD / 4-deltav. Because the voltages across the capacitors C0 and C1 cannot change suddenly, the voltages of VIP and VIN are: VIP= Volcm+offset / 2+2×deltav; VIN= Volcm+offset / 2-2×deltav.

[0080] At this time, the phase error comparator 122 is in the comparison stage. Since VIP is greater than VIN, the output result is 1. The state holder 1222 sends the output result of the phase error comparator 122 to the digital state machine 131. The digital state machine 131 outputs a load reduction of the DLL delay cell 3, so that the phase difference between phase180 and phase270 is reduced, and the phase difference between phase270 and phase0 is increased.

[0081] In step2, if the phase shift between phase180 and phase270 is smaller than the phase shift between phase270 and phase0, phase180 / phase270 / phase0 is used instead. The process is the same as step1 and will not be described in detail. Then, the duty cycle of clk2 is greater than the duty cycle of clk3. After passing through the low-pass filter 1214, the output voltage V0 is VDD / 4+deltav, V1 is VDD / 4-deltav, V2 is VDD / 4-deltav, and V3 is VDD / 4+deltav.

[0082] When the non-overlapping clock signal clock reset is 1, SW0 / SW1 and SW4 / SW5 are turned on at the same time, and SW2 / SW3 is turned off. At this time, the voltage information of VIP0 / VIN0 and VIP / VIN is as follows: Figure 8 As shown, the VIP0 voltage is VDD / 4+deltav, and the VIN0 voltage is VDD / 4-deltav; at this time, the output terminal VOUTP / VOUTN of the automatic zeroing comparator 1221 is connected to the input terminal VIP / VIN, and the differential input terminal voltage is equal to Volcm+offset / 2. The voltage difference between the capacitors C0 and C1 is: VC0 = Volcm+offset / 2-(VDD / 4+deltav); VC1 = Volcm+offset / 2-(VDD / 4-deltav).

[0083] At this time, the state holder 1222 holds the result of the previous comparator output 0. When the non-overlapping clock signal clock reset becomes 0 and clock_latch becomes 1, the VIP0 voltage switches from VDD / 4+deltav to VDD / 4-deltav, and the VIN0 voltage switches from VDD / 4-deltav to VDD / 4+deltav. Because the voltages across capacitors C0 and C1 cannot change suddenly, the voltages of VIP and VIN are: VIP= Volcm+offset / 2-2×deltav; VIN= Volcm+offset / 2+2×deltav.

[0084] At this time, the phase error comparator 122 is in the comparison stage. Since VIP is less than VIN, the output result is 0. Latch sends the comparator output result to the digital state machine 131. The digital state machine 131 outputs an increase in the load of the delay cell delay cell3 of the DLL loop 110, thereby increasing the phase difference from phase180 to phase270 and reducing the phase difference between phase270 and phase0.

[0085] Through the above process, the load size in delay_cell3 is continuously adjusted, and finally the phase difference between phase180 and phase270 is equal to the phase difference between phase270 and phase0, and the calibration of step2 is completed.

[0086] After step1 and step2 are completed, the phase shift from phase0 to phase90 is equal to the phase shift from phase90 to phase180, and the phase shift from phase180 to phase270 is equal to the phase shift from phase270 to phase0. However, at this time, the phase shift from phase0 to phase90 or the phase shift from phase90 to phase180 may not be equal to the phase shift from phase180 to phase270 or the phase shift from phase270 to phase0. In order to achieve that the phase shift from phase0 to phase90 or the phase shift from phase90 to phase180 is equal to the phase shift from phase180 to phase270 or the phase shift from phase270 to phase0, step3 and step4 need to be continued.

[0087] The process of step 3 and step 4 is consistent with the process of step 1 / step 2 above, and will not be described in detail. The only difference is that the orthogonal phase signals to be compared are different. Step 3 compares the phase shift from phase 90 to phase 180 with the phase shift from phase 180 to phase 270. If the phase shift from phase 90 to phase 180 is greater than the phase shift from phase 180 to phase 270, the digital state machine 131 outputs a load reduction of the delay cell delay_cell2 of the DLL loop 110, so that the phase difference between phase 90 and phase 180 is reduced, and the phase difference between phase 180 and phase 270 is increased; on the contrary, if the phase shift from phase 90 to phase 180 is less than the phase shift from phase 180 to phase 270, the digital state machine 131 outputs an load increase of the delay cell delay cell2 of the DLL loop 110, so that the phase difference between phase 90 and phase 180 is increased, and the phase difference between phase 180 and phase 270 is reduced. Through this process, the load size in delay cell 2 is continuously adjusted, and finally the phase difference between phase 90 and phase 180 is equal to the phase difference between phase 180 and phase 270, and the calibration of step 3 is completed.

[0088] After step 3 is completed, step 4 is performed. The process is consistent with the above step 1 / step 2 / step 3 process. Step 4 compares the phase shift from phase 270 to phase 0 with the phase shift between phase 0 and phase 90. If the phase shift from phase 270 to phase 0 is greater than the phase shift between phase 0 and phase 90, the digital state machine 131 outputs a load reduction of the delay cell delay cell 4 in the DLL loop 110, so that the phase difference between phase 270 and phase 0 is reduced, and the phase difference between phase 0 and phase 90 is increased; on the contrary, if the phase shift from phase 270 to phase 0 is less than the phase shift between phase 0 and phase 90, the digital state machine 131 outputs an increase in the load of the delay cell delay cell 4 in the DLL loop 110, so that the phase difference between phase 270 and phase 0 is increased, and the phase difference between phase 0 and phase 90 is reduced. Through this process, the load size in delay_cell 4 is continuously adjusted, and finally the phase difference between phase 270 and phase 0 is equal to the phase difference between phase 0 and phase 90, and the calibration of step 4 is completed.

[0089] After step 1, step 2, step 3 and step 4 are calibrated, the above four-step calibration process can be repeated to improve the calibration accuracy and reliability. The calibration between the four orthogonal phases of phase 0, phase 90, phase 180 and phase 270 can be achieved. In the above calibration process, the bandwidth of the calibration loop of the phase calibration module 130 is much smaller than the bandwidth of the DLL loop 110 to ensure that the DLL loop 110 is in a stable state at the beginning of each calibration. In addition, after the DLL loop 110 is stable, the digital filter control code can be maintained, the DLL loop 110 can be disconnected, and after a four-step calibration is completed, the delay unit control code of the DLL can be maintained, and then the DLL loop 110 can be opened again, so that the DLL loop 110 can be re-locked to generate the clock signal of the required orthogonal phase, and the high-precision and stable output of the clock signal can be achieved.

[0090] Embodiment 2 Fig.10 FIG. 1 is a flow chart of an embodiment of a method for calibrating a clock signal quadrature phase error according to the present invention; Fig.10 The present invention also provides a clock signal quadrature phase error calibration method according to an embodiment of the present invention, which can be applied to the calibration device described in the first embodiment. The method includes: S210, generating multiple groups of orthogonal phase clock signals; S220, comparing the phase differences of two adjacent groups of orthogonal phase clock signals, and outputting phase error information; S230. Control at least one delay unit in the delay link 111 according to the phase error information to calibrate the phase error of the orthogonal phase clock signal.

[0091] In some specific embodiments, the phase difference between two adjacent groups of orthogonal phase clock signals is compared to output phase error information, including: monitoring the phase relationship between the input orthogonal phase clock signals, and outputting the phase difference information of each group of orthogonal phase clock signals; comparing the phase difference information of two adjacent groups to generate a logic value representing the phase error information of two adjacent groups of orthogonal phase clock signals; and controlling at least one delay unit in the delay link 111 according to the logic value to calibrate the phase error of the orthogonal phase clock signal.

[0092] In some specific embodiments, the outputting of phase error information based on the comparison of the phase difference between two adjacent groups of orthogonal phase clock signals includes: receiving and outputting the multiple groups of orthogonal phase clock signals; the multiple groups of orthogonal phase clock signals include: a first group of orthogonal phase clock signals, a second group of orthogonal phase clock signals, a third group of orthogonal phase clock signals and a fourth group of orthogonal phase clock signals; selecting two adjacent groups of orthogonal phase clock signals and outputting them through a low-pass filter 1214; according to an input selection signal, controlling the state of the switch to selectively turn on, and outputting the selected two adjacent groups of orthogonal phase clock signals to the phase error comparator 122 in a predetermined phase error comparison order.

[0093] In some specific embodiments, the predetermined phase error comparison sequence is: the first group of quadrature phase clock signals are compared with the second group of quadrature phase clock signals, the third group of quadrature phase clock signals are compared with the fourth group of quadrature phase clock signals, the second group of quadrature phase clock signals are compared with the third group of quadrature phase clock signals, and the fourth group of quadrature phase clock signals are compared with the first group of quadrature phase clock signals; wherein, The order of comparing the first group of quadrature phase clock signals with the second group of quadrature phase clock signals and the order of comparing the third group of quadrature phase clock signals with the fourth group of quadrature phase clock signals can be interchanged; The order of comparing the second group of quadrature phase clock signals with the third group of quadrature phase clock signals and the order of comparing the fourth group of quadrature phase clock signals with the first group of quadrature phase clock signals can be interchanged; The first group of orthogonal phase clock signals are compared with the second group of orthogonal phase clock signals and the third group of orthogonal phase clock signals are compared with the fourth group of orthogonal phase clock signals, and are overall prior to or after the second group of orthogonal phase clock signals are compared with the third group of orthogonal phase clock signals and the fourth group of orthogonal phase clock signals are compared with the first group of orthogonal phase clock signals.

[0094] In some specific embodiments, after outputting two adjacent groups of selected orthogonal phase clock signals to the phase error comparator 122 in a predetermined phase error comparison order, the method further includes: performing comparison based on output voltage information of the two adjacent groups of orthogonal phase clock signals, and outputting the comparison result to the state holder 1222, so that the state holder 1222 temporarily maintains and outputs the comparison result when the input signal is not switched.

[0095] The step of controlling at least one delay unit in the delay link 111 according to the phase error information to calibrate the phase error of the orthogonal phase clock signal includes: controlling the corresponding delay unit in the delay link 111 according to the comparison result, and controlling the respective phase differences of two adjacent groups of orthogonal phase clock signals until the phase error of the two adjacent groups of orthogonal phase clock signals reaches an expected value.

[0096] It should be noted that the scheme of this embodiment has corresponding specific technical features as the first embodiment, and its specific technical scheme and technical effects are similar to those of the first embodiment. The difference is that the measurement method of the embodiment of the present invention can be implemented by all the hardware provided including but not limited to the first embodiment.

[0097] For each embodiment provided by the present invention, the technical solutions and technical effects are basically the same, and the relevant parts can be referenced to each other.

[0098] Based on the clock signal quadrature phase error calibration device provided in the aforementioned embodiment 1, the present invention further provides a chip in an embodiment, including: the clock signal quadrature phase error calibration device described in any one of the embodiments 1. Since the clock signal quadrature phase error calibration device is integrated internally, a high-precision and stable clock signal can be output, thereby improving the performance of the chip.

[0099] In summary, the clock signal orthogonal phase error calibration device, method and chip provided by the embodiments of the present invention can reduce the power consumption of the clock link by placing part of the core circuit of the orthogonal phase calibration module inside the DLL loop, so that the orthogonal phase calibration module and the DLL loop share the delay link, thereby facilitating the calibration of the orthogonal phase error of the clock signal in a low-power form.

[0100] Furthermore, by introducing an automatic zeroing comparator and using a zeroing technical solution for comparison, the calibration error introduced by the comparator's own misalignment can be eliminated, thereby improving the calibration accuracy.

[0101] Furthermore, an innovative four-step calibration process is proposed to achieve accurate calibration of the phase errors between four groups of orthogonal phase clock signals, namely phase 0, phase 90, phase 180 and phase 270, thereby improving the accuracy of system signal transmission and control.

[0102] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0103] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0104] For the convenience of description, the above chip internal clock period jitter measurement device is described as being divided into various functional units / circuits / modules by function. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0105] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A clock signal quadrature phase error calibration device, characterized in that: The device includes: a DLL loop configured to generate a plurality of sets of quadrature phase clock signals; A phase error detection module, used to compare the phase difference between two adjacent groups of orthogonal phase clock signals and output phase error information; The phase calibration module comprises: a delay link and a digital state machine, wherein the delay link is located inside the DLL loop, the delay link comprises a plurality of cascaded delay units, a first pin of the digital state machine is connected to the phase error detection module, a second pin of the digital state machine is connected to each delay unit of the delay link, and is configured to control at least one delay unit in the delay link according to the phase error information to calibrate the phase error of the orthogonal phase clock signal.

2. The clock signal quadrature phase error calibration device according to claim 1, characterized in that: The phase error detection module comprises: a phase error detector and a phase error comparator connected to the phase error detector; The phase error detector is configured to monitor the phase relationship between the input quadrature phase clock signals and output phase difference information of each group of quadrature phase clock signals; The phase error comparator is configured to generate a logic value representing the phase error information of two adjacent groups of orthogonal phase clock signals according to the comparison of the phase difference information of two adjacent groups; The first pin of the digital state machine is connected to the phase error comparator in the phase error detection module, and is specifically configured to control at least one delay unit in the delay link according to the logic value to calibrate the phase error of the orthogonal phase clock signal.

3. The clock signal quadrature phase error calibration device according to claim 2, characterized in that: The phase error detector comprises: a phase deviation generating module, a phase deviation selecting module and a clock control switch connected in sequence; The phase skew generation module is configured to receive and output the multiple groups of quadrature phase clock signals; the multiple groups of quadrature phase clock signals include: a first group of quadrature phase clock signals, a second group of quadrature phase clock signals, a third group of quadrature phase clock signals and a fourth group of quadrature phase clock signals; The phase skew selection module is configured to select two adjacent groups of orthogonal phase clock signals and output them via a low-pass filter; The clock control switch is configured to control the state of the switch to selectively conduct according to the input selection signal, and output the selected two adjacent groups of orthogonal phase clock signals to the phase error comparator in a predetermined phase error comparison order.

4. The clock signal quadrature phase error calibration device according to claim 3, characterized in that: The predetermined phase error comparison order is: the first group of quadrature phase clock signals are compared with the second group of quadrature phase clock signals, the third group of quadrature phase clock signals are compared with the fourth group of quadrature phase clock signals, the second group of quadrature phase clock signals are compared with the third group of quadrature phase clock signals, and the fourth group of quadrature phase clock signals are compared with the first group of quadrature phase clock signals.

5. The clock signal quadrature phase error calibration device according to claim 4, characterized in that: The order of comparing the first group of quadrature phase clock signals with the second group of quadrature phase clock signals and the order of comparing the third group of quadrature phase clock signals with the fourth group of quadrature phase clock signals can be interchanged; The order of comparing the second group of quadrature phase clock signals with the third group of quadrature phase clock signals and the order of comparing the fourth group of quadrature phase clock signals with the first group of quadrature phase clock signals can be interchanged; The first group of orthogonal phase clock signals are compared with the second group of orthogonal phase clock signals and the third group of orthogonal phase clock signals are compared with the fourth group of orthogonal phase clock signals, and are overall prior to or after the second group of orthogonal phase clock signals are compared with the third group of orthogonal phase clock signals and the fourth group of orthogonal phase clock signals are compared with the first group of orthogonal phase clock signals.

6. The clock signal quadrature phase error calibration device according to any one of claims 2 to 5, characterized in that: The phase error comparator includes an automatic zeroing comparator and a state holder. The automatic zeroing comparator is configured to compare the output voltage information of the orthogonal phase clock signals of two adjacent groups and output the comparison result to the state holder; The state holder is configured to temporarily hold and output the comparison result when no input signal is switched; The digital state machine controls the corresponding delay unit in the delay link according to the comparison result, and controls the respective phase differences of the two adjacent groups of orthogonal phase clock signals until the phase error of the two adjacent groups of orthogonal phase clock signals reaches the expected value.

7. A clock signal quadrature phase error calibration method, characterized in that: The method comprises: generating a plurality of sets of quadrature phase clock signals; Compare the phase differences of two adjacent groups of quadrature-phase clock signals and output phase error information; At least one delay unit in a delay link is controlled according to the phase error information to calibrate the phase error of the quadrature phase clock signal.

8. The clock signal quadrature phase error calibration method according to claim 7, characterized in that: The step of comparing the phase difference between two adjacent groups of quadrature phase clock signals and outputting phase error information comprises: monitoring the phase relationship between the input quadrature phase clock signals and outputting the phase difference information of each group of quadrature phase clock signals; Generate a logic value representing the phase error information of two adjacent groups of orthogonal phase clock signals by comparing the phase difference information of two adjacent groups; At least one delay unit in the delay chain is controlled according to the logic value to calibrate the phase error of the orthogonal phase clock signal.

9. The clock signal quadrature phase error calibration method according to claim 7, characterized in that: Outputting phase error information by comparing the phase differences between two adjacent groups of quadrature phase clock signals comprises: receiving and outputting the multiple groups of quadrature phase clock signals; the multiple groups of quadrature phase clock signals comprise: a first group of quadrature phase clock signals, a second group of quadrature phase clock signals, a third group of quadrature phase clock signals and a fourth group of quadrature phase clock signals; Select two adjacent groups of orthogonal phase clock signals and output them through a low-pass filter; According to the input selection signal, the state of the switch is controlled to be selectively turned on, and the selected two adjacent groups of orthogonal phase clock signals are output to the phase error comparator in a predetermined phase error comparison sequence.

10. The clock signal quadrature phase error calibration method according to claim 9, characterized in that: The predetermined phase error comparison sequence is: the first group of quadrature phase clock signals are compared with the second group of quadrature phase clock signals, the third group of quadrature phase clock signals are compared with the fourth group of quadrature phase clock signals, the second group of quadrature phase clock signals are compared with the third group of quadrature phase clock signals, and the fourth group of quadrature phase clock signals are compared with the first group of quadrature phase clock signals; wherein, The order of comparing the first group of quadrature phase clock signals with the second group of quadrature phase clock signals and the order of comparing the third group of quadrature phase clock signals with the fourth group of quadrature phase clock signals can be interchanged; The order of comparing the second group of quadrature phase clock signals with the third group of quadrature phase clock signals and the order of comparing the fourth group of quadrature phase clock signals with the first group of quadrature phase clock signals can be interchanged; The first group of orthogonal phase clock signals are compared with the second group of orthogonal phase clock signals and the third group of orthogonal phase clock signals are compared with the fourth group of orthogonal phase clock signals, and are overall prior to or after the second group of orthogonal phase clock signals are compared with the third group of orthogonal phase clock signals and the fourth group of orthogonal phase clock signals are compared with the first group of orthogonal phase clock signals.

11. The clock signal quadrature phase error calibration method according to claim 9 or 10, characterized in that: After outputting the selected two adjacent groups of quadrature phase clock signals to the phase error comparator in a predetermined phase error comparison order, the method further includes: comparing the output voltage information of the two adjacent groups of quadrature phase clock signals, and outputting the comparison result to the state holder, so that the state holder temporarily holds and outputs the comparison result when the input signal is not switched; The step of controlling at least one delay unit in the delay link according to the phase error information to calibrate the phase error of the orthogonal phase clock signal includes: controlling the corresponding delay unit in the delay link according to the comparison result, and controlling the respective phase differences of two adjacent groups of orthogonal phase clock signals until the phase error of the two adjacent groups of orthogonal phase clock signals reaches an expected value.

12. A chip, characterized in that: include: The clock signal quadrature phase error calibration device according to any one of claims 1 to 6.

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