Device for generating digital signal according to current slope

Abstract

The invention relates to a device for generating a digital signal according to a current slope. An apparatus for generating a digital signal dependent on an average slope of a first current flowing through a circuit element during a sampling period includes a delta-sigma modulator configured to sense the first current during the sampling period and to generate the digital signal using the sensed first current.

Description

[0001] The present disclosure relates to an apparatus for generating a digital signal that is dependent on the average slope of a current flowing through a circuit element.

[0002] background

[0003] There is a system in the prior art for measuring the average inductor current and converting the result into a digital number (US2023155472A1).

[0004] The knowledge of the average inductor current slope in the digital domain is very useful for diagnostics and self-calibration of current-mode switching converters.

[0005] In known systems, the slope can be determined by measuring the current and converting it with an analog-to-digital converter (ADC), then measuring the incremental change between samples. With knowledge of the sampling rate and channel gain, the current slope can be calculated (US9419627B2, US9667260B2).

[0006] Overview

[0007] It would be desirable to provide a system for current slope sensing that operates with greater accuracy and / or lower power requirements than known systems.

[0008] It is desirable to provide a system for current slope sensing and analog-to-digital conversion that can provide higher accuracy than known systems at high switching converter frequencies and over a wide range of duty cycles, and with lower power.

[0009] According to a first aspect of the present disclosure, there is provided a device for generating a digital signal, the digital signal depending on an average slope of a first current flowing through a circuit element during a sampling period, the device comprising a delta-sigma modulator configured to sense the first current during the sampling period and generate a digital signal using the sensed first current.

[0010] Optionally, the apparatus comprises a slope calculation unit configured to receive the digital signal and determine an average slope of the first current during the sampling period using the digital signal.

[0011] Optionally, the delta-sigma modulator is configured to sense a first current flowing through a circuit element of the switching converter.

[0012] Optionally, the circuit element is an inductor and the switching converter is one of a buck converter, a boost converter and a buck-boost converter.

[0013] Optionally, the delta-sigma modulator is configured to sense the first current flowing through the circuit element by sensing a current flowing through a first power switch of the switching converter.

[0014] Optionally, the apparatus comprises a diagnostic unit configured to use the determined average slope of the first current to diagnose the switching converter operation.

[0015] Optionally, the apparatus comprises a self-calibration unit configured to calibrate the switching converter based on the determined average slope of the first current.

[0016] Optionally, the delta-sigma modulator is configured to sense the first current at a first time step and a second time step within a sampling period, and generate a digital signal using the first current sensed at the first time step and the second time step.

[0017] Optionally, the delta-sigma modulator includes a summing circuit configured to sense a first current at a first time step by measuring a first voltage on a sensing element at a first time step, sense the first current at a second time step by measuring the first voltage on the sensing element at a second time step, and generate a differential signal that depends on subtracting the first voltage at a second time step from the first voltage at the first time step, wherein the first voltage depends on the first current.

[0018] Optionally, the first current is equal to the first voltage divided by a first resistance of the sensing element.

[0019] Optionally, the sensing element comprises a first switch having a first resistance, the summing circuit comprises a mirror switch having a second resistance, and a switch pair is formed comprising the first switch and the mirror switch.

[0020] Optionally, the first switch comprises a first transistor and the mirror switch comprises a second transistor, wherein a gate of each of the first and second transistors is configured to receive a power supply voltage.

[0021] Optionally, the second resistor is a multiple of the first resistor.

[0022] Optionally, the gate voltages of the first and second transistors are approximately equal, and the drain-source voltages of the first and second transistors are approximately equal.

[0023] Optionally, the summing circuit includes a first capacitor having a first terminal and a second terminal, the first terminal being coupled to the first terminal of the first transistor via a first switch, coupled to a ground terminal via a second switch, the second terminal being coupled to a differential node via a third switch, and coupled to a common-mode gain terminal via a fourth switch, and the second capacitor having a first terminal and a second terminal, the first terminal being coupled to the first terminal of the mirror transistor via a fifth switch, coupled to the common-mode gain terminal via a sixth switch, the second terminal being coupled to the differential node via a seventh switch, and coupled to the ground terminal via an eighth switch.

[0024] Optionally, the delta-sigma modulator comprises a first integration circuit configured to receive the differential signal and generate an integrated voltage signal.

[0025] Optionally, the first integration circuit comprises a first differential amplifier.

[0026] Optionally, the first differential amplifier includes a first input terminal configured to receive a differential signal and an output terminal configured to output an integrated voltage signal and coupled to the first input terminal.

[0027] Optionally, the first integration circuit comprises a first integration circuit capacitor, and the first input terminal of the first differential amplifier is coupled to the output terminal of the first differential amplifier via the first integration circuit capacitor.

[0028] Optionally, the delta-sigma modulator comprises a first comparator configured to receive the integrated voltage signal and output a digital signal.

[0029] Optionally, the first comparator receives a clock signal, and the sampling rate of the delta-sigma modulator depends on the clock signal.

[0030] Optionally, the sensing element comprises a first switch having a first resistance, the summing circuit comprises a mirror switch having a second resistance, and a switch pair is formed comprising the first switch and the mirror switch.

[0031] Optionally, the first switch comprises a first transistor and the mirror switch comprises a second transistor, wherein a gate of each of the first and second transistors is configured to receive a power supply voltage.

[0032] Optionally, the second resistor is a multiple of the first resistor.

[0033] Optionally, the gate voltages of the first and second transistors are approximately equal, and the drain-source voltages of the first and second transistors are approximately equal.

[0034] Optionally, the delta-sigma modulator includes a current source coupled to the second transistor, and a feedback circuit configured to receive a digital signal and control the current source based on the received digital signal.

[0035] Optionally, the feedback circuit comprises an AND gate.

[0036] Optionally, the pulse density of the digital signal depends on an average slope of the first current during a sampling period.

[0037] Optionally, the pulse density is proportional to an average slope of the first current during a sampling period.

[0038] Optionally, the slope calculation unit is configured to determine an average slope of the first current during the sampling period by calculating an average value of the digital signal and using the average value of the digital signal to determine an average difference of the first current during the sampling period.

[0039] Optionally, the slope calculation unit is configured to determine an average slope of the first current during the sampling period by dividing an average difference of the first current during the sampling period by a duration of the sampling period.

[0040] Optionally, the digital signal comprises a plurality of bits.

[0041] Optionally, the delta-sigma modulator comprises a multi-bit quantizer configured to generate a digital signal.

[0042] Optionally, the multi-bit quantizer comprises an inverter, wherein the digital signal is inverted using the inverter before being provided as an output.

[0043] Optionally, the multi-bit quantizer comprises an analog-to-digital converter.

[0044] Optionally, the analog-to-digital converter is a flash ADC.

[0045] Optionally, the delta-sigma modulator is configured to sense the first current at a first time step and a second time step within a sampling period, and generate a digital signal using the first current sensed at the first time step and the second time step.

[0046] Optionally, the delta-sigma modulator includes a summing circuit configured to sense a first current at a first time step by measuring a first voltage across a sensing element at a first time step, sense the first current at a second time step by measuring the first voltage across the sensing element at a second time step, and generate a differential signal that depends on subtracting a second voltage from the first voltage, wherein the first voltage depends on the first current.

[0047] Optionally, the delta-sigma modulator comprises a first integration circuit configured to receive the differential signal and generate an integrated voltage signal.

[0048] Optionally, the first integration circuit comprises a first differential amplifier.

[0049] Optionally, the first differential amplifier includes a first input terminal configured to receive a differential signal and an output terminal configured to output an integrated voltage signal and coupled to the first input terminal.

[0050] Optionally, the first integration circuit comprises a first integration circuit capacitor, and the first input terminal of the first differential amplifier is coupled to the output terminal of the first differential amplifier via the first integration circuit capacitor.

[0051] Optionally, the delta-sigma modulator includes a most significant bit digital-to-analog converter for generating a first analog output signal for use in generating the most significant bit of the digital signal, and a least significant bit digital-to-analog converter for generating a second analog output signal for use in generating the least significant bit of the digital signal.

[0052] Optionally, the sensing element includes a first switch having a first resistance, the most significant digital-to-analog converter includes a first mirror switch having a second resistance, the least significant digital-to-analog converter includes a second mirror switch having a third resistance, and a switch triplet is formed, the switch triplet includes the first switch, the first mirror switch, and the second mirror switch.

[0053] Optionally, the first switch comprises a first transistor, and the first mirror switch comprises a first mirror transistor, and the second mirror switch comprises a second mirror transistor, wherein a gate of each of the first transistor, the first mirror transistor and the second mirror transistor is configured to receive a power supply voltage.

[0054] Optionally, the second resistor and the third resistor are multiples of the first resistor.

[0055] Optionally, gate voltages of the first, second and third transistors are approximately equal, and drain-source voltages of the first, second and third transistors are approximately equal.

[0056] Optionally, the delta-sigma modulator includes a first current source coupled to the first mirror transistor, a second current source coupled to the second mirror transistor, and a feedback circuit configured to receive a digital signal and control the first current source and the second current source based on the received digital signal.

[0057] Optionally, the feedback circuit includes a feedback digital-to-analog converter control circuit.

[0058] According to a second aspect of the present disclosure, there is provided a method for generating a digital signal that depends on an average slope of a first current flowing through a circuit element during a sampling period, the method comprising sensing the first current during the sampling period using a delta-sigma modulator, and generating a digital signal using the sensed first current using the delta-sigma modulator.

[0059] It will be appreciated that the method of the second aspect may include the features set out in the first aspect, and may be combined with other features as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0061] Figure 1 is a schematic diagram of a buck converter;

[0062] FIG2(a) is a schematic diagram of an apparatus for generating a digital signal according to a first embodiment of the present disclosure, FIG2(b) is a time diagram showing a current flowing through a circuit element of FIG2(a) changing with time, FIG2(c) is a timing diagram showing a digital signal for a first average slope of the current, and FIG2(d) is a timing diagram showing a digital signal for a second average slope of the current;

[0063] FIG3( a ) is a schematic diagram of a device for generating a digital signal according to a second embodiment of the present disclosure, FIG3( b ) is a schematic diagram of a device according to a third embodiment of the present disclosure, and FIG3( c ) is a schematic diagram of a device according to a fourth embodiment of the present disclosure;

[0064] FIG. 4( a ) is a schematic diagram of a device according to a fifth embodiment of the present disclosure, FIG. 4( b ) is a schematic diagram of a device according to a sixth embodiment of the present disclosure, and FIG. 4( c ) is a schematic diagram of a device according to a seventh embodiment of the present disclosure;

[0065] FIG5(a) is a schematic diagram of an apparatus according to an eighth embodiment of the present disclosure, FIG5(b) is a schematic diagram of an example embodiment of a sensing element and a summing circuit, and FIG5(c) is a schematic diagram of an example embodiment of a switch;

[0066] FIG. 6( a ) is a schematic diagram of a device according to a ninth embodiment of the present disclosure, and FIG. 6( b ) is a schematic diagram of a specific embodiment of an integration circuit including a differential amplifier;

[0067] Figure 7 is a schematic diagram of a device according to a tenth embodiment of the present disclosure;

[0068] Figure 8 is a timing diagram showing the buck converter of FIG4(a) for use with Figure 7 Example operation of a delta-sigma modulator;

[0069] Fig. 9 is a schematic diagram of a device according to an eleventh embodiment of the present disclosure;

[0070] FIG. 10( a ) is a schematic diagram of a device according to a twelfth embodiment of the present disclosure, and FIG. 10( b ) is a schematic diagram of a specific embodiment of a multi-bit quantizer;

[0071] FIG. 11( a ) is a schematic diagram of an apparatus according to a thirteenth embodiment of the present disclosure, FIG. 11( b ) is a schematic diagram of an example embodiment of a sensing element and a summing circuit, and FIG. 11( c ) is a schematic diagram of an example embodiment of a switch;

[0072] FIG. 12( a ) is a schematic diagram of a device according to a fourteenth embodiment of the present disclosure, and FIG. 12( b ) is a graph showing a transfer characteristic of a multi-bit quantizer;

[0073] Figure 13(a) is used for Figure 7 FIG. 13( b) is a schematic diagram of a reference capacitor portion of a low-side switch sensing device shown in FIG. Fig. 9 The schematic diagram of the high-side switch sensing reference capacitor portion of the device shown in FIG13(c) can replace Figure 7 and Fig. 9 FIG13( d) is a schematic diagram of an alternative embodiment of a reference capacitor portion of a reference capacitor portion of a buck-boost converter. FIG13( d) is a schematic diagram of an embodiment of a reference capacitor portion that can be applied to a buck-boost converter.

[0074] Fig.14 is a timing diagram showing Fig. 9 Example operation of a delta-sigma modulator used with the buck converter of FIG. 4( a ) and using the reference capacitor portion of FIG. 13( c );

[0075] Fig.15 yes Figure 7 An alternative schematic diagram of the device;

[0076] Fig.16 is a timing diagram showing Fig.15 Example operation of the delta-sigma modulator used with the buck converter of FIG. 4( a );

[0077] Fig.17 is a schematic diagram of a device according to a fifteenth embodiment of the present disclosure; and

[0078] Fig.18 is a timing diagram showing Fig.17 4(a) is an example operation of a delta-sigma modulator used with the buck converter of FIG. 4(a).

[0079] Detailed Description

[0080] Figure 1 The invention comprises an inverting level shifter 102; a non-inverting level shifter 104; a power switch M HS , M LS ; and inductor L; resistor R L ; and a schematic diagram of a buck converter 100 having a capacitor C. The buck converter 100 receives an input voltage V BAT And generate output voltage V OUT .

[0081] During operation, if HS=1, the control signal HS turns on M HS (due to the inverting level shifter 102). Similarly, if LS=1, the control signal LS turns on M LS .

[0082] If each corresponding switching device (M HS , M LS) is required to have a maximum gate-source voltage VGS(MAX) lower than the input voltage V BAT , an intermediate power supply (VSS HS and VDD LS ).

[0083] During operation, the level shifters 102, 104 will drive node SW to V BAT or ground. Due to the filter formed by L and C, the output voltage V OUT There will be a filtered version of the voltage at SW with low ripple.

[0084] R L is a resistance including inductor resistance and wiring resistance. In order for the buck converter 100 to work properly, the two switches M HS and switch M LS They must not be activated simultaneously during operation.

[0085] Low side switch current I LS The direction of the inductor current I L The same is used to simplify the explanation of the behavior of the buck converter 100.

[0086] Since a voltage is applied to the inductor L, an inductor current I is generated in the inductor L. L For current mode control, it is necessary to measure this current.

[0087] Since the switch M HS Or switch M LS When activated, the inductor current I L Flow through switch M HS Or switch M LS , measure the M through these path devices HS , M LS The current is sufficient to estimate the current I in the inductor L L .

[0088] In addition, since the inductor current I L is continuous, so in many cases it is not always necessary to measure M HS and M LS , because they provide redundant information. As described in more detail below, specific embodiments of the present disclosure focus on sensing current by measuring the current through these switch pass devices.

[0089] The embodiments of the present disclosure may be applied to a current mode switching power converter, such as a buck converter 100, or a boost converter or a buck-boost converter. However, it should be understood that the embodiments of the present disclosure may be applied to other systems according to the understanding of the skilled person.

[0090] 2(a) is a schematic diagram of an apparatus 200 for generating a digital signal D1 according to a first embodiment of the present disclosure, the digital signal D1 being dependent on the average slope of a current I1 flowing through a circuit element 202 during a sampling period. The apparatus 200 includes a delta-sigma modulator 204 configured to sense the current I1 during a sampling period and generate a digital signal D1 using the sensed current I1. A delta-sigma modulator is a system that converts an analog signal into a digital signal using oversampling. The average slope refers to the average rate of change of the current I1 over time. This may also be referred to as the average gradient of the slope. The digital signal D1 may be a data stream generated by sensing the average current slope and converting it into a digital signal.

[0091] FIG2( b) is a time graph 206 showing the current flowing through the circuit element 202 as a function of time. In this example, to aid in explanation, we will consider the application of the present system to a buck converter 100, such that the circuit element is an inductor L. However, it should be understood that the circuit element 202 may be part of a system other than a buck converter, and it may be a component other than an inductor, according to the understanding of the skilled person. It should be noted that the waveform shape shown in FIG2( b) will apply to a two-state converter, such as a buck converter and a boost converter, but more complex shapes may occur in other topologies.

[0092] In this example, the timing diagram 206 shows the inductor current I L flows through an inductor L, such as the inductor L of the buck converter 100. As mentioned above, the sampling period is denoted by "TS" in FIG. 2(b).

[0093] Returning to the apparatus 200, the delta-sigma modulator 204 may sense the current I1 at the first time step t1 and the second time step t2. The current I1 sensed at the time steps t1, t2 may then be used to generate a digital signal D1.

[0094] In a specific embodiment, the pulse density of the digital signal D1 may depend on the average slope of the current I1 during the sampling period TS.

[0095] 2( c ) is a timing diagram 208 , showing the digital signal D1 at a first average slope of the current I1 (trace 210 ). FIG. 2( d ) is a timing diagram 212 , showing the digital signal D1 at a second average slope of the current I1 (trace 214 ).

[0096] In this example, as shown in Figures 2(c) and 2(d), the pulse density of the digital signal D1 is proportional to the average slope of the current I1, so that Figure 2(c) can represent an example with an average slope less than the average slope of the example provided in Figure 2(d).

[0097] In another embodiment, there may be a different relationship between the pulse density and the average slope. For example, the pulse density may be inversely proportional to the average slope of the current I1 during the sampling period TS.

[0098] 3(a) is a schematic diagram of an apparatus 300 for generating a digital signal D1 according to a second embodiment of the present disclosure, the digital signal D1 depending on the average slope of the current I1 flowing through the circuit element 202 during a sampling period. In this embodiment, the apparatus 300 further includes a slope calculation unit 302. During operation, the slope calculation unit 302 receives the digital signal D1 and then uses the digital signal D1 to determine the average slope of the current I1 during the sampling period TS.

[0099] Since the digital signal D1 depends on the average slope of the current I1 , this information can be extracted from the digital signal D1 , and this function is implemented by the slope calculation unit 302 .

[0100] For example, the slope calculation unit 302 may determine an average value of the digital signal D1. Referring to Figures 2(c) and 2(d), the average value of D1 over several pulses will depend on the pulse density, which in turn depends on the average slope of the current I1.

[0101] In a specific embodiment, the average value of the digital signal D1 can be used to determine the average difference in the current I1 during the sampling period. The average difference in the current I1 can then be divided by the duration of the sampling period to determine the average slope.

[0102] As an example, and referring to FIG. 2( b ), we may consider that the current I1 at time t1 is represented by I1(t1) and the current I1 at time t2 is represented by I1(t2), where the average difference in current is represented by:

[0103]

[0104] In this embodiment, the average value of the digital signal D1 can be used to determine the value provided by equation (1): The average slope can then be calculated as follows:

[0105]

[0106] 3( b ) is a device 304 according to a third embodiment of the present disclosure. In this embodiment, the device 304 further includes a diagnosis unit 306 configured to diagnose the switching converter operation using the determined average slope of the current I1 .

[0107] Fig. 3(c) is a device 308 according to a fourth embodiment of the present disclosure. In this embodiment, the device 308 further includes a self-calibration unit 310, which is configured to calibrate the switching converter based on the determined average slope of the current I1.

[0108] The delta-sigma modulator may be configured to sense a current I1 flowing through a circuit element 202 of a switching converter such as a buck converter, a boost converter, or a buck-boost converter. The circuit element 202 may be an inductor. The current flowing through the circuit element 202 may be sensed by sensing a current flowing through a power switch of the switching converter.

[0109] FIG4(a) is a schematic diagram of a device 400 according to a fifth embodiment of the present disclosure. In this embodiment, the circuit element 202 is an inductor L as part of the buck converter 402. In this embodiment, by sensing the current flowing through the low-side power switch M LS The current flowing through the inductor L can be sensed by the current of the high-side power switch M HS To sense the current.

[0110] Buck converter 402 includes a power switch M LS , M HS Gate drivers 408, 410, inductor L, resistor R L and capacitor C.

[0111] In this embodiment, the delta-sigma modulator 204 measures the current through the low-side switch M LS The current ILS is used to measure the slope of the inductor current IL.

[0112] It should be understood that LS means "low side", which is typically an NMOS switch connected from the switch node to ground. Likewise, HS means "high side", which is typically a PMOS or an NMOS with a bootstrap capacitor to drive the gate of the NMOS. In some cases, such as at negative voltages, the type of transistor can be reversed. Therefore, it should be understood that the use of LS and HS instead of NMOS / PMOS is a means of indicating the position of the transistor rather than the type.

[0113] FIG4( b ) is a schematic diagram of a device 412 according to a sixth embodiment of the present disclosure. In this embodiment, the circuit element 202 is an inductor L as part of a boost converter 414. This is an example of a boost converter with an NMOS high side. HS is driven by a gate driver whose positive supply is derived from a bootstrap circuit to provide a HS Generates enough VGS to turn on. Note that the direction of current flow is opposite.

[0114] FIG4( c ) is a schematic diagram of a device 416 according to a seventh embodiment of the present disclosure. In this embodiment, the circuit element is an inductor L as part of a buck-boost converter 418. The buck-boost converter includes gate drivers 420, 422, 424, 426 and a switch M. HS_BUCK , M LS_BUCK , M HS_BOOST , M LS_BOOST .

[0115] This is an example of positive buck-boost. In the positive current case, there are 4 possible paths for the current:

[0116] 1.VBAT->MHS_BUCK->L, RL->MLS_BOOST->GND: (boost magnetization) using MLS_BOOST sensing

[0117] 2.VBAT->MHS_BUCK->L, RL->MHS_BOOST->VOUT: (Buck magnetization) using MHS_BUCK sensing

[0118] 3. GND->MLS_BUCK->L, RL->MHS_BOOST->VOUT: (Demagnetization) using MLS_BUCK sensing

[0119] 4. GND->MLS_BUCK->L, RL->MLS_BOOST->GND: (invalid) no sensing is used

[0120] Three current sensing schemes around three switches can be used for the three cases (1 to 3) described above.

[0121] It should be noted that for VBAT->MHS_BUCK->L, RL->MHS_BOOST->VOUT (Case 2), the current slope can be rising or falling, so special changes should be made to the reference feedback of HSBUCK.

[0122] 5(a) is a schematic diagram of an apparatus 500 according to an eighth embodiment of the present disclosure. In this embodiment, the delta-sigma modulator 204 includes a summing circuit 502, which is configured to sense the current I1 at time step t1 by measuring the voltage V1 across the sensing element 504 at time step t1; and sense the current I1 at time step t2 by measuring the voltage V1 across the sensing element 504 at time step t2.

[0123] The summing circuit 502 is configured to then generate a differential signal 505 that is dependent on subtracting the voltage V1 at the second time step t2 from the voltage V1 at the first time step t1 . The current I1 may be equal to the voltage V1 divided by the resistance of the sensing element 504 .

[0124] Sensing element 504 enables the average current slope in circuit element 202 to be measured by proxy. For example, in a buck converter where circuit element 202 is an inductor, sensing element 504 may be a power switch (e.g., switch M of FIG. 4( a)). LS ).

[0125] 5( b ) is a schematic diagram of an example embodiment of a sensing element 504 and a summing circuit 502. In this embodiment, the sensing element 504 includes a switch 506 having a resistance; the summing circuit 502 includes a mirror switch 508 having a resistance. A switch pair is formed by the switches 506 and 508, and a current I1 flows through the switch 506, and a current I2 flows through the switch 508.

[0126] FIG. 5( c ) is a schematic diagram of an example embodiment of switches 506 , 508 implemented using transistors 510 , 512 , each having a gate coupled to a supply voltage Vdd.

[0127] The resistance of transistor 512 may be a multiple of the resistance of transistor 510. The gate voltages of transistors 510, 512 may be approximately equal, and the drain-source voltages of transistors 510, 512 may be approximately equal.

[0128] It should be understood that in this disclosure, several embodiments are described using a mirror transistor based approach as shown in FIG5(c) for sensing using a pass device 510. It should be understood that in another embodiment, rather than a mirror based approach, a sense resistor may be used to extract relevant voltage information for sensing current flow.

[0129] 6( a ) is a schematic diagram of a device 600 according to a ninth embodiment of the present disclosure. In this embodiment, the delta-sigma modulator 204 comprises an integration circuit 602 configured to receive the differential signal 505 and generate an integrated voltage signal 603 .

[0130] 6( b) is a schematic diagram of a specific embodiment of an integration circuit 602 including a differential amplifier 604. The differential amplifier 604 includes an input terminal configured to receive the differential signal 505, and has an output terminal for outputting an integrated voltage signal 603. The output terminal is coupled to the input terminal via a capacitor 608. The input of the differential amplifier 604 can be coupled to a voltage VA.

[0131] The delta-sigma modulator 204 may further include a comparator 610 configured to receive the integrated voltage signal 603 and output a digital signal D1. The comparator 610 may receive a clock signal CLK, wherein the sampling rate of the delta-sigma modulator 204 depends on the clock signal CLK. An input of the comparator 610 may be coupled to a voltage VA.

[0132] In a specific embodiment, during operation, the integrator 602 may integrate the charge injected into the node NA from the correlated double sampling (CDS) circuit.

[0133] Figure 7 4( a) is a schematic diagram of an apparatus 700 according to a tenth embodiment of the present disclosure. In this example, a specific embodiment of a delta-sigma modulator 204 used with the buck converter 402 of FIG. 4( a) is shown. It should be understood that only the low-side switch M of the buck converter 402 LS The Δ-Σ modulator 204 and the driver 410 are shown to facilitate clarity of the drawing and description. It should be understood that in another embodiment, the Δ-Σ modulator 204 can be coupled to the high-side switch M HS Use together.

[0134] In this example, the summing circuit 502 includes a capacitor C REF and C S ; and switches 702, 704, 706, 708, 710, 712, 714, 716. The summing circuit 502 also includes a differential node N1 and a common mode terminal N2 at a common mode voltage ACM. It should be understood that the differential node N1 can be referred to as a virtual common mode or summing node. It should be understood that due to the infinite gain / bandwidth of the ideal differential amplifier 604, node N1 will typically see very little voltage change. And this summing node N1 actually ends up summing the charge pumped in from various other nodes through the capacitors.

[0135] The common-mode voltage ACM can only be applied to A INTEG The voltage of the + input of the ACM node should be the same as the voltage of the other nodes marked ACM. In practice, it is chosen to be INTEG within the input common-mode range.

[0136] Delta-sigma modulator 204 may further include a current source 718 coupled to transistor 512 and a feedback circuit 720 configured to receive digital signal D1 and control current source 718 based on the received digital signal D1. Feedback circuit 720 may include an AND gate.

[0137] A mirror device (transistor 512) is used in the feedback path of delta-sigma modulator 204. In operation, the delta-sigma modulator integrates the voltage difference on node SW and will attempt to cancel that voltage difference with the voltage feedback across transistor 512.

[0138] Delta-sigma modulator 204 is a "discrete-time switched capacitor" circuit that samples and integrates charge onto integrating capacitor 608, which produces a corresponding voltage at the output of differential amplifier 604. Unlike conventional delta-sigma modulator 204, summing circuit 502 (which may be referred to as a correlated double sampler) samples the input signal twice and, with the connections shown, seeks to dump charge into integrating capacitor 608 corresponding to the voltage difference at these two different times.

[0139] Figure 8 is a timing diagram 800 showing a timing diagram for use with the buck converter 402 of FIG. 4( a ) Figure 7 8. Example operation of the delta-sigma modulator 204 of FIG. 8 shows a high-side switch control signal (trace 802); a low-side switch control signal (trace 804); a current flowing through the inductor (trace 805); and a current flowing through the low-side switch M LS The current (trace 806); the voltage at the switch node SW (trace 808); the clock signal DS CLK (also labeled CLK in other embodiments and shown by trace 810); and provided to Figure 7 The control signals of the switches shown are labeled as follows φ1 (trace 812), φ2 (trace 814), φ4 (trace 816), φ5 (trace 818), φ6 (trace 820); and the digital signal D1 (also labeled DS L , and is shown by trace 822). Note that the numbers provided for the SW waveform (trace 808) are for illustration purposes only and may actually be different, but have a similar shape.

[0140] Mirror device 512 (also labeled) M LSS Its ground will be connected to the same ground as the pass device 510, and its gate will be connected to the same ground as the switch M. LS The driver has the same power supply VDD LS (labeled as Vdd in other embodiments) so that when pass device 510 is turned on, the gate voltages of both will be the same.

[0141] Switch M LSS It can be switch M LS A scaled-down version (at a known fixed ratio, K N ). When switch M LS When it is turned on, due to the common connection, the switch M LSS The drain-source resistance of the switch M LS The drain-source resistance K N times.

[0142] In this example, the current slope in the inductor is measured by a proxy, and by measuring the switch M LSIn general, this involves measuring the voltage at two different times, via a correlated double sampling (CDS) circuit combined with a discrete time delta-sigma circuit, that is, the voltage is equal to the current multiplied by the resistance (in this case, the on-resistance of the switch). In this example, the CDS circuit includes switches 710, 712, 714, 716 and capacitor C S .

[0143] To understand Figure 7 To illustrate the operation of the system, we start by tracing the signal from LS, which is the low-side switch control signal. When LS goes high, switch M LS is turned on, so the current I LS Will make the voltage V LS =R DS(ON)，MLS ×-I LS Formed on the SW node (note that I LS direction). DS(ON)，MLS Yes switch M LS The on-resistance.

[0144] It should be understood that Figure 8 The timing shown represents a single example, and further embodiments may exhibit different timing characteristics. For example, the duration of any of the control signals φ1-φ6 may be made shorter without changing the basic function of the circuit. Figure 7 , control signal φ 2N It is the inversion of the control signal φ2.

[0145] According to the timing of φ1 and φ2, we see that when both are high, switches 710 and 716 corresponding to these signals are turned on, so capacitor C S The voltage across the terminals tracks the voltage V LS An optional pre-charge switch 712 receiving a control signal φp may be used prior to this operation (and typically during the HS activation time) to enable C S The voltage across both ends reaches (GND-VCM) to reduce the settling time and reduce the coupling problem caused by high SW swing, which may be coupled through the parasitic capacitance of φ1 during HS. VCM refers to the voltage on the virtual common node (also called node N1).

[0146] φ2 off ( Figure 8 After Tstart is turned on, φ2n is also turned on. Due to the action of integrator 602, V LS Any change in the capacitor C INT The voltage across the terminals (hence V INTEG ) changes. INTEG ” is the integrated voltage signal.

[0147] For such a switching cycle (at T start and T end Between), V INTEG The changes are as follows:

[0148]

[0149] ΔV LS is the voltage V LS The change of current ΔI LS is the current I LS Please note that ΔI LS is negative because the current is falling during the LS period. This means that the integrator output will fall, and to close the loop of the delta-sigma modulator we need a current that causes ΔV INTEG Feedback of positive change occurs.

[0150] V INTEG It may correspond to the integrated voltage signal 603 as described above. ΔV LS will be located at node SW. Ideally, there will not be any voltage change on virtual CM. This change is ultimately converted into a charge on CINT and thus into output 603.

[0151] Note LS The direction is the same as the inductor current (i.e., through M LS away from ground). During the LS phase, the inductor is connected to a positive voltage, V OUT This will cause a virtual rising current in the inductor to ground, but since we specified the inductor current to be in the opposite direction, then I LS has a negative meaning (it is falling, hence negative). This is also true for the boost converter (since we have a positive VBAT), as well as the buck in reverse current mode and the LS switch for buck-boost. Therefore, this circuit is sufficient for all of these cases. However, a variation will be shown to cover the opposite case, where ΔV INTEG Rising during sampling. This can occur in alternative embodiments where the output is a negative voltage and is connected to ground through the inductor and LS switch as described above. This can also easily occur with the HS switch in buck-boost mode.

[0152] As the integrated voltage V INTEG becomes negative, which causes comparator 610 to go high (logic 1). In the general case of a multi-bit quantizer (as described in further detail below), this means that the quantizer has a minus sign in front of it for the falling I LS .

[0153] The above integrated voltage change ΔV INTEGIn the rising case, the input of comparator 610 will invert for the same reason.

[0154] Using a clock signal DS that defines the delta-sigma sampling rate CLK The comparator 610 is clocked. The comparator output enables the current source 718 (after being gated with φ4). This results in a voltage V FB In switch 512 (also labeled) M LSS Then, through switches 702 and 708, a capacitor C REF When it is sampled to capacitor C using switches 704 and 706, INT When the output of each output pulse changes,

[0155]

[0156] Note that a non-inverting integrator configuration is used here to obtain positive changes. This will be offset by the measured low-side switch current I LS A positive change caused by a negative change.

[0157] Note that if the output of comparator 610 is low, current source 718 will not conduct, and thus the associated phases φ4, φ5 and φ6 do not need to conduct.

[0158] In a delta-sigma modulator, the long-term averages of the forward and feedback expressions are equal in magnitude because V INTEG will try to converge to zero. Therefore, by equating and cancelling the common terms, and taking the average of the variable terms, we get:

[0159]

[0160] We assume that M LS To M LSS Matching preservation (as demonstrated in US2023155472A1). L is the output of delta-sigma modulator 204 (previously referred to as “ D1 ”).

[0161] Because except for D SL , all variables on the right hand side of equation (5) are constants, and we can output DS by taking the Δ-Σ L The average slope is obtained by averaging the values ​​of

[0162] Note the phase φ 5a、5b and φ 6a、6b are provided separately to possibly alleviate charge injection issues. In many cases, for simplicity, φ 5a = =φ 5b and / or φ 6a = =φ 6b .

[0163] Delta-Sigma Data Stream DS L Will be reflected at 2 time points through M LS I LS In this example, the two time points are the time defined by the decrease of φ2 (Tstart) and the time defined by the decrease of φ1 (Tend). L The average value of the output will be LS The slope of I increases proportionally, and knowing the times of Tstart and Tend and the various gain terms in the channel, the actual I LS Slope.

[0164] Because we only sample during the time when LS is on, and during this time, M LS The current in is the same as the current in inductor L and this measurement gives the slope of the inductor current.

[0165] Note that the time between Tstart and Tend does not need to span the entire slope (the time when LS is on). Knowing Tstart and Tend, the average of the slopes within Tstart and Tend is usually sufficient for many purposes.

[0166] According to the actual slope of the inductor current, the output DS L will go high or low, resulting in a pulse density that is proportional to the current slope. As mentioned before, for a steeper slope there will be a greater number of high pulses compared to a flatter current slope.

[0167] Fig. 9 4( a) is a schematic diagram of an apparatus 900 according to an eleventh embodiment of the present disclosure. In this example, a specific embodiment of a delta-sigma modulator 204 used with the buck converter 402 of FIG. 4( a) is shown. It should be understood that only the high-side switch M of the buck converter 402 HS and driver 408 are shown to aid clarity of drawing and description.

[0168] When with Figure 7 When compared with the device 700, this example involves using a high-side switch M HS Instead of the low-side switch M LS is sensed, and the behavior of this embodiment largely reflects the Figure 7 The described behavior is clear to the skilled person.

[0169] It should be understood that Fig. 9The PMOS HS case is shown, and in another embodiment, an NMOS HS switch as shown in FIG. 4( b ) and in accordance with the understanding of the skilled person may be provided. Since NMOS is used on the HS, the mirror transistor should be M HS A smaller version of the PMOS M HS Similar connections (same as previous circuit, M HSS Gate to VBOOT, drain to VOUT, source to delta-sigma / reference).

[0170] In such Fig. 9 In the example shown, the analog common mode (ACM) should preferably be referenced to VBAT to minimize power supply rejection ratio (PSRR) issues.

[0171] Note that for this embodiment, Figure 7 Compared to the embodiment shown in FIG. 1 , the SW node voltage slope is inverse (i.e., current increases and SW voltage decreases). This is because in the HS phase, assuming the voltage at VBAT is positive, when VOUT is less than VBAT, the current in the inductor increases, and as the current increases, the voltage at the inductor increases due to M HS The voltage drop across the terminals results in a falling SW voltage.

[0172] Fig. 10(a) is a schematic diagram of an apparatus 1000 according to a twelfth embodiment of the present disclosure. In this example, the digital signal D1 includes a plurality of bits. The delta-sigma modulator 204 includes a multi-bit quantizer 1002 configured to generate the digital signal D1.

[0173] FIG10( b ) is a schematic diagram of a specific embodiment of a multi-bit quantizer 1002 . In this embodiment, the multi-bit quantizer 1002 includes an inverter 1004 , which is configured to invert the digital signal D1 before providing it to the output terminal. The multi-bit quantizer 1002 may also include an analog-to-digital converter 1006 .

[0174] In another embodiment, inverter 1004 may be located before ADC 1006. It will be appreciated that there is little practical difference between the two cases as this is largely symbolic; in reality, the "-1" is just part of the overall ADC implementation.

[0175] 11(a) is a schematic diagram of a device 1100 according to a thirteenth embodiment of the present disclosure. The delta-sigma modulator 204 may include a most significant bit digital-to-analog converter (MSBDAC) for generating a first analog output signal used in generating the most significant bit of the digital signal D1; and a least significant bit digital-to-analog converter (LSBDAC) for generating a second analog output signal associated with the least significant bit of the digital signal D1.

[0176] 11( b ) is a schematic diagram of an example embodiment of a sensing element 504 and a summing circuit 502. In this embodiment, the sensing element 504 includes a switch 506 having a resistance; and the summing circuit 502 includes mirror switches 1104, 1106 each having a resistance. A switch triad is formed by switches 506, 1104, 1106, with current I1 flowing through switch 506; current I2 flowing through switch 1104; current I3 flowing through switch 1106, switch 1104 relates to the most significant bit, and switch 1106 relates to the least significant bit.

[0177] 11( c ) is a schematic diagram of an example embodiment of switches 506 , 1104 , 1106 implemented using transistors 510 , 1108 , 1110 , each having its gate coupled to a supply voltage Vdd.

[0178] 12(a) is a schematic diagram of an apparatus 1200 according to a fourteenth embodiment of the present disclosure. In this embodiment, there is a current source 1202 coupled to the mirror transistor 1108 and a current source 1204 coupled to the mirror transistor 1110. The delta-sigma modulator 204 also includes a feedback circuit 1206, which is configured to receive the digital signal D1 and control the current sources 1202, 1204 based on the received digital signal D1. The feedback circuit 1206 may include a feedback digital-to-analog converter control circuit.

[0179] In this example, the most significant bit DAC (MSBDAC) receives input from the quantizer 1002 and includes a current source 1202, a mirror device M LSS,M 、Capacitor C REF,M and capacitor C REF,M In this example, the least significant bit DAC (LSBDAC) receives input from the quantizer 1002 and includes a current source 1204, a mirror device M LSS,L 、Capacitor C REF,L0 , C REF,L1 , C REF,L2 and capacitor C REF,L0 , C REF,L1 , C REF,L2 The associated switch.

[0180] In this example we have 2 sub-DACs:

[0181] 1.2-bit LSB-DAC, including current source 1204I DAC，L 、Capacitor C REF，L0，1，2 (with corresponding switch), and switch M LSS，L ,

[0182] 2.1-bit MSB-DAC, including current source 1202I DAC，M 、Capacitor CREF，M (with corresponding switch), and switch M LSS，M .

[0183] The bitstream output of the delta-sigma modulator will have noise shaping, which means that the quantization noise contribution will be low at low frequencies and will increase for high frequencies. As with most delta-sigma modulators, decimation and filtering are required to extract a higher resolution version of the current slope, which necessarily results in a smaller output data rate with a smaller bandwidth. One potential way to increase the bandwidth is to reduce the OSR (oversampling rate), but if no other changes are made, this will increase the noise and thus increase the resolution of the output. A common way to increase the effective resolution is to use a multi-bit quantizer, such as provided in the present embodiment.

[0184] In this embodiment, a single bit data stream DS L Replaced with a multi-bit stream. The comparator 610 has been replaced by a multi-bit quantizer 1002 (typically a flash ADC or similar). This means that the feedback to the circuit is also multi-bit, and there are 3 ways to apply this feedback:

[0185] 1) Multiple I DAC element,

[0186] 2) Multiple Cs REF components, the possible sharing of their switches depends on charge injection and parasitic capacitance issues,

[0187] 3) Multiple M LSS element.

[0188] These elements will switch in and out based on the DAC code. Any of the above elements can be weighted. Any combination of the above can also be used, with different weights, thus dividing the DAC resolution into several sub-fields that are applied to the different element arrays above.

[0189] The clock DS fed to the quantizer 1006 CLK The frequency is usually the same as the switching converter frequency or a multiple of it.

[0190] FIG12( b) is a graph showing the transfer characteristic of the multi-bit quantizer 1002. The inversion before the multi-bit quantizer 1002 is to indicate that the feedback needs to be in the opposite direction. In practice, this means that the transfer characteristic of the quantizer is as shown in FIG12( b) (for a 3-bit pure negative quantizer with inversion).

[0191] As shown in the figure, the output of the quantizer changes monotonically as the voltage value decreases. For example, when the voltage is -V REF / 14 crosses, the output changes from 000 to 001. In this case, the lower 2 bits will be fed back through the first (LSB) branch, and the upper 1 bit will be fed back through the second (MSB) branch. The 2 LSB bits will determine the CREF corresponding to the LSB branch and the number of switches turned on, and the corresponding MSB bit will determine whether the MSB branch is turned on. As mentioned above, by changing its C REF,M 、M LSS,M , or DAC,M , the second branch will be weighted appropriately (4x).

[0192] Since the output of integrator 602 does not rise positively (assuming the slope at SW is positive), for this example, the positive half does not need to be quantized. It should be noted that in another embodiment with a negative slope (such as buck-boost), this will be flipped (positive side rising, negative side flat to 0).

[0193] In this example, M is measured in the LS phase. LS voltage across the terminals. This works best when the width of the LS phase exceeds that of the HS phase. For cases where the HS phase is significantly larger than the LS phase (e.g., a buck converter operating at nearly full duty cycle, since V OUT Only V BAT Slightly lower), usually in the HS path device M HS It is more efficient to measure the same signal on

[0194] For the following switches, we can have an inverted voltage slope compared to each of the above configurations:

[0195] 1) LS side operation at negative terminal voltage

[0196] 2) HS side operation at negative terminal voltage

[0197] 3) Buck-Boost, where both sides of HS are active. Depends on V BAT and V OUT The relative difference between the current and the slope can be in either direction.

[0198] This can be done by REF The switch connections were changed slightly to accommodate.

[0199] Figure 13(a) is used for Figure 7 A schematic diagram of a reference capacitor portion of a low-side switch sensing apparatus 700 is shown.

[0200] Figure 13(b) is used for Fig. 9 A schematic diagram of a reference capacitor portion of a high-side switch sensing apparatus 900 is shown.

[0201] In the two cases shown in Figure 13(a) and Figure 13(b), the input switches can be swapped and the phase can be changed to the following timing. This will result in φ 5a and φ 6a of removal, because now M LSS / M HSS and I DAC Also serving the same purpose.

[0202] FIG. 13( c ) is a schematic diagram of an alternative embodiment of a reference capacitor portion that may replace Figure 7 and Fig. 9 of the reference capacitor section.

[0203] FIG. 13( d ) is a schematic diagram of an embodiment of a reference capacitor portion applicable to a buck-boost converter.

[0204] Switches marked with “:n” are for normal operation and “:i” are for reverse operation. 6b is common. Note that the timing should be reconfigured according to the situation and will be generated appropriately using the timing generator.

[0205] It should be understood that for a typical switching converter, there may be multiple switches. For example, in a buck converter, there may be both LS sensing and HS sensing. In some cases, one or more of the switches may be omitted if there is redundancy in the information. For example, in a buck converter, both switches pass the same information. If the input V IN The voltage is significantly higher than V OUT , the typical duty cycle will be lower (M LS The opening time will be significantly longer than M HS ), and measure M HS The current circuit can be omitted because M HS Phase ratio M LS The phases are much shorter and provide no value.

[0206] Embodiments of the present disclosure can also be used to estimate the equivalent inductance under the prevailing operating conditions. This information can be used to:

[0207] 1. Monitor circuit characteristics, including component aging.

[0208] a) Inductance of the inductor

[0209] 2. It is possible to estimate the true inductance curve as a function of current, allowing adaptive tuning.

[0210] Fig.14 is a timing diagram 1400 showing a timing diagram for use with the buck converter 402 of FIG. 4( a) and using the reference capacitor portion of FIG. 13( c) Fig. 914. Example operation of the delta-sigma modulator 204. The high-side switch control signal (trace 1402); the low-side switch control signal (trace 1404); the current flowing through the inductor (trace 1405); the current flowing through the low-side switch M LS The current (trace 1406); the voltage at the switch node SW (trace 1408); the clock signal DS CLK (also labeled CLK in other embodiments and shown by trace 1410); and provided to Fig. 9 The control signals of the switches shown are labeled as follows φ1 (trace 1412), φ2 (trace 1414), φ4 (trace 1416), φ5 (trace 1418), φ6 (trace 1420); and the digital signal D1 (also labeled DS L , and shown by trace 1422).

[0211] Fig.15 yes Figure 7 An alternative schematic diagram of apparatus 700 is shown. Fig.16 is a timing diagram 1600 showing a timing diagram for use with the buck converter 402 of FIG. 4( a ) Fig.15 15. Example operation of the delta-sigma modulator 204. The high-side switch control signal (trace 1502); the low-side switch control signal (trace 1504); the current flowing through the inductor (trace 1505); the current flowing through the low-side switch M LS The current (trace 1506); the voltage at the switch node SW (trace 1508); the clock signal DS CLK (also labeled CLK in other embodiments and shown by trace 1510); and provided to Fig.15 The control signals of the switches shown are labeled as follows φ1 (trace 1512), φ2 (trace 1514), φ4 (trace 1516), φ5 (trace 1518), φ6 (trace 1520); the digital signal D1 (also labeled DS L , and is shown by trace 1522); capacitor C S The voltage across the capacitor C is shown by trace 1524; REF The voltage across the capacitor C INT The voltage across the terminals (also labeled by numeral 608 and shown by trace 1528); the integrated voltage signal V INTEG (also labeled by reference numeral 603 and illustrated by trace 1530).

[0212] When the low-side switch control signal LS is low, the circuit does not operate, the voltage across the capacitor remains at the same level, and as a result everything remains "frozen".

[0213] When the low-side switch control signal LS becomes high, MLS Driven to open (M LSS Always on). LS Flowing through M LS , in M LS A voltage develops across SW, which can be seen at node SW relative to ground.

[0214] We initially assume that φ1 is low and φ2 is high. In this case, capacitor C S Connect to ground and analog common mode (ACM).

[0215] Once φ1 goes high, capacitor C S The charging starts and will track the voltage at node SW. In normal closed-loop operation, the voltage at the virtual CM is maintained at ACM (assuming an ideal A INTEG ). Therefore φ2 does not affect the capacitor C S The voltage at the negative terminal. Therefore, we can assume that the capacitor C S The charging / tracking operation of depends only on φ1. We keep φ1 active only during the LS period, and this helps to isolate the delta-sigma converter 204 from the switching noise on node SW during the HS phase.

[0216] φ2 is only active for a subset of φ1. During this phase, the current flowing through capacitor C S The current will flow through the capacitor C through the corresponding switch INT This means that during this φ2 period, the actual signal on node SW is only sampled to the integrating capacitor C INT superior.

[0217] Note that capacitor C S , C INT are in series, the polarity is the same, so we see that during the low phase φ2, C INT The voltage change across the terminals will be,

[0218]

[0219] It can be seen that the charge Q in the capacitor = CV moves to the capacitor C S The charge in the capacitor moves to C INT The charges in are the same.

[0220] This is accumulated (integrated) in the loop. Output V INTEG Will be (ACM-V CINT ).

[0221] This φ2 sampling operation is referred to herein as a correlated double sampling operation because two samples are taken (when φ2 falls, then when φ2 rises). As described above, the difference between these two points is the only portion that is sampled into the integrating capacitor.

[0222] Now, we follow the reference path. We assume that the output of the integrator (V INTEG ) is initially slightly negative. This results in A COMP Output in DS CLK The upper assertion is high, as shown in the figure, causing φ4, φ5, and φ6 to switch as shown in the figure. φ4 drives the current through M LSS , resulting in a voltage V on the feedback node shown FB .

[0223] When φ5 becomes high, it will cause the voltage V FB is sampled to capacitor C REF The polarity is noted in the timing diagram. This voltage is retained because even if φ5 is off, the charge has nowhere to go until φ6 goes high. At this point, the charge is held high by A INTEG In normal operation of closed loop operation, it charges capacitor C INT Discharge. As with the above changes, we get capacitor C INT changes, but in the opposite direction, because φ6 causes the capacitor C INT Discharge in the opposite direction. Therefore, when φ6 becomes high, it causes capacitor C INT The sudden drop of V INTEG corresponding increase).

[0224] Since V INTEG The change of V INTEG The absolute voltage now becomes positive and comparator 610 is switched to the next DS CLK The edge will not become high level, so φ4, φ5, φ6 will not become high, so V INTEG There are no negative jumps.

[0225] Over an extended period of time, the accumulated magnitude of the negative jumps should match the amount of the positive change, so by accumulating the pulses from comparator 610 we can estimate the change in node SW, and therefore the current slope.

[0226] Note that we assume that the gain and bandwidth of the differential amplifier 604 are infinite, so this is an ideal diagram.

[0227] Fig.174( a) is a schematic diagram of an apparatus 1700 according to a fifteenth embodiment of the present disclosure. In this example, a specific embodiment of a delta-sigma modulator 204 used with the buck converter 402 of FIG. 4( a) is shown. It should be understood that only the high-side switch M of the buck converter 402 HS and driver 408 are shown to aid clarity of drawing and description. Fig.18 is a timing diagram 1800 showing a timing diagram for use with the buck converter 402 of FIG. 4( a ) Fig.17 Example operation of delta-sigma modulator 204.

[0228] Various improvements and modifications may be made to the above without departing from the scope of the present disclosure.

Claims

1. An apparatus for generating a digital signal, the digital signal being dependent on an average slope of a first current flowing through a circuit element during a sampling period, the apparatus comprising: A delta-sigma modulator, the delta-sigma modulator being configured as: sensing the first current during the sampling period; and The digital signal is generated using the sensed first current.

2. The device according to claim 1, wherein: The delta-sigma modulator is configured to sense the first current flowing through the circuit element of the switching converter.

3. The device according to claim 2, wherein: The delta-sigma modulator is configured to sense the first current flowing through the circuit element by sensing a current flowing through a first power switch of the switching converter.

4. The device according to claim 1, wherein: The delta-sigma modulator is configured as: sensing the first current at a first time step and a second time step within the sampling period; and The digital signal is generated using the first current sensed at the first time step and at the second time step.

5. The device according to claim 4, wherein: The delta-sigma modulator comprises: A summing circuit, the summing circuit being configured as: sensing the first current at the first time step by measuring a first voltage across a sensing element at the first time step; sensing the first current at the second time step by measuring the first voltage across the sensing element at the second time step; generating a differential signal that is dependent upon subtracting the first voltage at the second time step from the first voltage at the first time step; in: The first voltage depends on the first current.

6. The device according to claim 5, wherein: The sensing element includes a first switch having a first resistance; The summing circuit includes a mirror switch having a second resistance and forms a switch pair including the first switch and the mirror switch.

7. The device according to claim 6, wherein: The first switch comprises a first transistor; and The mirror switch comprises a second transistor; wherein: A gate of each of the first transistor and the second transistor is configured to receive a power supply voltage.

8. The device according to claim 7, wherein: The summing circuit comprises: A first capacitor, the first capacitor having: The first terminal: i) coupled to a first terminal of the first transistor via a first switch; and ii) coupled to a ground terminal via a second switch; and The second terminal: i) coupled to the differential node via a third switch; and ii) coupled to the common mode gain terminal via a fourth switch; and A second capacitor, the second capacitor having: The first terminal: i) coupled to the first terminal of the mirror transistor via a fifth switch; and ii) coupled to the common-mode gain terminal via a sixth switch; and The second terminal: i) coupled to the differential node via a seventh switch; and ii) coupled to the ground terminal via an eighth switch.

9. The device according to any one of claims 5 to 8, wherein: The delta-sigma modulator includes a first integration circuit configured to receive the differential signal and generate an integrated voltage signal.

10. The device according to claim 9, wherein: The first integration circuit comprises a first differential amplifier; and / or The delta-sigma modulator includes a first comparator configured to receive the integrated voltage signal and output the digital signal.

11. The device according to any one of claims 1 to 5, wherein: The digital signal includes a plurality of bits.

12. The device according to claim 11, wherein The delta-sigma modulator includes a multi-bit quantizer configured to generate the digital signal.

13. A method of generating a digital signal, the digital signal being dependent on an average slope of a first current flowing through a circuit element during a sampling period, the method comprising: sensing the first current during the sampling period using a delta-sigma modulator; and Using the delta-sigma modulator, the digital signal is generated using the sensed first current.

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