Narrow-band band-pass delta-sigma modulator with low power consumption and high dynamic range
By adopting a multi-stage resonator and variable gain amplifier design in CT-DSM, combining continuous time and discrete time modes, the existing CT-DSM has solved the problems of high power consumption and system instability in large bandwidth and high dynamic range, and a narrowband bandpass delta-sigma modulator with low power consumption and high dynamic range is realized.
Patent Information
- Application Number
- CN202411576568.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-06
- Publication Date
- 2025-02-25
AI Technical Summary
The existing CT-DSM consumes a lot of power when meeting large bandwidth and high dynamic range, and the phase delay introduced by the higher-order loop filters leads to system instability.
Design a low-power high dynamic range narrowband bandpass delta-sigma modulator with first- and second-stage resonators, variable gain amplifiers and third-stage resonators, combined with continuous and discrete-time modes to reduce power consumption of the op amp and simplify the architecture.
It effectively reduces the power consumption and delay of the delta-sigma modulator, and improves the stability and dynamic range of the system.
Smart Images
Figure CN119519719A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-power consumption, high-dynamic range, narrow-band passband delta-sigma modulator. Background Art
[0002] With the development of mobile communication standards, the requirements for analog-to-digital converters (ADCs) in communication systems are constantly increasing. In addition to requiring a larger operating bandwidth and dynamic range, the ADC is also required to have lower power consumption.
[0003] The continuous-time Delta-Sigma modulator (CT-DSM) is a commonly used ADC structure that achieves high conversion accuracy by using oversampling, noise shaping, and digital filtering techniques. However, CT-DSM can only work at a low oversampling rate while meeting the requirements of large bandwidth and high dynamic range. To this end, we need to optimize the noise performance of the modulator, which requires the introduction of a high-order noise transfer function (high-order NTF), which means that a high-order loop filter is needed.
[0004] However, the phase delay introduced by the high-order loop filter will cause system instability, and the high-order loop filter requires more operational amplifiers, which consume a lot of power, and ultimately lead to high power consumption of the modulator. In order to avoid using too high-order loop filters, multi-bit quantizers are generally used in the modulator system, but multi-bit quantizers also have disadvantages such as high power consumption and poor linearity compared to 1-bit quantizers. Summary of the invention
[0005] The purpose of the present invention is to solve the shortcomings in the prior art and to propose a low-power consumption, high-dynamic range, narrow-band passband delta-sigma modulator.
[0006] In order to achieve the above object, the present invention adopts the following technical solutions:
[0007] A low power consumption, high dynamic range, narrow band pass delta-sigma modulator, comprising a first stage resonator, a variable gain amplifier, a second stage resonator, a third stage resonator, a quantizer and a DAC;
[0008] The first-stage resonator is electrically connected to a variable gain amplifier, and the first-stage resonator has low noise and high Q value characteristics;
[0009] The variable gain amplifier is electrically connected to the second-stage resonator, the variable gain amplifier is located between the first-stage resonator and the second-stage resonator, and the variable gain amplifier is used to adjust the output amplitude of the first-stage resonator to avoid saturation of the second-stage resonator;
[0010] The output end of the second-stage resonator is electrically connected to a resistor R3, the other end of the resistor R3 is electrically connected to a switch S1, and the other end of the switch S1 is electrically connected to the third-stage resonator; the working mode of the second-stage resonator is continuous time, and the second-stage resonator works in the continuous time mode, which can reduce the power consumption of the operational amplifier U2, and adopt a feedforward structure to reduce the number of DACs to further reduce power consumption and simplify the architecture;
[0011] The output end of the third-stage resonator is electrically connected to the quantizer. In order to ensure a high Q value, the third-stage resonator operates in a discrete time mode. The first-stage resonator, the variable gain amplifier, the second-stage resonator, the third-stage resonator, and the quantizer are all electrically connected to the DAC.
[0012] Preferably, the first-stage resonator is located outside the chip, and the first-stage resonator is composed of an off-chip capacitor C1 and an off-chip inductor L1, and one end of the capacitor C1 and one end of the inductor L1 are both grounded;
[0013] The variable gain amplifier is a VGA signal amplifier U1 , and the other end of the capacitor C1 and the other end of the inductor L1 are both electrically connected to the input end of the VGA signal amplifier U1 .
[0014] Preferably, the second-stage resonator includes a resistor 1 R1, a resistor 2 R2, an operational amplifier 2 U2, a comparator 1 Q1, a comparator 2 Q2, a capacitor 2 C2, and a capacitor 3 C3;
[0015] The input end of the comparator Q1 is electrically connected to the output end of the VGA signal amplifier U1, one end of the resistor R1 and one end of the capacitor C2 are electrically connected to the reverse input end of the comparator Q1, the output end of the comparator Q1 is electrically connected to one end of the resistor R2, one end of the capacitor C3 and the reverse input end of the comparator Q2 are both electrically connected to the other end of the resistor R2, the positive input end of the comparator Q2 is grounded, the output end of the comparator Q2 and the other end of the capacitor C3 are both electrically connected to one end of the operational amplifier U2, and the other end of the operational amplifier U2 is electrically connected to the other end of the resistor R1.
[0016] Preferably, the output end of the comparator 2 Q2 is electrically connected to the resistor 3 R3, the other end of the switch 1 S1 is electrically connected to one end of the switch 2 S2, the other end of the switch 2 S2 is grounded, one end of the switch 1 S1 is electrically connected to the resistor 4 R4, the other end of the resistor 4 R4 is electrically connected to the operational amplifier 4 U4, and the other end of the operational amplifier 4 U4 is electrically connected to the other end of the capacitor 2 C2.
[0017] Preferably, the third-stage resonator includes capacitor four C4, capacitor five C5, capacitor six C6, capacitor seven C7, capacitor eight C8, switch two S2, switch three S3, switch four S4, switch five S5, switch six S6, switch seven S7, switch eight S8, switch nine S9, switch ten S10, operational amplifier three U3, comparator three Q3, and comparator four Q4;
[0018] One end of the capacitor C4 is electrically connected to the other end of the switch S1, one end of the switch S4 and one end of the switch S3 are both electrically connected to the other end of the capacitor C4, the inverting input end of the comparator Q3 and one end of the capacitor C6 are both electrically connected to the other end of the switch S4, the output end of the comparator Q3 and the other end of the capacitor C6 are both electrically connected to one end of the switch S7, one end of the switch S8 and the other end of the switch S7 are both electrically connected to one end of the capacitor C7, and the other end of the capacitor C7 and one end of the switch S9 are both electrically connected to one end of the switch S10 The other end of the switch S10 and one end of the capacitor C8 are both electrically connected to the inverting input end of the comparator Q4, the output end of the comparator Q4 and one end of the capacitor C8 are both electrically connected to one end of the operational amplifier U3, the other end of the operational amplifier U3 is electrically connected to one end of the switch S6, the other end of the switch S6 and one end of the switch S5 are both electrically connected to one end of the capacitor C5, the positive input end of the comparator Q3 and the positive input end of the comparator Q4 are both grounded, and the other ends of the switch S3, the switch S5, the switch S8, and the switch S9 are all grounded.
[0019] Preferably, the quantizer adopts a flash architecture, and the output end of the comparator Q4 is electrically connected to the input end of the quantizer.
[0020] Preferably, the DAC is composed of a current steering DAC 1, a current steering DAC 2, a capacitor array DAC 3 and a capacitor array DAC 4;
[0021] One end of the current steering DAC 1 is electrically connected to the input end of the VGA signal amplifier U1, one end of the current steering DAC 2 is electrically connected to the reverse input end of the comparator Q1, one end of the capacitor array DAC 3 is electrically connected to one end of the capacitor five C5, one end of the capacitor array DAC 4 is electrically connected to the other end of the capacitor seven C7, and the current steering DAC 1, current steering DAC 2, capacitor array DAC 3 and capacitor array DAC 4 are all electrically connected to the output end of the quantizer.
[0022] The beneficial effects of the present invention are:
[0023] In the present invention, through the design of a first-stage resonator, a variable gain amplifier, a second-stage resonator, a third-stage resonator, a quantizer and a DAC, the variable gain amplifier is located between the first-stage resonator and the second-stage resonator, the variable gain amplifier is used to adjust the output amplitude of the first-stage resonator to avoid saturation of the second-stage resonator, the working mode of the second-stage resonator is continuous time, and the second-stage resonator works in a continuous time mode, which can reduce the power consumption of the operational amplifier U2, and adopt a feedforward structure to reduce the number of DACs to further reduce power consumption and simplify the architecture, and finally effectively reduce the power consumption and delay of the delta-sigma modulator. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 The present invention is a schematic structural diagram of a low-power, high-dynamic-range, narrow-band-pass delta-sigma modulator.
[0025] Numbers in the figure: 100, first-stage resonator; 200, variable gain amplifier; 300, second-stage resonator; 400, third-stage resonator; 500, quantizer; 600, DAC; 601, current-steering DAC one; 602, current-steering DAC two; 603, capacitor array DAC three; 604, capacitor array DAC four. DETAILED DESCRIPTION
[0026] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.
[0027] As attached Figure 1 As shown:
[0028] A low power consumption, high dynamic range, narrow band pass delta-sigma modulator, comprising a first stage resonator 100, a variable gain amplifier 200, a second stage resonator 300, a third stage resonator 400, a quantizer 500 and a DAC 600;
[0029] The first-stage resonator 100 is electrically connected to the variable gain amplifier 200, and the first-stage resonator 100 has low noise and high Q value characteristics;
[0030] The variable gain amplifier 200 is electrically connected to the second-stage resonator 300. The variable gain amplifier 200 is located between the first-stage resonator 100 and the second-stage resonator 300. The variable gain amplifier 200 is used to adjust the output amplitude of the first-stage resonator 100 to avoid saturation of the second-stage resonator 300.
[0031] The output end of the second-stage resonator 300 is electrically connected to a resistor R3, the other end of the resistor R3 is electrically connected to a switch S1, and the other end of the switch S1 is electrically connected to the third-stage resonator 400; the working mode of the second-stage resonator 300 is continuous time. When the second-stage resonator 300 works in the continuous time mode, the power consumption of the operational amplifier U2 can be reduced. The feedforward structure is used to reduce the number of DACs to further reduce power consumption and simplify the architecture;
[0032] The output end of the third-stage resonator 400 is electrically connected to the quantizer 500. In order to ensure a high Q value, the third-stage resonator 400 operates in a discrete time mode. The first-stage resonator 100, the variable gain amplifier 200, the second-stage resonator 300, the third-stage resonator 400, and the quantizer 500 are all electrically connected to the DAC 600.
[0033] The first-stage resonator 100 is located outside the chip. The first-stage resonator 100 is composed of an off-chip capacitor C1 and an off-chip inductor L1. One end of the capacitor C1 and one end of the inductor L1 are both grounded.
[0034] The variable gain amplifier 200 is a VGA signal amplifier U1 , and the other end of the capacitor C1 and the other end of the inductor L1 are both electrically connected to the input end of the VGA signal amplifier U1 .
[0035] The second-stage resonator 300 includes a resistor 1 R1, a resistor 2 R2, an operational amplifier 2 U2, a comparator 1 Q1, a comparator 2 Q2, a capacitor 2 C2, and a capacitor 3 C3;
[0036] The input end of comparator Q1 is electrically connected to the output end of VGA signal amplifier U1, one end of resistor R1 and one end of capacitor C2 are electrically connected to the reverse input end of comparator Q1, the output end of comparator Q1 is electrically connected to one end of resistor R2, one end of capacitor C3 and the reverse input end of comparator Q2 are both electrically connected to the other end of resistor R2, the positive input end of comparator Q2 is grounded, the output end of comparator Q2 and the other end of capacitor C3 are both electrically connected to one end of operational amplifier U2, and the other end of operational amplifier U2 is electrically connected to the other end of resistor R1.
[0037] Preferably, the output end of the comparator 2 Q2 is electrically connected to the resistor 3 R3, the other end of the switch 1 S1 is electrically connected to one end of the switch 2 S2, the other end of the switch 2 S2 is grounded, one end of the switch 1 S1 is electrically connected to the resistor 4 R4, the other end of the resistor 4 R4 is electrically connected to the operational amplifier 4 U4, and the other end of the operational amplifier 4 U4 is electrically connected to the other end of the capacitor 2 C2.
[0038] The third-stage resonator 400 includes a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6, a switch S7, a switch S8, a switch S9, a switch S10, an operational amplifier U3, a comparator Q3, and a comparator Q4;
[0039] One end of the capacitor C4 is electrically connected to the other end of the switch S1, one end of the switch S4 and one end of the switch S3 are both electrically connected to the other end of the capacitor C4, the inverting input end of the comparator Q3 and one end of the capacitor C6 are both electrically connected to the other end of the switch S4, the output end of the comparator Q3 and the other end of the capacitor C6 are both electrically connected to one end of the switch S7, one end of the switch S8 and the other end of the switch S7 are both electrically connected to one end of the capacitor C7, and the other end of the capacitor C7 and one end of the switch S9 are both electrically connected to one end of the switch S10 , the other end of the switch S10 and one end of the capacitor C8 are both electrically connected to the reverse input end of the comparator Q4, the output end of the comparator Q4 and one end of the capacitor C8 are both electrically connected to one end of the operational amplifier U3, the other end of the operational amplifier U3 is electrically connected to one end of the switch S6, the other end of the switch S6 and one end of the switch S5 are both electrically connected to one end of the capacitor C5, the positive input end of the comparator Q3 and the positive input end of the comparator Q4 are both grounded, and the other ends of the switch S3, the switch S5, the switch S8, and the switch S9 are all grounded.
[0040] The quantizer 500 adopts a flash architecture, and the output end of the comparator Q4 is electrically connected to the input end of the quantizer 500 .
[0041] DAC600 is composed of current steering DAC 1 601, current steering DAC 2 602, capacitor array DAC 3 603 and capacitor array DAC 4 603;
[0042] One end of the current steering DAC 601 is electrically connected to the input end of the VGA signal amplifier U1, one end of the current steering DAC 2 602 is electrically connected to the reverse input end of the comparator Q1, one end of the capacitor array DAC 3 603 is electrically connected to one end of the capacitor C5, one end of the capacitor array DAC 4 604 is electrically connected to the other end of the capacitor C7, and the current steering DAC 1 601, the current steering DAC 2 602, the capacitor array DAC 3 603 and the capacitor array DAC 4 603 are all electrically connected to the output end of the quantizer 500.
[0043] The specific usage and function of this embodiment are as follows:
[0044] The test signal in the present invention is a single tone signal, the test frequency is 200MHz, and the Transceiver chip is YXWIF700;
[0045] Reference Figure 1 , the implementation method of the present invention includes:
[0046] S1, after the input voltage signal is converted into a current signal by the LNA and the mixer, it is converted into a voltage signal by the first-stage resonator 100 outside the chip;
[0047] S2, the difference between the first stage resonator 100 and the DAC 600 is amplified by the variable gain amplifier 200 and input to the next stage;
[0048] S3, the difference between the output of the variable gain amplifier 200 and the DAC 600 is modulated by the second stage resonator 300 continuous time resonator;
[0049] S4, the output of the second-stage resonator 300 is modulated by the third-stage resonator 400;
[0050] S5 . The output of the third-stage resonator 400 is converted by the quantizer 500 .
[0051] For the above structure and process, please refer to Figure 1 .
[0052] The above are only preferred specific implementation modes of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solutions and inventive concepts of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.
Claims
1. A low power consumption, high dynamic range, narrow-band passband delta-sigma modulator, characterized in that: It includes a first-stage resonator (100), a variable gain amplifier (200), a second-stage resonator (300), a third-stage resonator (400), a quantizer (500) and a DAC (600); The first-stage resonator (100) is electrically connected to the variable gain amplifier (200), and the first-stage resonator (100) has low noise and high Q value characteristics; The variable gain amplifier (200) is electrically connected to the second-stage resonator (300), the variable gain amplifier (200) is located between the first-stage resonator (100) and the second-stage resonator (300), and the variable gain amplifier (200) is used to adjust the output amplitude of the first-stage resonator (100) to avoid saturation of the second-stage resonator (300); The output end of the second-stage resonator (300) is electrically connected to a resistor R3, the other end of the resistor R3 is electrically connected to a switch S1, and the other end of the switch S1 is electrically connected to the third-stage resonator (400); the working mode of the second-stage resonator (300) is continuous time, and the second-stage resonator (300) works in the continuous time mode, which can reduce the power consumption of the operational amplifier U2, and adopt a feedforward structure to reduce the number of DACs to further reduce power consumption and simplify the architecture; The output end of the third-stage resonator (400) is electrically connected to the quantizer (500). In order to ensure a high Q value, the third-stage resonator (400) operates in a discrete time mode. The first-stage resonator (100), the variable gain amplifier (200), the second-stage resonator (300), the third-stage resonator (400), and the quantizer (500) are all electrically connected to a DAC (600).
2. A low power consumption, high dynamic range, narrow-band passband delta-sigma modulator according to claim 1, characterized in that: The first-stage resonator (100) is located outside the chip, and the first-stage resonator (100) is composed of an off-chip capacitor C1 and an off-chip inductor L1, and one end of the capacitor C1 and one end of the inductor L1 are both grounded; The variable gain amplifier (200) is a VGA signal amplifier U1, and the other end of the capacitor C1 and the other end of the inductor L1 are both electrically connected to the input end of the VGA signal amplifier U1.
3. A low power consumption, high dynamic range, narrow-band passband delta-sigma modulator according to claim 2, characterized in that: The second-stage resonator (300) comprises a resistor 1 R1, a resistor 2 R2, an operational amplifier 2 U2, a comparator 1 Q1, a comparator 2 Q2, a capacitor 2 C2, and a capacitor 3 C3; The input end of the comparator Q1 is electrically connected to the output end of the VGA signal amplifier U1, one end of the resistor R1 and one end of the capacitor C2 are electrically connected to the reverse input end of the comparator Q1, the output end of the comparator Q1 is electrically connected to one end of the resistor R2, one end of the capacitor C3 and the reverse input end of the comparator Q2 are both electrically connected to the other end of the resistor R2, the positive input end of the comparator Q2 is grounded, the output end of the comparator Q2 and the other end of the capacitor C3 are both electrically connected to one end of the operational amplifier U2, and the other end of the operational amplifier U2 is electrically connected to the other end of the resistor R1.
4. A low power consumption, high dynamic range, narrow-band passband delta-sigma modulator according to claim 3, characterized in that: The output end of the comparator 2 Q2 is electrically connected to the resistor 3 R3, the other end of the switch 1 S1 is electrically connected to one end of the switch 2 S2, the other end of the switch 2 S2 is grounded, one end of the switch 1 S1 is electrically connected to the resistor 4 R4, the other end of the resistor 4 R4 is electrically connected to the operational amplifier 4 U4, and the other end of the operational amplifier 4 U4 is electrically connected to the other end of the capacitor 2 C2.
5. A low power consumption, high dynamic range, narrow band pass delta-sigma modulator according to claim 4, characterized in that: The third-stage resonator (400) comprises a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6, a switch S7, a switch S8, a switch S9, a switch S10, an operational amplifier U3, a comparator Q3, and a comparator Q4; One end of the capacitor C4 is electrically connected to the other end of the switch S1, one end of the switch S4 and one end of the switch S3 are both electrically connected to the other end of the capacitor C4, the inverting input end of the comparator Q3 and one end of the capacitor C6 are both electrically connected to the other end of the switch S4, the output end of the comparator Q3 and the other end of the capacitor C6 are both electrically connected to one end of the switch S7, one end of the switch S8 and the other end of the switch S7 are both electrically connected to one end of the capacitor C7, and the other end of the capacitor C7 and one end of the switch S9 are both electrically connected to one end of the switch S10 The other end of the switch S10 and one end of the capacitor C8 are both electrically connected to the inverting input end of the comparator Q4, the output end of the comparator Q4 and one end of the capacitor C8 are both electrically connected to one end of the operational amplifier U3, the other end of the operational amplifier U3 is electrically connected to one end of the switch S6, the other end of the switch S6 and one end of the switch S5 are both electrically connected to one end of the capacitor C5, the positive input end of the comparator Q3 and the positive input end of the comparator Q4 are both grounded, and the other ends of the switch S3, the switch S5, the switch S8, and the switch S9 are all grounded.
6. A low power consumption, high dynamic range, narrow-band passband delta-sigma modulator according to claim 5, characterized in that: The quantizer (500) adopts a flash architecture, and the output end of the comparator Q4 is electrically connected to the input end of the quantizer (500).
7. A low power consumption, high dynamic range, narrow-band passband delta-sigma modulator according to claim 6, characterized in that: The DAC (600) is composed of a current steering DAC 1 (601), a current steering DAC 2 (602), a capacitor array DAC 3 (603) and a capacitor array DAC 4 (603); One end of the current steering DAC 1 (601) is electrically connected to the input end of the VGA signal amplifier U1, one end of the current steering DAC 2 (602) is electrically connected to the reverse input end of the comparator 1 Q1, one end of the capacitor array DAC 3 (603) is electrically connected to one end of the capacitor 5 C5, one end of the capacitor array DAC 4 (604) is electrically connected to the other end of the capacitor 7 C7, and the current steering DAC 1 (601), the current steering DAC 2 (602), the capacitor array DAC 3 (603) and the capacitor array DAC 4 (603) are all electrically connected to the output end of the quantizer (500).