Circuit board manufacturing method and circuit board
By cutting and reducing thin layers on the dielectric layer of the circuit board and setting a resistor layer, the problem of poor electrical connection quality when buried resistors is solved, and high reliability and thin circuit board production is achieved.
Patent Information
- Application Number
- CN202311083551.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-24
- Publication Date
- 2025-02-25
AI Technical Summary
When the resistor is buried in the circuit board, it is difficult to ensure the quality of the electrical connection, and it is difficult to assemble, which affects the thickness and reliability of the circuit board.
By cutting and reducing thin layers on the dielectric layer of the circuit board, forming blind holes and setting a resistive layer therein, connecting the resistive layer with the copper layer, and subsequently pressing the circuit board to achieve electrical connection.
This method does not require opening holes to set conductive holes, which improves the reliability of electrical connections and reduces the overall thickness of the circuit board through the buried resistor layer.
Smart Images
Figure CN119521570A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of circuit boards, and in particular to a method for manufacturing a circuit board and a circuit board. Background Art
[0002] As a kind of passive component, the resistor can be embedded in the circuit board to reduce the thickness of the circuit board. However, when the resistor is embedded in the circuit board, the resistor needs to be electrically connected to the circuit board. As the component is reduced in size, the assembly is difficult and it is difficult to ensure the quality of the electrical connection. Summary of the invention
[0003] A method for manufacturing a circuit board includes the following steps: providing a first substrate, including a first dielectric layer and a first copper layer, wherein the first copper layer is located on the surface of the first dielectric layer; cutting part of the first dielectric layer along the direction in which the first dielectric layer and the first copper layer are stacked, so as to reduce the thickness of the first dielectric layer in a part of the region, thereby forming a thinned layer; forming two blind holes on the thinned layer, wherein the first copper layer is exposed to the blind holes; forming a resistor layer in the blind holes and on the surface of the first dielectric layer between the two blind holes, wherein the resistor layer is connected to the first copper layer; providing an adhesive layer and a second substrate, and arranging the adhesive layer between the second substrate and the surface of the first substrate having the resistor layer, and pressing them together to form a circuit board.
[0004] In some embodiments of the present application, the resistance layer extends to the surface of the first dielectric layer in an area where the first dielectric layer is not thinned.
[0005] In some embodiments of the present application, the manufacturing method also includes performing circuit manufacturing on the first copper layer to form a first circuit layer, wherein at least a portion of the surface of the thinning layer is exposed to the first circuit layer; and covering the first circuit layer and the surface of the first dielectric layer exposed to the first circuit layer with a covering layer.
[0006] In some embodiments of the present application, the manufacturing method further includes forming a via hole penetrating the first substrate and the second substrate, and the via hole also penetrates the resistor layer and is connected to the resistor layer.
[0007] A method for manufacturing a circuit board includes the following steps: providing a first circuit substrate, including a first dielectric layer and a first circuit layer, wherein the first circuit layer is located on the surface of the first dielectric layer; cutting part of the first dielectric layer to reduce the thickness of the first dielectric layer in a part of the area, thereby forming a thinned layer; forming two blind holes on the thinned layer, wherein the first circuit layer is exposed to the blind holes; forming a resistor layer in the blind holes and on the surface of the first dielectric layer between the two blind holes, wherein the resistor layer is connected to the first circuit layer; providing an adhesive layer and a second circuit substrate, arranging the adhesive layer between the second circuit substrate and the surface of the first circuit substrate having the resistor layer, and pressing them together to form a circuit board.
[0008] A circuit board includes a first circuit substrate, a resistor layer, an adhesive layer, and a second circuit substrate. The first circuit substrate includes a first dielectric layer and a first circuit layer located on the surface of the first dielectric layer, the first dielectric layer includes a main layer and a thinning layer, the thinning layer is recessed relative to the main layer, and there are blind holes between the two ends of the thinning layer and the main layer; the resistor layer includes a first resistor, the first resistor is located on the surface of the thinning layer away from the first circuit layer and filled in the blind hole, and connected to the first circuit layer; the adhesive layer covers the surface of the first circuit substrate provided with the first resistor; the second circuit substrate is located on the surface of the adhesive layer away from the first circuit substrate.
[0009] In some embodiments of the present application, at least a portion of the surface of the thinned layer facing away from the first resistor is exposed to the first circuit layer.
[0010] In some embodiments of the present application, the resistance layer also includes a second resistor, which extends to the surface of the main layer; the circuit board also includes at least one via hole, which passes through the first circuit substrate and the second circuit substrate and is connected to the second resistor.
[0011] In some embodiments of the present application, one end of the second resistor facing away from the via is connected to the first resistor.
[0012] In some embodiments of the present application, the resistance layer further includes a third resistor, the number of the via holes is at least two, and two ends of the third resistor are connected to two adjacent via holes.
[0013] The circuit board manufactured by the circuit board manufacturing method provided in the embodiment of the present application has a resistor layer buried in the circuit board. During the manufacturing process, the resistor layer is connected to a large area of the copper layer, and the electrical connection can be achieved by subsequently removing the area that does not require electrical connection. Compared with the related art, the present application does not require opening holes to set conductive holes, and the reliability of achieving electrical connection in the present application is high. In addition, the resistor layer of the present application is set on the surface of the thinning layer, which is conducive to the size control of the resistor layer and does not increase the overall thickness of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 A schematic cross-sectional view of a circuit board with embedded resistors provided in the related art of this application.
[0015] Figure 2 A schematic cross-sectional view of the first substrate provided in an embodiment of the present application.
[0016] Figure 3 For Figure 2 A schematic cross-sectional view of a first dielectric layer in a first substrate after being cut.
[0017] Figure 4 For Figure 3 The cross-sectional schematic diagram after a blind hole is formed on the first dielectric layer is shown.
[0018] Figure 5 For Figure 4 The cross-sectional schematic diagram is shown after a resistance layer is formed on the surface of the first dielectric layer.
[0019] Figure 6 In accordance with Figure 5 The cross-sectional schematic diagram shown is a first substrate provided with a resistor layer and an adhesive layer, an intermediate circuit substrate, another adhesive layer, and a second substrate arranged in sequence.
[0020] Figure 7 For pressing Figure 6 A schematic cross-sectional view of the components obtained is shown.
[0021] Figure 8 To form a penetration Figure 7 The first substrate, the resistor layer, the bonding layer, the intermediate circuit substrate, another bonding layer, the conductive hole of the second substrate, and the cross-sectional schematic diagram after the circuit is fabricated are shown.
[0022] Fig. 9 For Figure 8 A schematic cross-sectional view of a circuit board obtained after a solder mask is formed on the structure shown.
[0023] Main component symbols
[0024]
[0025] DETAILED DESCRIPTION
[0026] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other. In the following description, many specific details are set forth to facilitate a full understanding of the present application, and the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.
[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this article are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes all and any combination of one or more related listed items.
[0028] In the embodiments of the present application, for the convenience of description and not to limit the present application, the term "connection" used in the patent application specification and claims of the present application is not limited to physical or mechanical connection, whether direct or indirect. "Up", "down", "above", "below", "left", "right", etc. are only used to indicate relative position relationship. When the absolute position of the described object changes, the relative position relationship also changes accordingly.
[0029] See also Figure 1 The related technology of the present application provides a circuit board 100', including a dielectric layer 81', a circuit layer 82', a glue layer 83' and a resistor 84'. The circuit layer 82' is located at the outer layer of the circuit board 100', the resistor 84' is buried in the dielectric layer 81' and connected to the glue layer 83', and the solder joints on the resistor 84' are electrically connected to the circuit layer 82' through conductive holes 85' that penetrate the dielectric layer 81'. In the process of manufacturing the circuit board 100', the assembly is difficult and it is difficult to ensure the quality of the electrical connection; and the resistor 84' is connected through the conductive hole 85', which makes it difficult to further reduce the thickness of the circuit board 100'.
[0030] See also Figures 2 to 9 The present application embodiment provides a method for manufacturing a circuit board 100 with embedded resistors, which may include the following steps:
[0031] Step S1: Please refer to Figure 2 , providing a first substrate 101 including a first dielectric layer 11 and a first copper layer 13 , wherein the first copper layer 13 is located on a surface of the first dielectric layer 11 .
[0032] In this embodiment, the first copper layer 13 is disposed on one surface of the first dielectric layer 11 . In subsequent processes, the first copper layer 13 is used to form a first circuit layer 132 .
[0033] Step S2: Please refer to Figure 3 , a portion of the first dielectric layer 11 is cut along the direction in which the first dielectric layer 11 and the first copper layer 13 are stacked, so that the thickness of the first dielectric layer 11 in a partial area is reduced, thereby forming a thinned layer 111 .
[0034] After the first dielectric layer 11 is cut, it includes a main layer 113 and a thinning layer 111. The main layer 113 is the area of the first dielectric layer 11 that has not been thinned. The thinning layer 111 is recessed relative to the main layer 113. The number of the thinning layers 111 is not limited to one, but may be multiple, and the multiple thinning layers 111 may be arranged at intervals.
[0035] Step S3: Please refer to Figure 4 , two blind holes 115 are formed on the thinned layer 111 , and the first copper layer 13 is exposed in the blind holes 115 .
[0036] The two blind holes 115 are arranged at intervals, and the two blind holes 115 can be located at two ends of the thinning layer 111 respectively.
[0037] Step S4: Please refer to Figure 5 A resistance layer 20 is formed in the blind hole 115 and on the surface of the first dielectric layer 11 between two blind holes 115 , and the resistance layer 20 is connected to the first copper layer 13 .
[0038] The material of the resistance layer 20 may be phosphorus-nickel alloy.
[0039] The resistor layer 20 may also extend to the surface of the main layer 113 and may be used to form other resistors in subsequent processes.
[0040] Step S5: Please refer to Figure 6 and Figure 7 Two adhesive layers 30, an intermediate circuit substrate 40 and a second substrate 501 are provided, and the first substrate 101 provided with a resistor layer 20, one adhesive layer 30, the intermediate circuit substrate 40, another adhesive layer 30 and the second circuit substrate 50 are stacked and pressed in this order.
[0041] The surface of the first substrate 101 provided with the resistance layer 20 is connected to the adhesive layer 30 .
[0042] The intermediate circuit substrate 40 may be a hard board or a soft board. In this embodiment, the intermediate circuit substrate 40 is a soft board. The adhesive layer 30 may pre-open a window in a region corresponding to the intermediate circuit substrate 40 for forming a bending region.
[0043] The second substrate 501 includes a second dielectric layer 51 and a second copper layer 53 . The second copper layer 53 is located on a surface of the second dielectric layer 51 away from the first substrate 101 . The second copper layer 53 is subsequently used to form a second circuit layer 532 .
[0044] In some embodiments, the number of intermediate circuit substrates 40 is not limited, and may be one or more, or may be omitted, that is, no intermediate circuit substrate 40 is provided. The number of adhesive layers 30 may also change with the number of intermediate circuit substrates 40 .
[0045] Step S6: Please refer to Figure 8 , forming a through hole 61 penetrating the first substrate 101 , the adhesive layer 30 , the intermediate circuit substrate 40 , and the second substrate 501 , and forming a copper plating layer 65 in the through hole 61 to form a conductive hole 60 .
[0046] The copper plating layer 65 may be formed by electroplating, and the copper plating layer 65 connects the first substrate 101 and the second substrate 501. In the process of forming the copper plating layer 65, the copper plating layer 65 may also be formed on the surfaces of the first substrate 101 and the second substrate 501, and the copper plating layer 65 is located on the surfaces of the first copper layer 13 and the second copper layer 53.
[0047] The resistor layer 20 in the blind hole 115 and the resistor layer 20 on the surface of the first dielectric layer 11 can be used together to form the first resistor 21. The through hole 61 can also penetrate the resistor layer 20 on the surface of the main layer 113, and divide the resistor layer 20 on the surface of the main layer 113 into a second resistor 23 and a third resistor 25, the second resistor 23 is connected to the first resistor 21, and the third resistor 25 and the second resistor 23 are spaced apart through the through hole 61. After the copper plating layer 65 is formed, the end of the second resistor 23 facing away from the first resistor 21 is connected to the copper plating layer 65 in the through hole 61 to achieve electrical connection; both ends of the third resistor 25 are connected to the copper plating layer 65 in the through hole 61 to achieve electrical connection.
[0048] Step S7: Please refer again Figure 8 , circuits are fabricated to form a circuit layer.
[0049] The first copper layer 13 and the copper-plated layer 65 located on the surface of the first copper layer 13 are subjected to circuit manufacturing to form a first circuit layer 132, and the first dielectric layer 11 and the first circuit layer 132 form a first circuit substrate 10; the second copper layer 53 and the copper-plated layer 65 located on the surface of the second copper layer 53 are subjected to circuit manufacturing to form a second circuit layer 532, and the second dielectric layer 51 and the second circuit layer 532 form a second circuit substrate 50.
[0050] During the circuit manufacturing process, the first copper layer 13 and the copper plating layer 65 corresponding to the first resistor 21 are etched, and at least part of the surface of the thinned layer 111 is exposed to the first circuit layer 132, and the surfaces of the two ends of the thinned layer 111 are not exposed, so that the two ends of the first resistor 21 are electrically connected to the first circuit layer 132, and the electrical connection reliability is high, and there is no need to consider the precise alignment with the solder joints on the smaller resistor 84' in the related art to achieve electrical connection. During the circuit manufacturing process, the thinned layer 111 also has the function of preventing the first resistor 21 from being etched, and the etching times of the above manufacturing steps are small, and the manufacturing process is small.
[0051] The second resistor 23 and the third resistor 25 are electrically connected via the via hole 60 . During the process of manufacturing the via hole 60 , it can be achieved by deposition over a large area, and the electrical connection reliability is high.
[0052] Step S8: Please refer to Fig. 9 , covering the solder mask 70 to form a circuit board 100.
[0053] The solder resist layer 70 covers the first circuit layer 132 and the first dielectric layer 11 exposed to the first circuit layer 132, and covers the second circuit layer 532 and the second dielectric layer 51 exposed to the second circuit layer 532. The solder resist layer 70 is also filled in the via hole 60.
[0054] Before the step of covering the solder mask 70 , the manufacturing method may further include opening the first circuit substrate 10 and the second circuit substrate 50 to expose a portion of the middle circuit substrate 40 so that the circuit board 100 can be bent in the opening area.
[0055] In other embodiments, the first copper layer 13 may be replaced by the first circuit layer 132, the first circuit layer 132 may be disposed on two opposite surfaces of the first dielectric layer 11, and the second copper layer 53 may be replaced by the second circuit layer 532. Then, the circuit manufacturing step may be omitted in subsequent steps. The specific manufacturing steps may refer to the above manufacturing steps, which will not be described in detail here.
[0056] See also Fig. 9 The embodiment of the present application further provides a circuit board 100, which may include a first circuit substrate 10, a resistor layer 20, one of the adhesive layers 30, an intermediate circuit substrate 40, another adhesive layer 30, and a second circuit substrate 50, which are stacked. The circuit board 100 also includes a via 60 that penetrates the first circuit substrate 10, the resistor layer 20, one of the adhesive layers 30, the intermediate circuit substrate 40, another adhesive layer 30, and the second circuit substrate 50, and the via 60 electrically connects the first circuit substrate 10, the intermediate circuit substrate 40, and the second circuit substrate 50.
[0057] The first circuit substrate 10 includes a first dielectric layer 11 and a first circuit layer 132 located on the surface of the first dielectric layer 11 . The first circuit layer 132 may be located on the surface of the first dielectric layer 11 away from the adhesive layer 30 , or on two opposite surfaces of the first dielectric layer 11 .
[0058] The first dielectric layer 11 includes a main layer 113 and a thinning layer 111. The thinning layer 111 is recessed relative to the main layer 113. Blind holes 115 are provided between the two ends of the thinning layer 111 and the main layer 113. The first circuit layer 132 is exposed in the blind holes 115. The number of the thinning layer 111 can be one or more.
[0059] In this embodiment, the resistor layer 20 includes a first resistor 21, a second resistor 23, and a third resistor 25. In other embodiments, the number of resistors is not limited and can be one or more.
[0060] The first resistor 21 is located on the surface of the thinning layer 111 facing the bonding layer 30 and is filled in the blind hole 115 . The first resistor 21 is connected to the first circuit layer 132 facing away from the bonding layer 30 .
[0061] At least a portion of the surface of the thinned layer 111 facing away from the resistor layer 20 is exposed to the first circuit layer 132 , and surfaces at both ends of the thinned layer 111 are not exposed, so that both ends of the first resistor 21 are electrically connected to the first circuit layer 132 .
[0062] The second resistor 23 is located on the surface of the main layer 113 , one end of which is connected to the first resistor 21 , and the other end of which extends toward the via 60 and is connected to the via 60 .
[0063] In this embodiment, there are multiple via holes 60 . The third resistor 25 is located on the surface of the main layer 113 and between two via holes 60 . Both ends of the third resistor 25 are connected to two different via holes 60 , respectively.
[0064] The second circuit substrate 50 includes a second dielectric layer 51 and a second circuit layer 532 located on the surface of the second dielectric layer 51 .
[0065] In some embodiments, the number of the intermediate circuit substrates 40 is not limited, and may be one or more, or may be omitted.
[0066] The circuit board 100 manufactured by the manufacturing method of the circuit board 100 provided in the embodiment of the present application has the resistor layer 20 embedded in the circuit board 100. During the manufacturing process, the resistor layer 20 is connected to the large area of the copper layer, and the electrical connection can be achieved by subsequently removing the area that does not require electrical connection. Compared with the related art, the present application does not need to drill holes to set the conductive holes 85', and the reliability of achieving electrical connection in the present application is high; in addition, the resistor layer 20 of the present application is set on the surface of the thinning layer 111, which is conducive to the size control of the resistor layer 20 and does not increase the overall thickness of the circuit board 100.
[0067] The above implementation modes are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the above preferred implementation modes, a person skilled in the art should understand that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.
Claims
1. A method for manufacturing a circuit board, characterized in that: The following steps are involved: Providing a first substrate, comprising a first dielectric layer and a first copper layer, wherein the first copper layer is located on a surface of the first dielectric layer; Cutting a portion of the first dielectric layer along a direction in which the first dielectric layer and the first copper layer are stacked, so as to reduce the thickness of the first dielectric layer in a portion of the region, thereby forming a thinned layer; forming two blind holes on the thinned layer, wherein the first copper layer is exposed in the blind holes; forming a resistance layer in the blind hole and on the surface of the first dielectric layer between the two blind holes, wherein the resistance layer is connected to the first copper layer; as well as An adhesive layer and a second substrate are provided, and the adhesive layer is disposed between the second substrate and the surface of the first substrate having the resistance layer and pressed together to form the circuit board.
2. The method for manufacturing a circuit board according to claim 1, characterized in that: The resistance layer extends to the surface of the first dielectric layer in an area where the first dielectric layer is not thinned.
3. The method for manufacturing a circuit board according to any one of claims 1 to 2, characterized in that: The manufacturing method also includes performing circuit manufacturing on the first copper layer to form a first circuit layer, wherein at least a portion of the surface of the thinning layer is exposed to the first circuit layer; and covering the first circuit layer and the surface of the first dielectric layer exposed to the first circuit layer with a covering layer.
4. The method for manufacturing a circuit board according to any one of claims 1 to 2, characterized in that: The manufacturing method further includes forming a via hole penetrating the first substrate and the second substrate, wherein the via hole also penetrates the resistor layer and is connected to the resistor layer.
5. A method for manufacturing a circuit board, characterized in that: The following steps are involved: Providing a first circuit substrate, comprising a first dielectric layer and a first circuit layer, wherein the first circuit layer is located on a surface of the first dielectric layer; Cutting a portion of the first dielectric layer to reduce the thickness of the first dielectric layer in a portion of the region, thereby forming a thinned layer; forming two blind holes on the thinned layer, wherein the first circuit layer is exposed to the blind holes; A resistance layer is formed in the blind hole and on the surface of the first dielectric layer between the two blind holes, wherein the resistance layer is connected to the first circuit layer; as well as An adhesive layer and a second circuit substrate are provided, and the adhesive layer is disposed between the second circuit substrate and the surface of the first circuit substrate having the resistance layer, and the circuit boards are formed by pressing them together.
6. A circuit board, characterized in that: include: A first circuit substrate, comprising a first dielectric layer and a first circuit layer located on a surface of the first dielectric layer, wherein the first dielectric layer comprises a main layer and a thinning layer, wherein the thinning layer is recessed relative to the main layer, and a blind hole is provided between two ends of the thinning layer and the main layer; A resistor layer, comprising a first resistor, wherein the first resistor is located on a surface of the thinning layer away from the first circuit layer and is filled in the blind hole and connected to the first circuit layer; an adhesive layer covering a surface of the first circuit substrate on which the first resistor is disposed; as well as The second circuit substrate is located on the surface of the bonding layer away from the first circuit substrate.
7. The circuit board according to claim 6, characterized in that: At least a portion of a surface of the thinned layer facing away from the first resistor is exposed to the first circuit layer.
8. The circuit board according to claim 6, characterized in that: The resistor layer also includes a second resistor, which extends to the surface of the main layer; the circuit board also includes at least one via hole, which passes through the first circuit substrate and the second circuit substrate and is connected to the second resistor.
9. The circuit board according to claim 8, characterized in that: One end of the second resistor away from the via is connected to the first resistor.
10. The circuit board according to claim 8, characterized in that: The resistance layer further includes a third resistor, the number of the via holes is at least two, and two ends of the third resistor are connected to two adjacent via holes.