Semiconductor memory device

Abstract

The invention discloses a semiconductor memory device. The semiconductor memory device comprises a substrate, a plurality of capacitor structures, a stress insulating layer and an interface layer, the capacitor structures are arranged on the substrate in a mutually separated mode and comprise a plurality of capacitors. The stress insulating layer is arranged on the substrate and covers the capacitor structure. The interface layer is arranged in the stress insulation layer and between any two adjacent capacitor structures, and the end part of the interface layer is higher than the top surface of each capacitor structure. Therefore, the stress form of the substrate can be adjusted by means of the arrangement of the interface layer, so that the effect of eliminating excess stress is achieved, and the structural reliability of the device is enhanced.

Description

[0001] The present invention is a divisional application of the invention with application number "202210716508.6", application date "June 22, 2022", and application name "Semiconductor storage device and its manufacturing method". Technical Field

[0002] The present invention relates to a semiconductor storage device and a manufacturing method thereof, in particular to a semiconductor storage device. Background Art

[0003] In modern electronic products, memory plays an indispensable and important role. In addition to storing user data, memory is also responsible for storing program codes executed by the central processing unit and information that needs to be temporarily saved during the operation process. Memory can be divided into volatile memory and non-volatile memory. Common volatile memories include dynamic random access memory (DRAM) and static random access memory (SRAM). Their data will disappear after power failure and must be re-entered when power is supplied next time.

[0004] Dynamic random access memory is an indispensable key component in many electronic products. It is composed of a large number of memory cells gathered to form an array area for storing data, and each memory cell can be composed of a metal oxide semiconductor (MOS) transistor and a capacitor in series. As the density of DRAM increases, the construction of electrical connections within and between memory cells becomes increasingly difficult. At the same time, the transistor components and capacitor components in each memory cell have many different structural designs due to product requirements and / or memory cell density considerations. Therefore, how to develop DRAM devices and their manufacturing processes that can maintain performance has always been a technical direction that the field has continued to work on. Summary of the invention

[0005] The present invention aims to provide a semiconductor memory device, in which a stress insulating layer is arranged between mutually separated capacitor structures, and an interface layer higher than the top surface of the capacitor structure can be generated in the stress insulating layer. Here, the stress pattern of the substrate can be adjusted by means of the arrangement of the interface layer, thereby achieving the effect of eliminating excess stress and enhancing the structural reliability of the device.

[0006] A semiconductor storage device provided by one embodiment of the present invention includes a substrate, a plurality of capacitor structures, which are arranged on the substrate in a spaced-apart manner, each of the capacitor structures includes a plurality of capacitors, the capacitors include a lower electrode layer, a capacitor dielectric layer and an upper electrode layer stacked in sequence, a stress insulating layer, which is arranged on the substrate and covers the capacitor structures, and an interface layer, which is arranged in the stress insulating layer and is between any two adjacent capacitor structures, wherein the interface layer is made of the same material as the stress insulating layer, and the interface layer is away from the upper electrode layer and does not contact the upper electrode layer.

[0007] Another semiconductor storage device provided by one embodiment of the present invention includes a substrate, a plurality of capacitor structures arranged on the substrate in a mutually separated manner, a stress insulating layer arranged on the substrate and covering the capacitor structures; and at least one interface layer arranged in the stress insulating layer and between any two adjacent capacitor structures, wherein the at least one interface layer is made of the same material as the stress insulating layer, and the at least one interface layer does not directly contact the capacitor structure.

[0008] Another semiconductor storage device provided by an embodiment of the present invention includes a substrate, a plurality of capacitor structures arranged on the substrate in a mutually separated manner, each of the capacitor structures including a plurality of capacitors, a stress insulating layer arranged on the substrate and covering the capacitor structures, and at least one interface layer arranged in the stress insulating layer and between any two adjacent capacitor structures, wherein an end of the at least one interface layer is higher than a top surface of each of the capacitor structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Illustrated is a schematic diagram of steps of a method for manufacturing a semiconductor memory device according to a first embodiment of the present invention.

[0010] Figures 2 to 3 FIG. 1 is a schematic diagram of steps of a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention, wherein: Figure 2 is a schematic cross-sectional view of a semiconductor memory device after a stress insulating layer is formed; and Figure 3 It is a cross-sectional schematic diagram of a semiconductor memory device after a planarization process.

[0011] Figures 4 to 5 FIG. 1 is a schematic diagram of steps of a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention, wherein: Figure 4 is a schematic cross-sectional view of a semiconductor memory device after a stress insulating layer is formed; and Figure 5 It is a cross-sectional schematic diagram of a semiconductor memory device after a planarization process.

[0012] Figure 6Illustrated is a schematic diagram of the steps of a method for manufacturing a semiconductor memory device according to a fourth embodiment of the present invention.

[0013] The reference numerals are described as follows:

[0014] 10, 20, 30, 40-semiconductor memory device, 100-substrate, 101-storage area, 102-peripheral area, 105-shallow trench isolation, 120-word line, 121-gate dielectric layer, 123-gate electrode layer, 125-cap layer, 130-transistor, 140-contact plug, 150-capacitor, 151-semiconductor layer, 153-conductive layer, 155-insulating layer, 160-capacitor structure, 180-insulating layer, 181-joint, 190-dielectric layer, 191-top surface, 280 -insulating layer, 281-seam, 283-interface layer, 283a-end, 290-dielectric layer, 291-top surface, 380-insulating layer, 383-interface layer, 383a-end, 390-dielectric layer, 391-top surface, 480-insulating layer, 483-first interface layer, 485-second interface layer, 490-dielectric layer, g1, g2-spacing, H1, H2, H3-height, S1, S2, S3-spacing, W2, W3-bottom width, θ1-point angle, θ2, θ3-included angle. DETAILED DESCRIPTION

[0015] In order to enable a person skilled in the art to further understand the present invention, several preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with the accompanying drawings. A person skilled in the art to which the present invention belongs can refer to the following embodiments and replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention.

[0016] Please refer to Figure 1 , which is a schematic diagram of the steps of a method for manufacturing a semiconductor memory device 10 in a first embodiment of the present invention. The semiconductor memory device 10 is, for example, a dynamic random access memory device, which includes at least one transistor element 130 and at least one capacitor 150, which are used as the smallest component unit (memory cell) in a DRAM array and receive voltage signals from a bit line (BL, not shown) and a word line (WL) 120.

[0017] Specifically, the semiconductor memory device 10 includes a substrate 100, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator (SOI) substrate, etc. The substrate 100 also includes a storage region (cell region) 101 and a peripheral region (periphery region) 102 located on at least one side of the storage region 101. In this embodiment, two storage regions 101 are set on the substrate 100, and the two storage regions 101 are separated by the peripheral region 102. Figure 1 However, those skilled in the art should easily understand that the specific number and position of the storage area 101 and the peripheral area 102 can be adjusted according to actual component requirements. Figure 1 The examples shown are limited to those shown. At least one shallow trench isolation (STI) 105 is formed in the substrate 100 to define a plurality of active areas (AA, not shown). The manufacturing process of each shallow trench isolation is, for example, to first form a plurality of trenches (not shown) in the substrate 100 by etching, and then fill the trenches with an insulating material, the insulating material including, for example, silicon oxide (SiOx), silicon nitride (SiN) or silicon oxynitride (SiCN), etc., but not limited thereto. Furthermore, a plurality of buried word lines (BWL) 120 are formed in the two storage areas 101 of the substrate 100, extending in parallel along a direction, and interlaced with each of the active areas and the shallow trench isolation 105. In this way, a portion of each buried word line 120 may be buried in the shallow trench isolation 105, while another portion may be buried in each of the active areas, such as Figure 1 shown.

[0018] Specifically, each buried word line 120 at least includes a gate dielectric layer 121, such as silicon oxide, a gate electrode layer 123, such as tungsten (W), aluminum (Al) or copper (Cu) and other low-resistance metal materials, and a cap layer 125, such as silicon nitride, silicon oxynitride (SiON), silicon carbide nitride and other insulating materials. The gate dielectric layer 121, the gate electrode layer 123 and the cap layer 125 can be formed by first forming a plurality of trenches (not shown) in the substrate 100, and then using deposition, etching and planarization processes to sequentially form a gate dielectric layer 121 covering the entire surface of the trench and a gate electrode layer 123 filling the lower half of the trench in the trench, and then after etching back, a cap layer 125 filling the upper half of the trench is formed, and the cap layer 125 is cut flush with the surface of the substrate 100. In this embodiment, each buried word line 120 and the doped regions in the substrate 100 at both sides thereof can further form a transistor 130 .

[0019] Next, a dielectric layer 110 and a plurality of capacitor structures 160 are formed on the substrate 100. Each capacitor structure 160 is formed on the substrate 100 in a spaced manner and further includes a plurality of capacitors 150, wherein the capacitors 150 are electrically connected to the doped regions on both sides of each transistor 130 through a plurality of contact plugs 140 located in the dielectric layer 110 and a metal silicide layer (not shown) formed on the surface of the substrate 100. Figure 1 As shown. Thus, each capacitor 150 can be used as a storage node (SN), and together with each transistor 130 in the substrate 100, it constitutes a memory unit to form a DRAM array. Specifically, each capacitor 150 includes a bottom electrode layer (not shown) stacked in sequence, a capacitor dielectric layer (not shown), such as a dielectric material with a dielectric constant greater than 4 such as hafnium oxide (HfO2), and an upper electrode layer (not shown). Among them, the upper electrode layer and the lower electrode layer of each capacitor 150 can, for example, include conductive materials such as tungsten, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and aluminum (Al), but are not limited to this. It should be noted that, although the lower electrode layer, the capacitor dielectric layer and the upper electrode layer of this embodiment are all covered on the support structure (not shown) above the substrate 100 in a conformal manner as an example of implementation, the specific configuration is not limited thereto and can be adjusted arbitrarily according to product requirements. For example, in another embodiment, the lower electrode layer can also be selected to have a vertical columnar structure, or the capacitor dielectric layer can be made to cover the gaps between the lower electrodes in addition to covering the lower electrodes, so that the upper electrode formed subsequently can cover all the lower electrodes (not shown) as a whole, but it is not limited thereto.

[0020] Each capacitor structure 160 also includes a stacked layer structure sequentially stacked on each capacitor 150, and its manufacturing method includes but is not limited to the following steps. First, at least one deposition process is performed, such as a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, to sequentially form a semiconductor layer 151, such as a semiconductor material including polysilicon or silicon germanium (SiGe), a conductive layer 153, such as a metal material with low resistance including tungsten or copper, and an insulating layer 155, such as a dielectric material including silicon oxide, on each capacitor 150, but not limited thereto. In the present embodiment, the semiconductor layer 151, for example, covers the substrate 100 and each capacitor 150 to directly contact the capacitor 150, and further fills the gap between each capacitor 150, and the conductive layer 153 and the insulating layer 155 formed subsequently are conformally disposed on the semiconductor layer 151. The semiconductor layer 151, the conductive layer 153 and the insulating layer 155 of the stacked layer structure not only cover all the capacitors 150, but also extend further to the peripheral regions 102 on both sides of the storage region 101. An etching process is required under the cover of a mask layer (not shown) to partially remove the stacked layer structure in the peripheral region 102, so as to obtain a capacitor structure 160. Figure 1 It should be noted that two adjacent capacitor structures 160 are separated from each other by a spacing S1, and the distance of the spacing S1 in a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction) is, for example, approximately equal to the height H1 of the capacitor structure 160 in a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction), but is not limited thereto.

[0021] Subsequently, an insulating layer 180 and a dielectric layer 190 are continuously formed on the substrate 100, wherein the insulating layer 180 includes materials such as silicon oxide, covers each capacitor structure 160 and further fills the space between adjacent capacitor structures 160. Thus, the manufacturing process of the semiconductor memory device 10 of the present embodiment is completed. It should be noted that the insulating layer 180 of the present embodiment is formed through a deposition manufacturing process. However, due to the high aspect ratio of the capacitor structure 160, when the insulating layer 180 is deposited between two adjacent capacitor structures 160, it is easy to generate a seam 181 above the spacing S1, and the subsequently formed dielectric layer 190 will have a relatively concave top surface 191 above the seam 181, such as Figure 1Then, at least one planarization process is required to planarize the top surface 191 of the dielectric layer 190, and further remove the seam 181 of the insulating layer 180. However, in some cases, the seam 181 has a larger extension range, for example, it can extend to a height close to the top surface of each capacitor structure 160 in the vertical direction (such as Figure 1 As shown in FIG. 1 , the planarization process cannot completely remove the surface of the semiconductor memory device 10 . Therefore, the structural reliability of the semiconductor memory device 10 may be seriously negatively affected.

[0022] Those skilled in the art should be able to easily understand that the semiconductor memory device of the present invention may also be formed in other ways and have other features, and is not limited to the aforementioned steps and structures. The following will further describe other embodiments or variations of the semiconductor memory device of the present invention and its manufacturing method. And to simplify the description, the following description mainly details the differences between the embodiments, and will not repeat the same parts. In addition, the same components in the various embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the various embodiments.

[0023] Please refer to Figures 2 to 3 , which illustrates a method for manufacturing a semiconductor memory device 20 in a second embodiment of the present invention. The preceding steps of this embodiment are substantially the same as those of the aforementioned first embodiment and are not described in detail herein. The main difference between the manufacturing process of this embodiment and that of the aforementioned first embodiment is that this embodiment uses a plasma-enhanced tetraethoxysilane (PETEOS) manufacturing process to prepare the insulating layer 280, and that adjacent capacitor structures 160 have a relatively large spacing S2, wherein the spacing S2 in the horizontal direction is, for example, greater than the height H1 of the capacitor structure 160 in the vertical direction, and is preferably approximately greater than 1.5 times the height H1.

[0024] In detail, Figure 2 As shown, after the capacitor structure 160 is formed, a plasma enhanced tetraethyl orthosilicate deposition silicon dioxide manufacturing process is performed to form an insulating layer 280 on the substrate 100, which includes a dielectric material such as silicon oxide, and then a dielectric layer 290 is formed, which also has a relatively concave top surface 291. It should be particularly noted that when the insulating layer 280 is quickly deposited at the interval S2 between two adjacent capacitor structures 160, it is also easy to generate a seam 281 above the interval S2. However, a relatively large interval S2 can effectively reduce the range of the formation of the seam 281, and it is preferably formed at a position higher than the height H1 of the capacitor structure 160, such as Figure 2On the other hand, the relatively large spacing S2 can initially compensate for the stress rebound from the substrate 100 when the insulating layer 280 is deposited quickly, so that an interface layer 283 can be formed in the insulating layer 280. The interface layer 283 has the same dielectric material as the insulating layer 280 but with a relatively higher density.

[0025] It should be noted that the interface layer 283 is formed between two adjacent capacitor structures 160, located below the seam 281, and has, for example, Figure 2 The triangular shape shown in the figure, in this way, the end 283a of the interface layer 283 may present a sharp angle θ1, which is, for example, smaller than the two included angles θ2 at the bottom of the interface layer 283. The included angle θ2, for example, refers to the angle between the side of the interface layer 283 and the surface of the substrate 100, for example, is about 45±5 degrees to 45±10 degrees, but is not limited thereto. Preferably, the end 283a of the interface layer 283 may be higher than the top surface of each capacitor structure 160, so that the height H2 of the interface layer 283 in the vertical direction may be greater than the height H1 of the capacitor structure, for example, about 1.3 to 1.5 times the height H1, but still less than the spacing S2 between the two capacitor structures 160. In addition, it should be noted that the interface layer 283 does not directly contact the capacitor structures 160 on both sides, and is spaced apart from the capacitor structures 160 on both sides by the spacing g1, such as Figure 2 As shown, to avoid any impact on the capacitor structure 160.

[0026] Subsequent, such as Figure 3 As shown, a planarization process is performed to remove the relatively concave top surface 291 of the dielectric layer 290, and the top surfaces of the dielectric layer 290 and the insulating layer 280 are planarized as a whole, thereby completing the manufacturing process of the semiconductor memory device 20 of this embodiment. Thereafter, another planarization process (not shown) may be performed to further remove the seam 281 of the insulating layer 280.

[0027] The manufacturing method of this embodiment is to quickly deposit the insulating layer 280 at a relatively large spacing S2 between two adjacent capacitor structures 160 through a plasma enhanced tetraethyl orthosilicate deposition silicon dioxide manufacturing process. In this way, the range of the formation of the seam 281 can be effectively reduced, and the position where the seam 281 is formed is limited to a position higher than the height H1 of the capacitor structure 160, so that the seam 281 can be completely removed by means of a planarization manufacturing process in subsequent manufacturing. In addition, the relatively large spacing S2 can preliminarily compensate for the stress recoil from the substrate 100 when the insulating layer 280 is quickly deposited, so that an interface layer 283 with the same material and relatively high density can be formed in the insulating layer 280, which has, for example, Figure 2In this configuration, the insulating layer 280 can be used as a stress insulating layer to buffer the stress that is not completely eliminated on the substrate 100, reduce the impact of the stress rebound from the substrate 100 on the semiconductor memory device 20, and thus improve the structural reliability of the semiconductor memory device 20.

[0028] In addition, those skilled in the art should be able to easily understand that, in a preferred embodiment, a stress test process may be selectively performed before the plasma enhanced tetraethoxysilane process is performed to measure the stress morphology of the substrate 100, and the insulating layer 280 may be made of different materials according to the stress morphology of the substrate 100. For example, when the substrate 100 has a compressive stress morphology, it is necessary to apply an additional tensile stress through the insulating layer 280 for buffering. On the other hand, when the substrate 100 has a tensile stress morphology, it is necessary to apply an additional compressive stress through the insulating layer 280 for buffering. In this way, the insulating layer 280 may include other suitable materials such as silicon nitride, etc., to provide tensile stress or compressive stress in response to the stress morphology of the substrate 100, but is not limited thereto.

[0029] Please refer to Figures 4 to 5 , which illustrates a method for manufacturing a semiconductor memory device 30 in a third embodiment of the present invention. The first step of this embodiment is substantially the same as the first embodiment or the second embodiment, and will not be described in detail here. The main difference between the manufacturing process of this embodiment and the aforementioned embodiment is that, in this embodiment, there is a relatively large spacing S3 between adjacent capacitor structures 160. Preferably, the value of the spacing S3 in the horizontal direction is, for example, greater than about 2 times the height H1 of the capacitor structure 160.

[0030] In detail, the present embodiment also uses a plasma enhanced tetraethyl orthosilicate deposition silicon dioxide manufacturing process to form an insulating layer 380 on the substrate 100, which includes, for example, a dielectric material such as silicon oxide, and then forms a dielectric layer 390, which also has a relatively concave top surface 391. It should be particularly noted that when the insulating layer 380 is rapidly deposited at the spacing S3 between two adjacent capacitor structures 160, the relatively large spacing S3 can further optimize the deposition quality of the insulating layer 380, and can effectively avoid the formation of seams. At the same time, the relatively large spacing S3 can preliminarily compensate for the stress recoil from the substrate 100 when the insulating layer 380 is rapidly deposited, so that an interface layer 383 of the same material and relatively high density can be formed in the insulating layer 380, which has, for example, Figure 4 Trapezoidal shape shown, but not limited to.

[0031] In the present embodiment, the interface layer 383 is also formed between two adjacent capacitor structures 160. However, because the interface layer 383 has a trapezoidal shape, its end 383a is a plane, and the two angles (for example, the angles formed between the side edges of the interface layer 383 and the surface of the substrate 100) θ3 at the top are also approximately 45±5 degrees to 45±10 degrees, but are not limited thereto. Preferably, the end 383a of the interface layer 383 may be higher than the top surface of each capacitor structure 160, so that the height H3 of the interface layer 383 in the vertical direction may be greater than the height H1 of the capacitor structure, for example, approximately 1.8 to 2 times the height H1, but still less than the spacing S3 between the two capacitor structures 160. In addition, it should be noted that the interface layer 383 does not directly contact the capacitor structures 160 on both sides, and is spaced apart from the capacitor structures 160 on both sides by the spacing g2, such as Figure 4 As shown, to avoid any impact on the capacitor structure 160.

[0032] Subsequent, such as Figure 5 As shown, a planarization process is performed to remove the relatively concave top surface 391 on the dielectric layer 390, and the top surfaces of the dielectric layer 390 and the insulating layer 380 are planarized as a whole, thereby completing the manufacturing process of the semiconductor memory device 30 of this embodiment. Under this setting, the insulating layer 380 can also be used as a stress insulating layer to buffer the stress that has not been completely eliminated on the substrate 100, and reduce the impact of the stress rebound from the substrate 100 on the semiconductor memory device 30, thereby improving the structural reliability of the semiconductor memory device 30. In addition, in this embodiment, before the plasma enhanced tetraethoxysilane manufacturing process is performed, an additional stress test manufacturing process can be performed to measure the stress morphology of the substrate 100, and according to the stress morphology (compressive stress morphology or tensile stress morphology) of the substrate 100, the insulating layer 380 can include other suitable materials such as silicon nitride, etc., to provide tensile stress or compressive stress in response to the stress morphology of the substrate 100, but it is not limited thereto.

[0033] Therefore, the manufacturing method of this embodiment can not only effectively avoid the generation of seams and omit the subsequent planarization manufacturing process, but also use the relatively large spacing S3 to initially compensate for the stress rebound from the substrate 100 when the insulating layer 380 is quickly deposited, so that an interface layer 383 with the same material and relatively high density can be formed in the insulating layer 380, which has, for example, Figure 4 The trapezoidal shape shown serves as the stress insulating layer to buffer the stress that has not been completely eliminated on the substrate 100 , thereby alleviating the impact of the stress rebound from the substrate 100 on the semiconductor memory device 30 , thereby improving the structural reliability of the semiconductor memory device 30 .

[0034] Please refer to Figure 6, which illustrates a method for manufacturing a semiconductor memory device 40 in a fourth embodiment of the present invention. The previous steps of this embodiment are substantially the same as those of the aforementioned second embodiment or the aforementioned third embodiment, and are not described in detail here. The main difference between the manufacturing process of this embodiment and the aforementioned embodiments is that, in this embodiment, any adjacent capacitor structures 160 may have different first and second spacings, such as spacing S2 and spacing S3, and the values ​​of spacing S2 and spacing S3 in the horizontal direction are both greater than the height H1 of the capacitor structure 160.

[0035] In detail, the present embodiment also uses a plasma enhanced tetraethyl orthosilicate deposition silicon dioxide manufacturing process to form an insulating layer 480 on the substrate 100, which includes a dielectric material such as silicon oxide, and then forms a dielectric layer 490. It should be noted that when the insulating layer 480 is quickly deposited at the spacing S2 and the spacing S3 between two adjacent capacitor structures 160, a first interface layer 483 and a second interface layer 485 of the same material and relatively high density can be formed in the insulating layer 480 in response to different stress compensations, and are located at the spacing S2 and the spacing S3, respectively. Figure 6 As shown, but not limited to this. The first interface layer 483 has a triangular shape, for example, and the second interface layer 485 has a trapezoidal shape, for example. The bottom width W2 of the first interface layer 483 in the horizontal direction and the height H2 in the vertical direction are different from the bottom width W3 and height H3 of the second interface layer 485. However, the bottom width W2 of the first interface layer 483 and the bottom width W3 of the second interface layer 485 are both greater than the height H1 of the capacitor structure 160 in the vertical direction, for example, they are respectively greater than 1.5 times and 2 times of the height H1, but not limited to this.

[0036] Subsequently, a planarization process (not shown) may be performed to further remove the relatively concave top surface (not shown) on the dielectric layer 490, and planarize the top surfaces of the dielectric layer 490 and the insulating layer 480 as a whole, thereby completing the manufacturing process of the semiconductor memory device 40 of this embodiment. The manufacturing method of this embodiment can also effectively avoid or reduce the generation of seams, and can also compensate for the stress rebound from the substrate 100 when the insulating layer 480 is quickly deposited by using relatively large spacings S2 and S3, so that a first interface layer 483 and a second interface layer 485 of the same material and relatively high density can be formed in the insulating layer 480, which are respectively located on the spacings S2 and S3 and have a triangular or trapezoidal shape, so as to serve as the stress insulating layer, buffer the stress on the substrate 100 that has not been completely eliminated, and reduce the influence of the stress rebound from the substrate 100 on the semiconductor memory device 40, thereby improving the structural reliability of the semiconductor memory device 40.

[0037] In general, the manufacturing process of the present invention utilizes a plasma enhanced tetraethyl orthosilicate deposition silicon dioxide manufacturing process and cooperates with the formation of a relatively large spacing between adjacent capacitor structures to effectively reduce the range of seams generated in the insulating layer, or to avoid the formation of seams in the insulating layer. At the same time, the manufacturing process of the present invention can also compensate for the stress recoil from the substrate when the insulating layer is deposited quickly by means of a relatively large spacing, thereby forming an interface layer of the same material and relatively high density in the insulating layer, which has, for example, a triangular or trapezoidal shape, to serve as a stress insulating layer to buffer the stress that has not been completely eliminated on the substrate, reduce the impact of the stress recoil on the semiconductor storage device, and thereby improve the structural reliability of the semiconductor storage device.

[0038] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor storage device, characterized in that: include: substrate; A plurality of capacitor structures are disposed on the substrate in a mutually separated manner, each of the capacitor structures comprises a plurality of capacitors, and the capacitors comprise a lower electrode layer, a capacitor dielectric layer and an upper electrode layer stacked in sequence; A stress insulating layer, disposed on the substrate and covering the capacitor structure; The interface layer is disposed in the stress insulating layer and between any two adjacent capacitor structures, wherein the interface layer is made of the same material as the stress insulating layer, and the interface layer is away from the upper electrode layer and does not contact the upper electrode layer.

2. The semiconductor memory device according to claim 1, wherein The stress insulating layer includes a dielectric material, and the dielectric material includes silicon oxide.

3. The semiconductor memory device according to claim 1, wherein: Also includes: The insulating layer is located between the upper electrode layer and the stress insulating layer in any two adjacent capacitor structures and covers each capacitor structure, so that the interface layer and any two adjacent capacitor structures are spaced apart from each other.

4. The semiconductor memory device according to claim 1, wherein: The distance between any two adjacent capacitor structures is greater than the height of each capacitor structure.

5. The semiconductor memory device according to claim 1, wherein: The distance between any two adjacent capacitor structures is greater than the height of the interface layer.

6. The semiconductor memory device according to claim 1, wherein: There are different first and second spacings between any two adjacent capacitor structures, and the interface layer includes a first interface layer arranged in the first spacing, and a second interface layer arranged in the second spacing, and the bottom width of the first interface layer is different from the bottom width of the second interface layer.

7. The semiconductor memory device according to claim 6, wherein: A height of the first interface layer is different from a height of the second interface layer.

8. The semiconductor memory device according to claim 1, wherein: The interface layer has a trapezoidal shape, and the end portion is a plane.

9. The semiconductor memory device according to claim 1, wherein: The interface layer has a triangular shape, and the end portion is a sharp corner.

10. The semiconductor memory device according to claim 9, wherein: An angle is formed between the side edge of the interface layer and the substrate surface, and the angle of the angle is greater than or equal to the sharp angle.

11. A semiconductor storage device, characterized in that: include: substrate; A plurality of capacitor structures are disposed on the substrate in a spaced-apart manner; A stress insulating layer, disposed on the substrate and covering the capacitor structure; as well as At least one interface layer is disposed in the stress insulating layer and between any two adjacent capacitor structures, wherein the at least one interface layer is made of the same material as the stress insulating layer, and the at least one interface layer does not directly contact the capacitor structure.

12. The semiconductor memory device according to claim 11, wherein In the horizontal direction, there is a gap between the at least one interface layer and any two adjacent capacitor structures.

13. The semiconductor memory device according to claim 12, wherein: The distance between any two adjacent capacitor structures is greater than the width of the interval in the horizontal direction.

14. The semiconductor memory device according to claim 11, wherein The distance between any two adjacent capacitor structures is greater than the height of each capacitor structure.

15. The semiconductor memory device according to claim 11, wherein The distance between any two adjacent capacitor structures is greater than the height of the interface layer.

16. The semiconductor memory device according to claim 11, wherein The at least one interface layer has a trapezoidal shape, and the end portion is a plane.

17. The semiconductor memory device according to claim 11, wherein: The at least one interface layer has a triangular shape, and the end portion is a sharp corner.

18. The semiconductor memory device according to claim 17, wherein: An angle is formed between the side edge of the at least one interface layer and the substrate surface, and the angle of the angle is greater than or equal to the sharp angle.

19. The semiconductor memory device according to claim 11, wherein The stress insulating layer includes a dielectric material, and the dielectric material includes silicon oxide.

20. A semiconductor storage device, characterized in that: include: substrate; A plurality of capacitor structures are disposed on the substrate in a mutually separated manner, each of the capacitor structures comprising a plurality of capacitors; A stress insulating layer, disposed on the substrate and covering the capacitor structure; as well as At least one interface layer is disposed in the stress insulating layer and between any two adjacent capacitor structures, wherein an end of the at least one interface layer is higher than a top surface of each capacitor structure.

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