LED chip and manufacturing method thereof

Abstract

The invention provides an LED chip and a manufacturing method thereof, the LED chip is provided with an epitaxial lamination unit, and the epitaxial lamination unit at least comprises a first type semiconductor layer, an active region and a second type semiconductor layer which are sequentially laminated on a substrate from bottom to top; wherein the edge area of the upper surface of the second type semiconductor layer is provided with a concave-convex microstructure, and the microstructure can be used as a nucleation point in the forming process of the insulating protection layer, so that the compactness and the adhesion of the insulating protection layer are improved, stress concentration of the edge area of the upper surface of the LED chip is relieved, and the moisture-proof capability of the LED chip is improved; the manufacturing process of the LED chip is simple and convenient, and the LED chip is convenient to produce.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device manufacturing, and more specifically, relates to an LED chip and a manufacturing method thereof. Background Art

[0002] In current LED chip products, the commonly used passivation layer is a single layer of silicon oxide. It is widely used due to its low cost, simple manufacturing method and ideal refractive index. As the size of LED chips becomes smaller and smaller, and the application fields become wider and wider, various products have higher and higher requirements for the water vapor resistance of LED chips, especially automotive LED chips.

[0003] In order to improve the water vapor resistance of LED chips, the current conventional practice is to use PECVD (chemical vapor deposition) technology to deposit a layer of silicon oxide as a passivation layer to prevent water vapor from entering. However, the inventors have found that if Figure 1 As shown, there is still stress concentration in the edge area (black part) of the upper surface of the LED chip, which is easily corroded by water vapor, resulting in the problem of low reliability of the LED chip. Summary of the invention

[0004] In view of this, the present invention provides an LED chip and a manufacturing method thereof to solve the problem in the prior art that the edge region of the upper surface of the LED chip has stress concentration and is easily corroded by water vapor, resulting in low reliability of the LED chip.

[0005] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0006] An LED chip comprises a substrate and a plurality of LED light-emitting units arranged on the surface of the substrate and spaced apart from each other through cutting paths, wherein the LED light-emitting units comprise:

[0007] An epitaxial stacking unit is arranged on the surface of the substrate, the epitaxial stacking unit at least comprising: a first-type semiconductor layer, an active region and a second-type semiconductor layer stacked on the substrate in sequence from bottom to top; a groove is provided on a side of the epitaxial stacking unit away from the substrate to expose a portion of the first-type semiconductor layer; wherein a concave-convex microstructure is provided in an edge region of an upper surface of the second-type semiconductor layer;

[0008] A first electrode and a second electrode are arranged on the epitaxial stack unit: the first electrode is arranged at the bottom of the groove to form an electrical connection with the first-type semiconductor layer and is insulated from the sidewall of the groove; the second electrode is arranged at a side of the second-type semiconductor layer away from the active region and is electrically connected to the second-type semiconductor layer, and the first electrode and the second electrode are arranged far apart;

[0009] An insulating protection layer covers the microstructure and the exposed surface of the epitaxial stacking unit and exposes the first electrode and the second electrode.

[0010] Preferably, the roughness of the microstructure is no greater than 0.5 μm.

[0011] Preferably, the microstructure at least extends to a side wall of the second-type semiconductor layer.

[0012] Preferably, the sidewall of the epitaxial stack unit forms a terrace structure by exposing a portion of the first-type semiconductor layer; and a concave-convex microstructure is provided in the edge region of the terrace structure.

[0013] Preferably, the microstructure extends from the surface of the mesa-shaped structure to the sidewall of the mesa-shaped structure.

[0014] Preferably, the starting layer of the insulating protection layer comprises an aluminum oxide layer, and the aluminum oxide layer forms an island structure on the microstructure in an atomic layer deposition manner.

[0015] Preferably, the insulating protection layer further includes a first passivation layer, a reflective layer and a second passivation layer sequentially stacked on the aluminum oxide layer.

[0016] Preferably, the epitaxial stack further includes a transparent conductive layer, a first pad and a second pad; wherein the transparent conductive layer is arranged on a surface of the second-type semiconductor layer away from the active region, and the second electrode is deposited on the surface of the transparent conductive layer or is connected to the second-type semiconductor layer by embedding the transparent conductive layer through a first through hole;

[0017] The insulating protection layer has a second through hole exposing the first electrode and a third through hole exposing the second electrode;

[0018] The first pad is electrically connected to the first electrode through the second through hole, the second pad is electrically connected to the second electrode through the third through hole, and the first pad is spaced apart from the second pad.

[0019] The present invention also provides a method for manufacturing an LED chip, the method comprising the following steps:

[0020] Step S100, providing a substrate, and stacking an epitaxial stack on the substrate, wherein the epitaxial stack at least includes: a first-type semiconductor layer, an active region, and a second-type semiconductor layer stacked in sequence in a direction away from the substrate;

[0021] Step S200, etching the epitaxial stack by a first photolithography process to form a cutting path preset area and a groove, wherein the cutting path preset area and the groove respectively expose the corresponding first-type semiconductor layer; at the same time, forming a concave-convex microstructure in the edge area of ​​the upper surface of the second-type semiconductor layer;

[0022] Step S300, deeply etching the epitaxial stack by a second photolithography process to form a plurality of epitaxial stack units spaced apart from each other by cutting paths, wherein the cutting paths expose the substrate surface;

[0023] Step S400, manufacturing a first electrode and a second electrode on each of the epitaxial stack units to form a plurality of LED light-emitting units; the first electrode is disposed at the bottom of the groove to form an electrical connection with the first-type semiconductor layer, and is insulated from the sidewall of the groove; the second electrode is disposed on a side of the second-type semiconductor layer away from the active region and is electrically connected to the second-type semiconductor layer, and the first electrode and the second electrode are disposed far apart;

[0024] Step S500 , manufacturing an insulating protection layer, which covers the microstructure and the exposed surfaces of each of the epitaxial stacking units and exposes the first electrode and the second electrode.

[0025] Preferably, the roughness of the microstructure is no greater than 0.5 μm.

[0026] Preferably, in step S200, the first photolithography process specifically includes the following steps:

[0027] Step S201, depositing a whole layer of first photoresist on the epitaxial stack;

[0028] Step S202, patterning the first photoresist to expose a portion of the epitaxial stack surface, and then forming a first photolithography pattern through a hardening process, while forming a sawtooth shape at the edge area of ​​the upper surface of the first photolithography pattern;

[0029] Step S203, using the first photolithography pattern as a mask, and simultaneously forming the cutting street preset area, the groove and the microstructure on the second-type semiconductor layer on the epitaxial stack through an etching process.

[0030] Preferably, the first photolithography process further allows the microstructure to extend at least to a side wall of the second-type semiconductor layer.

[0031] Preferably, the step S300 further includes etching the epitaxial stack by a second photolithography process so that the sidewall of the epitaxial stack unit forms a mesa structure by exposing a portion of the first-type semiconductor layer; and forming a concave-convex microstructure in the edge region of the mesa structure, specifically including the following steps:

[0032] Step S301, depositing a whole layer of second photoresist on the chip structure formed after the first photolithography, so that the second photoresist covers the epitaxial stack, the cutting path preset area and the groove;

[0033] Step S302, patterning the second photoresist to expose a portion of the preset cutting path area, and then forming a second photolithography pattern through a hardening process, and forming a sawtooth shape at the edge area of ​​the upper surface of the second photolithography pattern;

[0034] Step S303: using the second photolithography pattern as a mask, and simultaneously forming the cutting road, the mesa-shaped structure, and the microstructure on the mesa-shaped structure through an etching process.

[0035] Preferably, the second photolithography process further allows the microstructure to extend from the surface of the mesa-shaped structure to the sidewall of the mesa-shaped structure.

[0036] Preferably, the starting layer of the insulating protection layer comprises an aluminum oxide layer, and the aluminum oxide layer grows in an island structure on the microstructure by atomic layer deposition.

[0037] Preferably, the insulating protection layer further includes a first passivation layer, a reflective layer and a second passivation layer sequentially stacked on the aluminum oxide layer.

[0038] Through the above technical solution, the following effects are achieved:

[0039] 1. The LED chip provided by the present invention is provided with an epitaxial stacking unit, and the epitaxial stacking unit at least includes: a first-type semiconductor layer, an active area and a second-type semiconductor layer stacked on a substrate from bottom to top; wherein a concave-convex microstructure is provided in the edge area of ​​the upper surface of the second-type semiconductor layer, and the microstructure can be used as a nucleation point in the formation process of the insulating protective layer to improve the density and adhesion of the insulating protective layer, which is conducive to alleviating the stress concentration in the edge area of ​​the upper surface of the LED chip to enhance the water vapor resistance of the LED chip, thereby improving the reliability of the LED chip.

[0040] 2. Furthermore, by setting the roughness of the microstructure to be no greater than 0.5 μm, the insulating protective layer formed on the microstructure has higher density and adhesion, thereby further improving the water vapor resistance of the LED chip.

[0041] 3. Furthermore, by setting the microstructure to extend at least to the side wall of the second-type semiconductor layer, the microstructure of the edge area of ​​the upper surface of the second-type semiconductor layer overlaps with the microstructure of the side wall of the second-type semiconductor layer, which is helpful to alleviate the stress concentration at the corner of the LED chip and further enhance the water vapor resistance of the LED chip.

[0042] 4. Furthermore, a terrace-like structure is formed by exposing a portion of the first-type semiconductor layer through the sidewalls of the epitaxial stacking unit; a concave-convex microstructure is provided in the edge region of the terrace-like structure, and the microstructure can be used as a nucleation point in the process of forming the insulating protective layer to improve the density and adhesion of the insulating protective layer at the sidewalls of the epitaxial stacking unit, thereby improving the water vapor resistance of the LED chip.

[0043] 5. Furthermore, by arranging a microstructure extending from the surface of the terrace structure to the side wall of the terrace structure, the microstructure of the edge area of ​​the terrace structure overlaps with the microstructure of the side wall of the terrace structure, which is helpful to alleviate the stress concentration at the corner of the side wall of the epitaxial stacking unit, further improve the density and adhesion of the insulating protective layer at the side wall of the epitaxial stacking unit, and thus enhance the water vapor resistance of the LED chip.

[0044] 6. Furthermore, by setting the starting layer of the insulating protective layer to include an aluminum oxide layer, the microstructure is more conducive to the aluminum oxide layer forming an island structure on the microstructure in a manner of atomic layer deposition, so that the aluminum oxide layer forms a good density, which can relieve the stress of the aluminum oxide layer on the epitaxial stacking unit and further improve the density and adhesion of the insulating protective layer.

[0045] 7. The method for manufacturing an LED chip provided by the present invention forms a preset cutting path area and a groove by etching the epitaxial stack through a first photolithography process, and at the same time forms a concave-convex microstructure in the edge area of ​​the upper surface of the second semiconductor layer. The microstructure can be used as a nucleation point in the formation process of the insulating protective layer to improve the density and adhesion of the insulating protective layer, which is beneficial to alleviate the stress concentration in the edge area of ​​the upper surface of the LED chip to enhance the water vapor resistance of the LED chip, thereby improving the reliability of the LED chip; and the microstructure on the second semiconductor layer is formed in the first photolithography etching process, and there is no need to add a roughening process step, which can simplify the process, save costs, and increase production. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0047] Figure 1 This is a metallographic microscope image of an LED chip corroded by water vapor in the prior art;

[0048] Figure 2 A schematic diagram of the structure of an LED chip provided by an embodiment of the present invention;

[0049] Figure 3A schematic diagram of the structure of another LED chip provided by an embodiment of the present invention;

[0050] Figure 4 A schematic diagram of the structure of another LED chip provided by an embodiment of the present invention;

[0051] Figure 5 A schematic diagram of the structure of another LED chip provided by an embodiment of the present invention;

[0052] Figure 6 A schematic diagram of the structure of another LED chip provided by an embodiment of the present invention;

[0053] Figure 7 A flow chart of a method for manufacturing an LED chip provided by an embodiment of the present invention;

[0054] Figures 8 to 11 for Figure 7 Process cross-sectional diagram corresponding to each step of the manufacturing method shown;

[0055] Figures 12 to 15 It is a process cross-sectional diagram corresponding to each step of the manufacturing method of the first photolithography;

[0056] Figures 16 to 20 It is a process cross-sectional diagram corresponding to each step of the manufacturing method of the second photolithography.

[0057] Explanation of symbols in the figure:

[0058] 1. Substrate; 2. Epitaxial stacking unit; 21. First type semiconductor layer; 22. Active area; 23. Second type semiconductor layer; 24. Recess; 3. First electrode; 4. Second electrode; 5. Insulating protection layer; 51. Aluminum oxide layer; 52. First passivation layer; 53. Reflective layer; 54. Second passivation layer; 6. Transparent conductive layer; 7. First pad; 8. Second pad; 9. First photoresist; 10. First photolithography pattern; 11. Second photoresist; 12. Second photolithography pattern; A. Cutting path preset area; B. Cutting path; C. Sawtooth; D. Microstructure; T. Terrace structure; S1. Area of ​​the side wall of the recess occupied by the microstructure; S2. Area of ​​the side wall of the recess; S3. Area of ​​the side wall of the epitaxial stacking unit occupied by the microstructure; S4. Area of ​​the side wall of the epitaxial stacking unit. DETAILED DESCRIPTION

[0059] To make the content of the present invention clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0060] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0061] Secondly, the present application is described in detail with reference to the schematic diagram. When describing the embodiments of the present application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0062] The present application embodiment provides an LED chip, such as Figure 2 As shown, it includes a substrate 1 and a plurality of LED light-emitting units ( Figure 2 Only one is shown), the LED light emitting unit comprises:

[0063] An epitaxial stacking unit 2 is arranged on the surface of a substrate 1, and the epitaxial stacking unit 2 at least comprises: a first-type semiconductor layer 21, an active region 22, and a second-type semiconductor layer 23 stacked on the substrate 1 from bottom to top; a groove 24 is provided on the side of the epitaxial stacking unit 2 away from the substrate 1 to expose a portion of the first-type semiconductor layer 21; wherein a concave-convex microstructure D is provided in the edge region of the upper surface of the second-type semiconductor layer 23;

[0064] A first electrode 3 and a second electrode 4 are arranged on the epitaxial stack unit 2: the first electrode 3 is arranged at the bottom of the groove 24 to form an electrical connection with the first-type semiconductor layer 21, and is insulated from the sidewall of the groove 24; the second electrode 4 is arranged on a side of the second-type semiconductor layer 23 away from the active region 22 and is electrically connected to the second-type semiconductor layer 23, and the first electrode 3 and the second electrode 4 are arranged far apart;

[0065] The insulating protection layer 5 covers the microstructure D and the exposed surface of the epitaxial stack unit 2 and exposes the first electrode 3 and the second electrode 4 .

[0066] In this embodiment, there is no limitation on the specific type of the substrate 1. Optionally, the substrate 1 may be a semiconductor substrate such as a sapphire substrate, a silicon substrate or a silicon carbide substrate. The specific material of the substrate 1 may be selected and used according to the requirements.

[0067] It should be noted that the present embodiment does not limit the specific doping types of the first-type semiconductor layer 21 and the second-type semiconductor layer 23. The doping types of the first-type semiconductor layer 21 and the second-type semiconductor layer 23 are opposite. The first-type semiconductor layer 21 can be a P-type semiconductor layer or an N-type semiconductor layer. The materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN or AlGaN.

[0068] Optionally, in this embodiment, the groove 24 has a structure that is wide at the top and narrow at the bottom, and the sidewalls of the groove 24 are inclined sidewalls.

[0069] Optionally, in this embodiment, the epitaxial stack unit 2 has a structure that is narrow at the top and wide at the bottom, and the sidewalls of the epitaxial stack unit 2 are inclined sidewalls.

[0070] On the basis of the above embodiments, in one embodiment of the present application, the roughness of the microstructure D is no greater than 0.5 μm.

[0071] Based on the above embodiments, in an embodiment of the present application, Figure 3 As shown, the microstructure D at least extends to the sidewall of the second-type semiconductor layer 23 .

[0072] On the basis of the above embodiments, in one embodiment of the present application, the microstructure D occupies 0%-3% of the area of ​​the upper surface of the second-type semiconductor layer 23 , excluding the end point value.

[0073] On the basis of the above embodiments, in one embodiment of the present application, the area of ​​the sidewall of the groove occupied by the microstructure is S1, and the area of ​​the sidewall of the groove is S2, then, 0<S1≤S2.

[0074] On the basis of the above embodiments, in one embodiment of the present application, the area of ​​the sidewall of the epitaxial stacking unit occupied by the microstructure is S3, and the area of ​​the sidewall of the epitaxial stacking unit is S4, then, 0<S3≤S4.

[0075] Based on the above embodiments, in an embodiment of the present application, Figure 4 As shown, the sidewall of the epitaxial stack unit 2 forms a mesa-shaped structure T by exposing a portion of the first-type semiconductor layer 21 ; a concave-convex microstructure D is provided at the edge region of the mesa-shaped structure T.

[0076] On the basis of the above-mentioned embodiment, in one embodiment of the present application, the microstructure D occupies 0%-3% of the area of ​​the surface of the mesa structure T, excluding the endpoint value.

[0077] Based on the above embodiments, in an embodiment of the present application, Figure 5 As shown, the microstructure D extends from the surface of the mesa structure T to the sidewall of the mesa structure T.

[0078] Based on the above embodiments, in one embodiment of the present application, refer to Figure 5 As shown, the starting layer of the insulating protection layer 5 includes an aluminum oxide layer 51, and the aluminum oxide layer 51 forms an island structure on the microstructure D in an atomic layer deposition manner.

[0079] Based on the above embodiments, in one embodiment of the present application, continue to refer to Figure 5 As shown, the insulating protection layer 5 further includes a first passivation layer 52 , a reflective layer 53 and a second passivation layer 54 which are sequentially stacked on the aluminum oxide layer 51 .

[0080] Optionally, in this embodiment, the materials of the first passivation layer 52 and the second passivation layer 54 include but are not limited to one or more of silicon oxide and silicon nitride.

[0081] Optionally, in this embodiment, the reflective layer 53 includes a DBR structure.

[0082] It should be noted that, in the present embodiment, the DBR structure is a periodic structure in which two materials with different refractive indices are alternately stacked in an ABAB manner, wherein the high refractive index layer may be a Ti3O5 layer, and the low refractive index layer may be a SiO2 layer; and, the number of periods of the alternating stacking of the DBR structure is not specifically limited and can be set according to actual needs.

[0083] Based on the above embodiments, in an embodiment of the present application, Figure 6 As shown, the epitaxial stack further includes a transparent conductive layer 6, a first pad 7 and a second pad 8; wherein the transparent conductive layer 6 is disposed on a surface of the second-type semiconductor layer 23 that is away from the active area 22, and the second electrode 4 is deposited on the surface of the transparent conductive layer 6 or is connected to the second-type semiconductor layer 23 by embedding the transparent conductive layer 6 through the first through hole;

[0084] The insulating protection layer 5 has a second through hole exposing the first electrode 3 and a third through hole exposing the second electrode 4;

[0085] The first pad 7 is electrically connected to the first electrode 3 through the second through hole, and the second pad 8 is electrically connected to the second electrode 4 through the third through hole, and the first pad 7 and the second pad 8 are spaced apart.

[0086] The present application also provides a method for manufacturing an LED chip. Figure 7 As shown, the method for manufacturing an LED chip includes the following steps:

[0087] Step S100: Figure 8 As shown, a substrate 1 is provided, and an epitaxial stack is stacked on the substrate 1, wherein the epitaxial stack at least includes: a first-type semiconductor layer 21, an active region 22, and a second-type semiconductor layer 23 which are sequentially stacked in a direction away from the substrate 1;

[0088] In this embodiment, there is no limitation on the specific type of the substrate 1. Optionally, the substrate 1 may be a semiconductor substrate such as a sapphire substrate, a silicon substrate or a silicon carbide substrate. The specific material of the substrate 1 may be selected and used according to the requirements.

[0089] It should be noted that the present embodiment does not limit the specific doping types of the first-type semiconductor layer 21 and the second-type semiconductor layer 23. The doping types of the first-type semiconductor layer 21 and the second-type semiconductor layer 23 are opposite. The first-type semiconductor layer 21 can be a P-type semiconductor layer or an N-type semiconductor layer. The materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN or AlGaN.

[0090] Step S200: Fig. 9 As shown, the epitaxial stack is etched by a first photolithography process to form a cutting path preset area A and a groove 24, wherein the cutting path preset area A and the groove 24 respectively expose the corresponding first-type semiconductor layer 21; at the same time, a concave-convex microstructure D is formed in the edge area of ​​the upper surface of the second-type semiconductor layer 23;

[0091] Step S300: Fig.10 As shown, the epitaxial stack is deeply etched by a second photolithography process to form a plurality of epitaxial stack units 2 which are arranged at intervals from each other through a cutting line B, and the cutting line B exposes the surface of the substrate 1;

[0092] It should be noted that this embodiment Fig.10 Only one epitaxial stack unit 2 is shown, which corresponds to one LED light-emitting unit. It can be understood that there are many epitaxial stacks. Fig.10 The epitaxial stack unit 2 is shown.

[0093] Step S400: Fig.11 As shown, a first electrode 3 and a second electrode 4 are fabricated on each epitaxial stack unit 2 to form a plurality of LED light-emitting units ( Fig.11 Only one is shown in the figure); the first electrode 3 is arranged at the bottom of the groove 24 to form an electrical connection with the first-type semiconductor layer 21, and is insulated from the sidewall of the groove 24; the second electrode 4 is arranged on the side of the second-type semiconductor layer 23 away from the active area 22 and is electrically connected to the second-type semiconductor layer 23, and the first electrode 3 and the second electrode 4 are arranged far apart;

[0094] Step S500, reference Figure 2 As shown, an insulating protection layer 5 is formed, which covers the microstructure D and the exposed surface of each epitaxial stacking unit 2 and exposes the first electrode 3 and the second electrode 4.

[0095] Optionally, in this embodiment, the groove 24 has a structure that is wide at the top and narrow at the bottom, and the sidewalls of the groove 24 are inclined sidewalls.

[0096] Optionally, in this embodiment, the epitaxial stack unit 2 has a structure that is narrow at the top and wide at the bottom, and the sidewalls of the epitaxial stack unit 2 are inclined sidewalls.

[0097] On the basis of the above embodiments, in one embodiment of the present application, the roughness of the microstructure D is no greater than 0.5 μm.

[0098] On the basis of the above embodiment, in one embodiment of the present application, in step S200, the first photolithography process specifically includes the following steps:

[0099] Step S201: Fig.12 As shown, a whole layer of first photoresist 9 is deposited on the epitaxial stack;

[0100] Step S202: Fig.13 As shown, the first photoresist 9 is patterned to expose a portion of the epitaxial stack surface, and then a first photolithography pattern 10 is formed by a hardening process, and a sawtooth C is formed at the edge area of ​​the upper surface of the first photolithography pattern 10;

[0101] Step S203, reference Fig. 9 As shown, the first photolithography pattern 10 is used as a mask, and a cutting street preset area A, a groove 24 and a microstructure D on the second semiconductor layer 23 are simultaneously formed on the epitaxial stack through an etching process.

[0102] On the basis of the above-mentioned embodiment, in an embodiment of the present application, the first photolithography process further allows the microstructure D to at least extend to the sidewall of the second-type semiconductor layer 23 .

[0103] The specific processes include:

[0104] Step A101, reference Fig.12 As shown, a whole layer of first photoresist 9 is deposited on the epitaxial stack;

[0105] Step A102: Fig.14 As shown, the first photoresist 9 is patterned by exposure and development processes to expose part of the epitaxial stack surface, and the first photoresist 9 is narrow at the top and wide at the bottom, and the sidewalls of the first photoresist 9 are inclined sidewalls, and then the first photolithography pattern 10 is formed by a hardening process. At the same time, a sawtooth C is formed in the edge area of ​​the upper surface of the first photolithography pattern 10, and the sawtooth C extends to the sidewalls of the first photolithography pattern 10.

[0106] Step A103: Fig.15 As shown, the first photolithography pattern 10 is used as a mask to simultaneously form the cutting street preset area A, the groove 24 and the microstructure D on the second semiconductor layer 23 on the epitaxial stack through an etching process, and the microstructure D at least extends to the sidewall of the second semiconductor layer 23.

[0107] On the basis of the above-mentioned embodiment, in one embodiment of the present application, the first photoresist 9 may be hardened on the baking plate using a first hardening temperature and a first hardening time.

[0108] On the basis of the above embodiments, in one embodiment of the present application, the microstructure D occupies 0%-3% of the area of ​​the upper surface of the second-type semiconductor layer 23 , excluding the end point value.

[0109] On the basis of the above embodiments, in one embodiment of the present application, the area of ​​the sidewall of the groove occupied by the microstructure is S1, and the area of ​​the sidewall of the groove is S2, then, 0<S1≤S2.

[0110] On the basis of the above embodiments, in one embodiment of the present application, the area of ​​the sidewall of the epitaxial stacking unit occupied by the microstructure is S3, and the area of ​​the sidewall of the epitaxial stacking unit is S4, then, 0<S3≤S4.

[0111] On the basis of the above-mentioned embodiment, in one embodiment of the present application, step S300 further includes etching the epitaxial stack by a second photolithography process, so that the sidewall of the epitaxial stack unit forms a mesa-shaped structure T by exposing a portion of the first-type semiconductor layer 21; and forming a concave-convex microstructure D in the edge region of the mesa-shaped structure T, specifically including the following steps:

[0112] Step S301: Fig.16 As shown, a whole layer of second photoresist 11 is deposited on the chip structure formed after the first photolithography, so that the second photoresist 11 covers the epitaxial stack, the cutting path preset area A and the groove 24;

[0113] Step S302: Fig.17 As shown, the second photoresist 11 is patterned to expose a portion of the preset cutting path area A, and then a second photolithography pattern 12 is formed by a hardening process, and a sawtooth shape C is formed in the edge area of ​​the upper surface of the second photolithography pattern 12;

[0114] Step S303: Fig.18 As shown, the second photolithography pattern 12 is used as a mask, and the cutting road B, the mesa-shaped structure T and the microstructure D on the mesa-shaped structure T are simultaneously formed through an etching process.

[0115] It should be noted that, in this embodiment, Fig.15 The device structure shown in FIG. 1 is prepared. In other embodiments, the device structure shown in FIG. 1 may be prepared on the device structure shown in FIG. Fig. 9 The device structure is shown in the figure and will not be described in detail here.

[0116] It should also be noted that, in this embodiment, the epitaxial stack is deeply etched through the second photolithography process, so that the epitaxial stack unit forms a terrace structure T by exposing a portion of the first-type semiconductor layer 21, and at the same time, a concave-convex microstructure D is formed in the edge area of ​​the terrace structure T. The microstructure can be used as a nucleation point in the process of forming the insulating protective layer to improve the density and adhesion of the insulating protective layer 5 at the side wall of the epitaxial stack unit 2, thereby improving the water vapor resistance of the LED chip; and the microstructure D on the terrace structure T is formed during the second photolithography process, and there is no need to add a roughening process step, which can simplify the process, save costs, and increase production.

[0117] On the basis of the above-mentioned embodiment, in one embodiment of the present application, the second photolithography process further allows the microstructure D to extend from the surface of the mesa-shaped structure T to the sidewall of the mesa-shaped structure T.

[0118] The specific processes include:

[0119] Step A201, reference Fig.16 As shown, a whole layer of second photoresist 11 is deposited on the chip structure formed after the first photolithography, so that the second photoresist 11 covers the epitaxial stack, the cutting path preset area A and the groove 24;

[0120] Step A202: Fig.19 As shown, the second photoresist 11 is patterned by exposure and development processes to expose a portion of the preset cutting path area A, and the second photoresist 11 is narrow at the top and wide at the bottom, and the sidewalls of the second photoresist 11 are inclined sidewalls, and then a second photolithography pattern 12 is formed by a hardening process, and a sawtooth C is formed at the edge area of ​​the upper surface of the second photolithography pattern 12, and the sawtooth C extends to the sidewalls of the second photolithography pattern 12;

[0121] Step A203: Fig. 20 As shown, the second photolithography pattern 12 is used as a mask to simultaneously form the cutting road B, the mesa structure T and the microstructure D on the mesa structure T through an etching process, and the microstructure D extends from the surface of the mesa structure T to the sidewall of the mesa structure T.

[0122] On the basis of the above-mentioned embodiment, in one embodiment of the present application, the second photoresist 11 may be hardened in an oven using a second hardening temperature and a second hardening time.

[0123] On the basis of the above-mentioned embodiment, in one embodiment of the present application, the microstructure D occupies 0%-3% of the area of ​​the surface of the mesa structure T, excluding the endpoint value.

[0124] Based on the above embodiments, in one embodiment of the present application, refer to Figure 5 As shown, the starting layer of the insulating protection layer 5 includes an aluminum oxide layer 51, and the aluminum oxide layer 51 grows in an island structure on the microstructure D in an atomic layer deposition manner.

[0125] Optionally, in this embodiment, the aluminum oxide layer 51 is deposited by ALD (atomic layer deposition) technology. ALD is a thin film preparation technology that grows layer by layer at the atomic level. The precursor is adsorbed on the surface of the substrate and reacts to form a thin film with good density.

[0126] Based on the above embodiments, in one embodiment of the present application, continue to refer to Figure 5 As shown, the insulating protection layer 5 further includes a first passivation layer 52 , a reflective layer 53 and a second passivation layer 54 which are sequentially stacked on the aluminum oxide layer 51 .

[0127] Optionally, in this embodiment, the materials of the first passivation layer 52 and the second passivation layer 54 include but are not limited to one or more of silicon oxide and silicon nitride.

[0128] Optionally, in this embodiment, the reflective layer 53 includes a DBR structure.

[0129] It should be noted that, in the present embodiment, the DBR structure is a periodic structure in which two materials with different refractive indices are alternately stacked in an ABAB manner, wherein the high refractive index layer may be a Ti3O5 layer, and the low refractive index layer may be a SiO2 layer; and, the number of periods of the alternating stacking of the DBR structure is not specifically limited and can be set according to actual needs.

[0130] Based on the above embodiments, in one embodiment of the present application, refer to Figure 6 As shown, the epitaxial stack further includes a transparent conductive layer 6, a first pad 7 and a second pad 8; wherein the transparent conductive layer 6 is disposed on a surface of the second-type semiconductor layer 23 that is away from the active area 22, and the second electrode 4 is deposited on the surface of the transparent conductive layer 6 or is connected to the second-type semiconductor layer 23 by embedding the transparent conductive layer 6 through the first through hole;

[0131] The insulating protection layer 5 has a second through hole exposing the first electrode 3 and a third through hole exposing the second electrode 4;

[0132] The first pad 7 is electrically connected to the first electrode 3 through the second through hole, and the second pad 8 is electrically connected to the second electrode 4 through the third through hole, and the first pad 7 and the second pad 8 are spaced apart.

[0133] In summary, through the above technical solution, the following effects are achieved:

[0134] 1. The LED chip provided in this embodiment is provided with an epitaxial stacking unit, and the epitaxial stacking unit at least includes: a first-type semiconductor layer, an active area and a second-type semiconductor layer stacked on a substrate from bottom to top; wherein a concave-convex microstructure is provided in the edge area of ​​the upper surface of the second-type semiconductor layer, and the microstructure can be used as a nucleation point in the formation process of the insulating protective layer to improve the density and adhesion of the insulating protective layer, which is conducive to alleviating the stress concentration in the edge area of ​​the upper surface of the LED chip to enhance the water vapor resistance of the LED chip, thereby improving the reliability of the LED chip.

[0135] 2. Furthermore, by setting the roughness of the microstructure to be no greater than 0.5 μm, the insulating protective layer formed on the microstructure has higher density and adhesion, thereby further improving the water vapor resistance of the LED chip.

[0136] 3. Furthermore, by setting the microstructure to extend at least to the side wall of the second-type semiconductor layer, the microstructure of the edge area of ​​the upper surface of the second-type semiconductor layer overlaps with the microstructure of the side wall of the second-type semiconductor layer, which is helpful to alleviate the stress concentration at the corner of the LED chip and further enhance the water vapor resistance of the LED chip.

[0137] 4. Furthermore, a terrace-like structure is formed by exposing a portion of the first-type semiconductor layer through the sidewalls of the epitaxial stacking unit; a concave-convex microstructure is provided in the edge region of the terrace-like structure, and the microstructure can be used as a nucleation point in the process of forming the insulating protective layer to improve the density and adhesion of the insulating protective layer at the sidewalls of the epitaxial stacking unit, thereby improving the water vapor resistance of the LED chip.

[0138] 5. Furthermore, by arranging a microstructure extending from the surface of the terrace structure to the side wall of the terrace structure, the microstructure of the edge area of ​​the terrace structure overlaps with the microstructure of the side wall of the terrace structure, which is helpful to alleviate the stress concentration at the corner of the side wall of the epitaxial stacking unit, further improve the density and adhesion of the insulating protective layer at the side wall of the epitaxial stacking unit, and thus enhance the water vapor resistance of the LED chip.

[0139] 6. Furthermore, by setting the starting layer of the insulating protective layer to include an aluminum oxide layer, the microstructure is more conducive to the aluminum oxide layer forming an island structure on the microstructure in a manner of atomic layer deposition, so that the aluminum oxide layer forms a good density, which can relieve the stress of the aluminum oxide layer on the epitaxial stacking unit and further improve the density and adhesion of the insulating protective layer.

[0140] 5. The method for manufacturing the LED chip provided in this embodiment forms a preset cutting path area and a groove by etching the epitaxial stack through a first photolithography process, and at the same time forms a concave-convex microstructure in the edge area of ​​the upper surface of the second semiconductor layer. The microstructure can be used as a nucleation point in the formation process of the insulating protective layer to improve the density and adhesion of the insulating protective layer, which is beneficial to alleviate the stress concentration in the edge area of ​​the upper surface of the LED chip to enhance the water vapor resistance of the LED chip, thereby improving the reliability of the LED chip; and the microstructure on the second semiconductor layer is formed in the first photolithography etching process, and there is no need to add a roughening process step, which can simplify the process, save costs, and increase production.

[0141] Those skilled in the art should understand that, in the disclosure of the present invention, the terms "horizontal", "vertical", "upper", "lower", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.

[0142] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0143] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, comprising a substrate and a plurality of LED light-emitting units arranged on the surface of the substrate and spaced apart from each other by cutting paths, characterized in that: The LED light emitting unit comprises: An epitaxial stacking unit is arranged on the surface of the substrate, the epitaxial stacking unit at least comprising: a first-type semiconductor layer, an active region and a second-type semiconductor layer stacked on the substrate in sequence from bottom to top; a groove is provided on a side of the epitaxial stacking unit away from the substrate to expose a portion of the first-type semiconductor layer; wherein a concave-convex microstructure is provided in an edge region of an upper surface of the second-type semiconductor layer; A first electrode and a second electrode are arranged on the epitaxial stack unit: the first electrode is arranged at the bottom of the groove to form an electrical connection with the first-type semiconductor layer and is insulated from the sidewall of the groove; the second electrode is arranged at a side of the second-type semiconductor layer away from the active region and is electrically connected to the second-type semiconductor layer, and the first electrode and the second electrode are arranged far apart; An insulating protection layer covers the microstructure and the exposed surface of the epitaxial stacking unit and exposes the first electrode and the second electrode.

2. The LED chip according to claim 1, characterized in that: The roughness of the microstructure is no greater than 0.5 μm.

3. The LED chip according to claim 1, characterized in that: The microstructure at least extends to a side wall of the second-type semiconductor layer.

4. The LED chip according to claim 1, characterized in that: The sidewall of the epitaxial stack unit forms a terrace structure by exposing a portion of the first-type semiconductor layer; a concave-convex microstructure is provided in the edge region of the terrace structure.

5. The LED chip according to claim 4, characterized in that: The microstructure extends from the surface of the mesa-shaped structure to the sidewall of the mesa-shaped structure.

6. The LED chip according to claim 1, characterized in that: The starting layer of the insulating protection layer includes an aluminum oxide layer, and the aluminum oxide layer forms an island structure on the microstructure in an atomic layer deposition manner.

7. The LED chip according to claim 6, characterized in that: The insulating protection layer also includes a first passivation layer, a reflective layer and a second passivation layer which are sequentially stacked on the aluminum oxide layer.

8. The LED chip according to claim 1, characterized in that: The epitaxial stack further includes a transparent conductive layer, a first pad and a second pad; wherein the transparent conductive layer is disposed on a surface of the second-type semiconductor layer facing away from the active region, and the second electrode is deposited on the surface of the transparent conductive layer or is connected to the second-type semiconductor layer by embedding the transparent conductive layer through a first through hole; The insulating protection layer has a second through hole exposing the first electrode and a third through hole exposing the second electrode; The first pad is electrically connected to the first electrode through the second through hole, the second pad is electrically connected to the second electrode through the third through hole, and the first pad is spaced apart from the second pad.

9. A method for manufacturing an LED chip, characterized in that: include: Step S100, providing a substrate, and stacking an epitaxial stack on the substrate, wherein the epitaxial stack at least includes: a first-type semiconductor layer, an active region, and a second-type semiconductor layer stacked in sequence in a direction away from the substrate; Step S200, etching the epitaxial stack by a first photolithography process to form a cutting path preset area and a groove, wherein the cutting path preset area and the groove respectively expose the corresponding first-type semiconductor layer; at the same time, forming a concave-convex microstructure in the edge area of ​​the upper surface of the second-type semiconductor layer; Step S300, deeply etching the epitaxial stack by a second photolithography process to form a plurality of epitaxial stack units spaced apart from each other by cutting paths, wherein the cutting paths expose the substrate surface; Step S400, manufacturing a first electrode and a second electrode on each of the epitaxial stack units to form a plurality of LED light-emitting units; the first electrode is disposed at the bottom of the groove to form an electrical connection with the first-type semiconductor layer, and is insulated from the sidewall of the groove; the second electrode is disposed on a side of the second-type semiconductor layer away from the active region and is electrically connected to the second-type semiconductor layer, and the first electrode and the second electrode are disposed far apart; Step S500 , manufacturing an insulating protection layer, which covers the microstructure and the exposed surfaces of each of the epitaxial stacking units and exposes the first electrode and the second electrode.

10. The method for manufacturing an LED chip according to claim 9, characterized in that: The roughness of the microstructure is no greater than 0.5 μm.

11. The method for manufacturing an LED chip according to claim 9, characterized in that: In the step S200, the first photolithography process specifically includes the following steps: Step S201, depositing a whole layer of first photoresist on the epitaxial stack; Step S202, patterning the first photoresist to expose a portion of the epitaxial stack surface, and then forming a first photolithography pattern through a hardening process, while forming a sawtooth shape at the edge area of ​​the upper surface of the first photolithography pattern; Step S203, using the first photolithography pattern as a mask, and simultaneously forming the cutting street preset area, the groove and the microstructure on the second-type semiconductor layer on the epitaxial stack through an etching process.

12. The LED chip according to claim 9, characterized in that: The first photolithography process also allows the microstructure to extend at least to the sidewall of the second-type semiconductor layer.

13. The method for manufacturing an LED chip according to claim 9, characterized in that: The step S300 further includes etching the epitaxial stack by a second photolithography process so that the sidewall of the epitaxial stack unit forms a mesa structure by exposing a portion of the first-type semiconductor layer; and forming a concave-convex microstructure in the edge region of the mesa structure, specifically including the following steps: Step S301, depositing a whole layer of second photoresist on the chip structure formed after the first photolithography, so that the second photoresist covers the epitaxial stack, the cutting path preset area and the groove; Step S302, patterning the second photoresist to expose a portion of the preset cutting path area, and then forming a second photolithography pattern through a hardening process, and forming a sawtooth shape at the edge area of ​​the upper surface of the second photolithography pattern; Step S303: using the second photolithography pattern as a mask, and simultaneously forming the cutting road, the mesa-shaped structure, and the microstructure on the mesa-shaped structure through an etching process.

14. The method for manufacturing an LED chip according to claim 13, characterized in that: The second photolithography process also causes the microstructure to extend from the surface of the mesa structure to the sidewall of the mesa structure.

15. The method for manufacturing an LED chip according to claim 9, characterized in that: The starting layer of the insulating protection layer includes an aluminum oxide layer, and the aluminum oxide layer grows on the microstructure in an island structure by atomic layer deposition.

16. The method for manufacturing an LED chip according to claim 9, characterized in that: The insulating protection layer also includes a first passivation layer, a reflective layer and a second passivation layer which are sequentially stacked on the aluminum oxide layer.

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