Semiconductor device and preparation method thereof, and memory system

Abstract

The invention provides a semiconductor device, a preparation method thereof and a memory system. The semiconductor device comprises a stacked structure and a plurality of lead-out contact groups located in the stacked structure. The stacked structure comprises gate layers and insulating layers which are alternately stacked, one lead-out contact group comprises a plurality of lead-out contacts which are mutually insulated, and the plurality of lead-out contacts respectively extend to different depths of the stacked structure along a first direction and are respectively connected with one gate layer located at different layers. Therefore, one lead-out contact group can be connected with a plurality of grid layers, the utilization rate of the lead-out contact group is improved, and the number of the lead-out contact group and the overall occupied area are reduced.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for manufacturing the same, as well as a memory system. Background Art

[0002] NAND memory devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. Planar NAND devices have reached their practical expansion limit. In order to further increase storage capacity and reduce the storage cost per bit, 3D NAND memory is proposed. In the 3D NAND memory structure, a stacked memory structure is realized by vertically stacking multiple layers of data storage units.

[0003] As the number of 3D NAND layers increases, the number of lead contacts further increases, and the area occupied is too large, raising the question of how to reduce the area. Summary of the invention

[0004] In view of this, the present application provides a semiconductor device and a manufacturing method thereof, as well as a memory system that can solve the above-mentioned technical problems.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a semiconductor device, which includes: a stacking structure, including alternately stacked gate layers, first insulating layers and dielectric layers, the first insulating layers and the gate layers are stacked in a first direction, and the dielectric layers and the first insulating portions are arranged in the same layer as the gate layers; and a lead contact group, which is located in the stacking structure; one of the lead contact groups includes a plurality of mutually insulated lead contacts, the plurality of lead contacts respectively extend along the first direction to different depths of the stacking structure and are respectively connected to a gate layer located at a different layer.

[0007] In some embodiments, the stacked structure also includes a second insulating layer, the second insulating layer includes a first insulating portion, the dielectric layer and the first insulating portion are arranged on the same layer as the gate layer, the dielectric layer is located between the gate layer and the first insulating portion, and the second insulating layer is in contact with the lead contact at one end away from the gate layer.

[0008] In some embodiments, one end of the first insulating portion away from the gate layer is directly connected to the lead-out contact.

[0009] In some embodiments, the first insulating portion is located between two adjacent first insulating layers.

[0010] In some embodiments, the second insulating layer further includes a second insulating portion, wherein the second insulating portion extends along the first direction and is connected to the first insulating portion.

[0011] In some embodiments, the second insulating portion surrounds one of the lead-out contacts and is connected to the lead-out contact.

[0012] In some embodiments, one second insulating portion connects at least one first insulating portion and at least one first insulating layer.

[0013] In some embodiments, the gate layer extends along a second direction perpendicular to the first direction, and the gate layer, the dielectric layer and the first insulating portion of the same layer are arranged along the second direction;

[0014] The second insulating portion includes a first inclined surface extending along a third direction, the third direction intersecting the first direction and the second direction, the first inclined surface being away from the first insulating portion connected to the second insulating portion, and the first inclined surface being connected to one of the lead contacts.

[0015] In some embodiments, one of the lead-out contact groups includes a first lead-out contact and a second lead-out contact, the first lead-out contact is arranged around the second lead-out contact; and the first insulating portion is connected to the first lead-out contact.

[0016] In some embodiments, the stacking structure also includes a first surface, and the lead-out contact group extends from the first surface along the first direction toward the inside of the stacking structure; the first lead-out contact includes a first connecting portion and a second connecting portion, the first connecting portion is located between two adjacent first insulating layers and is connected to the gate layer, the second connecting portion extends along the first direction and is connected to an end of the first connecting portion away from the gate layer, and the second connecting portion extends to the first surface away from an end of the first connecting portion.

[0017] In some embodiments, the second lead-out contact includes a third connection portion, a fourth connection portion and a fifth connection portion, the third connection portion is located between two adjacent first insulating layers and is connected to the gate layer, the fourth connection portion extends along the first direction and is connected to an end of the third connection portion away from the gate layer, an end of the fourth connection portion away from the third connection portion is connected to the fifth connection portion, an end of the fifth connection portion away from the fourth connection portion extends to the first surface, and the second connection portion is arranged around a portion of the fifth connection portion.

[0018] In some embodiments, one end of the fifth connection portion away from the first surface includes a second inclined surface, the second inclined surface extends along a third direction intersecting the first direction and the gate layer extension direction, and the second inclined surface is connected to the fourth connection portion.

[0019] In some embodiments, the lead-out contact group also includes a third insulating layer, the third insulating layer includes a third insulating portion and a fourth insulating portion, the third insulating portion and the fourth insulating portion are discontinuously arranged, the third insulating portion is located between the second connecting portion of the first lead-out contact and the fifth connecting portion of the second lead-out contact, the fourth connecting portion surrounds the fourth insulating portion, and the fifth connecting portion is located on the fourth insulating portion.

[0020] In some embodiments, different groups of extraction contacts are connected to different gate layers.

[0021] The present application also provides a method for preparing a semiconductor device, comprising: forming an initial stacking structure including alternatingly stacked gate layers and first insulating layers; the initial stacking structure also includes a dielectric layer, and the dielectric layer is arranged in the same layer as the gate layer; forming a first groove and a second groove penetrating at least a portion of the first insulating layer and at least a portion of the dielectric layer on the initial stacking structure, the first groove and the second groove extending in a first direction and being connected; and forming a plurality of lead contact groups penetrating the initial stacking structure in the first groove and the second groove, one of the lead contact groups including a plurality of lead contacts extending along the first direction to different depths of the initial stacking structure and insulated from each other, and the plurality of lead contacts are respectively connected to one of the gate layers.

[0022] In some embodiments, before the step of forming a plurality of lead contact groups penetrating the initial stacking structure in the first groove and the second groove, the step further includes: removing a portion of the dielectric layer to obtain a plurality of third grooves; the third grooves extend along the extension direction of the gate layer and are respectively connected to the first groove and the second groove; filling the side walls and bottom walls of the first groove and the second groove and the third groove with insulating material; and removing at least a portion of the insulating material and retaining the insulating material located in the third groove, and exposing at least a portion of the dielectric layer at the junction of the first groove and the second groove and at least a portion of the dielectric layer located below the bottom of the second groove.

[0023] In some embodiments, before the step of removing part of the dielectric layer to obtain a plurality of third grooves, a first insulating layer is located at the bottom of the second groove; the step of removing at least part of the insulating material and retaining the insulating material located in the third groove includes: removing at least part of the insulating material located on the side walls of the first groove and the second groove and all of the insulating material located at the bottom of the second groove to obtain a second insulating layer; the second insulating layer includes a first insulating portion located in the third groove; and removing the first insulating layer located at the bottom of the second groove to expose at least part of the dielectric layer.

[0024] In some embodiments, in the step of removing at least a portion of the insulating material on the side walls of the first groove and the second groove and all of the insulating material at the bottom of the second groove to obtain a second insulating layer, a portion of the insulating material on the side walls of the first groove and / or the second groove is retained, and the portion of the insulating material is a second insulating portion, and the second insulating portion is connected to the multiple first insulating portions.

[0025] In some embodiments, the step of forming a plurality of lead-out contact groups penetrating the initial stacking structure in the first groove and the second groove includes: removing the entire dielectric layer where the dielectric layer exposed from the first groove and the second groove is located, forming a fourth groove connected to the first groove and a fifth groove connected to the second groove; forming a first lead-out contact in the fourth groove and on the side wall of the first groove; and forming an initial second lead-out contact in the fifth groove and on the side wall of the second groove; forming a third insulating portion on the surface of the first lead-out contact located in the first groove and forming a fourth insulating portion in the space formed by the initial second lead-out contact located in the second groove and the dielectric layer exposed from the second groove, so as to obtain a third insulating layer; and forming a conductive material connected to the initial second lead-out contact in the space surrounded by the third insulating portion, so as to obtain a second lead-out contact.

[0026] The present application also provides a storage system, comprising: the semiconductor device as described above; and a controller coupled to the memory and used to control the memory to store data.

[0027] The semiconductor device and its preparation method and memory system provided by the present application include a stacking structure and a plurality of lead contact groups located in the stacking structure. The stacking structure includes alternately stacked gate layers and insulating layers, and one of the lead contact groups includes a plurality of mutually insulated lead contacts, and the plurality of lead contacts extend to different depths of the stacking structure along a first direction and are respectively connected to a gate layer located at a different layer. Therefore, one lead contact group can connect multiple gate layers, thereby improving the utilization rate of the lead contact group and reducing the number of lead contact groups and the overall occupied area. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1A A top view of a semiconductor structure provided for some embodiments of the present application.

[0030] Figure 1B For along Figure 1A A cross-sectional view of II is shown.

[0031] Figure 2 A flow chart of a method for preparing a semiconductor structure provided in some embodiments of the present application.

[0032] Figure 3 A cross-sectional view of the initial stacking structure provided for this application.

[0033] Figure 4 For Figure 3 A cross-sectional view of the initial stacking structure after a first groove and a second groove are formed.

[0034] Figure 5 For Figure 4 A cross-sectional view of the initial stacking structure after a third groove is formed.

[0035] Figure 6 For Figure 5 The third groove and the cross-sectional view after the first groove and the second groove are filled with insulating material are shown.

[0036] Figure 7 To remove Figure 6 The cross-sectional view of the portion of insulating material shown is after obtaining the second insulating layer.

[0037] Figure 8 For Figure 7A cross-sectional view of the initial stacking structure after a fourth groove and a fifth groove are formed thereon is shown.

[0038] Fig. 9 For Figure 8 A cross-sectional view of the fourth groove, the fifth groove, the first groove and the second groove after the initial lead-out contact layer is formed.

[0039] Fig.10 For the general Fig. 9 The cross-sectional view shown is after the initial lead-out contact layer is formed into the first lead-out contact layer.

[0040] Fig.11 For Fig.10 A cross-sectional view after a third insulating layer is formed in the first groove and the second groove is shown.

[0041] Fig.12 A module diagram of a memory system provided for some embodiments of the present application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0043] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0044] In the description of the present application, it is to be understood that the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is less than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.

[0045] The present application may repeat reference numerals and / or reference letters in different implementations. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0046] The present application aims to solve the technical problem that as the number of 3D NAND layers increases, the number of lead contacts further increases, and the occupied area is too large. A semiconductor device and a method for manufacturing the same, as well as a memory system are provided. The semiconductor device includes a stacked structure and a plurality of lead contact groups located in the stacked structure. The stacked structure includes alternatingly stacked gate layers and insulating layers, and one of the lead contact groups includes a plurality of mutually insulated lead contacts, which extend to different depths of the stacked structure along a first direction and are respectively connected to a gate layer located at a different layer. Therefore, one lead contact group can connect multiple gate layers, thereby improving the utilization efficiency of the lead contact group and reducing the number of lead contact groups and the overall occupied area.

[0047] The following will be combined Figure 1A and 1B , the structure of the semiconductor device 100 is described in detail.

[0048] The semiconductor device 100 may be a wafer or a three-dimensional memory, or a part of a three-dimensional memory. The three-dimensional memory may be applied to communication products, consumer electronic products, automotive products, aerospace products, artificial intelligence products or big data, etc. Among them, consumer electronic products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses or game products, etc.

[0049] The semiconductor device 100 includes a stacking structure 120 and a lead contact group 130. The stacking structure 120 includes alternately stacked gate layers 11 and first insulating layers 12. The first insulating layers 12 and the gate layers 11 are stacked in a first direction Z. The lead contact group 130 is located in the stacking structure 120. One lead contact group 130 includes a plurality of mutually insulated lead contacts. The plurality of lead contacts extend to different depths of the stacking structure 120 along the first direction Z and are respectively connected to a gate layer 11 located at a different layer.

[0050] In some embodiments, the gate layer 11 extends along a second direction X that is perpendicular to the first direction Z.

[0051] In some embodiments, different extraction contact groups 130 are connected to different gate layers 11 .

[0052] A lead contact group 130 of the semiconductor device 100 provided in the present application includes a plurality of lead contacts which are insulated from each other, so that a lead contact group 130 can connect a plurality of gate layers 11, thereby improving the utilization rate of the lead contact group 130, reducing the number of lead contact groups 130, and saving the overall occupied area of ​​the non-core area (lead contact group).

[0053] A cross-section of a lead-out contact in the first direction Z is L-shaped, a portion of the lead-out contact extends along the first direction Z to different depths of the stacked structure 120, and another portion extends along a second direction X perpendicular to the first direction Z, is located between two adjacent first insulating layers 12 and is connected to the gate layer 11.

[0054] Among them, the part of the lead-out contact extending along the second direction X, located between two adjacent first insulating layers 12 and connected to the gate layer 11 can lead out the signal of the gate layer 11, and the part of the lead-out contact extending along the first direction Z to different depths of the stacking structure 120 can conduct the signal from the gate layer 11 to the outside of the stacking structure 120. A lead-out contact is arranged in an L shape, which can also increase the connection reliability between the lead-out contact and the stacking structure 120 and the gate layer 11.

[0055] The gate layer 11 includes but is not limited to at least one of tungsten, cobalt, copper, aluminum, doped silicon or doped silicide, and the first insulating layer 12 includes but is not limited to any one or more combinations of silicon oxide, silicon nitride and silicon oxynitride. In this embodiment, the material of the first insulating layer 12 is silicon oxide. The application does not limit the number of the gate layer 11 and the first insulating layer 12.

[0056] In some embodiments, the stacked structure 120 may further include a dielectric layer 13 disposed at the same layer as the gate layer 11. The dielectric layer 13 is located between two adjacent first insulating layers 12. In the same etching solution, the dielectric layer 13 and the first insulating layer 12 have different etching rates.

[0057] The dielectric layer 13 includes but is not limited to any one or more combinations of silicon oxide, silicon nitride and silicon oxynitride. In this embodiment, the dielectric layer 13 is made of silicon nitride or the like.

[0058] The stacked structure 120 may include a core region 101 and a non-core region 102 adjacent to the core region 101, the core region 101 is used to form a storage channel structure 30, and the non-core region 102 is used to form a lead contact group 130. The first insulating layer is located in the core region 101 and the non-core region 102, the dielectric layer 13 is located in the non-core region 102, the gate layer 11 is located in the core region 101, the storage channel structure 30 penetrates the gate layer 11 and the first insulating layer 12 along the first direction Z, and the lead contact group 130 penetrates the dielectric layer 13 and the first insulating layer 12 along the first direction Z.

[0059] In some of the embodiments, the gate layer 11 may include a dielectric layer and a conductive layer, and the conductive layer may include a first conductive layer and a second conductive layer formed in sequence, and the first conductive layer is located between the dielectric layer and the second conductive layer. The function of the dielectric layer is to isolate the conductive layer from the storage channel structure 30, and the dielectric layer has an upper surface and a lower surface in contact with two adjacent first insulating layers 12, and a side surface in contact with the storage channel structure 30, and the conductive layer is surrounded by the upper surface, the lower surface and the side surface of the dielectric layer. The material of the dielectric layer may include a high-K dielectric layer (such as aluminum oxide), the material of the first conductive layer may include titanium nitride, and the material of the second conductive layer may include tungsten. The function of the first conductive layer is mainly to alleviate the diffusion of the second conductive layer into the dielectric layer, and to improve the adhesion of the second conductive layer. The first conductive layer can also improve the diffusion of fluorine in the second conductive layer.

[0060] In some embodiments, the stacked structure 120 also includes a second insulating layer 14, the second insulating layer 14 includes a first insulating portion 141, the first insulating portion 141 is arranged in the same layer as the dielectric layer 13 and the gate layer 11, the dielectric layer 13 is located between the gate layer 11 and the first insulating portion 141, and the end of the second insulating layer 14 away from the gate layer 11 is in contact with the lead contact.

[0061] In some embodiments, the second insulating layer 14 includes but is not limited to any one or more combinations of silicon oxide, silicon nitride and silicon oxynitride. In this embodiment, the material of the second insulating layer 14 is silicon oxide. The present application does not limit the number of the second insulating layer 14.

[0062] In some embodiments, the first insulating portion 141 is located between two adjacent first insulating layers 12 .

[0063] In some embodiments, one end of the dielectric layer 13 contacts the gate layer 11 , and the other end contacts the second insulating layer 14 .

[0064] In some embodiments, one end of the first insulating portion 141 away from the gate layer 11 is directly connected to the lead-out contact.

[0065] Among them, when forming the lead-out contact, the industry generally adopts the method of first opening at least two holes (nested holes, one hole has a large aperture and the other hole has a small aperture) arranged along the first direction Z and connected to each other on the stacked structure, then forming an oxide layer on the groove wall, and then removing part of the oxide layer on the groove wall by a punching process. In this punching process, the oxide layer on the inner wall of the hole with a small aperture in the nested holes close to the hole with a large aperture is easily completely etched away, resulting in part of the sacrificial layer (for example: dielectric layer 13) in the stacked structure being exposed from the hole with a small aperture in the nested holes. When part of the sacrificial layer (for example: dielectric layer 13) in the stacked structure is subsequently replaced with a gate by an etching process, multiple adjacently arranged gates will be obtained, and the lead-out contact will connect the adjacently arranged gates in series. Here, "adjacently arranged" refers to two gates located on both sides of the first insulating layer in the first direction Z. The present application sets a second insulating layer 14 (for example, a first insulating portion 141) at an end away from the gate layer 11 and close to the lead-out contact. It can be understood that the second insulating layer 14 (for example, a first insulating portion 141) is set between the gate layer 11 and the lead-out contact. In the process of forming the lead-out contact, the dielectric layer 13 between two adjacent lead-out contacts can be better protected to reduce the risk of etching the dielectric layer 13 between two adjacent lead-out contacts, thereby reducing the risk of indiscriminate etching of the dielectric layer 13, so as to solve the problem of multiple gates being connected in series.

[0066] In some embodiments, the second insulating layer 14 further includes a second insulating portion 142, which extends along the first direction Z and is connected to the first insulating portion 141. The second insulating portion 142 surrounds the lead-out contact and is connected to the lead-out contact. One second insulating portion 142 connects at least one first insulating portion 141 and at least one first insulating layer 12. At this time, the first insulating portion 141 is indirectly connected to the lead-out contact through the second insulating portion 142.

[0067] In some embodiments, the second insulating portion 142 includes a first inclined surface 214 extending along a third direction Y perpendicular to the first direction Z and intersecting the second direction X. The first inclined surface 214 is away from the first insulating portion 141 connected to the second insulating portion 142, and the first inclined surface 214 is connected to the lead contact.

[0068] The second insulating layer 14 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the material of the second insulating layer 14 is silicon oxide. The present application does not limit the number of the second insulating layer 14. The number of the second insulating layer 14 is less than the number of the gate layer 11.

[0069] The second insulating portion 142 can further protect the dielectric layer 13 between two adjacent lead contacts during the process of forming the lead contacts, so as to further reduce the risk of etching the dielectric layer 13 between two adjacent lead contacts, and further reduce the risk of indiscriminate etching of the dielectric layer 13, so as to better solve the problem of multiple gates being connected in series.

[0070] The stacked structure 120 further includes a first surface 15 and a second surface 16 opposite to the first surface 15 in the first direction Z. The lead-out contacts extend from the first surface 15 to the second surface 16 and penetrate the first surface 15 .

[0071] In some embodiments, one of the lead contact groups 130 includes a first lead contact 21 and a second lead contact 22 insulated from each other, and the depth of the first lead contact 21 extending along the first direction Z in the stacking structure 120 is less than the depth of the second lead contact 22 along the first direction Z in the stacking structure 120.

[0072] In other embodiments, one of the lead-out contact groups 130 may also include other lead-out contacts in addition to the first lead-out contact 21 and the second lead-out contact 22, and the depth of the other lead-out contacts extending along the first direction Z within the stacking structure 120 is the same as the depth of the first lead-out contact 21 extending along the first direction Z within the stacking structure 120 and the depth of the second lead-out contact 22 along the first direction Z within the stacking structure 120.

[0073] In some embodiments, the first lead-out contact 21 includes a first connection portion 211 and a second connection portion 212, the first connection portion 211 is located between two adjacent first insulating layers 12 and is connected to the gate layer 11, the second connection portion 212 extends along the first direction Z and is connected to an end of the first connection portion 211 away from the gate layer 11, and an end of the second connection portion 212 away from the first connection portion 211 extends along the first direction Z to the first surface 15.

[0074] The second lead-out contact 22 includes a third connection portion 221, a fourth connection portion 222 and a fifth connection portion 223. The third connection portion 221 is located between two adjacent first insulating layers 12 and connected to the gate layer 11. The fourth connection portion 222 extends along the first direction Z and is connected to one end of the third connection portion 221 away from the gate layer 11. The fourth connection portion 222 extends from the third connection portion 221 to the first surface 15 along the first direction Z. One end of the fourth connection portion 222 away from the third connection portion 221 is connected to the fifth connection portion 223. One end of the fifth connection portion 223 away from the fourth connection portion 222 extends to the first surface 15. The second connection portion 212 is arranged around a portion of the fifth connection portion 223. The third connection portion 221 is insulated from the second connection portion 212, which can also be understood as the third connection portion 221 is not connected to the second connection portion 212. The second connection portion 212 is insulated from the fifth connection portion 223, which can also be understood as the second connection portion 212 is not connected to the fifth connection portion 223. The fourth connection portion 222 is insulated from the second connection portion 212 and the distance to the first surface 15 is greater than 0. If the first surface 15 is taken as the upper side and the second surface 16 is taken as the lower side, the fourth connection portion 222 is insulated from the second connection portion 212 and the distance to the first surface 15 is greater than 0, which can also be understood as the fourth connection portion 222 is located below the second connection portion 212, and the fifth connection portion 223 can lead the signal from the gate layer 11 from the fourth connection portion 222 to the outside of the stacked structure 120.

[0075] In some embodiments, the surface where the fourth connection portion 222 is connected to the second insulating portion 142 is an inclined surface, and the inclined surface is caused by the process.

[0076] In some embodiments, the second insulating layer 14 opposite to the second connection portion 212 of the first lead-out contact 21 may also include a second insulating portion 142. In this case, the surface where the second insulating portion 142 connects to the second connection portion 212 of the first lead-out contact 21 may be an inclined surface or may not be an inclined surface.

[0077] In some embodiments, one end of the fifth connection portion 223 away from the first surface 15 includes a second inclined surface 213, the second inclined surface 213 extends along a third direction Y intersecting the first direction Z and the second direction X, and the second inclined surface 213 is connected to the fourth connection portion 222. The surface where the fourth connection portion 222 is connected to the second inclined surface 213 is also an inclined surface.

[0078] In some embodiments, the lead contact group 130 further includes a third insulating layer 23, the third insulating layer 23 includes a third insulating portion 231 and a fourth insulating portion 232, the third insulating portion 231 and the fourth insulating portion 232 are discontinuously arranged, and it can also be understood that the third insulating portion 231 and the fourth insulating portion 232 are disconnected. The third insulating portion 231 is located between the second connecting portion 212 of the first lead contact 21 and the fifth connecting portion 223 of the second lead contact 22, the fourth connecting portion 222 surrounds the fourth insulating portion 232, and the fifth connecting portion 223 is located on the fourth insulating portion 232. The third insulating portion 231 is used to separate the first lead contact 21 and the second lead contact 22, and the fourth insulating portion 232 is used to support the fifth connecting portion 223.

[0079] See also Figures 1A to 11 Some embodiments of the present application provide a method for preparing a semiconductor device 100, including:

[0080] Step S1, see Figure 2 and Figure 3 , forming an initial stacking structure 110 including alternately stacked gate layers 11 and first insulating layers 12, the initial stacking structure 110 also includes a dielectric layer 13, the dielectric layer 13 and the gate layer 11 are arranged in the same layer, and the gate layer 11 and the dielectric layer 13 on the same layer are arranged along the second direction X.

[0081] The stacked structure 120 may include a core region 101 and a non-core region 102 adjacent to the core region 101, the core region 101 is used to form a storage channel structure 30, and the non-core region 102 is used to form a lead contact group 130. The first insulating layer 12 is located in the core region 101 and the non-core region 102, the dielectric layer 13 is located in the non-core region 102, the gate layer 11 is located in the core region 101, the storage channel structure 30 penetrates the gate layer 11 and the first insulating layer 12 along the first direction Z, and the lead contact group 130 penetrates the dielectric layer 13 and the first insulating layer 12 along the first direction Z.

[0082] The stacked structure 120 further includes a first surface 15 and a second surface 16 opposite to the first surface 15 in the first direction Z. The lead-out contacts extend from the first surface 15 to the second surface 16 and penetrate the first surface 15 .

[0083] Step S2, see Figure 2 and Figure 4 A first groove 103 and a second groove 104 penetrating at least a portion of the first insulating layer 12 and at least a portion of the dielectric layer 13 are formed on the initial stack structure 110 . The first groove 103 and the second groove 104 extend in the first direction Z and are connected.

[0084] In other embodiments, other grooves penetrating at least a portion of the first insulating layer 12 and at least a portion of the dielectric layer 13 are formed on the initial stacked structure 110. The present application takes the nested slots or nested holes formed by two grooves as an example for description.

[0085] The size of the first groove 103 in the second direction X is greater than the size of the second groove 104 in the second direction X. A first insulating layer 12 is exposed from the first groove 103 and the second groove 104 respectively, which can also be understood as that, in step S2, the bottom of the first groove 103 and the second groove 104 are both a first insulating layer 12. The orthographic projection of the second groove 104 on the first insulating layer 12 is located within the orthographic projection of the first groove 103 on the first insulating layer 12.

[0086] Step S3, see Figure 2 and Figure 5 , a portion of the dielectric layer 13 is removed to obtain a plurality of third grooves 105 , which extend along the extension direction of the gate layer 11 and are connected to the first groove 103 and the second groove 104 respectively.

[0087] Step S4, see Figure 2 and Figure 6 Insulating material is filled on the side walls and bottom walls of the first groove 103 and the second groove 104 and in the third groove 105 .

[0088] The material of the insulating material and the material of the first insulating layer 12 include but are not limited to any one or more combinations of silicon oxide, silicon nitride and silicon oxynitride. In this embodiment, the material of the insulating material and the material of the first insulating layer 12 are both silicon oxide.

[0089] Step S5, see Figure 2 and Figure 7 , remove at least part of the insulating material and retain the insulating material in the third groove 105 , and expose at least part of the dielectric layer 13 at the junction of the first groove 103 and the second groove 104 and at least part of the dielectric layer 13 below the bottom of the second groove 104 .

[0090] In some implementations, a portion of the insulating material is removed by a punching process. In other embodiments, a process other than the punching process may also be used to remove a portion of the insulating material.

[0091] The insulating material remaining in the third groove 105 is the first insulating part 141, and the insulating material remaining on the sidewall of the first groove 103 and / or the second groove 104 and connected to the first insulating part 141 is the second insulating part 142. The second insulating part 142 extends along the first direction Z and is connected to the plurality of first insulating parts 141. The first insulating part 141 or the first insulating part 141 and the second insulating part 142 constitute the second insulating layer 14.

[0092] In the present application, the subsequent description is made by taking the case where only the second insulating portion 142 is included on the inner wall of the second groove 104 as an example.

[0093] In some implementations, step S5 includes: removing at least part of the insulating material on the side walls of the first groove 103 and the second groove 104 and all of the insulating material at the bottom of the second groove 104 to obtain the second insulating layer 14; and removing the first insulating layer 12 at the bottom of the second groove 104 to expose at least part of the dielectric layer 13.

[0094] Step S6, see Figure 2 and Figures 8 to 10 A plurality of lead contact groups 130 penetrating the initial stacking structure 110 are formed in the first groove 103 and the second groove 104. One lead contact group 130 includes a plurality of lead contacts extending along the first direction Z to different depths of the initial stacking structure 110 and insulated from each other. The plurality of lead contacts are respectively connected to a gate layer 11.

[0095] In some implementations, step S6 includes: first, refer to Figure 8 , remove the entire dielectric layer where the dielectric layer 13 exposed from the first groove 103 and the second groove 104 is located, forming a fourth groove 106 connected to the first groove 103 and a fifth groove 107 connected to the second groove 104; secondly, please refer to Fig. 9 and Fig.10 , forming a first lead contact 21 in the fourth groove 106 and on the sidewall of the first groove 103 and forming an initial second lead contact 220 in the fifth groove 107 and on the sidewall of the second groove 104; again, please refer to Fig.11 , forming a third insulating portion 231 on the surface of the first lead contact 21 located in the first groove 103 and forming a fourth insulating portion 232 in the space formed by the initial second lead contact 220 located in the second groove 104 and the dielectric layer 13 exposed from the second groove 104, so as to obtain a third insulating layer 23; finally, refer to Figure 1A and Figure 1B , a conductive material (fifth connecting portion) connected to the initial second lead-out contact 220 is formed in the space surrounded by the third insulating portion 231 to obtain the second lead-out contact 22.

[0096] In some embodiments, the steps of forming the first lead-out contact 21 in the fourth groove 106 and on the sidewall of the first groove 103 and forming the initial second lead-out contact 220 in the fifth groove 107 and on the sidewall of the second groove 104 include: Fig. 9, an initial lead-out contact layer 109 is formed in the fourth groove 106 and on the sidewall of the first groove 103 ; a portion of the initial lead-out contact layer 109 is removed to obtain a first lead-out contact 21 and an initial second lead-out contact 220 .

[0097] In some embodiments, a portion of the initial lead-out contact layer 109 is removed by a punching process to obtain the first lead-out contact 21 and the initial second lead-out contact 220 .

[0098] In some embodiments, the initial lead-out contact layer 109 is formed by a deposition process. The initial lead-out contact layer 109 includes, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide.

[0099] The conductive material formed in the space surrounded by the third insulating portion 231 and connected to the initial second lead-out contact 220 is the fifth connecting portion 223 .

[0100] In some embodiments, the first lead-out contact 21 includes a first connection portion 211 and a second connection portion 212, the first connection portion 211 is located between two adjacent first insulating layers 12 and is connected to the gate layer 11, the second connection portion 212 extends along the first direction Z and is connected to an end of the first connection portion 211 away from the gate layer 11, and an end of the second connection portion 212 away from the first connection portion 211 extends along the first direction Z to the first surface 15.

[0101] The second lead-out contact 22 includes a third connection portion 221, a fourth connection portion 222 and a fifth connection portion 223. The third connection portion 221 is located between two adjacent first insulating layers 12 and connected to the gate layer 11. The fourth connection portion 222 extends along the first direction Z and is connected to one end of the third connection portion 221 away from the gate layer 11. The fourth connection portion 222 extends from the third connection portion 221 to the first surface 15 along the first direction Z. One end of the fourth connection portion 222 away from the third connection portion 221 is connected to the fifth connection portion 223. One end of the fifth connection portion 223 away from the fourth connection portion 222 extends to the first surface 15. The second connection portion 212 is arranged around a portion of the fifth connection portion 223. The third connection portion 221 is insulated from the second connection portion 212, which can also be understood as the third connection portion 221 is not connected to the second connection portion 212. The second connection portion 212 is insulated from the fifth connection portion 223, which can also be understood as the second connection portion 212 is not connected to the fifth connection portion 223. The fourth connection portion 222 is insulated from the second connection portion 212 and the distance to the first surface 15 is greater than 0. If the first surface 15 is taken as the upper side and the second surface 16 is taken as the lower side, the fourth connection portion 222 is insulated from the second connection portion 212 and the distance to the first surface 15 is greater than 0, which can also be understood as the fourth connection portion 222 is located below the second connection portion 212, and the fifth connection portion 223 can lead the signal from the gate layer 11 from the fourth connection portion 222 to the outside of the stacked structure 120.

[0102] In some embodiments, the surface where the fourth connection portion 222 is connected to the second insulating portion 142 is an inclined surface, and the inclined surface is caused by the process.

[0103] In some embodiments, the second insulating layer 14 opposite to the second connection portion 212 of the first lead-out contact 21 may also include a second insulating portion 142. In this case, the surface where the second insulating portion 142 connects to the second connection portion 212 of the first lead-out contact 21 may be an inclined surface or may not be an inclined surface.

[0104] In some embodiments, one end of the fifth connection portion 223 away from the first surface 15 includes a second inclined surface 213, the second inclined surface 213 extends along a third direction Y intersecting the first direction Z and the second direction X, and the second inclined surface 213 is connected to the fourth connection portion 222. The surface where the fourth connection portion 222 is connected to the second inclined surface 213 is also an inclined surface.

[0105] In some embodiments, the lead contact group 130 further includes a third insulating layer 23, the third insulating layer 23 includes a third insulating portion 231 and a fourth insulating portion 232, the third insulating portion 231 and the fourth insulating portion 232 are discontinuously arranged, and it can also be understood that the third insulating portion 231 and the fourth insulating portion 232 are disconnected. The third insulating portion 231 is located between the second connecting portion 212 of the first lead contact 21 and the fifth connecting portion 223 of the second lead contact 22, the fourth connecting portion 222 surrounds the fourth insulating portion 232, and the fifth connecting portion 223 is located on the fourth insulating portion 232. The third insulating portion 231 is used to separate the first lead contact 21 and the second lead contact 22, and the fourth insulating portion 232 is used to support the fifth connecting portion 223.

[0106] See also Fig.12 The present application also provides a memory system 1000 , which includes one or more semiconductor devices 100 as described above and a controller 200 , wherein the controller 200 is coupled to the semiconductor device 100 , and the controller 200 is configured to control the semiconductor device 100 .

[0107] The memory system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The controller may be configured to control operations of the semiconductor device, such as read, erase, and program operations.

[0108] In some embodiments, the controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0109] In some embodiments, the controller is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0110] In some embodiments, when the semiconductor device 100 is part of a three-dimensional memory, the memory system 1000 includes a peripheral circuit (not shown), which may be a CMOS (complementary metal oxide semiconductor). The peripheral circuit is electrically connected to the semiconductor device to transmit signals to the semiconductor device. The peripheral circuit can be used for logical operations and to control and detect the switching state of each storage unit in the semiconductor device 301 through metal wiring to achieve data storage and reading.

[0111] The semiconductor device and its preparation method and memory system provided by the present application include a stacking structure and a plurality of lead contact groups located in the stacking structure. The stacking structure includes alternately stacked gate layers and insulating layers, and one of the lead contact groups includes a plurality of mutually insulated lead contacts, and the plurality of lead contacts extend to different depths of the stacking structure along a first direction and are respectively connected to a gate layer located at a different layer. Therefore, one lead contact group can connect multiple gate layers, thereby improving the utilization rate of the lead contact group and reducing the number of lead contact groups and the overall occupied area.

[0112] In addition, the present application sets a second insulating layer (for example, the first insulating portion) at one end away from the gate layer and close to the lead-out contact. It can be understood that the second insulating layer (for example, the first insulating portion) is set between the gate layer and the lead-out contact, which can better protect the dielectric layer between two adjacent lead-out contacts during the formation of the lead-out contacts, thereby reducing the risk of etching the dielectric layer between two adjacent lead-out contacts, and further reducing the risk of indiscriminate etching of the dielectric layer, so as to solve the problem of multiple gates being connected in series.

[0113] In addition, the second insulating layer also includes a second insulating portion that can further protect the dielectric layer between two adjacent lead-out contacts during the process of forming the lead-out contacts, so as to further reduce the risk of etching the dielectric layer between the two adjacent lead-out contacts, thereby further reducing the risk of indiscriminate etching of the dielectric layer, so as to better solve the problem of multiple gates being connected in series.

[0114] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A stacked structure, comprising a gate layer, a first insulating layer and a dielectric layer alternately stacked, wherein the first insulating layer and the gate layer are stacked in a first direction, and the dielectric layer and the gate layer are arranged in the same layer; and A lead contact group is located in the stacking structure; each of the lead contact groups includes a plurality of lead contacts insulated from each other, and the plurality of lead contacts respectively extend to different depths of the stacking structure along a first direction and are respectively connected to a gate layer located at a different layer.

2. The semiconductor device according to claim 1, wherein The stacked structure also includes a second insulating layer, which includes a first insulating portion. The dielectric layer and the first insulating portion are arranged on the same layer as the gate layer. The dielectric layer is located between the gate layer and the first insulating portion. An end of the second insulating layer away from the gate layer is in contact with the lead contact.

3. The semiconductor device according to claim 2, wherein: One end of the first insulating portion away from the gate layer is directly connected to the lead contact.

4. The semiconductor device according to claim 2, wherein: The first insulating portion is located between two adjacent first insulating layers.

5. The semiconductor device according to claim 2, wherein: The second insulating layer further includes a second insulating portion extending along the first direction and connected to the first insulating portion.

6. The semiconductor device according to claim 5, characterized in that The second insulating portion surrounds the lead-out contact and is connected to the lead-out contact.

7. The semiconductor device according to claim 5, characterized in that One second insulating portion connects at least one first insulating portion and at least one first insulating layer.

8. The semiconductor device according to claim 5, wherein: The gate layer extends along a second direction perpendicular to the first direction, and the gate layer, the dielectric layer and the first insulating portion of the same layer are arranged along the second direction; The second insulating portion includes a first inclined surface extending along a third direction, the third direction intersecting the first direction and the second direction, the first inclined surface being away from the first insulating portion connected to the second insulating portion, and the first inclined surface being connected to one of the lead contacts.

9. The semiconductor device according to claim 2, wherein: One of the lead-out contact groups includes a first lead-out contact and a second lead-out contact, wherein the first lead-out contact is arranged around the second lead-out contact; and the first insulating portion is connected to the first lead-out contact.

10. The semiconductor device according to claim 9, wherein: The stacking structure further includes a first surface, and the lead contact group extends from the first surface toward the inside of the stacking structure along the first direction; The first lead-out contact includes a first connecting portion and a second connecting portion, the first connecting portion is located between two adjacent first insulating layers and connected to the gate layer, the second connecting portion extends along the first direction and is connected to an end of the first connecting portion away from the gate layer, and the end of the second connecting portion away from the first connecting portion extends to the first surface.

11. The semiconductor device according to claim 10, wherein: The second lead-out contact includes a third connection portion, a fourth connection portion and a fifth connection portion, the third connection portion is located between two adjacent first insulating layers and is connected to the gate layer, the fourth connection portion extends along the first direction and is connected to an end of the third connection portion away from the gate layer, an end of the fourth connection portion away from the third connection portion is connected to the fifth connection portion, an end of the fifth connection portion away from the fourth connection portion extends to the first surface, and the second connection portion is arranged around a portion of the fifth connection portion.

12. The semiconductor device according to claim 11, wherein One end of the fifth connection portion away from the first surface includes a second inclined surface, the second inclined surface extends along a third direction intersecting the first direction and the gate layer extension direction, and the second inclined surface is connected to the fourth connection portion.

13. The semiconductor device according to claim 11, wherein The lead-out contact group also includes a third insulating layer, the third insulating layer includes a third insulating portion and a fourth insulating portion, the third insulating portion and the fourth insulating portion are discontinuously arranged, the third insulating portion is located between the second connecting portion of the first lead-out contact and the fifth connecting portion of the second lead-out contact, the fourth connecting portion surrounds the fourth insulating portion, and the fifth connecting portion is located on the fourth insulating portion.

14. The semiconductor device according to any one of claims 1 to 13, characterized in that: Different groups of lead contacts are connected to different gate layers.

15. A method for preparing a semiconductor device, characterized in that: include: forming an initial stack structure including alternately stacked gate layers and first insulating layers; The initial stacking structure further includes a dielectric layer, and the dielectric layer is arranged in the same layer as the gate layer; forming a first groove and a second groove penetrating at least a portion of the first insulating layer and at least a portion of the dielectric layer on the initial stack structure, wherein the first groove and the second groove extend in a first direction and are connected; and A plurality of lead contact groups penetrating the initial stacking structure are formed in the first groove and the second groove, and one of the lead contact groups includes a plurality of lead contacts extending along a first direction to different depths of the stacking structure and insulated from each other, and the plurality of lead contacts are respectively connected to one of the gate layers.

16. The method for preparing a semiconductor device according to claim 15, characterized in that: Before the step of forming a plurality of lead contact groups penetrating the initial stacking structure in the first groove and the second groove, the method further includes: Removing part of the dielectric layer to obtain a plurality of third grooves; the third grooves extend along the extension direction of the gate layer and are respectively connected to the first groove and the second groove; Filling insulating material on the side walls and bottom walls of the first groove and the second groove and in the third groove; and At least a portion of the insulating material is removed and the insulating material in the third groove is retained, and at least a portion of the dielectric layer at the junction of the first groove and the second groove and at least a portion of the dielectric layer below the bottom of the second groove are exposed.

17. The method for preparing a semiconductor device according to claim 16, wherein: Before the step of removing part of the dielectric layer to obtain a plurality of third grooves, a first insulating layer is located at the bottom of the second groove; The step of removing at least part of the insulating material and retaining the insulating material in the third groove comprises: removing at least part of the insulating material on the sidewalls of the first groove and the second groove and all of the insulating material at the bottom of the second groove to obtain a second insulating layer; the second insulating layer includes a first insulating portion located in the third groove; and The first insulating layer at the bottom of the second groove is removed to expose at least a portion of the dielectric layer.

18. The method for preparing a semiconductor device according to claim 17, characterized in that: In the step of removing at least part of the insulating material on the sidewalls of the first groove and the second groove and all of the insulating material at the bottom of the second groove to obtain the second insulating layer, A portion of the insulating material located on the sidewalls of the first groove and / or the second groove is retained, and the portion of the insulating material is a second insulating portion, and the second insulating portion is connected to the plurality of first insulating portions.

19. The method for preparing a semiconductor device according to claim 16, wherein: The step of forming a plurality of lead contact groups penetrating the stacking structure in the first groove and the second groove comprises: Removing the entire dielectric layer where the dielectric layer is exposed from the first groove and the second groove, to form a fourth groove communicating with the first groove and a fifth groove communicating with the second groove; forming a first lead-out contact in the fourth groove and on the sidewall of the first groove; and forming an initial second lead-out contact in the fifth groove and on the sidewall of the second groove; forming a third insulating portion on the surface of the first lead contact located in the first groove and forming a fourth insulating portion in a space formed by the initial second lead contact located in the second groove and the dielectric layer exposed from the second groove, so as to obtain a third insulating layer; and A conductive material connected to the initial second lead-out contact is formed in the space surrounded by the third insulating portion to obtain a second lead-out contact.

20. A storage system, characterized in that: include: The semiconductor device according to claims 1 to 14; and The controller is coupled to the memory and is used to control the memory to store data.

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