Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a first peripheral circuit structure, a cell array structure, a molded insulation structure disposed between the first peripheral circuit structure and the cell array structure, and a second peripheral circuit structure disposed in the molded insulation structure and including a pass transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0110513 filed in the Korean Intellectual Property Office on August 23, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to a semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device. Background Art

[0004] Semiconductor memory devices are applied to electronic devices in various fields such as automobiles, medical care, and data centers, as well as small electronic devices. Therefore, the demand for semiconductor memory devices is increasing.

[0005] A semiconductor memory device may include memory cells for data storage. In order to increase the capacity of a semiconductor memory device, technical development of a three-dimensional semiconductor memory device including memory cells arranged in three dimensions is being actively conducted. Summary of the invention

[0006] According to one embodiment of the present disclosure, a semiconductor memory device may include: a plurality of transistors; a lower insulating structure covering the plurality of transistors; a global line disposed within the lower insulating structure; a molded insulating structure disposed above the lower insulating structure and including a first region overlapping the global line and a second region extending laterally from the first region; a transfer gate disposed in the first region of the molded insulating structure; an active pillar passing through the transfer gate and contacting the global line; a transfer gate insulating layer located between the active pillar and the transfer gate; a first conductive connection structure disposed in the second region of the molded insulating structure; and a cell array structure including a plurality of memory cells arranged in three dimensions above the molded insulating structure.

[0007] According to one embodiment of the present disclosure, a semiconductor memory device may include: a first peripheral circuit structure including a block decoder; a gate stack, which is spaced apart from the first peripheral circuit structure in a first direction and includes a plurality of conductive layers spaced apart and stacked in the first direction; a molded insulating structure, which is disposed between the gate stack and the first peripheral circuit structure and includes a first region overlapping the block decoder and a second region extending laterally from the first region; and a second peripheral circuit structure, which is disposed within the first region of the molded insulating structure and includes a plurality of pass transistors configured to operate in response to a block selection signal output from the block decoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0009] Figure 2 is a circuit diagram illustrating a memory cell array and a transfer circuit according to one embodiment of the present disclosure.

[0010] Figure 3 and Figure 4 is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 5A is a cross-sectional view illustrating a pass transistor group according to one embodiment of the present disclosure, and Figure 5B The diagram is along Figure 5A A plan view of the transfer transistor group taken along line AA' shown in FIG.

[0012] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H , Fig.6I , Figure 6J , Figure 6K and Figure 6L is a cross-sectional view illustrating a method of manufacturing a first conductive connection structure and a transfer transistor group of a semiconductor memory device according to one embodiment of the present disclosure.

[0013] Figure 7 is a block diagram illustrating an electronic system including a semiconductor memory device according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] The specific structural or functional description of the embodiments of the concept of the present disclosure disclosed in this specification or application is exemplified to describe the embodiments of the concept of the present disclosure. The embodiments of the concept of the present disclosure should not be interpreted as being limited to the embodiments described in this specification or application, and various modifications may be made and replaced by other equivalent embodiments.

[0015] It will be understood that although the terms "first", "second", etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and the order or number of parts is not limited by these terms. In addition, unless there are special restrictions on the parts expressed in the singular or plural, it is not interpreted as limiting the number of parts. For ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper", etc. can be used in this article to describe the relationship between an element or feature and another (other) element or feature, as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "below" or "below" in other elements or features will be oriented to be "above" the other elements or features. Therefore, the example of the term "below" can cover both the orientation above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used in this article are interpreted accordingly. It will be understood that when an element, layer, etc. is referred to as being “on,” “connected to” or “coupled to” another element, layer, etc., it can be directly on, directly connected to or directly coupled to the other element, layer, etc., or intervening elements, layers, etc. may be present. In contrast, when an element, layer, etc. is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element, layer, etc., there are no intervening elements, layers, etc.

[0016] Various embodiments of the present disclosure may provide a semiconductor memory device capable of improving integration.

[0017] Figure 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0018] refer to Figure 1 , the semiconductor memory device 50 may include a memory cell array 10, a transfer circuit 40, and a peripheral circuit structure PS.

[0019] The memory cell array 10 may include a plurality of memory blocks. Each memory block in the memory block may include a plurality of memory cells. Each memory cell in the memory cell may be a nonvolatile memory cell. As an embodiment, each memory cell may be a NAND flash memory cell. Hereinafter, the embodiments of the present disclosure are described based on a semiconductor memory device 50 including a NAND flash memory cell, but the embodiments of the present disclosure are not limited thereto. As another embodiment, each memory cell may be configured by a ferroelectric memory cell, a variable resistance memory cell, etc.

[0020] The transfer circuit 40 may be connected to the memory cell array 10 through a plurality of local lines. As an embodiment, the plurality of local lines may include a plurality of word lines WL, at least one source select line SSL, and at least one drain select line DSL.

[0021] The peripheral circuit structure PS may be configured to perform a program operation for storing data in the memory cell array 10, a read operation for outputting data stored in the memory cell array 10, and an erase operation for erasing data stored in the memory cell array 10. As an embodiment, the peripheral circuit structure PS may include an input / output circuit 21, a control circuit 23, a voltage generating circuit 31, a block decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

[0022] The input / output circuit 21 may transfer a command CMD and an address ADD received from an external device (eg, a memory controller) of the semiconductor memory device 50 to the control circuit 23. The input / output circuit 21 may exchange data DATA with the external device and the column decoder 35.

[0023] The control circuit 23 may output an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to a command CMD and an address ADD.

[0024] The voltage generating circuit 31 may generate and output various operating voltages for program operation, read operation, and erase operation in response to the operating signal OP_S. The operating voltages output from the voltage generating circuit 31 may be transmitted to the transfer circuit 40 through a plurality of global lines GLL.

[0025] The block decoder 33 may output a block selection signal in response to the row address RADD. The block selection signal output from the block decoder 33 may be transmitted to the transfer circuit 40 through the block selection line BSEL.

[0026] The transfer circuit 40 may transfer the operating voltage transmitted to the plurality of global lines GLL to the drain select line DSL, the word line WL, and the source select line SSL in response to the block select signal transmitted to the block select line BSEL.

[0027] In response to the column address CADD, the column decoder 35 may transfer data DATA input from the input / output circuit 21 to the page buffer 37 or transfer data DATA stored in the page buffer 37 to the input / output circuit 21. The column decoder 35 may exchange data DATA with the input / output circuit 21 through the column lines CL. The column decoder 35 may exchange data DATA with the page buffer 37 through the data lines DL.

[0028] The page buffer 37 may store read data received through the bit line BL in response to the page buffer control signal PB_S. The page buffer 37 may sense a voltage or current of the bit line BL during a read operation. The page buffer 37 may be connected to the memory cell array 10 through the bit line BL.

[0029] The source line driver 39 may control a voltage applied to the common source line CSL in response to a source line control signal SL_S. The source line driver 39 may be connected to the memory cell array 10 through the common source line CSL.

[0030] Figure 2 is a circuit diagram illustrating a memory cell array and a transfer circuit according to one embodiment of the present disclosure.

[0031] refer to Figure 2 , the memory cell array 10 may include a plurality of memory cell strings CS. The plurality of memory cell strings CS may be connected to a plurality of bit lines BL and a common source line CSL.

[0032] Each memory cell string CS may include at least one source select transistor SST, a plurality of memory cells MC, and at least one drain select transistor DST.

[0033] The source select transistor SST may control the electrical connection between the plurality of memory cells MC and the common source line CSL, and the drain select transistor DST may control the electrical connection between the plurality of memory cells MC and the bit line BL.

[0034] Between the common source line CSL and the plurality of memory cells MC, one source selection transistor SST may be provided, or two or more source selection transistors connected in series may be provided. Between each bit line BL and the plurality of memory cells MC of the memory cell string CS corresponding thereto, one drain selection transistor DST may be provided, or two or more drain selection transistors connected in series may be provided.

[0035] A plurality of gates of a plurality of memory cells MC may be respectively connected to a plurality of word lines WL. A gate of a source selection transistor SST may be connected to a source selection line SSL. A gate of a drain selection transistor DST may be connected to a drain selection line DSL.

[0036] The source selection line SSL, the drain selection line DSL, and the plurality of word lines WL may be connected to the transfer circuit 40. The transfer circuit 40 may include a transfer transistor group, and each transfer transistor group may include a plurality of transfer transistors PT connected to the same block selection line BSEL. The plurality of transfer transistors PT may be respectively connected to a plurality of gate contact plugs GCT. The plurality of gate contact plugs GCT may be respectively connected to the source selection line SSL, the drain selection line DSL, and the plurality of word lines WL. Each transfer transistor PT may be connected to a corresponding local line among the source selection line SSL, the drain selection line DSL, and the plurality of word lines WL via the gate contact plug GCT corresponding thereto.

[0037] In response to a block selection signal applied to a block selection line BSEL, a plurality of transfer transistors PT may transfer a voltage applied to a plurality of global lines GLL to a source selection line SSL, a drain selection line DSL, and a plurality of word lines WL. The plurality of global lines GLL may include a global source selection line GSSL, a global drain selection line GDSL, and a plurality of global word lines GWL corresponding to the source selection line SSL, the drain selection line DSL, and the plurality of word lines WL, respectively.

[0038] Figure 3 and Figure 4 is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0039] refer to Figure 3 and Figure 4 , the semiconductor memory device 50A or 50B may include a cell array structure CAS, a doped semiconductor structure DPS, a first peripheral circuit structure PS1, a second peripheral circuit structure PS2, and an interconnection structure. The interconnection structure may include various conductive patterns for electrical connection between the cell array structure CAS, the first peripheral circuit structure PS1, and the second peripheral circuit structure PS2.

[0040] The cell array structure CAS may include a plurality of memory cells arranged in three dimensions. In one embodiment, the cell array structure CAS may include a plurality of memory cells arranged in three dimensions. Figure 3 and Figure 4 The gate stack GST, the memory layer ML and the channel layer CHL indicated by the dotted box in FIG. As an embodiment, a plurality of memory cells may be included in the reference Figure 2 Each memory cell string CS may be connected to a plurality of conductive layers CDL included in the gate stack GST. The plurality of conductive layers CDL may be used as Figure 2At least one drain select line DSL, a plurality of word lines WL, and at least one source select line SSL shown in . Each memory cell may be connected to a conductive layer used as a word line among a plurality of conductive layers CDL. The channel layer CHL may be used as a channel region of each memory cell string CS, and the memory layer ML may be used as a data storage region of each memory cell string CS. A plurality of memory cells may be defined between a plurality of channel layers CHL and a plurality of word lines among a plurality of conductive layers CDL. A plurality of word lines may be stacked vertically and surround a plurality of channel layers CHL. A plurality of channel layers CHL may be arranged in two dimensions and extend vertically. In one embodiment, the cell array structure CAS may include a three-dimensional memory array defined by vertically stacking memory cells upward on each memory cell located in a two-dimensional array.

[0041] The gate stack GST may be disposed on the semiconductor substrate 61. The semiconductor substrate 61 may include a first surface SU1 facing the first direction DR1. The gate stack GST may further include a plurality of interlayer insulating layers ILD alternately stacked with a plurality of conductive layers CDL in the first direction DR1. Each conductive layer CDL and each interlayer insulating layer ILD may extend in the second direction DR2 and the third direction DR3, and axes intersecting each other in a plane parallel to the first surface SU1 face the second direction DR2 and the third direction DR3. The above-mentioned first direction DR1, second direction DR2, and third direction DR3 may be defined as directions facing the X-axis, the Y-axis, and the Z-axis. Hereinafter, the direction facing the second surface SU2 of the semiconductor substrate 61 may be defined as a fourth direction DR4, and the second surface SU2 may be defined as a surface opposite to the first surface SU1.

[0042] The plurality of conductive layers CDL may include at least one of a doped semiconductor layer and a metal layer. The doped semiconductor layer of each conductive layer CDL may include a doped silicon layer. The metal layer of each conductive layer CDL may include tungsten, copper, molybdenum, etc. The plurality of conductive layers CDL may further include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc. The plurality of interlayer insulating layers ILD may include a silicon oxide layer, etc.

[0043] The memory layer ML and the channel layer CHL may pass through the gate stack GST. The memory layer ML and the channel layer CHL may be disposed in a channel hole extending in a first direction DR1 to pass through a plurality of conductive layers CDL and a plurality of interlayer insulating layers ILD of the gate stack GST. The channel layer CHL may be formed of a semiconductor material. As an embodiment, the channel layer CHL may include silicon, germanium, or a mixture thereof.

[0044] The channel layer CHL may include a contact surface CTS in contact with the doped semiconductor structure DPS. The doped semiconductor structure DPS may be used in at least one of a source region and a well region. As an embodiment, the doped semiconductor structure DPS may be provided as a source region, the source region including n-type impurities as majority carriers. The embodiments of the present disclosure are not limited thereto. As another embodiment, the doped semiconductor structure DPS may include at least one of the following: a first conductive type doped region including n-type impurities as majority carriers, and a second conductive type doped region including p-type impurities as majority carriers. The first conductive type doped region may be provided as a source region, and the second conductive type doped region may be provided as a well region.

[0045] The doped semiconductor structure DPS and the gate stack GST may be disposed at a position spaced apart from the semiconductor substrate 61 in the first direction DR1. The positions of the doped semiconductor structure DPS and the gate stack GST may have various designs. Figure 3 As shown, the doped semiconductor structure DPS may be disposed at a position farther from the semiconductor substrate 61 than the gate stack GST in the first direction DR1. Figure 4 As shown, the doped semiconductor structure DPS may be disposed at a position closer to the semiconductor substrate 61 than the gate stack GST in the first direction DR1 .

[0046] refer to Figure 3 , the gate stack GST may be disposed between the doped semiconductor structure DPS and the semiconductor substrate 61. The contact surface CTS of the channel layer CHL may be coplanar with the sidewall of the doped semiconductor structure DPS, the surface of the doped semiconductor structure DPS facing the fourth direction DR4, etc. As an embodiment, the doped semiconductor structure DPS may include a trench into which the channel layer CHL may be inserted, and the contact surface CTS of the channel layer CHL may be coplanar with the surface of the trench defined in the doped semiconductor structure DPS.

[0047] The gate stack GST and the doped semiconductor structure DPS may be covered by the upper insulating layer UI. A conductive contact CT may be disposed inside the upper insulating layer UI, and the conductive contact CT may be connected to the doped semiconductor structure DPS. Although not shown in the drawings, the conductive contact CT may transmit an electrical signal from a common source line disposed above the upper insulating layer UI to the doped semiconductor structure DPS.

[0048] refer to Figure 4, the doped semiconductor structure DPS may be disposed between the gate stack GST and the semiconductor substrate 61. The contact surface CTS of the channel layer CHL may be coplanar with the sidewalls of the doped semiconductor structure DPS, the surface of the doped semiconductor structure DSP facing the first direction DR1, and the like. As an embodiment, the doped semiconductor structure DPS may include a first semiconductor layer L1, a second semiconductor layer L2, and a third semiconductor layer L3 stacked in the first direction DR1. The channel layer CHL may pass through the third semiconductor layer L3 and extend into the first semiconductor layer L1. The second semiconductor layer L2 may include a sidewall coplanar with the contact surface CTS of the channel layer CHL. In other words, the sidewall of the second semiconductor layer L2 may contact the channel layer CHL.

[0049] Each of the first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 may include at least one of an n-type impurity and a p-type impurity. As an embodiment, each of the first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 may be provided as a first conductive type doping region including an n-type impurity as a majority carrier. As another embodiment, each of the second semiconductor layer L2 and the third semiconductor layer L3 may be provided as a first conductive type doping region including an n-type impurity as a majority carrier, and the first semiconductor layer L1 may be provided as a second conductive type doping region including a p-type impurity as a majority carrier. The first conductive type doping region may be provided as a source region, and the second conductive type doping region may be provided as a well region. The embodiments of the present disclosure are not limited thereto, and the doping regions of the first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 may have various designs. Each of the first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 may include a semiconductor material such as silicon.

[0050] The memory layer ML may be interposed between each of the first semiconductor layer L1 and the third semiconductor layer L3 and the channel layer CHL. The memory layer ML may be separated into the first memory layer ML1 and the second memory layer ML2 by a contact portion between the second semiconductor layer L2 and the channel layer CHL. The first memory layer ML1 may be interposed between the third semiconductor layer L3 and the channel layer CHL, and may extend in the first direction DR1 to be interposed between the gate stack GST and the channel layer CHL. The second memory layer ML2 may be interposed between the channel layer CHL and the first semiconductor layer L1.

[0051] refer to Figure 3 and Figure 4, the core insulating layer CO and the capping pattern CAP may be disposed in a central region of a channel hole passing through the gate stack GST. The channel layer CHL may extend along a side of the core insulating layer CO and a side of the capping pattern CAP. The capping pattern CAP may serve as a drain junction of the memory cell string CS. The capping pattern CAP may include at least one of an n-type impurity and a p-type impurity. As an embodiment, the capping pattern CAP may include an n-type impurity as a majority carrier.

[0052] Figure 3 The memory layer ML and Figure 4 Each of the first memory layers ML1 shown in the figure may include: a blocking insulating layer between the channel layer CHL and the gate stack GST, a data storage layer between the blocking insulating layer and the channel layer CHL, and a tunnel insulating layer between the data storage layer and the channel layer CHL. The blocking insulating layer may include an insulating material capable of blocking charges. The tunnel insulating layer may include an insulating material capable of charge tunneling. The blocking insulating layer may include an insulating layer having a dielectric constant higher than that of the tunnel insulating layer. The data storage layer may be formed of a material layer that can store changed data using Fowler Nordheim tunneling. As an embodiment, the data storage layer may be formed of a charge trapping insulating layer or an insulating layer including conductive nanodots. The charge trapping insulating layer may include a silicon nitride layer. The embodiments of the present disclosure are not limited thereto, and the data storage layer may be formed of a material layer capable of storing information based on an operating principle other than Fowler Nordheim tunneling. As an embodiment, the data storage layer may include a phase change material layer, a ferroelectric layer, etc. In this case, the channel layer CHL, the core insulating layer CO, and the capping pattern CAP may be replaced with a columnar electrode structure.

[0053] Figure 4 The second memory layer ML2 shown in FIG. 5 may be configured the same as the first memory layer ML1 .

[0054] refer to Figure 3 and Figure 4 The semiconductor memory device 50A or 50B may further include a bit line BL. The bit line BL may be disposed at a position spaced apart from the semiconductor substrate 61 in the first direction DR1. The position of the bit line BL may have various designs. As an embodiment, Figure 3 As shown, the bit line BL may be disposed at a position closer to the semiconductor substrate 61 than the gate stack GST in the first direction. In other words, the bit line BL may be disposed between the gate stack GST and the semiconductor substrate 61. As another embodiment, Figure 4As shown, the bit line BL may be disposed at a position farther from the semiconductor substrate 61 than the gate stack GST in the first direction DR1. In other words, the gate stack GST may be disposed between the bit line BL and the semiconductor substrate 61.

[0055] refer to Figure 3 and Figure 4 , the bit line BL may be connected to the capping pattern CAP via a bit line connection structure disposed between the gate stack GST and the bit line BL. As an embodiment, the bit line connection structure may include a conductive bit contact plug BCT and a conductive first via structure V1. The conductive bit contact plug BCT may be disposed inside the first interlayer insulating structure 89 between the gate stack GST and the bit line BL, and may be connected to the capping pattern CAP. The conductive first via structure V1 may be disposed inside the second interlayer insulating structure 91 between the first interlayer insulating structure 89 and the bit line BL, and may electrically connect the conductive bit contact plug BCT to the bit line BL. The bit line BL may be disposed within a bit line level insulating layer 93. The bit line level insulating layer 93 may overlap with the first interlayer insulating structure 89, with the second interlayer insulating structure 91 interposed therebetween.

[0056] The connection between the bit line BL and the capping pattern CAP is not limited to the above-described embodiment. Although not shown in the drawings, as another embodiment, the bit line BL may be directly connected to the capping pattern CAP.

[0057] A capping insulating structure CI may be formed between the gate stack GST and the first interlayer insulating structure 89. The channel layer CHL and the capping pattern CAP may extend toward the bit line BL to pass through a portion of the capping insulating structure CI.

[0058] As an embodiment, the plurality of conductive layers CDL of the gate stack GST may include an end portion forming a step structure. At this time, the capping insulating structure CI may cover the step structure. The embodiments of the present disclosure are not limited thereto, and the plurality of conductive layers CDL of the gate stack GST may include an end portion arranged in a row without forming a step structure.

[0059] refer to Figure 3 and Figure 4 , the semiconductor substrate 61 may include a plurality of active regions 61A separated by an isolation layer 63. A plurality of junction regions 61J1 and 61J2 of the plurality of transistors TR1 and TR2 may be formed in the plurality of active regions 61A.

[0060] The plurality of transistors TR1 and TR2 may configure a first peripheral circuit structure PS1. The first peripheral circuit structure PS1 is Figure 1 The first peripheral circuit structure PS1 may include a block decoder 33 and may include a reference Figure 1At least one of the remaining configurations except the transfer circuit 40 in the described peripheral circuit structure PS. As an embodiment, the first peripheral circuit structure PS1 may include a block decoder 33 and a page buffer 37. The plurality of transistors TR1 and TR2 may include a first transistor TR1 forming a portion of the block decoder 33 and a second transistor TR2 forming a portion of the page buffer 37.

[0061] The plurality of junction regions 61J1 and 61J2 may include a first junction region 61J1 and a second junction region 61J2, and the first junction region 61J1 and the second junction region 61J2 are provided as source junctions and drain junctions of each of the first transistor TR1 and the second transistor TR2. The first junction region 61J1 and the second junction region 61J2 may include at least one conductive type impurity of an n-type impurity and a p-type impurity. As an embodiment, when each of the first transistor TR1 and the second transistor TR2 is provided as an N-channel metal oxide semiconductor (NMOS) transistor, the first junction region 61J1 and the second junction region 61J2 may include an n-type impurity as a majority carrier.

[0062] A gate insulating layer 65 and a gate electrode 66 of each of the first transistor TR1 and the second transistor TR2 may be stacked over an active region 61A of a semiconductor substrate 61 disposed between the first junction region 61J1 and the second junction region 61J2 .

[0063] The gate stack GST may be spaced apart from the first peripheral circuit structure PS1 in the first direction DR1. A lower insulating structure LI may be disposed between the gate stack GST and the first peripheral circuit structure PS1. The lower insulating structure LI may be disposed on the semiconductor substrate 61 and may extend to cover the first transistor TR1 and the second transistor TR2 of the first peripheral circuit structure PS1.

[0064] A plurality of conductive lower connection structures LS and a plurality of global lines GLL may be disposed in the lower insulating structure LI. The plurality of conductive lower connection structures LS may be used as interconnect structures. The plurality of global lines GLL may be used to transmit signals from Figure 1 1 and 2. The conductive pattern of the operating voltage output by the voltage generating circuit 31 shown in FIG.

[0065] The plurality of conductive lower connection structures LS may include a first type of conductive lower connection structure connected to the first transistor TR1 and a second type of conductive lower connection structure connected to the second transistor TR2 . Figure 3 and Figure 4 A second type of conductive lower connection structure is representatively illustrated.

[0066] Each conductive lower connection structure LS may include a lower via structure LV and a lower pad pattern LP. The lower via structure LV may contact one of the gate electrode 66, the first junction region 61J1, and the second junction region 61J2 corresponding to the lower via structure LV, and may extend in the first direction DR1. The lower pad pattern LP may contact the lower via structure LV. The lower pad pattern LP may include an upper surface facing the first direction DR1, and the upper surface of the lower pad pattern LP may include an opening portion not covered by the lower insulating structure LI.

[0067] An upper surface of each global line GLL may include an open portion not covered by the lower insulation structure LI, and may face the first direction DR1.

[0068] The molded insulating structure MIS may be disposed between the lower insulating structure LI and the gate stack GST. The molded insulating structure MIS may include a first region AR1 overlapping the block decoder 33 and a second region AR2 extending from the first region AR1 to the side (e.g., in the second direction DR2). The first region AR1 of the molded insulating structure MIS may overlap the plurality of global lines GLL and the first transistor TR1, and the second region AR2 of the molded insulating structure MIS may overlap the transistor TR2.

[0069] The second peripheral circuit structure PS2 and the first conductive connection structure 81 may be disposed inside the molded insulating structure MIS.

[0070] The second peripheral circuit structure PS2 may include a transfer transistor group of the transfer circuit 40. The transfer transistor group may include a plurality of transfer transistors PT. The plurality of transfer transistors PT may be disposed in a first region AR1 of the molded insulating structure MIS. The plurality of transfer transistors PT may be connected in common to a transfer gate 79. The transfer gate 79 may be used as a gate electrode of each transfer transistor PT. The block selection signal output from the block decoder 33 may be transmitted to the transfer gate 79 through a block selection line (not shown). The transfer gate 79 may be disposed in the first region AR1 of the molded insulating structure MIS. The transfer gate 79 may be penetrated by an active pillar 70 of each transfer transistor PT. The active pillar 70 may contact a global line GLL corresponding thereto. The transfer gate insulating layer 71 of each transfer transistor PT may be disposed between the active pillar 70 and the transfer gate 79.

[0071] The plurality of first conductive connection structures 81 may be disposed in the second area AR2 of the molded insulation structure MIS. The plurality of first conductive connection structures 81 may be included in the interconnection structure.

[0072] The molded insulating structure MIS may include a first insulating layer 67, a second insulating layer 69, and a third insulating layer 83. The first insulating layer 67 may be disposed on the lower insulating structure LI. The first insulating layer 67 may extend along the bottom surface of the transfer gate 79 facing the fourth direction DR4. The second insulating layer 69 may be disposed on the first insulating layer 67. The second insulating layer 69 may face the side surface of the transfer gate 79. The third insulating layer 83 may be disposed on the second insulating layer 69. The third insulating layer 83 may extend along the upper surface of the transfer gate 79 facing the first direction DR1.

[0073] Each first conductive connection structure 81 may be connected to a conductive lower connection structure LS corresponding thereto. The first conductive connection structure 81 may pass through at least one of the first insulating layer 67, the second insulating layer 69, and the third insulating layer 83 in the second region AR2 of the molded insulation structure MIS. As an embodiment, the first conductive connection structure 81 may contact the conductive lower connection structure LS corresponding thereto, and may extend in the first direction DR1 to pass through the first insulating layer 67 and the second insulating layer 69.

[0074] Figure 5A is a cross-sectional view illustrating a pass transistor group according to one embodiment of the present disclosure, and Figure 5B The diagram is along Figure 5A A plan view of the transfer transistor group taken along line AA' shown in FIG.

[0075] refer to Figure 5A and Figure 5B , the plurality of transfer transistors PT of the transfer transistor group may correspond to Figure 3 or Figure 4 A plurality of conductive layers CDL are shown in FIG.

[0076] The channel of each transfer transistor PT of the transfer transistor group may be defined in the active pillar 70. The active pillar 70 may be surrounded by a transfer gate 79. Accordingly, the transfer transistor PT may be formed in a wrap-around gate transistor (SGT) structure. In one embodiment, when the transfer transistor PT is formed in the SGT structure, the area occupied by the transfer transistor PT may be reduced, and the on / off characteristics of the transfer transistor PT may be improved.

[0077] The transfer gate 79 may be formed of a conductive material. The transfer gate 79 may be spaced apart from the global line GLL and the lower insulating structure LI by the first insulating layer 67 of the molded insulating structure MIS. The transfer gate 79 may be formed using a process of replacing a portion of the second insulating layer 69 of the molded insulating structure MIS with a conductive material. In order to replace a portion of the second insulating layer 69 with a conductive material, a plurality of slits SI may be formed during the process of manufacturing the semiconductor memory device. A plurality of slits SI may be retained inside the transfer gate 79 to be spaced apart from each other. Each slit SI may be filled with an insulating material or a conductive material.

[0078] In order to use a process of replacing a portion of the second insulating layer 69 with a conductive material, the second insulating layer 69 may include a material having an etching selectivity with respect to the first insulating layer 67 and the third insulating layer 83. As an embodiment, each of the first insulating layer 67 and the third insulating layer 83 may include a silicon oxide layer, and the second insulating layer 69 may include a silicon nitride layer.

[0079] The active pillar 70 may pass through the first insulating layer 67 to contact the global line GLL. The active pillar 70 may include a channel layer 73 and a semiconductor capping pattern 77. The channel layer 73 and the semiconductor capping pattern 77 may include a semiconductor material such as silicon or germanium.

[0080] The channel layer 73 may pass through the first insulating layer 67 to contact the global line GLL. The channel layer 73 may include a horizontal portion 73HP and a vertical portion 73VP. The vertical portion 73VP may extend from the horizontal portion 73HP in the first direction DR1. The vertical portion 73VP may serve as a channel of the transfer transistor PT. The vertical portion 73VP may be an undoped region or a doped region including at least one of a p-type impurity and an n-type impurity. The horizontal portion 73HP may be a doped region including at least one of a p-type impurity and an n-type impurity having a higher concentration than that of the vertical portion 73VP, and may serve as a source junction of the transfer transistor PT.

[0081] The vertical portion 73VP of the channel layer 73 may be formed in a tubular shape. A semiconductor capping pattern 77 may be disposed in a tubular central region provided by the vertical portion 73VP. The semiconductor capping pattern 77 may be disposed at an upper end of the tubular central region, and a core insulating layer 75 may be disposed at a lower end of the tubular central region. The semiconductor capping pattern 77 may serve as a drain junction of the transfer transistor PT. The semiconductor capping pattern 77 may include impurities of the same conductivity type as the horizontal portion 73HP of the channel layer 73. As an embodiment, when the transfer transistor PT is provided as an NMOS transistor, the semiconductor capping pattern 77 and the horizontal portion 73HP of the channel layer 73 may include n-type impurities as majority carriers.

[0082] The channel length of the transfer transistor PT may be proportional to the length of the vertical portion 73VP of the channel layer 73 in the first direction DR1. In one embodiment, the length of the vertical portion 73VP may be measured in the first direction DR1. The length of the vertical portion 73VP may be proportional to the thickness of the second insulating layer 69 in the first direction DR1. In one embodiment, the thickness of the second insulating layer 69 may be measured in the first direction DR1. The channel length of the transfer transistor PT may be designed to transmit a high operating voltage. The channel length of the transfer transistor PT may be increased by controlling the thickness of the second insulating layer 69 in the first direction DR1. That is, in one embodiment, even without increasing the plane area of ​​the semiconductor substrate 61, the channel length of the transfer transistor PT may be increased, and thus the plane area of ​​the semiconductor substrate 61 allocated to the transfer transistor PT may be reduced. In one embodiment, the plane area of ​​the semiconductor substrate 61 is measured in a plane formed by the second direction DR2 and the third direction DR3. In one embodiment, in order to ensure the channel length of the transfer transistor PT, the second insulating layer 69 may be formed to be thicker than each of the first insulating layer 67 and the third insulating layer 83 in the first direction DR1. For example, the thickness of the second insulating layer 69 in the first direction DR1 may be greater than a total thickness equal to the thickness of the first insulating layer 67 in the first direction DR1 plus the thickness of the third insulating layer 83 in the first direction DR1. In one embodiment, the second insulating layer 69 may be formed thicker than the first insulating layer 67 in the first direction DR1. In one embodiment, the second insulating layer 69 may be formed thicker than the third insulating layer 83 in the first direction DR1.

[0083] The transfer gate insulating layer 71 may surround the sidewall of the vertical portion 73VP of the channel layer 73 .

[0084] refer to Figure 3 and Figure 4 , the interconnection structure of the semiconductor memory device 50A or 50B may further include a plurality of second conductive connection structures 85, a plurality of gate contact plugs GCT, a plurality of second conductive via structures V2, and a plurality of conductive lines CLI.

[0085] A plurality of second conductive connection structures 85 may be disposed inside the first intermediate insulating structure IS1. The first intermediate insulating structure IS1 may be disposed between the gate stack GST and the molded insulating structure MIS. The plurality of second conductive connection structures 85 may include a first type of second conductive connection structure connected to the first conductive connection structure 81 and a second type of second conductive connection structure connected to the active pillar 70. Each second conductive connection structure 85 may include a vertical via pattern and a line pattern. The plurality of second conductive connection structures 85 may pass through the third insulating layer 83 to contact the first conductive connection structure 81 or Figure 5AThe semiconductor capping pattern 77 of the active pillar 70 is shown in FIG.

[0086] The plurality of gate contact plugs GCT may be respectively connected to the plurality of conductive layers GP of the gate stack GST. The plurality of gate contact plugs GCT may extend inside the capping insulating structure CI. The plurality of gate contact plugs GCT may extend to pass through the first interlayer insulating structure 89.

[0087] A plurality of conductive second via structures V2 may be disposed inside the second interlayer insulating structure 91. The plurality of conductive second via structures V2 may be connected to the plurality of gate contact plugs GCT, respectively.

[0088] A plurality of conductive lines CLI may be disposed within the bit line level insulating layer 93. Each conductive line CLI may be connected to a pass transistor PT corresponding to the conductive line CLI via conductive patterns of various structures.

[0089] As an example, via Figure 3 The first conductive bonding structure corresponding to the conductive line CLI among the plurality of first conductive bonding structures 87 shown in FIG. Figure 3 A second conductive bonding structure corresponding to the conductive line CLI among the plurality of second conductive bonding structures 99 shown in FIG. 5 , the conductive line CLI may be connected to the transfer transistor PT.

[0090] refer to Figure 3 , a plurality of first conductive bonding structures 87 may be disposed inside the second intermediate insulating structure IS2. The second intermediate insulating structure IS2 may be disposed between the first intermediate insulating structure IS1 and the gate stack GST. The plurality of first conductive bonding structures 87 may include a metal such as copper. The plurality of first conductive bonding structures 87 may be respectively connected to the plurality of second conductive connection structures 85. The plurality of first conductive bonding structures 87 may be coupled to the plurality of second conductive bonding structures 99.

[0091] The plurality of second conductive bonding structures 99 may be disposed inside the third intermediate insulating structure IS3. The third intermediate insulating structure IS3 may be disposed between the second intermediate insulating structure IS2 and the gate stack GST. The plurality of second conductive bonding structures 99 may include a metal such as copper.

[0092] The interconnect structure of the semiconductor memory device 50A may further include a plurality of conductive third via structures 97. The plurality of conductive third via structures 97 may be disposed inside the fourth intermediate insulating structure 95. The plurality of conductive third via structures 97 may be respectively connected to the plurality of second conductive bonding structures 99. The plurality of conductive third via structures 97 may include a first type of conductive third via structure connected to the bit line BL and a second type of conductive third via structure connected to the conductive line CLI.

[0093] The active pillar 70 of the transfer transistor PT can be set to overlap with the gate contact plug GCT. Therefore, in one embodiment, the interconnect structure (e.g., GCT, V2, CLI, and 85) for connecting the transfer transistor PT and the conductive layer CDL corresponding thereto can be simplified. Each gate contact plug GCT can contact a corresponding conductive layer among the plurality of conductive layers CDL and can extend toward the second conductive bonding structure 99. The gate contact plug GCT can be electrically connected to the active pillar 70 corresponding thereto via the conductive second via structure V2, the conductive line CLI, the second type of conductive third via structure 97, the second conductive bonding structure 99, the first conductive bonding structure 87, and the second type of second conductive connection structure 85.

[0094] Figure 3 The semiconductor memory device 50A shown in FIG. 5 may be provided by the following process: separately performing a process of forming a first structure and a process of forming a second structure, and then combining the first structure and the second structure. The first structure may include: a first peripheral circuit structure PS1 including a block decoder 33, a second peripheral circuit structure PS2 including a transfer transistor PT, a first conductive connection structure 81, a second conductive connection structure 85, and a first conductive bonding structure 87. The second structure may include: a cell array structure CAS, a gate contact plug GCT, a conductive bit contact plug BCT, a bit line BL, a conductive line CLI, a conductive first via structure V1, a conductive second via structure V2, a conductive third via structure 97, and a second conductive bonding structure 99. The process of combining the first structure and the second structure may include combining the first conductive bonding structure 87 and the second conductive bonding structure 99 with each other. The doped semiconductor structure DPS, the upper insulating layer UI, and the conductive contact portion CT may be formed after combining the first structure and the second structure.

[0095] As another example, Figure 4 As shown, the gate stack GST may be inserted between the conductive line CLI and the transfer transistor PT. In this case, the second conductive connection structure 85 of the second type connected to the conductive line CLI and the transfer transistor PT may extend to overlap with the peripheral region (not shown in the drawings) of the semiconductor substrate 61. A via contact plug (not shown) may be provided between the overlapping portion of the conductive line CLI and the portion of the second conductive connection structure 85 of the second type in the peripheral region (not shown) of the semiconductor substrate 61. The conductive line CLI may be connected to the transfer transistor PT via the via contact plug.

[0096] refer to Figure 4The second intermediate insulating structure IS2 may be disposed between the first intermediate insulating structure IS1 and the gate stack GST. The doped semiconductor structure DPS may be disposed between the second intermediate insulating structure IS2 and the gate stack GST to be spaced apart from the second conductive connection structure 85 .

[0097] manufacture Figure 4 The method of the semiconductor memory device 50B shown in FIG. 1 may include a process of forming a first peripheral circuit structure PS1 including a block decoder 33, a second peripheral circuit structure PS2 including a pass transistor PT, and a lower structure including a first conductive connection structure 81 and a second conductive connection structure 85. On top of the lower structure, a process of forming a doped semiconductor structure DPS and a process of forming a doped semiconductor structure DPS may be performed. Figure 4 4. The process of the cell array structure CAS of the semiconductor memory device 50B is shown in FIG.

[0098] refer to Figure 3 and Figure 4 In one embodiment, by providing a transfer transistor PT of the transfer transistor group between the block decoder 33 and the gate stack GST, the area of ​​the interconnection structure for connection between the conductive layer CDL of the gate stack GST, the transfer transistor PT, and the block decoder 33 can be reduced. In one embodiment, by making the active pillar 70 of the transfer transistor PT overlap with and contact the global line GLL, the connection between the transfer transistor PT and the global line GLL can be simplified.

[0099] FIG. 6A to FIG. 6L is a cross-sectional view illustrating a method of manufacturing a first conductive connection structure and a transfer transistor group of a semiconductor memory device according to one embodiment of the present disclosure.

[0100] refer to Fig. 6A , a first peripheral circuit structure including a plurality of transistors TR1 and TR2 may be formed. As an embodiment, forming the first peripheral circuit structure may include: forming an isolation layer 103 separating a plurality of active regions 101A in the semiconductor substrate 101; forming a stacked structure of a gate insulating layer 105 and a gate electrode 107 on each of the plurality of active regions 101A separated by the isolation layer 103; and forming a first junction region 101J1 and a second junction region 101J2 by ​​injecting conductive impurities into the active region 101A.

[0101] As reference Figure 3 and Figure 4 As described, the plurality of transistors TR1 and TR2 may include a first transistor TR1 included in a block decoder, and a second transistor TR2 included in a page buffer.

[0102] Subsequently, a structure may be formed, which includes: a lower insulating structure 109 covering a plurality of transistors TR1 and TR2, a conductive lower connection structure 110 inside the lower insulating structure 109, and a global line 113B. As an embodiment, forming the structure may include: forming a lower insulating layer of the lower insulating structure 109 on the semiconductor substrate 101 to cover the plurality of transistors TR1 and TR2; forming a lower via structure 111, the lower via structure 111 passing through the lower insulating layer to contact one of the gate electrode 107, the first junction region 101J1, and the second junction region 101J2 corresponding to the lower via structure 111; forming an upper insulating layer of the lower insulating structure 109 on the lower insulating layer; and forming a lower pad pattern 113A and a global line 113B in the upper insulating layer. The lower pad pattern 113A may contact the lower via structure 111. The lower via structure 111 and the lower pad pattern 113A may form a conductive lower connection structure 110. The global line 113B may be formed simultaneously with the lower pad pattern 113A using the process of forming the lower pad pattern 113A. The words "simultaneously" and "simultaneously" as used herein with respect to a process mean that the process occurs at overlapping time intervals. For example, if a first process occurs over a first time interval and a second process occurs simultaneously over a second time interval, the first time interval and the second time interval at least partially overlap each other, so that there is a time when both the first process and the second process occur.

[0103] Thereafter, a first insulating layer 115 may be formed over the lower insulating structure 109. The first insulating layer 115 may include a first region AR1 overlapping the block decoder including the first transistor TR1 and the global line 113B, and a second region AR2 extending laterally from the first region AR1. In one embodiment, the second region AR2 extending laterally from the first region AR1 may be in a direction just opposite to the second direction DR2. The second region AR2 may overlap the second transistor TR2 and the conductive lower connection structure 110.

[0104] Subsequently, the second insulating layer 117 may be formed over the first insulating layer 115. The second insulating layer 117 may include a material having an etch selectivity with respect to the first insulating layer 115. As an embodiment, the first insulating layer 115 may include a silicon oxide layer, and the second insulating layer 117 may include a silicon nitride layer.

[0105] The second insulating layer 117 may extend to overlap the first and second regions AR1 and AR2 of the first insulating layer 115 .

[0106] refer to Figure 6B, a contact hole 118A and an active hole 118B may be formed through the first insulating layer 115 and the second insulating layer 117. As an embodiment, the process of forming the contact hole 118A and the active hole 118B may include: forming a mask pattern (not shown) on the second insulating layer 117, etching the first insulating layer 115 and the second insulating layer 117 through a plurality of openings of the mask pattern, and removing the mask pattern. The plurality of openings of the mask pattern may correspond to the contact hole 118A and the active hole 118B, respectively.

[0107] The active hole 118B may pass through the first area AR1 of the first insulating layer 115 and a portion of the second insulating layer 117 overlapping the first area AR1. A first width W1 of the active hole 118B may be twice or more the second width W2 of the contact hole 118A.

[0108] The contact hole 118A may pass through the second area AR2 of the first insulating layer 115 and a portion of the second insulating layer 117 overlapping the second area AR2. The contact hole 118A may expose the conductive lower connection structure 110 corresponding thereto.

[0109] refer to Figure 6C , a preliminary insulating layer 121 may be formed on the second insulating layer 117. The thickness of the preliminary insulating layer 121 may be controlled to fill the central region of the contact hole 118A and open the central region of the active hole 118B. As an embodiment, the thickness of the preliminary insulating layer 121 may be controlled to be half or more of the second width W2 and less than half of the first width W1.

[0110] refer to Fig.6D , can be etched Figure 6C 121, so that the preliminary insulating layer 121 may be separated into a transfer gate insulating layer 121G and a dummy insulating layer 121D. At this time, the global line 113B overlapping the active hole 118B may be exposed, and the second insulating layer 117 may be exposed.

[0111] The dummy insulating layer 121D may remain inside the contact hole 118A, and the transfer gate insulating layer 121G may remain on the sidewall of the active hole 118B. Figure 6C The preliminary insulating layer 121 shown in FIG. 1 may be etched by an etching process such as etch-back. The transfer gate insulating layer 121G remaining on the sidewall of the active hole 118B may have a thickness greater than Figure 6C The thickness of the preliminary insulating layer 121 is shown reduced.

[0112] refer to Fig. 6EIn a state where the dummy insulating layer 121D remains, the channel layer 123 may be formed inside the active hole 118B. The channel layer 123 may be formed to open the central region of the active hole 118B. The channel layer 123 may include silicon, germanium, or a mixture thereof.

[0113] The channel layer 123 may be spaced apart from the second insulating layer 117 by the transfer gate insulating layer 121G. The channel layer 123 may extend along the transfer gate insulating layer 121G. The channel layer 123 may extend along the surface of the global line 113B opened by the active hole 118B and may contact the global line 113B.

[0114] Subsequently, the conductive impurities 119 may be implanted through the central region of the active hole 118B opened by the channel layer 123. Thus, a junction region may be formed in a partial region of the channel layer 123 adjacent to the global line 113B.

[0115] refer to Fig. 6F , in a state where the dummy insulating layer 121D remains, a core insulating layer 125 and a semiconductor capping pattern 127 may be formed in a central region of the active hole 118B opened by the channel layer 123. The semiconductor capping pattern 127 may be separated from the global line 113B by the core insulating layer 125. The semiconductor capping pattern 127 may include silicon, germanium, or a mixture thereof. The semiconductor capping pattern 127 may be doped with impurities 129 of the same conductivity type as a junction region defined inside a partial region of the channel layer 123 adjacent to the global line 113B.

[0116] By reference Fig. 6E and Fig. 6F According to the described process, the active pillar 120 may be formed to include a channel layer 123 and a semiconductor capping pattern 127 and contact the global line 113B.

[0117] According to the above-described series of processes, the active hole 118B for the active pillar 120 may be formed using the process of forming the contact hole 118A, thereby reducing the number of unit processes required to manufacture a semiconductor device.

[0118] refer to Figure 6G , a buffer layer 129 may be formed on the second insulating layer 117. The buffer layer 129 may include an opening OP. The opening OP may expose the dummy insulating layer 121D corresponding thereto. Subsequently, by removing the dummy insulating layer 121D exposed through the opening OP, the contact hole 118A may be opened, as shown in FIG. Figure 6H shown.

[0119] refer to Figure 6H , the conductive lower connection structure 110 may be exposed through the opened contact hole 118A.

[0120] refer to Fig.6I, the first conductive connection structure 131 may be formed inside the contact hole 118A.

[0121] As an embodiment, forming the first conductive connection structure 131 may include: forming a conductive material to fill the inside of the contact hole 118A, and removing a portion of the conductive material. As an embodiment, a planarization process such as chemical mechanical polishing (CMP) may be used to remove a portion of the conductive material so that the second insulating layer 117 is exposed. At this time, the conductive material may be removed. Figure 6H Buffer layer 129 is shown in FIG.

[0122] The process of forming the first conductive connection structure 131 and the active pillar 120 is not limited to the above series of processes. As another embodiment, in the formation Figure 6B The process of forming the active hole 118B shown in FIG. Figure 6B The process of forming the contact hole 118A shown in FIG. 1 and the process of forming the contact hole 118A can be performed after filling the contact hole with the first conductive connection structure 131. Figure 6B After forming the first conductive connection structure 131, a transfer gate insulating layer 121G and an active pillar 120 may be formed inside the active hole. As another embodiment, in the process of forming the active hole 118B. Figure 6B The process of forming the contact hole 118A shown in FIG. Figure 6B The process of forming the active hole 118B shown in FIG. 1 and the formation of the active hole 118B may be performed after forming the transfer gate insulating layer 121G and the active pillar 120 inside the active hole. Figure 6B After forming the active pillar 120, a first conductive connection structure 131 may be formed inside the contact hole.

[0123] After the first conductive connection structure 131 and the active pillar 120 are formed by various methods as described above, a third insulating layer 137 may be formed on the second insulating layer 117. Fig.6I The third insulating layer 137 may extend to cover the first conductive connection structure 131 and the active pillar 120. The third insulating layer 137 may be formed of the same material as the first insulating layer 115. As an embodiment, the third insulating layer 137 may include a silicon oxide layer.

[0124] refer to Figure 6J , a slit 141 may be formed passing through the second insulating layer 117 and the third insulating layer 137. The slit 141 may overlap the first area AR1 of the first insulating layer 115.

[0125] refer to Figure 6K, the portion of the second insulating layer 117 exposed by the slit 141 may be selectively removed. Therefore, the gate region 143 may be opened between the first insulating layer 115 and the third insulating layer 137. The gate region 143 may be defined around the active pillar 120 and the transfer gate insulating layer 121G.

[0126] Then, if Figure 6L As shown, gate region 143 may be filled with transfer gate 145 .

[0127] refer to Figure 6L , a transfer gate 145 may be formed by introducing a conductive material through the slit 141. The transfer gate 145 may be formed to surround the active pillar 120 and the transfer gate insulating layer 121G.

[0128] The second insulating layer 117 may remain between the second region AR2 of the first insulating layer 115 and the third insulating layer 137 , and may face the side of the transfer gate 145 .

[0129] The slit 141 may be filled with a conductive material or an insulating material for the transfer gate 145 .

[0130] Through the above-described series of processes, the transfer transistor PT may be formed to include the transfer gate 145 , the active pillar 120 , and the transfer gate insulating layer 121G.

[0131] Subsequently, the process for forming a reference Figure 3 and Figure 4 The subsequent processes of the second conductive connection structure, the unit array structure, etc. are described.

[0132] Figure 7 is a block diagram illustrating an electronic system including a semiconductor memory device according to one embodiment of the present disclosure.

[0133] refer to Figure 7 The electronic system 1000 may be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system 1000 may include a host 1100 and a storage device 1200 .

[0134] Based on the interface, the host 1100 may store data in the storage device 1200 or read data stored in the storage device 1200. The interface may include at least one of a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a PCI-Express (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial-ATA interface, a parallel-ATA interface, a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE) interface, a FireWire interface, a universal flash storage (UFS) interface, and a non-volatile memory express (NVMe) interface.

[0135] The storage device 1200 may include a memory controller 1210 and a semiconductor memory device 1220. As one embodiment, the storage device 1200 may be a storage medium such as a solid state drive (SSD) or a USB memory.

[0136] The memory controller 1210 may store data in the semiconductor memory device 1220 or read data stored in the semiconductor memory device 1220 under the control of the host 1100 .

[0137] The semiconductor memory device 1220 may include one memory chip or a plurality of memory chips. The semiconductor memory device 1220 may store data or output stored data under the control of the memory controller 1210.

[0138] In one embodiment, the semiconductor memory device 1220 may be a non-volatile memory device. Figure 3 or Figure 4 As described, in one embodiment, the semiconductor memory device 1220 may include a first peripheral circuit structure, a cell array structure, a molding insulating structure disposed between the first peripheral circuit structure and the cell array structure, and a second peripheral circuit structure disposed in the molding insulating structure and including a transfer transistor.

[0139] According to various embodiments of the present disclosure, the area occupied by a pass transistor may be reduced, thereby improving the integration density of a semiconductor memory device.

Claims

1. A semiconductor memory device, comprising: Multiple transistors; a lower insulating structure covering the plurality of transistors; a global line disposed within the lower insulating structure; a molded insulating structure disposed over the lower insulating structure and comprising a first region overlapping the global line and a second region extending laterally from the first region; a transfer gate disposed in the first region of the molded insulating structure; an active pillar passing through the transfer gate and contacting the global line; a transfer gate insulating layer, located between the active pillar and the transfer gate; a first conductive connection structure disposed in the second region of the molded insulating structure; as well as A cell array structure includes a plurality of memory cells, and the cell array structure is arranged on the molded insulating structure.

2. The semiconductor memory device according to claim 1, wherein the molded insulating structure comprises: a first insulating layer disposed on the lower insulating structure and extending along a bottom surface of the transfer gate; a second insulating layer disposed on the first insulating layer and facing a side surface of the transfer gate; as well as A third insulating layer is disposed on the second insulating layer and extends along an upper surface of the transfer gate. 3 . The semiconductor memory device according to claim 2 , wherein the second insulating layer includes a material having an etching selectivity with respect to the first insulating layer and the third insulating layer.

4. The semiconductor memory device according to claim 1, wherein the plurality of transistors comprises: a first transistor overlapping the first region of the molded insulating structure; as well as A second transistor overlaps the second region of the molded insulating structure. 5 . The semiconductor memory device according to claim 4 , wherein the first transistor is included in a block decoder configured to output a block selection signal transmitted to the transfer gate.

6. The semiconductor memory device according to claim 4, further comprising: a conductive lower connecting structure disposed inside the lower insulating structure and connected to the second transistor, The first conductive connection structure contacts the conductive lower connection structure.

7. The semiconductor memory device of claim 1 , wherein the active pillar comprises: a channel layer including a horizontal portion contacting the global line and a vertical portion extending from the horizontal portion toward the cell array structure; as well as A semiconductor capping pattern is disposed in a central region of the vertical portion in the channel layer. 8 . The semiconductor memory device of claim 7 , wherein the horizontal portion of the channel layer and the semiconductor capping pattern include impurities of the same conductivity type.

9. The semiconductor memory device according to claim 1, further comprising: A plurality of slits are disposed inside the transfer gate and are spaced apart from each other.

10. The semiconductor memory device according to claim 1, wherein the cell array structure comprises: a gate stack on the molded insulating structure, the gate stack comprising a plurality of conductive layers spaced apart and stacked from each other in a first direction, the first direction being opposite to a direction toward the molded insulating structure; a channel layer passing through the gate stack; as well as A memory layer is between the channel layer and the gate stack.

11. The semiconductor memory device according to claim 10, further comprising: A first intermediate insulating structure disposed between the gate stack and the molded insulating structure; a conductive connection structure disposed inside the first intermediate insulating structure and connected to the active pillar; A second intermediate insulating structure, disposed between the first intermediate insulating structure and the gate stack; a first conductive bonding structure disposed inside the second intermediate insulating structure and connected to the conductive connecting structure; a third intermediate insulating structure disposed between the second intermediate insulating structure and the gate stack; a second conductive bonding structure disposed inside the third intermediate insulating structure and bonded to the first conductive bonding structure; as well as A gate contact plug extends from a conductive layer corresponding to the second conductive bonding structure among the plurality of conductive layers toward the second conductive bonding structure.

12. The semiconductor memory device according to claim 10, further comprising: A first intermediate insulating structure disposed between the gate stack and the molded insulating structure; a conductive connection structure disposed inside the first intermediate insulating structure and connected to the active pillar; A second intermediate insulating structure, disposed between the first intermediate insulating structure and the gate stack; a doped semiconductor structure disposed between the second intermediate insulating structure and the gate stack and connected to the channel layer; as well as A plurality of gate contact plugs are respectively connected to the plurality of conductive layers and extend in the first direction.

13. A semiconductor memory device comprising: A first peripheral circuit structure including a block decoder; a gate stack spaced apart from the first peripheral circuit structure in a first direction and comprising a plurality of conductive layers spaced apart and stacked in the first direction; a molded insulating structure disposed between the gate stack and the first peripheral circuit structure and comprising a first region overlapping the block decoder and a second region extending laterally from the first region; as well as A second peripheral circuit structure is disposed in the first region of the molded insulating structure and includes a plurality of pass transistors configured to operate in response to a block selection signal output from the block decoder.

14. The semiconductor memory device of claim 13 , wherein each of the plurality of pass transistors comprises: a transfer gate disposed in the first region of the molded insulating structure; an active pillar passing through the transfer gate; as well as A transfer gate insulating layer is located between the active pillar and the transfer gate.

15. The semiconductor memory device according to claim 14, further comprising: a lower insulating structure disposed between the first peripheral circuit structure and the molded insulating structure; as well as A global line is disposed within the lower insulating structure and contacts the active pillar.

16. The semiconductor memory device according to claim 14, further comprising: A plurality of slits are disposed inside the transfer gate and are spaced apart from each other.

17. The semiconductor memory device according to claim 14, wherein the molded insulating structure comprises: a first insulating layer extending along a bottom surface of the transfer gate and penetrated by the active pillar; a second insulating layer disposed on the first insulating layer and facing a side surface of the transfer gate; as well as A third insulating layer is disposed on the second insulating layer and extends along an upper surface of the transfer gate. 18 . The semiconductor memory device according to claim 17 , wherein the second insulating layer includes a material having an etching selectivity with respect to the first insulating layer and the third insulating layer.

19. The semiconductor memory device according to claim 13, further comprising: a plurality of first conductive bonding structures connected to the plurality of pass transistors; a channel layer passing through the gate stack; a memory layer between the channel layer and the gate stack; a plurality of gate contact plugs respectively contacting the plurality of conductive layers and extending toward the plurality of transfer transistors; as well as A plurality of second conductive bonding structures are respectively connected to the plurality of gate contact plugs and respectively bonded to the plurality of first conductive bonding structures.

20. The semiconductor memory device according to claim 13, further comprising: a channel layer passing through the gate stack; a memory layer between the channel layer and the gate stack; a doped semiconductor structure disposed between the gate stack and the molded insulating structure and connected to the channel layer; as well as A plurality of gate contact plugs respectively contact the plurality of conductive layers and extend in the first direction.

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