Capacitor assembly and amplifier

Abstract

A capacitor assembly includes an upper first capacitor and a lower second capacitor vertically stacked on a substrate. The invention also relates to an amplifier comprising such a capacitor assembly. According to the invention, the capacitor assembly comprises a ground plane (M2) arranged between a first conductive layer (M3) and a first terminal (T1HD) of a second capacitor, where a second terminal (T2HD) of the second capacitor is electrically connected to the ground plane (M2) and the first conductive layer (M3) through one or more vias (V1, V2), wherein the ground layer (M2) comprises a stress relief opening (M2o) laterally spaced from the stress relief opening (M3o) of the first conductive layer (M3).

Description

Technical Field

[0001] The present invention provides a capacitor assembly, comprising a first capacitor and a second capacitor vertically stacked on a substrate. The present invention also relates to an amplifier comprising the capacitor assembly. Background Art

[0002] Contemporary radiofrequency (RF) amplifiers used in telecommunication systems such as base stations are subject to stringent requirements in terms of system linearity. Nonlinear behavior may result in signal distortion. RF amplifiers typically include power transistors such as laterally diffused metal-oxide-semiconductor (LDMOS) transistors or gallium nitride field-effect transistors.

[0003] In order to improve the linearity of the RF amplifier, it is important to control the impedance of the output of the power transistor in the so-called video bandwidth. In the art, it is known that there is an RF short circuit in the video bandwidth, which is usually achieved by using a relatively large capacitor in the range of 0.1nF to 10nF. At the same time, a capacitor with a smaller capacitance in the range of 5pF to 500pF is connected to the output of the power transistor to obtain impedance matching.

[0004] In order to obtain a compact RF amplifier, it is preferred to implement as many components as possible within a given footprint without compromising performance. Furthermore, contemporary technology for manufacturing the above-mentioned large and small capacitors allows for vertical stacking of these capacitors.

[0005] US2023223332A1 discloses in its abstract a first well and a second well formed in a semiconductor substrate. The first and second trenches in the first and second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on the top surface of the semiconductor substrate. The second insulating layer above the second trench is selectively thinned. A polysilicon layer is deposited on the second insulating layer and then photolithographically patterned to form: a first polysilicon portion above the first well, which is electrically connected to the central conductor of the first trench to form a first capacitor plate, the second capacitor plate being formed by the first well; and a second polysilicon portion above the second well, which forms a floating gate electrode of a floating gate transistor of a memory cell, the memory cell having an access transistor, the control gate of the access transistor being formed by the central conductor of the second trench.

[0006] CN115631688A discloses a display panel, a method for preparing the same, and an electronic device.

[0007] Applicants have discovered that known methods for vertically stacking capacitors introduce unwanted coupling between the capacitors. Summary of the invention

[0008] An object of the present invention is to provide a capacitor assembly comprising a first capacitor and a second capacitor vertically stacked on a substrate, which reduces coupling between the capacitors.

[0009] According to the present invention, the first capacitor includes a first terminal and a second ground terminal, wherein the second ground terminal is formed by a first conductive layer including a release opening. The second capacitor includes a first terminal and a second ground terminal.

[0010] The second ground terminal of the first capacitor is located below the first terminal of the first capacitor relative to the surface of the substrate, and the second ground terminal of the second capacitor is located below the first terminal of the second capacitor. In addition, the second capacitor is located below the first capacitor.

[0011] According to the present invention, the capacitor assembly further comprises a grounding layer arranged between the first conductive layer and the first terminal of the second capacitor, wherein the second grounding terminal of the second capacitor is electrically connected to the grounding layer and the first conductive layer through one or more through holes, wherein the grounding layer comprises a release opening laterally spaced apart from the release opening of the first conductive layer.

[0012] In manufacturing technologies such as semiconductor technology, it is usually forbidden to use large metal planes. In order to comply with design rules, the plane should be provided with openings, the size of which can reach 5um. In the context of the present invention, these openings are called release openings.

[0013] It should be noted that in the context of the present invention, openings in different vertical layers of the capacitor component are referred to as being laterally spaced from each other when their respective normal projections on the surface of the substrate do not overlap.

[0014] The applicant has found that by using the configuration of the capacitor assembly according to the present invention, it is possible to prevent and / or limit the capacitive coupling between the first terminal of the first capacitor and the first terminal of the second capacitor, while ensuring high manufacturability and reliability of the capacitor assembly. More specifically, the normal projection of the second ground terminal of the first capacitor on the substrate is combined with the normal projection of the ground layer on the substrate to produce a plane that is completely "filled" with conductive material. Therefore, electromagnetic coupling between the first capacitor and the second capacitor is prevented or at least limited.

[0015] The first terminal of the first capacitor may be formed by a capacitor top metal layer. The capacitor top metal layer may include a release opening, wherein the release opening in the ground layer is laterally spaced from the release opening of the capacitor top metal layer. In this way, any field lines extending from the capacitor top metal layer perpendicular to the capacitor top metal layer and down to the substrate will "see" the ground plane and therefore will not cause or almost no electromagnetic coupling between the first capacitor and the second capacitor.

[0016] The capacitor top metal layer may comprise a plurality of strips arranged in parallel and laterally separated by release openings of the capacitor top metal layer.The release openings in the ground layer are preferably arranged below the strips, preferably completely below the strips.

[0017] The capacitor assembly may also include a second conductive layer separated from the capacitor top metal layer by a dielectric layer, wherein the second conductive layer is electrically connected to the capacitor top metal layer by one or more through holes through the dielectric layer. The second conductive layer may include a release opening laterally separated from the release opening in the capacitor top metal layer. The second conductive layer may typically be made using a thicker metal layer than the capacitor top metal layer, thereby reducing the resistance of the first capacitor.

[0018] The capacitor assembly may further include a third conductive layer separated from the second conductive layer by a dielectric layer, wherein the third conductive layer is electrically connected to the second conductive layer by one or more vias through the dielectric layer. The third conductive layer may include a release opening laterally aligned with the release opening in the first conductive layer.

[0019] The capacitor assembly may further include a fourth conductive layer that is separated from the ground plane by the dielectric layer and is electrically connected to the first terminal of the second capacitor and / or forms the first terminal of the second capacitor, wherein the fourth conductive layer includes a release opening that is laterally separated from the release opening in the ground plane. More specifically, the release opening in the fourth conductive layer may be formed around a through hole for connecting the second ground terminal of the second capacitor to the ground plane.

[0020] The first terminal of the second capacitor may be formed by a fifth conductive layer separated from the fourth conductive layer by a dielectric layer, wherein the fourth conductive layer is electrically connected to the fifth conductive layer by one or more vias passing through the dielectric layer. For example, the fifth conductive layer may include a polysilicon layer, and the fourth conductive layer may include a metal layer having a reduced sheet resistance compared to the polysilicon layer.

[0021] The capacitor assembly may include a plurality of identical and adjacently arranged unit cells, each unit cell including a first capacitor unit cell, a second capacitor unit cell and a ground plane segment. Typically, when a capacitor assembly is designed using a computer-aided design (CAD) tool, the capacitor assembly may be provided in the form of a scalable component, wherein a given capacitance value of the first capacitor and / or the second capacitor may be obtained by selecting the number of unit cells to be used and the size of such unit cells.

[0022] For such unit cells, the relief openings of the ground plane are preferably each arranged in a respective central region of one of the unit cells.

[0023] The release openings of the fourth conductive layer are preferably arranged at the corresponding corners of the corresponding second capacitor unit cores. Similarly, the release openings of the first conductive layer are preferably arranged at the corresponding edges of the corresponding first capacitor unit cores. The release openings of the second conductive layer are preferably arranged at the center of the corresponding first capacitor unit cores. The release openings of the third conductive layer are preferably arranged at the corresponding edges of the corresponding first capacitor unit cores.

[0024] The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the ground layer, and the capacitor top metal layer may each include one or more metals. Typically, these metals are part of a so-called metal stack. The fifth conductive layer may include a polysilicon layer. Alternatively, the fifth conductive layer may also include one or more metals.

[0025] The substrate may be a semiconductor substrate, such as a silicon substrate or a gallium nitride substrate. It should be noted that the gallium nitride substrate may include gallium nitride (GaN) and / or a gallium nitride-based layer, such as an AlN layer or an AlGaN layer, that has been grown on a substrate that may be different from GaN. For example, GaN substrates using silicon, silicon carbide or sapphire substrates are known, on which GaN or a GaN-based layer is grown.

[0026] The first capacitor may be a metal-insulator-metal capacitor, and / or the second capacitor may be a high-density capacitor. In the case where the second capacitor is a high-density capacitor, it may be implemented as a deep trench capacitor, the deep trench capacitor comprising a plurality of trenches in a semiconductor substrate, the inner walls of the trenches being covered with a first insulating layer, wherein a fifth conductive layer covers the first insulating layer, and wherein the semiconductor substrate comprises one or more doped regions forming a second ground terminal of the second capacitor. In addition, the metal-insulator-metal capacitor may include a second insulating layer arranged between the top metal layer of the capacitor and the first conductive layer. The insulating layer typically comprises silicon oxide, silicon oxynitride, or silicon nitride.

[0027] According to a second aspect of the present invention, there is provided an amplifier, comprising a field-effect transistor (FET) having an output capacitance and the above capacitor assembly. The amplifier further comprises a shunt network connected to the drain of the FET and comprising a series connection of a first inductor and a first capacitor of the capacitor assembly, wherein the first inductor is connected to the drain of the FET, and wherein a first terminal of the first capacitor of the capacitor assembly is connected to the first inductor.

[0028] The shunt network also includes a second capacitor of the capacitor assembly, the second capacitor being connected in series with the second inductor, wherein the second inductor is connected between a first terminal of the first capacitor of the capacitor assembly and a second capacitor of the capacitor assembly, wherein the first terminal of the second capacitor of the capacitor assembly is connected to the second inductor. As an example, the FET may include a silicon-based laterally diffused metal oxide semiconductor (LDMOS) transistor. In this case, the insulating layer of the deep trench capacitor may be formed by a gate oxide layer of the LDMOS transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Next, the present invention will be described with reference to the accompanying drawings, in which the same or similar components will be denoted by the same reference numerals, in which:

[0030] Figure 1 shows a cross section of an embodiment of a capacitor assembly according to the present invention;

[0031] Figure 2 Shown with Figure 1 further details relating to the second capacitor of the capacitor assembly;

[0032] Figure 3 The top view shows the method for manufacturing Figure 1 The individual layers of the unit cells of the capacitor assembly;

[0033] Figure 4 shows how to combine multiple unit cells to form a capacitor assembly; and

[0034] Figure 5 An amplifier including the capacitor assembly of the present invention is shown. DETAILED DESCRIPTION

[0035] Figure 1 A cross section of an embodiment of a capacitor assembly according to the invention is shown. Figure 2 Further details of the second capacitor used in this assembly are provided in.

[0036] The capacitor component 1 is implemented on a silicon substrate 2. The semiconductor technology used to manufacture the capacitor component 1 is the LDMOS process. Figure 5 As shown, according to the present invention, the capacitor assembly 1 can be advantageously combined with an LDMOS transistor.

[0037] The above technology includes several conductive layers as described in the following table: Layer Name Layer thickness Layer Material M1 400-800nm aluminum M2 400-800nm aluminum M3 400-800nm aluminum M4 1500-2500nm aluminum M5 2500-3500nm aluminum CTM 100-200nm Tin (TiN) P 500-800nm Polysilicon

[0038] Reference now Figure 2 , the second capacitor is formed as a deep trench capacitor (DTC). The deep trench capacitor includes a plurality of trenches T formed in the semiconductor substrate 2, usually using dry etching technology. The inner wall of the trench T is covered with a first insulating layer IN1. In this case, IN1 is a silicon oxide-silicon nitride-silicon oxide stack with a thickness between 100nm and 200nm.

[0039] On top of the layer IN1, a first terminal T1HD made using a polysilicon layer P is arranged. Since the sheet resistance of polysilicon is relatively high, a metal layer M1 is used. This layer is separated from the layer P by a dielectric layer D1, which in this case is a silicon oxide layer with a thickness between 1000nm and 2000nm. The electrical connection between the first terminal T1HD formed in the layer P and the metal structure formed in the layer M1 is realized using a via V1.

[0040] The second terminal T2HD of the deep trench capacitor is formed by the doped region 4 in the semiconductor substrate 2. In order to achieve an ohmic contact with the doped region 4, a highly doped n-type contact region 5 is formed in the semiconductor substrate 2. Typically, a contact metal layer (not shown) is arranged on the contact region 5 to form an ohmic contact. The contact metal layer is then connected to a patch M1P formed in the layer M1 using a via V1. The patch M1P is in turn connected to a ground plane implemented using the layer M2 using a via V2, wherein the ground plane is connected to the second terminal T2MIM of the first capacitor implemented in the metal layer M3 using a via V3. As shown in FIG. Figure 1 As shown, some of the vias V1, V2, V3 may be stacked to form pillars connecting the T2HD to the T2MIM.

[0041] Reference now Figure 1The first capacitor is a metal-insulator-metal capacitor (MIMCAP), wherein a second insulating layer IN2 is arranged between a first electrode T1MIM made in a capacitor top metal (CTM) layer and a second electrode T2MIM made in a metal layer M3, the second insulating layer IN2 comprising silicon nitride and having a thickness between 200 nm and 300 nm. The second electrode T2MIM is connected to a ground plane formed in the metal layer M2.

[0042] Hereinafter, reference numerals may refer to a specific layer, such as metal layer M2, or may refer to a structure formed in the layer. For example, a first capacitor is formed by a second insulating layer IN2 disposed between CTM and M2.

[0043] The second electrode T2MIM is connected to the ground plane M2 using a via V3. In addition, the metal layers M1 and M2 are separated by a dielectric layer D2, which is a layer made of silicon oxide with a thickness between 700nm and 1100nm. In addition, the metal layers M2 and M3 are separated by a dielectric layer D3, which is a layer made of silicon oxide with a thickness between 700nm and 1100nm. The electrical connection between the metal layers M2 and M3 is achieved using a via V3.

[0044] Since the sheet resistance of the CTM layer is relatively high, metal layers M4 and M5 are used. Here, the CTM layer and the metal layer M4 are separated by a dielectric layer D4, which is a layer made of silicon oxide with a thickness between 1000nm and 1400nm, and the metal layers M4 and M5 are separated by a dielectric layer D5, which is a layer made of silicon oxide with a thickness between 1000nm and 1300nm. The connection between the metal layer M5 and the metal layer M4 is achieved using a via V5, and the via V4 is used to connect the metal layer M4 and the CTM layer.

[0045] exist Figure 1 In FIG. 1 , the hyphen “{” is used to indicate openings in various layers. For example, M1o, M2o, M3o, M4o, and M5o are used to indicate openings in metal layers M1, M2, M3, M4, and M5, respectively. These openings are necessary for stress relief.

[0046] According to the present invention, the openings in the various layers have a specific relative arrangement. Figure 3 and Figure 4 To explain this. Figure 3 The top view shows the method for manufacturing Figure 1 The individual layers of the unit cells of the capacitor assembly, and Figure 4It shows how to combine multiple unit cells to form a capacitor assembly. Figure 3 In the figure, the headings between brackets "()" indicate a specific layer order.

[0047] exist Figure 3 , (I) represents a structure formed in the polysilicon layer P for a unit cell. In addition, vias V1 and V2 are represented by black rectangles. Figure 3 (II) represents a larger metal pad formed in metal layer M1. Similarly, a patch is formed in metal layer M1, which is electrically connected to via V2 but not to the larger metal pad in the center. It can be seen that an opening M1o exists between the patch in metal layer M1 and the larger pad in the center. Opening M1o is sufficient to meet the design rules of metal layer M1. The smaller dashed rectangle in the center corresponds to via V1 and indicates that the via is connected to the center pad and extends downward from this layer.

[0048] Figure 3 (III) represents a ground plane M2 connected to the second electrode T2MIM of the MIMCAP using a via V3, the second electrode T2MIM being formed in the metal layer M3. It can be seen that the via V2 extends through the ground plane M2. The ground plane M2 has an opening M2o at the center to comply with the design rule. Figure 3 In (III), the via V3 is not arranged directly under the CTM layer to comply with the design rules.

[0049] Figure 3 (IV) shows the metal layer M3. The opening M3o is arranged at the edge of the unit cell. Figure 3 As shown in (III+IV), the opening M3o in the metal layer M3 is laterally separated from the opening M2o in the ground plane M2. Since the ground plane M2 and the second electrode T2MIM formed in the metal layer M3 are both electrically grounded during operation, there is no path that does not pass through the ground metal layer between the first electrode T1MIM formed in the layers M4 and M5 and / or connected to the layers M4 and M5 and the first electrode T1HD formed in the layers P and M1 and / or connected to the layers P and M1. Figure 1 Instructions, Figure 1 Two paths from metal layer M4 to metal layer M1 are shown, which intersect the ground layer at the locations of the cross marks. Thus, electromagnetic coupling between the MIMCAP and the DTC is prevented and / or limited.

[0050] Figure 3(V) shows the CTM layer. This layer forms the first terminal T1MIM of the MIMCAP. The first terminal is formed as a plurality of strips, wherein each unit cell of the capacitor assembly 1 defines a portion of a single strip. The strips are connected to the metal layer M4 using vias V4. The remaining portion of the CTM layer (i.e., the portion outside the strip portion) forms an opening CTMo. It should be noted that Figure 3 (V) also represents the metal layer M3.

[0051] Figure 3 (VI) shows a metal layer M4, which includes an opening M4o in the central area, and as shown in FIG. Figure 3 As shown in (VII), the metal layer M4 is connected to the metal layer M5 using a via V5. It is worth noting that the vias V4 and V5 can be formed as a single via extending through the dielectric layers D4 and D5. The opening M5o in the metal layer M5 is aligned with the openings CTMo and M3o, and the opening M4o is aligned with the strip in the CTM layer and is therefore also aligned with the opening M2o.

[0052] Figure 4 At least for Figure 3 The layers P, M3 and CTM of (I), (V) show how the unit cells are combined to form the capacitor assembly 1. As can be clearly seen from these figures, the first terminal T1MIM comprises a plurality of parallel strips.

[0053] Figure 5 An amplifier 100 including a capacitor assembly of the present invention is shown. The amplifier 100 includes an LDMOS transistor Q1 at the gate of which a signal to be amplified is received. The output of Q1 is connected to the output of the amplifier 100 using an inductor L3, which is typically formed at least in part by a bond wire. Figure 5 In FIG. 1 , the output of the amplifier 100 is connected to the load impedance Zload. In addition, the bias signal is fed into Q1 through the feed inductor Lfeed.

[0054] The output of Q1 is connected to ground via a shunt network 101. The network includes an inductor L1 arranged in series with a capacitor C1. Capacitor C1 uses Figures 1 to 3 The MIMCAP of the capacitor assembly 1 is formed. The first terminal T1MIM is connected to the terminal of the capacitor C2 through the conductor L2. The capacitor C2 uses Figures 1 to 3 The DTC of capacitor assembly 1 is formed. The second terminal of C1 and the second terminal of C2 are electrically grounded.

[0055] The capacitance of capacitor C1 ranges from 0.1 pF to 10 pF, while the capacitance of capacitor C2 ranges from 5 nF to 500 nF. Typically, the inductance of L2 is large enough so that the resonant frequency of L2 and C2 is well below the operating frequency of amplifier 100, which typically ranges from 0.1 GHz to 50 GHz. Furthermore, in the case of a parallel combination of C1 and L2, the operating frequency is well above the resonant frequency of L1. Therefore, Q1 effectively sees a series inductor L3 and a shunt inductor that is substantially equal to the inductance of L1 at this operating frequency. The latter inductor is typically selected so that it resonates with the output capacitor Cds at or near this operating frequency. In this way, the negative effect of the output capacitance on the achievable impedance matching can be mitigated.

[0056] In the above, the present invention has been explained using detailed embodiments of the present invention. However, the present invention is not limited to these embodiments. On the contrary, various modifications are possible without departing from the scope of the present invention as defined by the appended claims and their equivalents.

Claims

1. A capacitor assembly (1), comprising a first capacitor (C1) and a second capacitor (C2) vertically stacked on a substrate (2); in, The first capacitor comprises a first terminal (T1MIM) and a second terminal (T2MIM), wherein the second terminal (T2MIM) is formed by a first conductive layer (M3) comprising a stress relief opening (M3o); wherein the second capacitor comprises a first terminal (T1HD) and a second terminal (T2HD); wherein, relative to the surface of the substrate (2), the second terminal (T2MIM) of the first capacitor is located below the first terminal (T1MIM) of the first capacitor, and wherein the second terminal (T2HD) of the second capacitor is located below the first terminal (T1HD) of the second capacitor, and wherein the second capacitor is located below the first capacitor; The capacitor assembly (1) further comprises a grounding layer (M2) arranged between the first conductive layer (M3) and the first terminal (T1HD) of the second capacitor, wherein the second terminal (T2HD) of the second capacitor is electrically connected to the grounding layer (M2) and the first conductive layer (M3) through one or more through holes (V1, V2), wherein the grounding layer (M2) comprises a stress relief opening (M2o) laterally separated from the relief opening (M3o) of the first conductive layer (M3); Wherein, the ground layer (M2) is configured to be electrically grounded during operation.

2. The capacitor assembly (1) according to claim 1, wherein: The first terminal (T1MIM) of the first capacitor is formed by a capacitor top metal layer (CTM), wherein the capacitor top metal layer includes a stress relief opening (CTMo), wherein the stress relief opening (M2o) in the ground layer (M2) is laterally spaced from the stress relief opening (CTMo) of the capacitor top metal layer (CTM).

3. The capacitor assembly (1) according to claim 2, wherein: The capacitor top metal layer (CTM) comprises a plurality of strips (3) arranged in parallel and laterally separated by the stress relief openings (CTMo) of the capacitor top metal layer (CTM).

4. The capacitor assembly (1) according to claim 3, wherein: The stress relief opening (M2o) in the ground layer (M2) is arranged below the strip (3), preferably completely below the strip (3).

5. The capacitor assembly (1) according to claim 2, further comprising a second conductive layer (M4), the second conductive layer (M4) being separated from the capacitor top metal layer (CTM) by a dielectric layer (D4), wherein The second conductive layer (M4) is electrically connected to the capacitor top metal layer (CTM) via one or more vias (V4) passing through the dielectric layer (D4), wherein the second conductive layer (M4) includes a stress relief opening (M4o) laterally spaced apart from the stress relief opening (CTMo) in the capacitor top metal layer (CTM).

6. The capacitor assembly (1) according to claim 5, further comprising a third conductive layer (M5), the third conductive layer (M5) being separated from the second conductive layer (M4) by a dielectric layer (D5), wherein The third conductive layer (M5) is electrically connected to the second conductive layer (M4) via one or more through holes (V5) passing through the dielectric layer (D5), wherein the third conductive layer (M5) includes a stress relief opening (M5o) laterally aligned with the stress relief opening (M3o) in the first conductive layer (M3).

7. The capacitor assembly (1) according to claim 1, further comprising a fourth conductive layer (M1), which is separated from the ground layer (M2) by a dielectric layer (D2) and is electrically connected to the first terminal (T1HD) of the second capacitor and / or forms the first terminal (T1HD) of the second capacitor, wherein: The fourth conductive layer (M1) includes a stress relief opening (M1o) laterally spaced apart from the stress relief opening (M2o) in the ground layer (M2).

8. The capacitor assembly (1) according to claim 7, wherein: The first terminal (T1HD) of the second capacitor is formed by a fifth conductive layer (P), which is separated from the fourth conductive layer (M1) by a dielectric layer (D1), wherein the fourth conductive layer (M1) is electrically connected to the fifth conductive layer (P) via one or more through holes (V1) passing through the dielectric layer (D1).

9. The capacitor assembly (1) according to claim 1, wherein: The capacitor assembly (1) comprises a plurality of identical and adjacently arranged unit cells, each unit cell comprising a first capacitor unit cell, a second capacitor unit cell and a ground plane segment.

10. The capacitor assembly (1) according to claim 9, wherein: The stress relief openings (M2o) of the ground layer (M2) are respectively arranged in a corresponding central region of one of the plurality of unit cells.

11. The capacitor assembly (1) according to claim 1, further comprising a fourth conductive layer (M1), which is separated from the ground layer (M2) by a dielectric layer (D2) and is electrically connected to the first terminal (T1HD) of the second capacitor and / or forms the first terminal (T1HD) of the second capacitor, wherein: The fourth conductive layer (M1) includes a stress relief opening (M1o) laterally separated from the stress relief opening (M2o) in the grounding layer (M2); wherein the capacitor assembly (1) includes a plurality of identical and adjacently arranged unit cells, each unit cell including a first capacitor unit cell, a second capacitor unit cell and a grounding plane segment; wherein the stress relief openings (M1o) of the fourth conductive layer (M1) are respectively arranged at corresponding corners of corresponding second capacitor unit cells.

12. The capacitor assembly (1) according to claim 9, wherein: The stress relief openings (M3o) of the first conductive layer (M3) are respectively arranged at corresponding edges of corresponding first capacitor unit cells.

13. The capacitor assembly (1) according to claim 5, wherein: The capacitor assembly (1) comprises a plurality of identical and adjacently arranged unit cells, each unit cell comprising a first capacitor unit cell, a second capacitor unit cell and a ground plane segment; wherein the stress release openings (M4o) of the second conductive layer (M4) are respectively arranged at the center position of the corresponding first capacitor unit cell.

14. The capacitor assembly (1) according to claim 6, wherein: The capacitor assembly (1) comprises a plurality of identical and adjacently arranged unit cells, each unit cell comprising a first capacitor unit cell, a second capacitor unit cell and a ground plane segment; wherein the stress release openings (M5o) of the third conductive layer (M5) are respectively arranged at corresponding edges of corresponding first capacitor unit cells.

15. The capacitor assembly (1) according to claim 1, wherein: The first conductive layer (M3), the second conductive layer (M4), the third conductive layer (M5) and the fourth conductive layer (M1), the ground layer (M2) and the capacitor top metal layer (CTM) all include one or more metals, and / or wherein the fifth conductive layer (P) includes a polysilicon layer.

16. The capacitor assembly (1) according to any one of the preceding claims, wherein: The substrate is a semiconductor substrate, such as a silicon substrate or a gallium nitride substrate; Wherein the first capacitor is a metal-insulator-metal capacitor, and / or wherein the second capacitor is a high density capacitor.

17. The capacitor assembly (1) according to claim 16, wherein: The second capacitor is a deep trench capacitor, the deep trench capacitor comprising a plurality of trenches in the semiconductor substrate (2), inner walls of the trenches being covered with a first insulating layer (IN1), wherein the fifth conductive layer (P) covers the first insulating layer (IN1), wherein the semiconductor substrate (2) comprises one or more doped regions forming the second terminal (T2HD) of the second capacitor; The metal-insulator-metal capacitor comprises a second insulating layer (IN2) arranged between the capacitor top metal layer (CTM) and the first conductive layer (M3).

18. An amplifier (100), comprising: A field effect transistor FET (Q1), wherein the FET (Q1) has an output capacitance (Cds); A capacitor assembly (1) as defined in claim 16; and a shunt network (101) connected to the drain of the FET and comprising a series connection of a first inductor (L1) and the first capacitor (C1) of the capacitor assembly (1), wherein the first inductor (L1) is connected to the drain of the FET, and wherein the first terminal (T1MIM) of the first capacitor (C1) of the capacitor assembly is connected to the first inductor (L1); The shunt network (101) further comprises the second capacitor (C2) of the capacitor assembly (1), the second capacitor (C2) being connected in series with a second inductor (L2), wherein the second inductor (L2) is connected between the first terminal (T1MIM) of the first capacitor (C1) of the capacitor assembly (1) and the second capacitor (C2) of the capacitor assembly (1), wherein the first terminal (T1HD) of the second capacitor (C2) of the capacitor assembly (1) is connected to the second inductor (L2).

19. The amplifier (100) of claim 18, wherein: The FET (Q1) comprises a laterally diffused metal oxide semiconductor LDMOS transistor.

20. The amplifier (100) of claim 19, wherein: The second capacitor is a deep trench capacitor, the deep trench capacitor comprising a plurality of trenches in the semiconductor substrate (2), inner walls of the trenches being covered with a first insulating layer (IN1), wherein the fifth conductive layer (P) covers the first insulating layer (IN1), wherein the semiconductor substrate (2) comprises one or more doped regions forming the second terminal (T2HD) of the second capacitor; wherein the first insulating layer (IN1) of the deep trench capacitor is formed by a gate oxide layer of the LDMOS transistor.

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