Diode avalanche shaper based on multiple trenches and floating junction and method of making same

Abstract

The application discloses a diode avalanche shaper based on multiple grooves and floating junctions and a preparation method thereof. The device comprises a SiC substrate, a SiC epitaxial layer, a groove region, a P+ region, a floating junction region, a negative electrode and a positive electrode. The groove region is arranged on the surface layer of the SiC epitaxial layer and comprises multiple grooves uniformly distributed. The P+ region extends downward from the upper surface of the SiC epitaxial layer on both sides of the groove region to the groove region below and forms a U-shaped structure. Multiple protruding structures are formed at the bottom of the P+ region. The floating junction region is arranged at the middle line position inside the SiC epitaxial layer and comprises multiple P+ type floating junctions. The number of the P+ type floating junctions is the same as the number of the grooves and the number of the protruding structures. The multiple P+ type floating junctions are arranged directly below the multiple grooves. The structure design can make the electric field distribution in the device more uniform, extend the range of delayed avalanche occurrence, improve the device performance, and does not need a complex doping process.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a diode avalanche shaper based on multiple grooves and a floating junction and a preparation method thereof. BACKGROUND

[0002] A diode avalanche shaper (DAS) is a semiconductor delay breakdown device, which is prepared based on a delay breakdown effect, can realize a fast conduction speed while maintaining a high withstand voltage, and is widely applied in various fields such as pulse power technology. And with the continuous increase of application scenarios, higher requirements are put forward for the performance of the device.

[0003] A traditional silicon-based DAS device can extend the range of delay avalanche occurrence and accelerate the conduction speed of the device by reducing the doping concentration of the drift region, so that the electric field in the device is in a trapezoidal distribution when a bias voltage is applied. With the development of third-generation semiconductor materials, SiC-based devices have gradually become the mainstream choice.

[0004] However, it is difficult to achieve a low doping concentration for SiC to make the electric field present a trapezoidal distribution due to process reasons, thereby limiting the performance improvement of the SiC-based DAS device. Therefore, there is an urgent need for a technology capable of improving the electric field distribution of the SiC-based DAS device to improve the performance of the device. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a diode avalanche shaper based on multiple grooves and a floating junction and a preparation method thereof. The technical problem to be solved by the application is solved by the following technical scheme:

[0006] In a first aspect, the application provides a diode avalanche shaper based on multiple grooves and a floating junction, comprising: a SiC substrate, a SiC epitaxial layer, a groove region, a P+ region, a floating junction region, a negative electrode and a positive electrode; wherein,

[0007] The SiC substrate has a first upper surface, a second upper surface and two bevel sides; the second upper surface is located above the first upper surface, and the length of the second upper surface is less than that of the first upper surface; the two bevel sides are symmetrically distributed at both ends of the second upper surface and connect the second upper surface and the first upper surface;

[0008] The SiC epitaxial layer is located above the second upper surface of the SiC substrate and has a trapezoidal structure; the two sides of the SiC epitaxial layer are located on the same straight line as the two bevel sides of the SiC substrate;

[0009] The groove region is provided on the surface layer of the SiC epitaxial layer and comprises a plurality of uniformly distributed grooves;

[0010] The P+ region extends downward from the upper surface of the SiC epitaxial layer on both sides of the trench region to below the trench region and forms a U-shaped structure; the bottom of the P+ region is formed with a plurality of protruding structures; the number of the protruding structures is the same as the number of the trenches, and the plurality of protruding structures are correspondingly arranged directly below the plurality of trenches;

[0011] The floating junction region is arranged at the middle line position inside the SiC epitaxial layer and includes a plurality of P+ type floating junctions; the number of the P+ type floating junctions is the same as the number of the trenches and the number of the protruding structures; and the plurality of P+ type floating junctions are correspondingly arranged directly below the plurality of protruding structures;

[0012] The negative electrode is located below the SiC substrate; and the positive electrode is located on the upper surface of the SiC epitaxial layer and covers the trench region and part of the P+ region.

[0013] In a second aspect, the present application provides a preparation method of a diode avalanche shaper based on a plurality of trenches and floating junctions, comprising the following steps:

[0014] Growing a lower half of a SiC epitaxial layer on a SiC substrate;

[0015] Performing P-type ion implantation on the lower half of the SiC epitaxial layer to form a floating junction region including a plurality of P+ type floating junctions; wherein the plurality of P+ type floating junctions are uniformly distributed;

[0016] Growing an upper half of the SiC epitaxial layer on the obtained sample to form a complete SiC epitaxial layer, and leaving the floating junction region inside the SiC epitaxial layer;

[0017] Performing etching on the surface layer of the SiC epitaxial layer to form a trench region including a plurality of trenches; wherein the plurality of trenches are correspondingly arranged directly above the plurality of P+ type floating junctions;

[0018] Performing ion implantation on the trench region and the SiC epitaxial layer on both sides of the trench region to form a P+ region; wherein the P+ region extends downward from the upper surface of the SiC epitaxial layer on both sides of the trench region to below the trench region and forms a U-shaped structure; the bottom of the P+ region is formed with a plurality of protruding structures; the number of the protruding structures is the same as the number of the trenches, and the plurality of protruding structures are correspondingly arranged directly below the plurality of trenches;

[0019] Performing etching on both ends of the SiC epitaxial layer and deep into the SiC substrate, so that the SiC epitaxial layer is in a trapezoidal structure, and part of the side edges of the SiC substrate is in an oblique angle shape;

[0020] Preparation of a negative electrode below the SiC substrate and a positive electrode on the upper surface of the SiC epitaxial layer.

[0021] The present application has the following beneficial effects:

[0022] 1. The diode avalanche shaper based on multiple trenches and floating junction provided by the application is provided with a trench area including multiple trenches on the surface of the epitaxial layer of the device, and a floating junction area including multiple P+ floating junctions is provided in the drift area of the device; wherein the multiple P+ floating junctions are located directly below the multiple trenches and correspond to each other one by one. The advantage of such design is that the structure is simple, and the internal electric field trapezoidal distribution of the SiC DAS device can be improved without low doping; during the process of applying a reverse pulse voltage to the device, the addition of the floating junctions will change the original triangular or trapezoidal longitudinal electric field distribution into two independent triangular or trapezoidal longitudinal electric field distributions above and below the floating junction structure, so that the internal electric field distribution is more uniform, and the delay avalanche occurs in the entire area of the device, and the opening speed of the device is faster.

[0023] 2. The terminal structure of the multiple trench and floating junction designed by the application is beneficial to relieving the electric field concentration on the surface of the device, introducing the electric field concentration into the device, preventing the device from being broken down in advance, and further improving the performance of the device.

[0024] The application will be further described in detail below with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0025] Figure 1 is a structure schematic diagram of the diode avalanche shaper based on multiple trenches and floating junction provided by the embodiment of the application;

[0026] Figure 2 is a flow schematic diagram of the preparation method of the diode avalanche shaper based on multiple trenches and floating junction provided by the embodiment of the application;

[0027] Figure 3 is a preparation process schematic diagram of the diode avalanche shaper based on multiple trenches and floating junction provided by the embodiment of the application;

[0028] Explanation of reference signs:

[0029] 1-SiC substrate, 2-SiC epitaxial layer, 3-trench area, 31-trench, 4-P+ area, 41-protruding structure, 5-floating junction area, 51-P+ floating junction, 6-negative electrode, 7-positive electrode, 8-passivation layer. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the application. Obviously, the described embodiments are only a part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.

[0031] The first aspect of the present application provides a multi-trench and floating junction based diode avalanche shaper. Figure 1 , Figure 1 is a structural schematic diagram of a multi-trench and floating junction based diode avalanche shaper provided by the embodiment of the present application, and the device specifically comprises a SiC substrate 1, a SiC epitaxial layer 2, a trench area 3, a P+ area 4, a floating junction area 5, a negative electrode 6 and a positive electrode 7; wherein,

[0032] The SiC substrate 1 has a first upper surface 11, a second upper surface 12 and two bevel side edges 13; the second upper surface 12 is located above the first upper surface 11, and the length of the second upper surface 12 is less than that of the first upper surface 11; the two bevel side edges 13 are symmetrically distributed at both ends of the second upper surface 12 and connect the second upper surface 12 and the first upper surface 11;

[0033] The SiC epitaxial layer 2 is located above the second upper surface 12 of the SiC substrate 1 and has a trapezoidal structure; the two side edges of the SiC epitaxial layer 2 are located on the same straight line as the two bevel side edges 13 of the SiC substrate 1;

[0034] The trench area 3 is arranged on the surface layer of the SiC epitaxial layer 2 and comprises a plurality of uniformly distributed trenches 31;

[0035] The P+ area 4 extends downward from the upper surface of the SiC epitaxial layer 2 on both sides of the trench area 3 to below the trench area 3 and forms a U-shaped structure; the bottom of the P+ area 4 is formed with a plurality of protruding structures 41; the number of the protruding structures 41 is the same as that of the trenches 31, and the plurality of protruding structures 41 are correspondingly arranged directly below the plurality of trenches 31;

[0036] The floating junction area 5 is arranged at the middle line position inside the SiC epitaxial layer 2 and comprises a plurality of P+ type floating junctions 51; the number of the P+ type floating junctions 51 is the same as that of the trenches 31 and that of the protruding structures 41; and the plurality of P+ type floating junctions 51 are correspondingly arranged directly below the plurality of protruding structures 41;

[0037] The negative electrode 6 is located below the SiC substrate 1 and has an ohmic contact with the SiC substrate 1; the positive electrode 7 is located on the upper surface of the SiC epitaxial layer 2 and covers the trench area 3 and part of the P+ area 4, and the contact interface is an ohmic contact.

[0038] Optionally, in the embodiment, the SiC substrate 1 is N+ type doped, and the doping concentration is 1×10 18 cm -3 ~ 1×10 20 cm -3 ; the SiC epitaxial layer 2 is N- type doped, and the doping concentration is 1×10 14 cm -3 ~ 1×10 17 cm-3 .

[0039] Specifically, as shown in Figure 1 , two steps are formed on the left and right sides of the SiC substrate 1 respectively, and the steps on the two sides are symmetrically distributed. The mesa of the two steps forms a first upper surface 11 of the SiC substrate 1, and the upper surface of the SiC substrate 1, i.e. a second upper surface 12, has an inclined side edge 13.

[0040] Optionally, as an implementation manner, an angle θ1 formed between the two inclined side edges 13 of the SiC substrate 1 and the reverse extension line of the first upper surface 11 satisfies 70°≤θ1≤90°. This design can alleviate the electric field concentration effect of the side edge and avoid premature breakdown of the device.

[0041] Further, please continue to refer to Figure 1 , in the trench area 3, the plurality of trenches 31 are of the same size and shape and are uniformly distributed, the width W1 of the top of the trench 31 is in the range of 0.5 μm to 2 μm; the depth h of the trench 31 is in the range of 0.5 μm to 1.5 μm; the spacing S1 between the two adjacent trenches 31 is in the range of 0.5 μm to 5 μm; the included angle θ2 formed by the side edge and the bottom edge of the trench 31 satisfies 65°≤θ2≤90°.

[0042] In this embodiment, the side edge of the trench 31 is designed as an inclined structure, and this inclined terminal design can avoid electric field concentration and help improve the performance of the device.

[0043] Further, this embodiment designs a U-shaped P+ area 4, as shown in Figure 1 , which mainly includes three parts, the U-shaped bottom located below the trench area 3, and the two sides of the U-shaped area extending to the two sides of the trench area 3. Among them, the U-shaped bottom forms a plurality of protruding structures 41 downward; the protruding structure 41 is arranged in the middle of the plurality of trenches 31 and the plurality of P+ floating junctions 51, and the number of the three is the same. The edge of the P+ area 4 on both sides in the SiC epitaxial layer 2 has an arc surface structure. This design can alleviate the electric field concentration at the sharp corner.

[0044] In addition, the two side edges of the P+ area 4 are a certain distance away from the edge of the SiC epitaxial layer 2, as shown as D in Figure 1 .

[0045] Optionally, as an implementation manner, the doping concentration of the P+ area 4 is in a Gaussian doping distribution from top to bottom, which can prevent the formation of abrupt change at the PN junction to alleviate the concentration effect of the electric field at the junction.

[0046] Further, please continue to refer to Figure 1For the floating junction 5, the embodiment is designed at the middle line position inside the SiC epitaxial layer 2, so as to ensure more uniform delay avalanche triggering of the upper and lower drift regions.

[0047] Optionally, as an implementation manner, the doping concentration of the P+ type floating junction 51 is 1×10 16 cm -3 ~1×10 20 cm -3 , and the doping ions are boron ions or aluminum ions.

[0048] It should be noted that the distance from the middle line position of the P+ type floating junction 51 to the convex structure 41 is equal to the distance from the middle line position of the P+ type floating junction 51 to the lower surface of the SiC epitaxial layer 2, that is, L in the above formula, so as to make the electric field distribution of the upper and lower drift regions more uniform, and the generation and avalanche of the carriers more uniform. Figure 1

[0049] Optionally, as an implementation manner, the width W2 of the P+ type floating junction 51 is greater than the width W1 of the groove top, and the value range of W2 is 1 μm~3 μm; the value range of the interval S2 between the adjacent two P+ type floating junctions 51 is 0.2 μm~4 μm.

[0050] It can be understood that the diode avalanche shaper based on the multi-groove and floating junction designed in the embodiment further comprises a passivation layer 8; the passivation layer 8 covers part of the P+ region 4, and extends downward from both ends of the upper surface of the SiC epitaxial layer 2, passes through the side of the SiC epitaxial layer 2 and the inclined side edge 13 of the SiC substrate 1, and covers the second upper surface 12 of the SiC substrate 1 completely.

[0051] In addition, in the embodiment, the thickness of the SiC substrate 1, the thickness of the SiC epitaxial layer 2, the materials and thicknesses of the negative electrode 6 and the positive electrode 7, etc. can be designed by referring to the conventional device structure, and the embodiment does not make specific limitation on this.

[0052] ​The diode avalanche shaper based on the multiple grooves and the floating junction provided by the application is characterized in that a groove area including multiple grooves is arranged on the surface of an epitaxial layer of the device, and a P+ type floating junction and a floating junction area are arranged in the drift area of the device; and the multiple P+ type floating junctions are located directly below the multiple grooves and correspond to the multiple grooves one by one.

[0053] In addition, the terminal structure of the multiple grooves and the floating junction designed by the application is also beneficial to relieving the electric field concentration on the surface of the device, introducing the electric field concentration into the device, preventing the device from being broken down in advance, and further improving the performance of the device.

[0054] Based on the same inventive concept, the second aspect of the application also provides a preparation method of a diode avalanche shaper based on multiple grooves and floating junctions. Figure 2-3 , Figure 2 Fig. 1 is a flowchart of the preparation method of the diode avalanche shaper based on multiple grooves and floating junctions provided by the application, Figure 3 Fig. 2 is a process diagram of the preparation method of the diode avalanche shaper based on multiple grooves and floating junctions provided by the application, Figure 3 In the figure, N+ represents an N+ type SiC substrate, N- represents an N- type SiC epitaxial layer, PR represents photoresist, and P+ represents a P+ type floating junction.

[0055] The preparation method of the diode avalanche shaper based on multiple grooves and floating junctions provided by the application will be described in detail below. Figure 3 The preparation method of the diode avalanche shaper based on multiple grooves and floating junctions provided by the application will be described in detail below.

[0056] Step 1: growing the lower half of the SiC epitaxial layer on the SiC substrate.

[0057] 11) Select an N+ type SiC semiconductor substrate for standard RCA cleaning to form an N+ type SiC substrate, as shown in (a) of Fig. 1. Figure 3 In the figure, N+ represents an N+ type SiC substrate.

[0058] In this embodiment, the thickness of the N+ type SiC substrate is 350 μm and the doping concentration is 1×10 18 cm -3 ~1×10 20 cm -3 .

[0059] 12) Using CVD method to grow N-type SiC epitaxially on N+ type SiC substrate to form the lower half of N-type SiC epitaxial layer, as shown in FIG. Figure 3 As shown in Figure (b), N- represents the N-type SiC epitaxial layer.

[0060] In this embodiment, the doping concentration of the N-type SiC epitaxial layer is 1×10 14 cm -3 ~1×10 17 cm -3 .

[0061] Step 2: Perform P-type ion implantation on the lower half of the SiC epitaxial layer to form a floating junction region including a plurality of P+-type floating junctions; wherein the plurality of P+-type floating junctions are evenly distributed.

[0062] 21) A photoresist (PR) mask is formed on the upper surface of the N-type SiC epitaxial layer based on the designed floating junction region, such as Figure 3 As shown in Figure (c), this embodiment is described by taking three floating knots as an example.

[0063] 22) Doping is performed on the upper surface of the N-type SiC epitaxial layer by ion implantation or diffusion using a photoresist mask, such as Figure 3 As shown in Figure (d), the doping type is opposite to that of the N+ region, that is, P-type doping. The doping ions are boron ions, aluminum ions and other third main group elements, thus forming a doping concentration of 1×10 16 cm -3 ~1×10 20 cm -3 The three P+ type floating junctions, such as Figure 3 As shown in Figure (e).

[0064] 23) Remove the photoresist on the sample surface to form a floating junction region including three P+ type floating junctions, such as Figure 3 As shown in Figure (f).

[0065] Step 3: Grow the upper half of the SiC epitaxial layer on the obtained sample to form a complete SiC epitaxial layer, and leave the floating junction region inside the SiC epitaxial layer.

[0066] Specifically, the upper half of the N-type SiC epitaxial layer is continuously grown by using the CVD method to form a complete N-type SiC epitaxial layer, so as to leave the floating junction region inside the N-type SiC epitaxial layer and make the floating junction region at the middle line position inside the entire N-type SiC epitaxial layer, as shown in FIG. 1. Figure 3 As shown in FIG. 2.

[0067] Step 4: Etching the surface layer of the SiC epitaxial layer to form a trench region including a plurality of trenches.

[0068] 41) Depositing a SiO2 layer on the N-type SiC epitaxial layer, as shown in FIG. 3. Figure 3 As shown in FIG. 4, the thickness of the SiO2 layer is 2-3 μm.

[0069] 42) Forming a photoresist (PR) mask on the SiO2 layer based on the designed trench region, as shown in FIG. 5. Figure 3 As shown in FIG. 6, the plurality of trenches are located directly above the plurality of P+ floating junctions.

[0070] 43) Etching the SiO2 layer according to the photoresist etching mask above the SiO2 layer, as shown in FIG. 7. Figure 3 As shown in FIG. 8.

[0071] 44) Removing the photoresist above the SiO2 layer, as shown in FIG. 9. Figure 3 As shown in FIG. 10.

[0072] 45) Using the SiO2 layer as a mask, etching the SiC epitaxial layer by using a dry etching process to form a plurality of trenches with steep side walls and an angle of 70-90° with the horizontal direction, as shown in FIG. 11. Figure 3 As shown in FIG. 12.

[0073] 46) Removing the SiO2 layer on the surface of the sample to form a trench region including three trenches, as shown in FIG. 13. Figure 3 As shown in FIG. 14.

[0074] Step 5: Ion implantation is performed on the trench region and the SiC epitaxial layer on both sides of the trench region to form a P+ region. The P+ region extends downward from the upper surface of the N-type epitaxial layer on both sides of the trench region to below the trench region and forms a U-shaped structure; the bottom of the P+ region is formed with a plurality of protruding structures; the number of the protruding structures is the same as the number of the trenches, and the plurality of protruding structures are arranged directly below the plurality of trenches.

[0075] 51) Depositing a SiO2 layer on the surface of the N-type SiC epitaxial layer with trenches, as shown in FIG. 15. Figure 3 As shown in FIG. 16.

[0076] 52) Based on the designed P+ region, a photoresist (PR) mask is formed on both sides of the SiO2 layer surface, such as Figure 3 As shown in the middle (o) figure.

[0077] 53) Etch the SiO2 layer to form an ion implantation mask with a beveled edge, such as Figure 3 As shown in Figure (p).

[0078] 54) Remove the photoresist above the SiO2 layer, such as Figure 3 As shown in the middle (q) figure.

[0079] 55) Ion implantation is performed on the SiO2 ion implantation mask with a beveled edge, such as Figure 3 Then, a rapid annealing process is performed at 1700°C for 10 minutes to form a P+ region with a U-shaped structure and a convex structure inside the upper surface of the SiC epitaxial layer, as shown in FIG. Figure 3 As shown in Figure (s).

[0080] 56) Remove the SiO2 layer on the sample surface, such as Figure 3 As shown in the figure (t).

[0081] Step 6: Etch both ends of the SiC epitaxial layer and deep into the SiC substrate to make the SiC epitaxial layer have a trapezoidal structure and make part of the side edges of the SiC substrate beveled.

[0082] 61) Deposit a SiO2 layer on the surface of the SiC epitaxial layer with grooves, such as Figure 3 As shown in the middle (u) figure.

[0083] 62) A photoresist etching mask is formed on the surface of the SiO2 layer. The photoresist is located above the P+ region. Redundancy for oblique etching is reserved on both sides of the photoresist, and a certain distance is ensured between the U-shaped P+ region and the edge of the SiC epitaxial layer, such as Figure 3 As shown in Figure (v).

[0084] 63) Etch the SiO2 layer according to the photoresist etching mask above the SiO2 layer, as shown in FIG. Figure 1 As shown in the middle (w) figure.

[0085] 64) Remove the photoresist above the SiO2 layer, such as Figure 3 As shown in the figure (x).

[0086] 65) Using SiO2 as a mask layer, the symmetrical bevel terminals are etched and the etching depth is as deep as Figure 3 The etching angle of H shown is θ1, and θ1 satisfies 70°≤θ1≤90°, so that the SiC epitaxial layer has a trapezoidal structure and the side edges of the SiC substrate are beveled, as shown in FIG.Figure 3 Fig. 2 shows a cross-sectional view along the line (y) of Fig. 1.

[0087] 66) removing the SiO2layer on the surface of the sample, such as Figure 3 Fig. 2 shows a cross-sectional view along the line (y) of Fig. 1.

[0088] Step 7: preparing the negative electrode and the positive electrode respectively under the SiC substrate and on the upper surface of the SiC epitaxial layer.

[0089] Sputtering metal on the lower surface of the SiC substrate, annealing to form an ohmic contact to form the negative electrode of the device, and sputtering metal on the surface of the P+ region, annealing to form an ohmic contact to form the positive electrode of the device, such as ​ Fig. 2 shows a cross-sectional view along the line (y) of Fig. 1.

[0090] It should be noted that after the negative electrode and the positive electrode are prepared, it further includes:

[0091] Step 8: depositing SiO2on the first surface of the SiC substrate, the bevel side edge of the device, and the upper surface of the SiC epitaxial layer and its bevel to form a passivation layer, such as ​ Fig. 2 shows a cross-sectional view along the line (y) of Fig. 1.

[0092] So far, the preparation of the diode avalanche shaper based on multiple trenches and floating junction has been completed.

[0093] The device prepared by the method has the same structure as the diode avalanche shaper based on multiple trenches and floating junction provided by the first aspect of the present application, and thus has the same beneficial effects as the device of the first aspect. For technical details not disclosed in the embodiment of the preparation method of the present application, please refer to the description of the device embodiment for understanding.

[0094] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0095] In the present application, unless specifically defined and limited otherwise, the "on" or "under" of a first feature to a second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the "on", "above", and "top" of a first feature to a second feature include that the first feature is directly above and obliquely above the second feature, or only means that the horizontal height of the first feature is higher than that of the second feature. The "under", "below", and "bottom" of a first feature to a second feature include that the first feature is directly below and obliquely below the second feature, or only means that the horizontal height of the first feature is less than that of the second feature.

[0096] In addition, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the specification.

[0097] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or replacements can be made, which should be considered as belonging to the protection scope of the present application.

Claims

1. A diode avalanche shaper based on multiple trenches and floating junctions, characterized in that, Comprise: SiC substrate (1), SiC epitaxial layer (2), trench area (3), P+ area (4), floating junction area (5), negative electrode (6) and positive electrode (7); wherein, The SiC substrate (1) has a first upper surface (11), a second upper surface (12) and two bevel side edges (13); the second upper surface (12) is above the first upper surface (11), and the length of the second upper surface (12) is less than that of the first upper surface (11); the two bevel side edges (13) are symmetrically distributed at both ends of the second upper surface (12) and connect the second upper surface (12) and the first upper surface (11); The SiC epitaxial layer (2) is above the second upper surface (12) of the SiC substrate (1) and has a trapezoidal structure; the two side edges of the SiC epitaxial layer (2) are respectively on the same straight line as the two bevel side edges (13) of the SiC substrate (1); The trench area (3) is arranged on the surface layer of the SiC epitaxial layer (2) and comprises a plurality of uniformly distributed trenches (31); The P+ area (4) extends downward from the upper surface of the SiC epitaxial layer (2) on both sides of the trench area (3) to below the trench area (3) and forms a U-shaped structure; the bottom of the P+ area (4) is formed with a plurality of protruding structures (41) downward; the number of the protruding structures (41) is the same as that of the trenches (31), and the plurality of protruding structures (41) are correspondingly arranged directly below the plurality of trenches (31); The floating junction area (5) is arranged at the middle line position inside the SiC epitaxial layer (2) and comprises a plurality of P+ type floating junctions (51); the number of the P+ type floating junctions (51) is the same as that of the trenches (31) and that of the protruding structures (41); and the plurality of P+ type floating junctions (51) are correspondingly arranged directly below the plurality of protruding structures (41); The negative electrode (6) is below the SiC substrate (1); and the positive electrode (7) is on the upper surface of the SiC epitaxial layer (2) and covers the trench area (3) and part of the P+ area (4).

2. The multi-trench and floating junction based diode avalanche shaper of claim 1, wherein, The angle θ1 formed between the two bevel side edges (13) of the SiC substrate (1) and the reverse extension line of the first upper surface (11) satisfies 70°≤θ1≤90°.

3. The multi-trench and floating junction based diode avalanche shaper of claim 1, wherein, The width W1 of the top of the trench (31) ranges from 0.5 μm to 2 μm; The depth h of the trench (31) ranges from 0.5 μm to 1.5 μm; The spacing S1 between adjacent two trenches (31) ranges from 0.5 μm to 5 μm; The included angle θ2 formed between the side edge and the bottom edge of the trench (31) satisfies 65°≤θ2≤90°.

4. The multi-trench and floating junction based diode avalanche shaper of claim 1, wherein, The doping concentration of the P+ area (4) presents a Gaussian doping distribution from top to bottom.

5. The multi-trench and floating junction based diode avalanche shaper of claim 1, wherein, The P+ type floating junction (51) has a doping concentration of 1 x 10 16 cm -3 ~ 1 x 10 20 cm -3 , and the doping ions are boron ions or aluminum ions.

6. The multi-trench and floating junction based diode avalanche shaper of claim 1, wherein, The distance from the middle line position of the P+ type floating junction (51) to the lower surface of the protruding structure (41) is equal to the distance from the middle line position of the P+ type floating junction (51) to the lower surface of the SiC epitaxial layer (2).

7. The multi-trench and floating junction based diode avalanche shaper of claim 1, wherein, The width W2 of the P+ type floating junction (51) is greater than the width W1 of the top of the trench (31), and the value range of W2 is 1-3 μm; the interval S2 of two adjacent P+ type floating junctions (51) is 0.2-4 μm.

8. The multi-trench and floating junction based diode avalanche shaper of claim 1, wherein, The SiC substrate (1) is N+ doped with a doping concentration of 1 x 10 18 cm -3 ~ 1 x 10 20 cm -3 ; the SiC epitaxial layer (2) is N- doped with a doping concentration of 1 x 10 14 cm -3 ~ 1 x 10 17 cm -3 .

9. The multi-trench and floating junction based diode avalanche shaper of claim 1, wherein, The multi-trench and floating junction based diode avalanche shaper further comprises a passivation layer (8); the passivation layer (8) covers part of the P+ region (4) and extends downward from both ends of the upper surface of the SiC epitaxial layer (2), through the side of the SiC epitaxial layer (2) and the bevel side (13) of the SiC substrate (1), until completely covering the second upper surface (12) of the SiC substrate (1).

10. A method for preparing a diode avalanche shaper based on multiple trenches and floating junctions, characterized in that: The method comprises the following steps: growing a lower half of a SiC epitaxial layer on a SiC substrate; performing P type ion implantation on the lower half of the SiC epitaxial layer to form a floating junction region comprising a plurality of P+ type floating junctions; wherein the plurality of P+ type floating junctions are uniformly distributed; growing an upper half of a SiC epitaxial layer on the obtained sample to form a complete SiC epitaxial layer, and leaving the floating junction region inside the SiC epitaxial layer; performing etching on the surface layer of the SiC epitaxial layer to form a trench region comprising a plurality of trenches; wherein the plurality of trenches are correspondingly arranged above the plurality of P+ type floating junctions; performing ion implantation on the trench region and the SiC epitaxial layer on both sides of the trench region to form a P+ region; wherein the P+ region extends downward from the upper surface of the SiC epitaxial layer on both sides of the trench region to below the trench region, and forms a U-shaped structure; the bottom of the P+ region is formed with a plurality of protruding structures downward; the number of the protruding structures is the same as the number of the trenches, and the plurality of protruding structures are correspondingly arranged below the plurality of trenches; performing etching on both ends of the SiC epitaxial layer and deep into the SiC substrate, so that the SiC epitaxial layer is in a trapezoidal structure, and part of the side of the SiC substrate is in a bevel shape; preparing a negative electrode and a positive electrode below the SiC substrate and on the upper surface of the SiC epitaxial layer, respectively.

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