Semiconductor device manufacturing method and semiconductor device

Abstract

The invention provides a semiconductor device manufacturing method and a semiconductor device. The semiconductor device manufacturing method comprises the steps that a substrate is provided, a first gate structure with a target shape is formed on the substrate, the target shape comprises that the size of a first surface, close to the substrate, of the first gate structure is smaller than that of a second surface, away from the substrate, of the first gate structure, and the first surface is opposite to the second surface; the first gate structure comprises a polycrystalline silicon gate; covering a stress film on the substrate and the first gate structure and executing stress treatment to enable the stress film to be matched with the first gate structure with the target shape to improve the stress of a channel region of the substrate under the first gate structure; and removing the stress film on the second surface of the first gate structure, and reserving the residual stress film covering the non-gate structure region of the substrate and the two sides of the first gate structure. The invention also provides a semiconductor device. According to the invention, the channel stress can be improved, the direct-current performance is improved, and the overlapping capacitance is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] With the continuous development of semiconductor technology, the size of transistors is constantly decreasing. When the channel length is reduced to the 22nm node and below, the DC and AC performance of the device continues to improve and must be taken into consideration.

[0003] During the manufacturing process of current transistors, since the gate is usually a regular rectangular gate, it is not conducive to the stress transmission to the channel area during stress treatment, which affects the performance of the device. In addition, as the size of transistors decreases, the capacitance of the parasitic capacitance between the gate and the source or drain region of the transistor increases, which also greatly affects the performance of the device. Summary of the invention

[0004] The present application provides a method for manufacturing a semiconductor device, which can simultaneously increase the DC performance of the device and alleviate the problem of overlapping capacitance caused by the shrinking size of transistors in the related art, effectively reduce the overlapping capacitance, and improve the channel stress.

[0005] To solve the above technical problems, the first aspect of the present application provides a method for manufacturing a semiconductor device, providing a substrate, and forming a first gate structure with a target shape on the substrate, wherein the target shape includes a size of the first gate structure close to a first surface of the substrate being smaller than a size of the first gate structure away from a second surface of the substrate, the first surface is opposite to the second surface, and the first gate structure with the target shape includes a polysilicon gate; covering the substrate and the first gate structure with the target shape with a stress film and performing stress treatment so that the stress film cooperates with the first gate structure with the target shape to improve the stress in the channel region of the substrate under the first gate structure with the target shape; removing the stress film on the second surface of the first gate structure with the target shape, and retaining the residual stress film covering the non-gate structure region of the substrate and on both sides of the first gate structure with the target shape.

[0006] In some embodiments, providing a substrate and forming a first gate structure having a target shape on the substrate includes: providing the substrate; forming a first gate structure on the substrate, wherein the width of the first gate structure is consistent along a direction close to the substrate; etching the first gate structure to form the first gate structure having a target shape, wherein the width of the first gate structure having a target shape gradually decreases along a direction close to the substrate; or the first surface of the first gate structure having a target shape has a notch relative to the second surface.

[0007] In some embodiments, after providing a substrate and forming a first gate structure having a target shape on the substrate, the manufacturing method further includes: forming side walls on both sides of the first gate structure having a target shape; using the first gate structure having a target shape and the side walls as masks to form a source region and a drain region in the substrate.

[0008] In some embodiments, removing the stress film on the second surface of the first gate structure having the target shape includes: covering the stress film with a first dielectric layer; and grinding away a portion of the dielectric layer and a portion of the stress film until the second surface of the first gate structure having the target shape is exposed.

[0009] In some embodiments, a second dielectric layer is formed on the remaining first dielectric layer, and a gate contact plug connected to the first gate structure having a target shape is formed in the second dielectric layer, wherein the polysilicon gate in the first gate structure having a target shape serves as a gate.

[0010] In some embodiments, the polysilicon gate in the first gate structure having the target shape is removed, and a metal gate is filled in the original area of ​​the polysilicon gate to form a second gate structure; a second dielectric layer is formed on the remaining first dielectric layer, and a gate contact plug connected to the metal gate is formed in the second dielectric layer, wherein the metal gate serves as a gate.

[0011] In order to solve the above-mentioned technical problems, the second aspect of the present application also provides a semiconductor device, comprising: a substrate; a gate structure having a target shape, arranged on the substrate, the target shape including a size of the first surface of the gate structure close to the substrate being smaller than a size of the second surface of the gate structure away from the substrate, the first surface being opposite to the second surface; and a residual stress film, covering the non-gate structure area of ​​the substrate and covering both sides of the gate structure.

[0012] In some embodiments, the width of the gate structure gradually decreases along a direction approaching the substrate; or a first surface of the gate structure has a notch relative to a second surface.

[0013] In some embodiments, the gate structure includes a gate and a gate oxide layer, wherein the gate oxide layer is located between the gate and the substrate, wherein the first surface of the gate structure is a surface of the gate oxide layer close to the substrate, and the second surface of the gate structure is a surface of the gate away from the substrate.

[0014] In some embodiments, the gate includes a polysilicon gate or a metal gate.

[0015] Some embodiments of the present application provide a substrate, and form a first gate structure with a target shape on the substrate, wherein the target shape includes a size of a first surface of the first gate structure close to the substrate that is smaller than a size of a second surface of the first gate structure away from the substrate, the first surface is opposite to the second surface, and the first gate structure with the target shape includes a polysilicon gate; a stress film is covered on the substrate and the first gate structure with the target shape and a stress treatment is performed, so that the stress film cooperates with the first gate structure with the target shape to improve the stress of the channel region of the substrate under the first gate structure with the target shape; the stress film on the second surface of the first gate structure with the target shape is removed, and the residual stress film covering the non-gate structure region of the substrate and the two sides of the first gate structure with the target shape is retained. Compared with the related art, the present application forms a first gate structure with a target shape, covers the stress film on the substrate and the first gate structure with the target shape, and performs a stress treatment, so that the stress film cooperates with the first gate structure with the target shape to improve the stress of the channel region of the substrate under the first gate structure with the target shape, improves the channel stress, and can effectively improve the carrier mobility of the device and improve the problem of overlap capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] in:

[0018] Figure 1 A flowchart of a method for manufacturing a semiconductor device provided in one embodiment of the present application;

[0019] Figure 2 A schematic diagram of providing a first gate structure for a semiconductor device;

[0020] Figure 3 A schematic diagram of forming a first gate structure having a target shape for a semiconductor device;

[0021] Figure 4 is a schematic diagram of a first gate structure having a target shape of a semiconductor device;

[0022] Figure 5 A schematic diagram of forming a sidewall, a source region and a drain region for a semiconductor device;

[0023] Figure 6 A schematic diagram of a stress film covering a semiconductor device;

[0024] Figure 7 A schematic diagram of a semiconductor device covered with a first dielectric layer;

[0025] Figure 8 for Figure 7 Schematic diagram of the semiconductor device after grinding;

[0026] Fig. 9 for Figure 8 A schematic diagram of forming a gate contact plug in a semiconductor device;

[0027] Fig.10 for Figure 8 Schematic diagram of removing polysilicon gate from a semiconductor device;

[0028] Fig.11 for Fig.10 Schematic diagram of a semiconductor device filled with a metal gate;

[0029] Fig.12 for Fig.11 Schematic diagram of forming a gate contact plug in a semiconductor device. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] The terms "first" and "second" in this application are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0032] All directional indications in the embodiments of the present application (such as up, down, left, right, front, back, top, bottom...) are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0033] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0034] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] In the prior art, when the size of transistors is reduced and the channel length is reduced to 22nm node and below, overlap capacitance and DC performance become key factors that restrict the continuous improvement of devices. When the current transistors are processed, since the gate is usually a regular rectangular gate, it is not conducive to the stress transmission to the channel area during stress treatment, which affects the performance of the device; and as the size of the transistor is reduced, the distance between the gate and the source or drain of the transistor becomes smaller accordingly, which easily causes the parasitic capacitance between the gate and the source or drain area of ​​the transistor to be larger, which also affects the performance of the device.

[0036] In order to solve the above technical problems, some embodiments of the present application provide a method for manufacturing a semiconductor device. The present application is described in detail below in conjunction with the accompanying drawings and embodiments.

[0037] Figure 1 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application; the method specifically comprises:

[0038] Step S11: providing a substrate, and forming a first gate structure having a target shape on the substrate, wherein the target shape includes a size of the first gate structure close to a first surface of the substrate being smaller than a size of the first gate structure away from a second surface of the substrate, the first surface is opposite to the second surface, and the first gate structure having the target shape includes a polysilicon gate.

[0039] In the specific implementation process, see Figures 2 to 5 , Figure 2 A schematic diagram of providing a first gate structure for a semiconductor device; Figure 3 A schematic diagram of forming a first gate structure having a target shape for a semiconductor device; Figure 4 is a schematic diagram of a first gate structure having a target shape of a semiconductor device; Figure 5Schematic diagram of forming sidewalls, source regions and drain regions for a semiconductor device. Specifically, step S11 includes:

[0040] Step S111: providing the substrate.

[0041] See also Figure 2 , Figure 2 A schematic diagram of a first gate structure is provided for a semiconductor device. The substrate 100 may be any suitable substrate known in the art, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, or a layered substrate of Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator, which is not limited in the present application.

[0042] In some embodiments, a substrate 100 is provided that includes a well region 101 formed in the substrate 100 and a shallow trench isolation (STI) 102 that isolates the well region 101 .

[0043] Step S112: forming a first gate structure on the substrate, wherein the width of the first gate structure is uniform along a direction close to the substrate.

[0044] Among them, see Figure 2 , Figure 2 Schematic diagram of a first gate structure provided for a semiconductor device. The first gate structure 115 includes a gate and a gate oxide layer 114, the gate oxide layer 114 is located between the gate and the substrate 100, the gate may be a polysilicon gate 113, the gate oxide layer 114 may be silicon oxide, etc., wherein the first gate structure 115 includes the polysilicon gate 113 and the gate oxide layer 114.

[0045] The first gate structure 115 has at least a first surface 111 and a second surface 112, wherein the first surface 111 of the first gate structure 115 is a surface of the gate oxide layer 114 close to the substrate 100, and the second surface 112 of the first gate structure 115 is a surface of the gate away from the substrate 100, and the second surface 112 is arranged opposite to the first surface 111. The cross-sectional view of the first gate structure 115 is a rectangle, for example, Figure 2 As shown, the widths of the first surface 111 and the second surface 112 are consistent. Of course, the width of the first surface 111 and the second surface 112 may not be completely consistent due to process errors during the formation of the first gate structure 115, and the consistency of the width of the first gate structure 115 also includes the situation where process errors occur.

[0046] Step S113: Etching the first gate structure to form the first gate structure having the target shape, wherein the width of the first gate structure having the target shape gradually decreases along the direction approaching the substrate; or the first surface of the first gate structure having the target shape has a notch relative to the second surface.

[0047] For details, see Figure 3 and Figure 4 , Figure 3 A schematic diagram of forming a first gate structure having a target shape for a semiconductor device; Figure 4 Schematic diagram of a first gate structure of a semiconductor device having a target shape. In one embodiment, as Figure 4 As shown in (a), the first gate structure 115 is etched to form a first gate structure 115 that conforms to a target shape, wherein the width of the first gate structure 115 with the target shape gradually decreases along a direction approaching the substrate 100, that is, the first surface 111 of the first gate structure 115 with the target shape is smaller than the second surface 112, and the first gate structure 115 with the target shape has a shape that is larger at the top and smaller at the bottom.

[0048] In one embodiment, if Figure 4 As shown in (b), the first surface 111 of the first gate structure 115 is etched to form a first gate structure 115 that conforms to a target shape. The first surface 111 of the first gate structure 115 with the target shape forms a notch relative to the second surface 112. The notch is located on both sides of the first gate structure 115 with the target shape. The shape of the notch may be an arc-shaped notch or a triangular notch, or other irregular-shaped notches. The first gate structure 115 with the target shape is in a shape that is larger at the top and smaller at the bottom.

[0049] The first gate structure 115 is etched according to the target shape, and dry etching may be used, wherein the etching gas used in the dry etching includes chlorine, oxygen, hydrogen bromide, etc.

[0050] In this embodiment, the following two steps are further included after step S113:

[0051] Step S114: forming sidewall spacers on both sides of the first gate structure having a target shape.

[0052] For details, see Figure 5 , Figure 5 Schematic diagram of forming spacers, source regions and drain regions of a semiconductor device. Spacers 130 are disposed on the substrate 100 and formed on the sidewalls of both sides of the first gate structure 115 having a target shape.

[0053] Step S115: using the first gate structure and the spacer having the target shape as a mask to form a source region and a drain region in the substrate.

[0054] For details, see Figure 5 In this embodiment, the first gate structure 115 and the sidewall 130 with the target shape are used as masks to perform source region ion implantation and drain region ion implantation, and an annealing process is performed to form a source region 140 and a drain region 150 in the substrate 100 below the first gate structure 115 and the sidewall 130 with the target shape, and the source region 140 and the drain region 150 are respectively located on both sides of the first gate structure 115 and the sidewall 130 with the target shape. In addition, in some embodiments, a lightly doped region 160 (Lightly Doped Drain, LDD) is also formed in the substrate 100 below the sidewall 130.

[0055] Step S12: Covering the substrate and the first gate structure with a target shape with a stress film and performing stress treatment so that the stress film cooperates with the first gate structure with a target shape to improve the stress of the channel region of the substrate under the first gate structure with a target shape.

[0056] In the specific implementation process, see Figure 6 , Figure 6 Schematic diagram of a semiconductor device covered with a stress film; a stress film 120 is covered on a substrate 100 and a first gate structure 115 having a target shape, and the stress film 120 is formed along the second surface 112 of the first gate structure 115 having a target shape, the surface of the sidewall 130 and the surface of the substrate 100, wherein the stress film 120 can be formed by deposition (DEP, Deposition), and stress treatment is performed during the deposition of the stress film 120, so that the stress film 120, which originally has no stress, has tensile stress or compressive stress, and the tensile stress or compressive stress is conducted to the channel region along the first gate structure 115 having a target shape. The magnitude of the stress in the final channel region is related to the thickness of the stress film 120, the shape of the first gate structure 115 and the height of the first gate structure 115. The stress film 120 can be silicon nitride and / or silicon oxynitride, etc., and the magnitude of the specific stress can also be adjusted by adjusting the ratio of nitrogen, silicon, etc. in the process gas during the deposition process to achieve a stress layer with a desired stress magnitude.

[0057] Since the size of the first surface 111 of the first gate structure 115 with a target shape becomes smaller, the channel area in the substrate 100 below the first gate structure 115 with a target shape becomes smaller. When performing stress treatment, the first gate structure 115 with a target shape having a larger top and a smaller bottom cooperates with the stress film 120, which can better conduct stress to the channel area, greatly improving the stress in the reduced channel area.

[0058] Step S13: removing the stress film on the second surface of the first gate structure having the target shape, and retaining the residual stress film covering the non-gate structure region of the substrate and both sides of the first gate structure having the target shape.

[0059] For details, see Figure 7 and Figure 8 , Figure 7 A schematic diagram of a semiconductor device covered with a first dielectric layer; Figure 8 for Figure 7 Schematic diagram of the semiconductor device after grinding, specifically, step S13 includes:

[0060] Step S131: Covering the stress film with a first dielectric layer.

[0061] For details, see Figure 7 , Figure 7 It is a schematic diagram of a semiconductor device covered with a first dielectric layer. In the present embodiment, after forming the stress film 120, a first dielectric layer 171 is formed on the surface of the stress film 120. The thickness of the first dielectric layer 171 is at least not less than the thickness of the first gate structure 115 having a target shape. The first dielectric layer 171 can be formed by a deposition process. The first dielectric layer 171 can be silicon dioxide or a compound of silicon and oxygen.

[0062] Step S132: grinding away a portion of the dielectric layer and a portion of the stress film until the second surface of the first gate structure having a target shape is exposed.

[0063] For details, see Figure 8 , Figure 8 for Figure 7 FIG. 1 is a schematic diagram of a semiconductor device after grinding. In the present embodiment, a CMP (Chemical Mechanical Polishing) process is used to thin and flatten the top of the first gate structure 115 having a target shape, and a portion of the first dielectric layer 171 and a portion of the stress film 120 are ground away until the second surface 112 of the first gate structure 115 having a target shape is exposed, and a residual stress film 121 covering the non-target-shaped first gate structure 115 region of the substrate 100 and on both sides of the first gate structure 115 having a target shape is retained, and the residual stress film 121 improves the stress of the shrunken channel region.

[0064] In some embodiments, see Fig. 9 , Fig. 9 for Figure 8 Schematic diagram of forming a gate contact plug in a semiconductor device, after step S132, the manufacturing method further includes:

[0065] Step S1330: forming a second dielectric layer on the remaining first dielectric layer, and forming a gate contact plug connected to the first gate structure having a target shape in the second dielectric layer, wherein the polysilicon gate in the first gate structure having a target shape serves as a gate.

[0066] For details, see Fig. 9 , Fig. 9 for Figure 8 Schematic diagram of forming a gate contact plug in a semiconductor device in the embodiment, in this embodiment, a second dielectric layer 172 is formed on the remaining first dielectric layer 171, and the second dielectric layer 172 covers the first dielectric layer 171 and the first gate structure 115 having a target shape, wherein the second dielectric layer 172 can be formed by a deposition process, and the second dielectric layer 172 can be silicon dioxide or a compound of silicon and oxygen, and further, the material of the second dielectric layer 172 can be the same as or different from the material of the first dielectric layer 171.

[0067] Continue to see Fig. 9 A gate contact plug 180 connected to the first gate structure 115 having a target shape is formed in the second dielectric layer 172, thereby realizing interconnection between the first gate structure 115 having a target shape and other metal layers. The gate contact plug 180 can be made of conductive materials such as metal tungsten and aluminum.

[0068] Continue to see Fig. 9 , a source-drain contact plug 190 connecting the source region 140 and the drain region 150 is formed in the second dielectric layer 172, the first dielectric layer 171 and the stress film 120. The source-drain contact plug 190 includes a source contact plug and a drain contact plug, thereby realizing the interconnection between the source region 140 and the drain region 150 and other metal layers. The source-drain contact plug 190 can be made of conductive materials such as metal tungsten and aluminum. That is, in this embodiment, the polysilicon gate 113 is directly used as the gate. The first gate structure 115 with a target shape forms the gate structure 110 of the semiconductor device 10.

[0069] In other embodiments, see Figures 10 to 12 , Fig.10 for Figure 8 Schematic diagram of removing polysilicon gate from a semiconductor device; Fig.11 for Fig.10 Schematic diagram of a semiconductor device filled with a metal gate; Fig.12 for Fig.11 Schematic diagram of forming a gate contact plug in a semiconductor device. After step S132, the manufacturing method further includes:

[0070] Step S1331: removing the polysilicon gate in the first gate structure having the target shape, and filling a metal gate in the original area of ​​the polysilicon gate to form a second gate structure.

[0071] See also Fig.10 and Fig.11 , Fig.10 for Figure 8 Schematic diagram of removing polysilicon gate from semiconductor device. Fig.11 for Fig.10 Schematic diagram of a semiconductor device filled with a metal gate. The polysilicon gate 113 in the first gate structure 115 having a target shape is removed by a gate-last process, and the removal operation can be performed by an etching process. A gap is formed in the area of ​​the original polysilicon gate. The gap is as shown in FIG. Fig.10 As shown. Fig.11 As shown, a metal gate 117 is filled in the gap. The metal gate 117 is formed by depositing a metal material in the gap. The material of the metal gate 117 can be selected by comprehensively considering the conductivity, thermal stability and compatibility with the dielectric material of the material. Generally speaking, tungsten and aluminum are commonly used choices. The second gate structure 116 includes the above-mentioned metal gate 117 and a gate oxide layer 114. In other embodiments, other methods can also be used to remove the polysilicon gate 113, such as chemical etching, reactive ion etching or other dry etching.

[0072] Step S1332: forming a second dielectric layer on the remaining first dielectric layer, and forming a gate contact plug connected to the metal gate in the second dielectric layer, wherein the metal gate serves as a gate.

[0073] For details, see Fig.12 , Fig.12 for Fig.11 Schematic diagram of forming a gate contact plug in a semiconductor device. In this embodiment, a second dielectric layer 172 is formed on the remaining first dielectric layer 171, and the second dielectric layer 172 covers the first dielectric layer 171 and the second gate structure 116. The second dielectric layer 172 can be formed by a deposition process. The second dielectric layer 172 can be silicon dioxide or a compound of silicon and oxygen. Furthermore, the material of the second dielectric layer 172 can be the same as or different from the material of the first dielectric layer 171.

[0074] Continue to see Fig.12 A gate contact plug 180 connected to the second gate structure 116 is formed in the second dielectric layer 172 to achieve interconnection between the second gate structure 116 and other metal layers. The gate contact plug 180 can be made of conductive materials such as metal tungsten and aluminum.

[0075] Continue to see Fig.12, a source-drain contact plug 190 connecting the source region 140 and the drain region 150 is formed in the second dielectric layer 172, the first dielectric layer 171 and the stress film 120. The source-drain contact plug 190 includes a source contact plug and a drain contact plug, thereby realizing the interconnection between the source region 140 and the drain region 150 and other metal layers. The source-drain contact plug 190 can be made of conductive materials such as metal tungsten and aluminum. In this embodiment, the polysilicon gate 113 is used as a pseudo gate, and the metal gate 117 is used as the subsequent actual gate. At this time, the second gate structure 116 forms the gate structure 110 of the semiconductor device 10. Among them, the gate structure 110 may also include an HK layer and a work function layer (not shown) located between the metal gate 117 and the gate oxide layer 114, which will not be described here.

[0076] The manufacturing method of the semiconductor device 10 provided in the present embodiment forms a gate structure 110 with a larger top and a smaller bottom by etching the gate structure 110. Since the bottom of the gate structure 110 becomes smaller, when performing stress treatment, the gate structure 110 with a target shape combined with the stress film 120 can more effectively conduct stress to the channel region through the gate structure 110, greatly improve the stress in the reduced channel region, and effectively improve the device performance of the semiconductor device 10. Fig. 9 and Fig.12 , the size of the first surface 111 of the gate structure 110 of the present application is etched smaller, which results in a smaller channel area in the substrate 100 below the gate structure 110 compared to the prior art. According to the capacitance formula: C = □*A / d. Wherein, □ is the dielectric constant, A is the capacitance area, and d is the distance between electrodes. When the gate structure 110 is in a shape with a large top and a small bottom, the distance between the gate and the drain region 150 increases, and the capacitance decreases accordingly, reducing the overlapping capacitance problem caused by the miniaturization of the size, and further improving the device performance of the semiconductor device 10.

[0077] Further, in order to solve the above problems, the second aspect of the present application provides a semiconductor device 10. Specifically, see Fig. 9 and Fig.12The semiconductor device 10 includes a substrate 100, and a gate structure 110 having a target shape, which is disposed on the substrate 100. The gate structure 110 has at least a first surface 111 and a second surface 112, wherein the first surface 111 is a side of the gate structure 110 in contact with the substrate 100, and the second surface 112 is disposed opposite to the first surface 111, and the second surface 112 is a side of the gate structure 110 away from the substrate 100. The target shape includes that the size of the first surface 111 of the gate structure 110 close to the substrate 100 is smaller than the size of the second surface 112 of the gate structure 110 away from the substrate 100, and the first surface 111 is opposite to the second surface 112; and a residual stress film 121, which covers the non-gate structure 110 area of ​​the substrate 100 and covers both sides of the gate structure 110. The residual stress film 121 is combined with the gate structure 110, which is conducive to retaining stress in the channel area below the gate structure 110, improving the carrier mobility, and thus improving the performance of the semiconductor device 10.

[0078] In some embodiments, see Figure 4 , along the direction close to the substrate 100, the width of the gate structure 110 gradually decreases, such as Figure 4 As shown in (a); or the first surface 111 of the gate structure 110 has a gap relative to the second surface 112, such as Figure 4 As shown in (b), the shape of the notch can be an arc-shaped notch or a triangular notch, or other irregular-shaped notches, as long as the gate structure 110 is in a shape with a larger top and a smaller bottom.

[0079] In some embodiments, the gate structure 110 includes a gate and a gate oxide layer 114. Specifically, the gate oxide layer 114 may be silicon oxide, etc., and the gate oxide layer 114 is located between the gate and the substrate 100. The first surface 111 of the gate structure 110 is the surface of the gate oxide layer 114 close to the substrate 100, and the second surface 112 of the gate structure 110 is the surface of the gate away from the substrate 100. The second surface 112 is arranged opposite to the first surface 111.

[0080] In some embodiments, the gate includes a polysilicon gate 113 or a metal gate 117 .

[0081] The semiconductor device 10 provided in this embodiment forms a gate structure 110 of a target shape on a substrate 100, wherein the size of the gate structure 110 close to the first surface 111 of the substrate 100 is smaller than the size of the gate structure 110 away from the second surface 112 of the substrate 100. A residual stress film 121 is covered on the non-gate structure 110 region of the substrate 100 and on both sides of the gate structure 110. The residual stress film 121 and the gate structure 110 work together to greatly improve the stress of the reduced channel region. Since the bottom of the gate structure 110 becomes smaller, the distance between the gate and the drain region 150 becomes larger, the gate-drain capacitance is further reduced, and the overlap capacitance is improved.

[0082] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0083] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the description and drawings of the present application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, and forming a first gate structure having a target shape on the substrate, wherein the target shape includes a size of the first gate structure close to a first surface of the substrate being smaller than a size of the first gate structure away from a second surface of the substrate, the first surface is opposite to the second surface, and the first gate structure having the target shape includes a polysilicon gate; Covering the substrate and the first gate structure having a target shape with a stress film and performing stress treatment, so that the stress film cooperates with the first gate structure having a target shape to improve the stress of the channel region of the substrate under the first gate structure having a target shape; The stress film on the second surface of the first gate structure having the target shape is removed, and a residual stress film covering the non-gate structure region of the substrate and both sides of the first gate structure having the target shape is retained.

2. The method according to claim 1, characterized in that: The step of providing a substrate and forming a first gate structure having a target shape on the substrate comprises: providing the substrate; forming a first gate structure on the substrate, wherein the width of the first gate structure is uniform along a direction close to the substrate; The first gate structure is etched to form the first gate structure having the target shape, wherein the width of the first gate structure having the target shape gradually decreases along a direction approaching the substrate; or the first surface of the first gate structure having the target shape has a notch relative to the second surface.

3. The method according to claim 1, characterized in that: After providing a substrate and forming a first gate structure having a target shape on the substrate, the manufacturing method further includes: Forming sidewall spacers on both sides of the first gate structure having a target shape; The first gate structure and the spacer having the target shape are used as masks to form a source region and a drain region in the substrate.

4. The method according to claim 1, characterized in that: The removing the stress film on the second surface of the first gate structure having the target shape comprises: Covering the stress film with a first dielectric layer; A portion of the dielectric layer and a portion of the stress film are ground away until the second surface of the first gate structure having a target shape is exposed.

5. The method according to claim 4, characterized in that: Also includes: A second dielectric layer is formed on the remaining first dielectric layer, and a gate contact plug connected to the first gate structure having a target shape is formed in the second dielectric layer, wherein the polysilicon gate in the first gate structure having a target shape serves as a gate.

6. The method according to claim 4, characterized in that: Also includes: Removing the polysilicon gate in the first gate structure having the target shape, and filling a metal gate in the original area of ​​the polysilicon gate to form a second gate structure; A second dielectric layer is formed on the remaining first dielectric layer, and a gate contact plug connected to the metal gate is formed in the second dielectric layer, wherein the metal gate serves as a gate.

7. A semiconductor device, characterized in that: include: substrate; A gate structure having a target shape is disposed on the substrate, wherein the target shape includes a size of the gate structure close to a first surface of the substrate being smaller than a size of the gate structure away from a second surface of the substrate, the first surface being opposite to the second surface; The residual stress film covers the non-gate structure region of the substrate and covers both sides of the gate structure.

8. The semiconductor device according to claim 7, characterized in that The width of the gate structure gradually decreases along a direction approaching the substrate; or The first surface of the gate structure has a notch relative to the second surface.

9. The semiconductor device according to claim 7, characterized in that The gate structure includes a gate and a gate oxide layer, wherein the gate oxide layer is located between the gate and the substrate, wherein the first surface of the gate structure is a surface of the gate oxide layer close to the substrate, and the second surface of the gate structure is a surface of the gate away from the substrate.

10. The semiconductor device according to claim 9, characterized in that The gate includes a polysilicon gate or a metal gate.

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