Formation of isolation regions with low parasitic capacitance and reduced damage

Abstract

The disclosure relates to forming isolation regions with low parasitic capacitance and reduced damage. A structure includes a plurality of semiconductor regions, a first gate stack and a second gate stack directly adjacent to each other, a first fin isolation region in the first gate stack, and a second fin isolation region in the second gate stack. The first fin isolation region and the second fin isolation region have a lateral overlap with an overlap distance equal to or greater than a pitch of the plurality of semiconductor regions. An overlap distance is measured in a longitudinal direction parallel to the first gate stack and the second gate stack. A plurality of source / drain regions are on opposite sides of the first gate stack and the second gate stack to form a plurality of transistors.

Description

Technical Field

[0001] The present disclosure relates to forming isolation regions with low parasitic capacitance and reduced damage. Background Art

[0002] Technological advances in integrated circuit (IC) materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generations. In the course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometric size has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This shrinkage has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances. For example, gate-all-around (GAA) transistors have been introduced to replace planar transistors. The structure of GAA transistors and methods of manufacturing GAA transistors are being developed.

[0004] The formation of a GAA transistor generally includes forming a long strip (comprising alternating semiconductor materials) and a long gate stack, and then forming an isolation region to cut the long strip and the long gate stack into shorter sections. The shorter sections can be used to form the channel layer and gate stack of the GAA transistor. Summary of the invention

[0005] According to an embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a plurality of semiconductor regions having a first longitudinal direction parallel to a first direction; forming a plurality of gate stacks having a second longitudinal direction parallel to a second direction, the second direction being perpendicular to the first direction, wherein the plurality of gate stacks are located on a first portion of the plurality of semiconductor regions; etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks, wherein the plurality of openings comprise: a first opening located in a first gate stack among the plurality of gate stacks; and a second opening located in a second gate stack among the plurality of gate stacks, wherein the first opening and the second opening are directly adjacent to each other and have a lateral overlap, the lateral overlap having an overlap distance equal to or greater than a spacing between the plurality of semiconductor regions, and wherein the overlap distance is parallel to the second longitudinal direction; etching the plurality of semiconductor regions exposed by the plurality of openings so that the plurality of openings extend downward between dielectric isolation regions; and filling the plurality of openings to form a fin isolation region.

[0006] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a plurality of semiconductor regions; a first gate stack and a second gate stack, directly adjacent to each other; a first fin isolation region, located in the first gate stack; a second fin isolation region, located in the second gate stack, wherein the first fin isolation region and the second fin isolation region have a lateral overlap, the lateral overlap having an overlap distance equal to or greater than a spacing between the plurality of semiconductor regions, and wherein the overlap distance is measured in a direction parallel to a longitudinal direction of the first gate stack and the second gate stack; and a plurality of source / drain regions, located on opposite sides of the first gate stack and the second gate stack to form a plurality of transistors.

[0007] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: an elongated semiconductor region comprising a plurality of portions, wherein the elongated semiconductor region comprises a first semiconductor material; a first gate stack and a second gate stack directly adjacent to each other; an epitaxial semiconductor region located between and in contact with the first and second portions of the elongated semiconductor region, wherein the epitaxial semiconductor region comprises a second semiconductor material different from the first semiconductor material; a first dielectric isolation region located in the first gate stack; and a second dielectric isolation region located in the second gate stack, wherein both the first dielectric isolation region and the second dielectric isolation region intersect with the elongated semiconductor region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features can be arbitrarily increased or reduced.

[0009] Figures 1 to 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B, Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig. 15C , Fig.15D , Fig.15E , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.18C , Fig.19 , Fig. 20 , Fig.21A , Fig. 21B , Fig.22A , Fig. 22B , Fig.23A and Fig. 23B A view of an intermediate stage in forming a gate all around (GAA) transistor is shown in accordance with some embodiments.

[0010] Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A , Fig.28B , Fig.29A , Fig.29B , Fig. 30A and Fig. 30B The formation of a continuous polysilicon on diffusion edge (CPODE) region with dummy fins is shown in accordance with some embodiments.

[0011] Fig.31 A process flow for forming a GAA transistor is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, spatially relative terms (e.g., "below," "beneath," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0014] Provided are gate all around (GAA) transistors and continuous polysilicon on diffusion edge (CPODE) isolation regions, continuous metal on diffusion edge (CMODE) isolation regions, and methods for forming them. According to some embodiments of the present disclosure, CPODE isolation regions (or CMODE isolation regions) located on adjacent gate stacks have overlap in the longitudinal direction of the gate. This produces wider photoresist strips in the photoresist used to pattern the CPODE / CMODE regions. Because wider photoresist strips are formed, the possibility of photoresist strip collapse is reduced, and the defect rate is reduced.

[0015] In the illustrated embodiment, the formation of a GAA transistor is used as an example to explain the concepts of the present disclosure. Other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors) may also employ the concepts of the present disclosure. The purpose of the embodiments discussed herein is to provide examples to enable the subject matter of the present disclosure to be made or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0016] Figures 1 to 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig. 15C , Fig.15D , Fig.15E , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.18C , Fig.19 , Fig. 20 , Fig.21A , Fig. 21B , Fig.22A and Fig. 22B FIG. 1 shows a view of an intermediate stage when forming a GAA transistor according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in FIG. Fig.31 The process flow is shown.

[0017] refer to Figure 1 , a perspective view of a wafer 10 is shown. The wafer 10 includes a multilayer structure including a multilayer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., but other substrates and / or structures may be used, such as semiconductor on insulator (SOI), strained SOI, silicon germanium on insulator, etc. The substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0018] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding processes are Fig.31 The process flow 200 is shown as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0019] According to some embodiments, the first layer 22A of the first semiconductor material is formed of or includes the following: SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is by epitaxial growth, and the corresponding deposition method can be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed at about Peace However, any suitable thickness may be used while remaining within the scope of the embodiments.

[0020] Once the first layer 22A has been deposited on the substrate 20, the second layer 22B is deposited on the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GasB, InAlAs, InGaAs, GasB, GaAsSB, and combinations thereof, and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments in which the first layer 22A is silicon germanium, the second layer 22B can be formed of silicon, and vice versa. It should be understood that any suitable material combination can be used for the first layer 22A and the second layer 22B.

[0021] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, for example, the second layer 22A has a thickness in a range between about 4 nm and 7 nm, while the second layer 22B has a thickness in a range between about 8 nm and 12 nm.

[0022] Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired topmost layer of the multilayer stack 22 has been formed. According to some embodiments, the first layer 22A has the same or similar thickness as each other, and the second layer 22B has the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as a sacrificial layer 22A throughout the specification. According to an alternative embodiment, the second layer 22B is sacrificed and removed in a subsequent process.

[0023] According to some embodiments, there may be some pad oxide layer(s) and hard mask layer(s) (not shown) formed on top of the multilayer stack 22 . These layers are patterned and used for subsequent patterning of the multilayer stack 22 .

[0024] refer to Figure 2 In the etching process, the multilayer stack 22 and a portion of the underlying substrate 20 are patterned so that the trench 23 is formed. Fig.31 The process flow 200 is shown as process 204. The trench 23 extends into the substrate 20. The remaining portion of the multilayer stack is referred to as the multilayer stack 22' below. Some portions of the substrate 20 are left below the multilayer stack 22' and are referred to as substrate strips 20' below. The multilayer stack 22' includes a semiconductor layer 22A and a semiconductor layer 22B. The semiconductor layer 22A is alternatively referred to as a sacrificial layer, and the semiconductor layer 22B is alternatively referred to as a nanostructure below. The multilayer stack 22' and the portions of the substrate strip 20' below are collectively referred to as semiconductor strips 24.

[0025] In the above-described embodiments, the GAA transistor structure can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning processes or multi-patterning processes) can be used to pattern these structures. Typically, a double patterning process or a multi-patterning process combines a photolithography process with a self-alignment process, thereby allowing the generation of patterns with, for example, a spacing smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0026] Figure 3 The formation of the isolation region 26 is shown, which is also referred to as the shallow trench isolation (STI) region throughout the specification. Fig.31The process flow 200 is shown as process 206. The STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high density plasma chemical vapor deposition (HDPCVD), CVD, etc. The STI region 26 may also include a dielectric material located above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, etc. A planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) may then be performed to make the top surface of the dielectric material flush, and the remaining portion of the dielectric material is the STI region 26.

[0027] The STI region 26 is then recessed so that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin 28. The protruding fin 28 includes the top of the substrate strip 20' and the multilayer stack 22'. The recessing of the STI region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. During the etching process, plasma can be generated. Argon gas can also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 26 is performed by a wet etching process. For example, the etching chemical can include HF.

[0028] refer to Figure 4 , forming a dummy gate stack 30 and a gate spacer 38 on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is Fig.31 The process flow 200 is shown as process 208. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 located on the dummy gate dielectric 32. The dummy gate electrode dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, polysilicon or amorphous silicon may be used to form the dummy gate electrode 34, and other materials such as amorphous carbon may also be used.

[0029] Each dummy gate stack 30 may also include one (or more) hard mask layers 36 located above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a multilayer thereof. The dummy gate stack 30 may span between a single or multiple protruding fins 28 and the STI region 26 between the protruding fins 28. The dummy gate stack 30 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fins 28. The formation of the dummy gate stack 30 includes: forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layer by (one or more) patterning processes.

[0030] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material (e.g., silicon nitride (SiN), silicon monoxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc.), and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. The formation process of the gate spacer 38 may include: depositing one or more dielectric layers, and then performing (one or more) anisotropic etching processes on (one or more) dielectric layers. The remaining portion of (one or more) dielectric layers is the gate spacer 38.

[0031] According to an alternative embodiment, the Fig.19 The process shown is used to form one or more layers of gate spacers 38, and the resulting layers of gate spacers 38 include reference Figures 19 to 21A and Fig. 21B The materials discussed. For example, the gate spacer 38 can be formed of or include SiOCNH. The details of the formation process are discussed in the subsequent paragraphs.

[0032] Figure 5A and Figure 5B Shows Figure 4 Cross-sectional view of the structure shown. Figure 5A Shows Figure 4 The reference cross section A1-A1 in FIG. 1 cuts through the portion of the protruding fin 28 that is not covered by the gate stack 30 and the gate spacer 38 and is perpendicular to the gate length direction. The fin spacer 38 located on the sidewall of the protruding fin 28 is also shown. Figure 5B Shows Figure 4 , which is parallel to the longitudinal direction of the protruding fin 28 .

[0033] refer to Fig. 6A and Figure 6B, the portion of the protruding fin 28 that is not directly below the dummy gate stack 30 and the gate spacer 38 is recessed by an etching process to form a recess 42. The corresponding process is Fig.31 The process flow 200 is shown as process 210. For example, a dry etching process can be performed using C2F6, CF4, SO2, a mixture of HBr, Cl2 and O2, a mixture of HBr, Cl2, O2 and CH2F2, etc. to etch the multilayer semiconductor stack 22' and the substrate strip 20' below. The bottom of the recess 42 is at least flush with the bottom of the multilayer semiconductor stack 22', or can be lower than the bottom of the multilayer semiconductor stack 22' (e.g., Figure 6B The etching may be anisotropic so that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown in FIG. Figure 6B shown.

[0034] refer to Fig. 7A and Figure 7B , the sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, and the lateral recess 41 is recessed from the edges of the corresponding upper nanostructure 22B and the corresponding lower nanostructure 22B. Fig.31 The process flow 200 is shown as process 212. The lateral recessing of the sacrificial semiconductor layer 22A can be achieved by a wet etching process using an etchant that is more selective to the material of the sacrificial semiconductor layer 22A (e.g., silicon germanium (SiGe)) than to the material of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructure 22B is formed of silicon, the wet etching process can be performed using an etchant such as hydrochloric acid (HCl). The wet etching process can be performed using a dipping process, a spraying process, a spin coating process, etc.

[0035] According to alternative embodiments, the lateral recessing of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

[0036] refer to Fig. 8A and Figure 8B , forming the internal spacer 44. The corresponding process is Fig.31 The process flow 200 is shown as process 214. According to some embodiments, the formation of the inner spacer 44 includes depositing a conformal dielectric layer that extends into the lateral recess 41 ( Figure 7B Next, an etching process (also referred to as a spacer trimming process) is performed to trim the portion of the spacer layer outside the lateral recess 41, thereby leaving a portion of the spacer layer in the lateral recess 41. The remaining portion of the spacer layer is referred to as an inner spacer layer 44.

[0037] Fig. 9A and Fig. 9B 4 shows a cross-sectional view and a perspective view of forming a source / drain region 48 in the recess 42 by epitaxy. Fig.31 The process flow 200 is shown as process 216. The source / drain region(s) may be referred to individually or collectively as source or drain, depending on the context. According to some embodiments, the source / drain region 48 may stress the nanostructure 22B that serves as the channel of the corresponding GAA transistor, thereby improving performance.

[0038] According to some embodiments, the corresponding transistor is n-type, and accordingly, the epitaxial source / drain region 48 is formed to be n-type by doping an n-type dopant. For example, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown to form the epitaxial source / drain region 48. According to alternative embodiments, the corresponding transistor is p-type, and accordingly, the epitaxial source / drain region 48 is formed to be p-type by doping a p-type dopant. For example, silicon phosphorus (SiP), silicon germanium boron (SiGeB), etc. can be grown to form the epitaxial source / drain region 48. After filling the recess 42 with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 causes the epitaxial region 48 to expand horizontally, and a small plane can be formed. Further growth of the epitaxial region 48 can also cause adjacent epitaxial regions 48 to merge with each other, thereby forming a gap 49 ( Fig. 10C ).

[0039] After the epitaxial process, the epitaxial region 48 may be further implanted with n-type impurities or p-type impurities to form source and drain regions, which are also denoted by reference numeral 48. According to an alternative embodiment of the present disclosure, the implantation process is skipped when the epitaxial region 48 is in-situ doped with n-type impurities or p-type impurities during epitaxy and the epitaxial region 48 is also a source / drain region.

[0040] Fig. 10A and Fig. 10B FIG. 4 shows a cross-sectional view of the structure after forming a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52. The corresponding process is shown in FIG. Fig.31The process flow 200 is shown as process 218. CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. ILD 52 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0041] CESL 50 and ILD 52 are planarized by a planarization process (eg, a CMP process or a mechanical grinding process). According to some embodiments, the planarization process may remove hard mask 36 to expose dummy gate electrode 34, such as Fig. 10A According to alternative embodiments, the planarization process may expose the hard mask 36 and be stopped on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), the gate spacer 38, and the ILD 52 are flush within process variations.

[0042] Fig. 10C According to some embodiments Fig. 10A and Fig. 10B The structure shown is a top view. The multilayer stack 22', substrate strip 20' and protruding fin 28 (refer to Fig. 10A ) has a longitudinal direction in the X direction (parallel to the X direction), and the corresponding cross-sectional view is referred to as an X-cut view. The dummy gate stack 30 including the dummy gate electrode 34 (e.g., a polysilicon strip) has a longitudinal direction in the Y direction (parallel to the Y direction), and the corresponding cross-sectional view is referred to as a Y-cut view. Based on some parts of the multilayer stack 22 ′ (e.g., Figure 5B and Fig. 10B 38 ) source / drain regions 48. Edges of the source / drain regions may be in contact with the gate spacers 38 or may be spaced apart from the gate spacers 38.

[0043] Fig.11A and FIG. 11B to FIG. 16A , Fig. 16B and Fig. 16C 1 shows a top view and a cross-sectional view of the formation of the fin isolation region 112 according to these embodiments, which is a continuous polysilicon on diffusion edge (CPODE) region. The name "fin isolation region" is used because the CPODE region and the CMODE region are formed to cut the protruding fin 28 and the semiconductor strip below. In the subsequent figures, from Fig. 10C or Fig.21A and Fig. 21B The Y-cut (in the Y direction) in FIG. 1 is used to obtain the drawings with the letter A after the corresponding reference numerals, while Fig. 10C or Fig.21A and 21B An X-cut (along the X direction) in the drawings results in the drawings having the letter B after the corresponding reference numerals.

[0044] According to some embodiments, the formation of the fin isolation region 112 involves cutting the dummy gate stack 30, the multilayer stack 22' and the substrate strip 20'. According to alternative embodiments, such as Fig.18C , Fig.19 and Fig. 20 As shown, the fin isolation region 112 is formed by cutting the replacement gate stack 70 and the semiconductor region below. Therefore, the fin isolation region 112 will be a CMODE region. Therefore, Fig.31 The processes 222 to 230 and the processes 238 to 240 in FIG. 1 are shown as dotted lines to indicate that one of the CPODE process or the CMODE process may be performed, while the other process may not be performed.

[0045] Fig.11A and Fig. 11B Shows Fig. 10C The structures in , and obtained from Y cutting and X cutting respectively. Fig.11A and Fig. 11B Also corresponds to Fig. 10A and Fig. 10B Accordingly, Fig.11A The multilayer stack 22 ′ and a dummy gate stack 30 on the multilayer stack 22 ′ are shown. Fig. 11B The source / drain regions 48 , the multilayer stack 22 ′, the internal spacers 44 , and the dummy gate stack 30 are shown.

[0046] refer to Fig. 12A and Fig. 12B , forming a hard mask 116. The corresponding process is Fig.31 The process flow 200 is shown as process 220. The hard mask 116 may include a dielectric material such as SiN, silicon, or multiple layers thereof. An etch mask 117 is formed over the hard mask 116. The corresponding process is shown in FIG. Fig.31 The process flow 200 is shown as process 222. According to some embodiments, the etch mask 117 includes a patterned photoresist having an opening 118 therein (and alternatively referred to as photoresist 117), and may or may not include other layers, such as a bottom anti-reflective coating. The etch mask 117 may also be a double-layer etch mask or a triple-layer etch mask. The hard mask 116 is etched so that the opening 118 passes through the hard mask 116.

[0047] Fig. 12C1 shows a top view of an etch mask 117 and a hard mask 116 in which openings 118 (including 118 - 1 to 118 - 8 ) are formed according to some embodiments. Fig.31 This is shown as process 224 in the illustrated process flow 200. It should be understood that the plurality of openings 118 are located directly above the dummy gate stack 30 and may or may not extend directly above the gate spacers 38. The openings 118 may be elongated with a longitudinal direction parallel to (in the longitudinal direction of) the dummy gate stack 30 (and the dummy gate electrode 34).

[0048] Throughout the specification, to simplify the discussion, the “+Y” direction is referred to as the “up” direction, and the “-Y” direction is referred to as the “down” direction. According to some embodiments, when two openings 118 are located on directly adjacent dummy gate stacks 30 and extend to the space between two adjacent multilayer stacks 22’, the two openings 118 span the same multilayer stack 22’. Throughout the specification, when two gate stacks (or openings) are described as “directly adjacent” gate stacks, it means that there is no gate stack (or opening) between them. Openings located on directly adjacent gate stacks or extending into directly adjacent gate stacks are also referred to as “directly adjacent” openings. For example, both opening 118-2 and opening 118-3 intersect with multilayer stack 22’-3, and both opening 118-1 and opening 118-2 intersect with multilayer stack 22’-1.

[0049] According to alternative embodiments, the opening 118 located on the directly adjacent dummy gate stack 30 may intersect two or more multilayer stacks 22 ′. Fig. 12C Both opening 118-2 and opening 118-3 are shown intersecting multilayer stack 22-3, while in alternative embodiments, opening 118-2 may extend upward in the +Y direction such that both opening 118-2 and opening 118-3 intersect multilayer stack 22-3 and multilayer stack 22-4.

[0050] In other words, the top end 118-2TE of the opening 118-2 extends in the +Y direction beyond the bottom end 118-3BE (the end in the -Y direction) of the opening 118-3. Moreover, the top end 118-1TE of the opening 118-1 extends in the +Y direction beyond the bottom end 118-2BE (the end in the -Y direction) of the opening 118-2. This can also be interpreted as that when the opening 118 is viewed from left to right (or from right to left), the opening 118-2 has a top that intersects with the bottom of the opening 118-1 (also referred to as lateral overlap when viewed from left to right), and the opening 118-2 has a bottom that intersects with the top of the opening 118-3 (lateral overlap).

[0051] Similarly, other openings 118 may have their top and / or bottom ends extending beyond the bottom and / or top ends of the openings 118 on the directly adjacent dummy gate stack 30, respectively.

[0052] Due to the side overlap of directly adjacent openings 118, the epitaxial regions 48 therebetween are not used to form transistors. For example, the epitaxial region 48-1 is located between the opening 118-2 and the opening 118-3, and is thus completely surrounded by dielectric material and is not part of any transistor.

[0053] According to some embodiments, the longer openings 118 (having a longitudinal direction in the gate longitudinal direction) are designed to be narrower and have a smaller width. For example, the openings 118-1, 118-2, and 118-3 have lengths L1, L2, and L3, and widths W1, W2, and W3, respectively. The dimensions of the openings 118 are designed to have the relationship L3 > L2 > L1. Correspondingly, the widths are designed to have the relationship W3 < W2 < W1 to fit the length difference. In other words, the longer openings 118 are made narrower, and vice versa. This will advantageously reduce the likelihood of photoresist collapse and delamination. For example, the openings 118-7 and 118-8 have photoresist portions between and within the region 119, and this photoresist portion has a length L9 and a width W9. This portion of the photoresist is smaller and prone to collapse.

[0054] By reducing the width W7 of the longer opening 118, the width W9 of the photoresist 117 portion in the region 119 increases, and thus it is less likely to collapse. In addition, by having adjacent openings overlap laterally in their longitudinal directions, the length of the photoresist 117 portion therebetween is longer. For example, the length L9 of the photoresist 117 portion in the region 119 can be large enough such that this portion of the photoresist 117 is less likely to collapse. Otherwise, if the top end of the opening 118-8 retreats in the -Y direction, and / or the bottom end of the opening 118-7 retreats in the +Y direction, the length L9 decreases, and this portion of the photoresist 117 is more likely to collapse. When the top end of the opening 118-8 has the same Y value as the bottom end of the opening 118-7, process errors may occur, and an opening connecting the opening 118-7 to the opening 118-8 may even be formed.

[0055] According to some embodiments, throughout the wafer 10, a threshold length is determined, and throughout the wafer 10 and the corresponding device die, the openings 118 with lengths less than the threshold length are referred to as short openings, while the openings 118 with lengths equal to or greater than the threshold length are referred to as long openings. The short openings 118 are designed to have a first width, and the long openings 118 with lengths equal to or greater than the threshold length are designed to have a second width smaller than the first width.

[0056] According to an alternative embodiment, instead of having one threshold length and therefore two length ranges, there may be a first threshold length and a second threshold length greater than the first threshold length. Throughout the wafer 10 and the corresponding device die, an opening 118 having a length less than the first threshold length may be a short opening having a first width. An opening having a length equal to or greater than the first threshold length but less than the second threshold length may be an intermediate length opening having a second width less than the first width. An opening having a length equal to or greater than the second threshold length may be a long opening having a third width less than the second width. There may also be three or more threshold lengths and corresponding length ranges, and their widths are therefore designed to have a reverse trend as described above.

[0057] According to some embodiments, the distance that an opening extends beyond its adjacent opening (in the +Y or -Y direction) is referred to as the "overlap distance" of the lateral overlap. For example, opening 118-7 and opening 118-8 have an overlap distance L9. The overlap distance between directly adjacent openings 118 can be equal to or greater than the pitch P1 of adjacent active regions (e.g., multilayer stack 22') to reliably reduce the possibility of photoresist collapse. The overlap distance can also be n*P1, where n is an integer or non-integer equal to or greater than 1 (2, 3, 4, 5 or more). In addition, the shorter opening can have its ends aligned in the middle between adjacent epitaxial regions 48. For example, the top 118-4TE of opening 118-6 is aligned with the center line MDL-1, while the top 118-5TE of opening 118-5 deviates from the center line MDL-2.

[0058] Fig.12D 1 shows a top view of a structure including a non-overlapping embodiment according to some embodiments. Openings 118-13 to 118-9 are formed in the etch mask 117 and may be located at the same Fig. 12C The openings 118 shown are on the same wafer (and the same device die). According to some embodiments, the openings 118-9 and 118-10 are located on adjacent dummy gate stacks 30 and have the same length L10. The openings 118-9 and 118-10 also extend on two adjacent multilayer stacks 22', and both extend into the same space between two adjacent multilayer stacks 22'. The midline between adjacent multilayer stacks 22' is MDL-3.

[0059] According to some embodiments, in order to reduce defects in the etching mask 117, both ends of the opening 118-9 and the opening 118-10 are recessed away from the center line MDL-3. For example, both the opening 118-9 and the opening 118-10 are recessed from the center line MDL3 in the Y direction by the same distance ΔS1, which may be in the range between about 1 nm and about 5 nm. However, both the opening 118-9 and the opening 118-10 still extend into the same space between two adjacent multilayer stacks 22'.

[0060] According to some embodiments, the opening 118-11 and the opening 118-12 are located on adjacent dummy gate stacks 30, and adjacent openings of the opening 118-11 and the opening 118-12 have different lengths L12 and L13 in the Y direction, wherein the length L12 is greater than the length L13. The longer opening 118-12 and the shorter opening 118-13 also extend on adjacent multilayer stacks 22' having a centerline MDL-4. According to these embodiments, the longer opening 118-12 is recessed from the centerline MDL-4 by a distance ΔS2, which may be in a range between about 1 nm and about 5 nm. However, the end of the shorter opening 118-13 remains aligned with the centerline MDL-4 and is not recessed. In addition, the width of the longer opening 118-12 may also be smaller than the width of the shorter opening 118-13, so that due to the etching load effect, Fig. 15C and Fig. 21B In the illustrated configuration, the corresponding widths are equal to each other.

[0061] According to some embodiments, the opening 118-12 and the opening 118-13 are located on a dummy gate stack 30, which is further spaced apart from each other by another dummy gate stack 30. Adjacent openings of the opening 118-12 and the opening 118-13 have different lengths L13 and L14 in the Y direction, respectively, wherein the length L13 is less than the length L14. The longer opening 118-13 and the shorter opening 118-12 also extend on adjacent multilayer stacks 22' having a centerline MDL-4. According to these embodiments, the longer opening 118-13 is recessed from the centerline MDL-4 by a distance ΔS2, which may be in a range between about 1 nm and about 5 nm. However, the end of the shorter opening 118-12 remains aligned with the centerline MDL-4 and is not recessed.

[0062] like Fig.13A and Fig. 13BAs shown, the hard mask 116 is then used to etch through the underlying dummy gate electrode 34 until the dummy gate dielectric 32 is exposed. The etch is anisotropic so that the edge of the dummy gate electrode 34 facing the opening 118 is vertical and straight. During the etching process, the dummy gate dielectric 32 can serve as an etch stop layer. The dummy gate dielectric 32 is then removed, for example, by an isotropic etching process, thereby exposing the multilayer stack 22'. The resulting structure is shown in FIG. Fig.14A and Fig. 14B The corresponding process is Fig.31 This is shown in the illustrated process flow 200 as process 226 .

[0063] Next, one or more etching processes are performed to remove the multilayer stack 22', followed by further etching of the underlying semiconductor material (eg, semiconductor strips 20'). Fig.31 The process flow 200 is shown as process 228. Thus, openings 120 are formed between adjacent STI regions 26, such as Fig.15A and 15B Opening 120 may extend to a level below the bottom surface of STI region 26 to reduce leakage. Fig. 15C Shown in Fig.15A and Fig. 15B A top view of the opening 118 in the structure shown. The opening 120 is not labeled and is located within the opening 118 and also at the location of the original multilayer stack 22'.

[0064] According to some embodiments, by forming the openings 118 ( Fig. 12C ), and due to the etching loading effect caused by different lengths and different overlap distances, Fig. 15C The openings 118 in the Fig.21A Widths W1 ' to W8' are shown.

[0065] Fig.15D and Fig.15E The following are respectively shown according to some embodiments Fig. 15C Cross section of the structure shown Figure 15D-15D and cross section Figure 15E-15E As described above, the width of the long opening 118 is reduced to be smaller, while the width of the short opening 120 is not reduced and is therefore larger. The larger width of the short opening results in a deeper opening 120 corresponding to the shorter opening 118, and the deeper opening 120 effectively reduces leakage. Fig.15D In the embodiment, the opening 120 corresponding to the two short openings 118 is deeper and thus is the main leakage barrier. Fig.15E , the opening 120 corresponding to the middle short opening 118 is deeper and is therefore the primary leakage barrier.

[0066] Fig.16A and Fig. 16B Filling of openings 118 and 120 to form CPODE isolation region 112 is shown. The corresponding process is Fig.31 The process flow 200 is shown as process 230. According to some embodiments, the filling process may include: depositing a dielectric liner 112A, and then depositing a dielectric layer 112B on the dielectric liner 112A. According to some embodiments, the material of the dielectric liner 112A and the dielectric layer 112B may be selected from SiN, SiO, SiON, SiOCN, SiCN, etc. or a combination thereof. Then a planarization process (e.g., a CMP process) may be performed to form the fin isolation region 112, which is a CPODE isolation region.

[0067] Fig. 16C 1 shows a top view of the fin isolation region 112, which includes fin isolation regions 112-1, 112-2, 112-3, 112-4, 112-5, 112-6, 112-7 and 112-8. As described above, the fin isolation region 112 can be formed by cutting the dummy gate stack 34. Alternatively, the fin isolation region 112 can be formed by cutting / etching the replacement gate stack 70 ( Fig. 20 ) to form, so it is not formed at this stage. Fig. 16C In FIG. 1 , the fin isolation regions 112 are shown as dashed lines to indicate that they may or may not be formed at this time. Fig.21A and Fig. 21B The dimensions and relationships of the fin isolation regions 112 are discussed.

[0068] When the isolation region 112 is formed by cutting / etching the replacement gate stack 70, the Fig.11A and FIG. 11B to FIG. 16A , Fig. 16B and Fig. 16C The process shown in FIG. Fig.17A and Fig. 17B The dummy gate electrode 34 and the dummy gate dielectric 32 (and the hard mask 36, if any) are removed in one or more etching processes, thereby forming a recess 58, as shown in FIG. Fig.17A and Fig. 17B The corresponding process is Fig.31The dummy gate electrode 34 and the dummy gate dielectric 32 are shown as process 232 in the illustrated process flow 200. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by an anisotropic dry etching process(es). For example, the etching process may be performed using a reactive gas(es) that selectively etches the dummy gate electrode 34 and the dummy gate dielectric 32 at a faster rate than the ILD 52. Each recess 58 exposes and / or covers a portion of the multilayer stack 22', which includes a future channel region in a subsequently completed transistor.

[0069] The sacrificial layer 22A is then removed to extend the recess 58 between the nanostructures 22B. The corresponding process is Fig.31 This is shown as process 234 in the illustrated process flow 200. The sacrificial layer 22A may be removed by performing an isotropic etching process (e.g., a wet etching process) using an etchant that is selective to the material of the sacrificial layer 22A, while the nanostructures 22B, the substrate 20, and the STI regions 26 remain relatively unetched compared to the sacrificial layer 22A. According to some embodiments where the sacrificial layer 22A includes, for example, SiGe and the nanostructures 22B include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. may be used to remove the sacrificial layer 22A.

[0070] refer to Fig.18A and Fig.18B , forming a gate dielectric 62 and a gate electrode 68, thereby forming a replacement gate stack 70. The corresponding process is Fig.31 The process flow 200 is shown as process 236. According to some embodiments, each of the gate dielectrics 62 includes an interfacial layer and a high-k dielectric layer located on the interfacial layer. The interfacial layer can be formed of or include silicon oxide, which can be deposited by a conformal deposition process (e.g., ALD or CVD) or by an oxidation process. According to some embodiments, the high-k dielectric layer includes one or more dielectric layers. For example, the (one or more) high-k dielectric layer can include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations of the foregoing.

[0071] A gate electrode 68 is also formed. When formed, a conductive layer is first formed on the high-k dielectric layer and fills the remaining portion of the recess 58. The gate electrode 68 may include a metal-containing material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations of the foregoing, and / or multiple layers of the foregoing. For example, the gate electrode 68 may include any number of layers, any number of work function layers, and may include a fill material. The gate dielectric 62 and the gate electrode 68 also fill the space between adjacent nanostructures 22B, and fill the space between the bottom nanostructure 22B and the substrate strip 20' below. After filling the recess 58, a planarization process (e.g., a CMP process or a mechanical grinding process) may be performed to remove excess portions of the gate dielectric and the gate electrode 68 above the top surface of the ILD 52. The gate electrode 68 and the gate dielectric 62 are collectively referred to as the gate stack 70 of the resulting transistor.

[0072] Fig.18C According to some embodiments Fig.18A and Fig.18B The top view of the structure shown in FIG. 1 is assumed that the fin isolation region 112 has not yet been formed. Otherwise, the top view of the resulting structure is as shown in FIG. Fig.21A and Fig. 21B shown. Fig.18C The structure shown is similar to Fig. 10C The structure shown is different in that Fig. 10C The dummy gate stack 30 in Fig.18C The nanostructures 22B and the semiconductor strips 20' therebelow have a longitudinal direction in the X direction.

[0073] Fig.19 and Fig. 20 FIG. 1 shows the formation of the fin isolation region 112 according to some embodiments. The process is substantially the same as Fig.11A and FIG. 11B to FIG. 16A , Fig. 16B and Fig. 16C The same is shown except that the dummy gate stack 30 in these figures is replaced by a replacement gate stack 70 .

[0074] refer to Fig.19 , forming a photoresist 117 and a hard mask 116 (also refer to Fig. 12A and Fig. 12B ), wherein the gate stack 70 and the underlying semiconductor strip are etched to form an opening 118 (including openings 118-1 to 118-8). The portion of the wafer outside the opening 118 is covered by a photoresist 117. The corresponding process is Fig.31 The process flow 200 is shown as process 238. The details of the photoresist 117, hard mask 116 and opening 118 are substantially the same as those shown in FIG. Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D The same as in the above, will not be repeated here. Next, execute Fig.13A and FIG. 13B to FIG. 15A , Fig. 15B and Fig. 15C The process is shown to form the opening 118 . Fig. 20 1 shows a top view of the opening 118 and the opening 120 according to some embodiments. The formation process is substantially the same as Fig.15A , Fig. 15B and Fig. 15C Same as shown.

[0075] The openings 118 and 120 are then filled with (one or more) dielectric materials to form the fin isolation region 112. The corresponding process is Fig.31 The process flow 200 is shown as process 240. According to these embodiments, the fin isolation region 112 is a CMODE isolation region. The resulting structure is as shown in FIG. Fig.21A and Fig. 21B The cross-sectional view of the resulting structure is basically the same as Fig.16A and Fig. 16B The cross-sectional diagram is the same as in Fig.16A and Fig. 16B The dummy gate stack 30 in has been replaced by a replacement gate stack 70 .

[0076] Fig.21A A top view of the fin isolation region 112 according to an alternative embodiment is shown. The fin isolation region 112 includes fin isolation regions 112-1, 112-2, 112-3, 112-4, 112-5, 112-6, 112-7 and 112-8, which are formed based on the openings 118-1, 118-2, 118-3, 118-4, 118-5, 118-6, 118-7 and 118-8, respectively. Accordingly, the fin isolation region 112 has a long fin isolation region and a short isolation region. The position and size of the fin isolation region 112 may be substantially the same as the position and size of the opening 118. The lengths (e.g., L1', L2', L3', L7' and L8') of the fin isolation region 112 may be equal to or slightly different from (e.g., slightly smaller than) the lengths (e.g., L1, L2, L3, L7 and L8) of the corresponding openings 118, respectively. Fig. 12C )). However, the relative relationship between the lengths (e.g., L1', L2', L3', L7', and L8') may be the same as the relative relationship between the lengths (e.g., L1, L2, L3, L7, and L8) of the corresponding openings 118. For example, there may be a relationship of L3'>L2'>L1' and L7'>L8'.

[0077] Similarly, the widths (e.g., W1’, W2’, W3’, W7’ and W8’) can be equal to or slightly different from (e.g., slightly less than) the widths of the corresponding openings 118 (e.g., W1, W2, W3, W7 and W8) respectively. Fig. 12C ). Also, the relative relationships between the widths (e.g., W1’, W2’, W3’, W7’ and W8’) can be the same as the relative relationships between the widths of the corresponding openings 118 (e.g., W1, W2, W3, W7 and W8). For example, according to some embodiments, there can be relationships W3’ < W2’ < W1’ and W7’ < W8’, while the widths W1’ to W8’ can also be equal to each other.

[0078] According to some embodiments, throughout the device die and wafer 10, any two adjacent openings 118 (and any two adjacent fin isolation regions 112) can span the same multi-layer stack 22’ (one or more) when directly adjacent and bringing their ends close to each other to reduce photoresist collapse.

[0079] In addition, according to some embodiments, the differences in the widths W1’, W2’, W3’, W7’ and W8’ (when different from each other) can be caused by the differences in the thicknesses T1, T2, T3, T7 and T8 of the gate spacers 38. For example, as Fig.21A shown, there can be relationships T1 < T2 < T3 and T7 > T8. According to some embodiments, the gate spacer 38 can include an inner layer 38A ( Fig. 14B ). and an outer layer 38B. According to some embodiments, the inner layer 38A includes silicon nitride, while the outer layer is a low-k dielectric layer formed of, for example, porous SiOCN. According to some embodiments, as Fig. 15B shown, when forming the opening 118, the outer layer 38B is thinned or removed, while the inner layer 38A remains unthinned. Accordingly, the differences in the thicknesses T1, T2, T3, T7 and T8 can be caused by the differences in the thicknesses T38A ( Fig. 15B ) of different gate spacers 38, while the thicknesses T38B of different gate spacers 38 can be the same as each other.

[0080] In addition, when forming the fin isolation region 112 (CMODE region), the openings 118 and the fin isolation regions 112 located on directly adjacent alternative gate stacks 70 also laterally overlap in the longitudinal direction (Y direction) and span the same nanostructure 22B ( Fig.21A ), such that some relevant portions of the photoresist 117 ( Fig.19 , also refer to Fig. 12B , Fig. 12C and Fig.12D ) have larger sizes and are not easily collapsed and delaminated.

[0081] According to some embodiments, by forming the openings 118 ( Fig. 12C ), and due to the loading effect caused by the different lengths and the different overlap distances, according to some embodiments, the fin isolation region 112 ( Fig.21A ) (which is also the width of Fig. 15C The widths of the openings 118 as shown may be equal to one another.

[0082] Fig.21B Shown by Fig.12D According to these embodiments, the fin isolation region 112-9 and the fin isolation region 112-10 have the same length L10 and L11 (refer to Fig.12D ), so the ends of both the fin isolation region 112-9 and the fin isolation region 112-10 are recessed from the corresponding center line MDL-3 by the same distance ΔS1. On the other hand, the fin isolation region 112-12 is longer than the fin isolation region 112-13, so the end of the longer fin isolation region 112-12 is recessed from the center line MDL4 by a distance ΔS2, while the end of the shorter fin isolation region 112-12 is not recessed and is aligned with the center line MDL-4. Similarly, the fin isolation region 112-13 is longer than the fin isolation region 112-12, so the end of the longer fin isolation region 112-13 is recessed, while the end of the shorter fin isolation region 112-12 is not recessed and is aligned with the center line MDL-4.

[0083] Next, if Fig.22A and Fig. 22B As shown, the gate stack 70 is recessed so that recesses are formed directly above the gate stack 70 and between opposite portions of the gate spacers 38. A gate mask 74 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in each recess, followed by a planarization process to remove excess portions of the dielectric material extending over the ILD 52.

[0084] like Fig.22A and Fig. 22B As further shown, ILD 76 is deposited over ILD 52 and gate mask 74. The corresponding process is Fig.31 This is shown as process 242 in the illustrated process flow 200. An etch stop layer (not shown) may or may not be deposited prior to forming ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, etc. ILD 76 is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, etc.

[0085] exist Fig.23A and Fig. 23BIn the embodiment, ILD 76, ILD 52, CESL 50, and gate mask 74 are etched to form recesses (occupied by contact plugs 80A and 80B) that expose the surface of source / drain regions 48 and / or gate stack 70. The recesses may be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.).

[0086] After forming the recess, a silicide region 78 is formed on the epitaxial source / drain region 48. The corresponding process is Fig.31 This is shown as process 244 in the illustrated process flow 200. A contact plug 80B is then formed over the silicide region 78. In addition, a contact 80A (also referred to as a gate contact plug) is formed in the recess, over the gate electrode 68, and in contact with the gate electrode 68. The corresponding process is shown in FIG. Fig.31 This is shown as process 246 in the illustrated process flow 200. Thus, transistor 82 is formed. Fig. 23B The contact plug 80A and the contact plug 80B are shown in the same cross-section, but in various embodiments, the contact plug 80A and the contact plug 80B may be formed in different cross-sections to reduce the risk of shorting each other.

[0087] Fig.24A and Figures 24B to 30A and Fig. 30B The formation of the fin isolation region 112 according to alternative embodiments is shown. These embodiments are substantially similar to Fig.11A Figure 11B to Fig.16A and Fig. 16B The embodiment shown is the same except that the dummy fin is formed so that when the gate stack is cut by forming the gate isolation region (also referred to as the cut metal gate (CMG) region) into a shorter portion, the gate isolation region can be located on the dummy fin. Fig.24A and Fig. 24B A dummy fin 140 is formed over the STI region 26, wherein the dummy gate stack 30 is formed over the dummy fin 140. The dummy fin 140 may have a multilayer structure formed of a dielectric material such as SiN, SiO, SiOCN, etc., and may include a high-k dielectric material. A hard mask 116 is formed over the dummy gate electrode 34.

[0088] Fig.25A and Fig.25B The formation of an etch mask 117 is shown, and an opening 118 is formed in the etch mask 117. The opening 118 may be Fig. 12C Next, Fig.26A and Fig.26BAs shown, hard mask 116 is etched such that opening 118 extends into hard mask 116 and the remaining portions of etch mask 117 are removed. Fig.27A and Fig.27B The etching of the dummy gate electrode 34 is shown. Fig.28A and Fig.28B The etching of the dummy gate dielectric 32, the multilayer stack 22' and the underlying semiconductor strip 20' is shown, thereby forming the opening 120. Next, as shown in FIG. Fig.29A and Fig.29B As shown, dielectric liner 112A and dielectric material 112B are deposited and may be formed of a material selected from SiN, SiO, SiON, SiCN, SiOCN, and the like.

[0089] A planarization process is then performed to remove excess portions of dielectric liner 112A and dielectric material 112B, leaving fin isolation region 112, such as Fig. 30A and Fig. 30B shown.

[0090] Embodiments of the present disclosure have some advantageous features. By forming fin isolation regions (CPODE or CMODE isolation regions) on adjacent gate stacks (which extend toward each other and span the same multilayer stack(s) (and the same semiconductor nanostructure(s)), and further adjusting the size of the fin isolation regions (and the corresponding openings in the corresponding photoresist), the collapse and delamination of the corresponding photoresist are reduced.

[0091] According to some embodiments of the present disclosure, a method includes: forming a plurality of semiconductor regions having a first longitudinal direction parallel to a first direction; forming a plurality of gate stacks having a second longitudinal direction parallel to a second direction, the second direction being perpendicular to the first direction, wherein the plurality of gate stacks are on a first portion of the plurality of semiconductor regions; etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks, wherein the plurality of openings include: a first opening located in a first gate stack among the plurality of gate stacks; and a second opening located in a second gate stack among the plurality of gate stacks, wherein the first opening and the second opening are directly adjacent to each other and have a lateral overlap, the lateral overlap having an overlap distance equal to or greater than a spacing between the plurality of semiconductor regions, and wherein the overlap distance is parallel to the second longitudinal direction; etching the plurality of semiconductor regions exposed through the plurality of openings so that the plurality of openings extend downward between dielectric isolation regions; and filling the plurality of openings to form a fin isolation region.

[0092] In one embodiment, wherein the overlap distance is equal to or greater than twice the pitch. In one embodiment, etching a plurality of gate stacks comprises: etching a plurality of dummy gate stacks, and the method further comprises: replacing a remaining portion of the dummy gate stack with a replacement gate stack after the fin isolation region is formed. In one embodiment, etching a plurality of gate stacks comprises: etching a plurality of replacement gate stacks. In one embodiment, the first opening has a first length and a first width, and the second opening has a second length and a second width, and wherein the first length is greater than the second length, and the first width is less than the second width.

[0093] In one embodiment, the method further comprises: forming a patterned photoresist including a first additional opening and a second additional opening, wherein the first opening is formed by etching a first portion of the first gate stack directly below the first additional opening, and the second opening is formed by etching a second portion of the second gate stack directly below the second additional opening, and wherein the first additional opening has a third length and a third width, and the second additional opening has a fourth length and a fourth width, wherein the third length is greater than the fourth length, and the third width is less than the fourth width. In one embodiment, a first end of the first opening is not aligned with a midpoint of two first adjacent source / drain regions, and a second end of the second opening is aligned with an additional midpoint of two second adjacent source / drain regions.

[0094] In an embodiment, the method further comprises: forming a dummy fin overlapping the dielectric isolation region, wherein the dummy fin is exposed to the plurality of openings after the plurality of gate stacks are etched. In an embodiment, the fin isolation region comprises a first fin isolation region located in the first opening and a second fin isolation region located in the second opening, and wherein both the first fin isolation region and the second fin isolation region intersect with the same semiconductor region of the plurality of semiconductor regions. In an embodiment, the method further comprises: forming an epitaxial region, wherein the epitaxial region is located between the first gate stack and the second gate stack and is located on the same semiconductor region.

[0095] In an embodiment, the epitaxial region is completely surrounded by the dielectric material. In an embodiment, portions of the plurality of semiconductor regions and the plurality of gate stacks form a plurality of transistors, and the epitaxial region and the plurality of source / drain regions of the plurality of transistors are formed in a common epitaxial process.

[0096] According to some embodiments of the present disclosure, a structure includes: multiple semiconductor regions; a first gate stack and a second gate stack, which are directly adjacent to each other; a first fin isolation region, located in the first gate stack; a second fin isolation region, located in the second gate stack, wherein the first fin isolation region and the second fin isolation region have a lateral overlap, the lateral overlap has an overlap distance equal to or greater than the spacing of the multiple semiconductor regions, and wherein the overlap distance is measured in a direction parallel to the longitudinal direction of the first gate stack and the second gate stack; and multiple source / drain regions, located on opposite sides of the first gate stack and the second gate stack to form multiple transistors.

[0097] In an embodiment, the plurality of semiconductor regions include semiconductor nanostructures. In an embodiment, the structure further includes: a semiconductor region located between the first gate stack and the second gate stack, wherein the semiconductor region includes a facet and the semiconductor region is formed of the same semiconductor material as the plurality of source / drain regions. In an embodiment, the overlap distance is equal to a multiple of the pitch.

[0098] According to some embodiments of the present disclosure, a structure includes: an elongated semiconductor region, including multiple parts, wherein the elongated semiconductor region includes a first semiconductor material; a first gate stack and a second gate stack, directly adjacent to each other; an epitaxial semiconductor region, located between the first part and the second part of the elongated semiconductor region and in contact with the first part and the second part of the elongated semiconductor region, wherein the epitaxial semiconductor region includes a second semiconductor material different from the first semiconductor material; a first dielectric isolation region, located in the first gate stack; and a second dielectric isolation region, located in the second gate stack, wherein both the first dielectric isolation region and the second dielectric isolation region intersect with the elongated semiconductor region.

[0099] In an embodiment, in a top view of the structure, the epitaxial semiconductor region is surrounded by a dielectric material. In an embodiment, the first dielectric isolation region is longer and narrower than the second dielectric isolation region. In an embodiment, the elongated semiconductor region comprises a nanostructure.

[0100] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0101] Example 1 is a method for forming a semiconductor structure, comprising: forming a plurality of semiconductor regions having a first longitudinal direction parallel to a first direction; forming a plurality of gate stacks having a second longitudinal direction parallel to a second direction, the second direction being perpendicular to the first direction, wherein the plurality of gate stacks are located on a first portion of the plurality of semiconductor regions; etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks, wherein the plurality of openings include: a first opening located in a first gate stack among the plurality of gate stacks; and a second opening located in a second gate stack among the plurality of gate stacks, wherein the first opening and the second opening are directly adjacent to each other and have a lateral overlap, the lateral overlap having an overlap distance equal to or greater than a spacing between the plurality of semiconductor regions, and wherein the overlap distance is parallel to the second longitudinal direction; etching the plurality of semiconductor regions exposed by the plurality of openings so that the plurality of openings extend downward between dielectric isolation regions; and filling the plurality of openings to form a fin isolation region.

[0102] Example 2 is the method of Example 1, wherein the overlapping distance is equal to or greater than twice the spacing.

[0103] Example 3 is the method described in Example 1, wherein etching the multiple gate stacks includes etching multiple dummy gate stacks, and the method further includes replacing the remaining portion of the dummy gate stack with a replacement gate stack after the fin isolation region is formed.

[0104] Example 4 is the method of Example 1, wherein etching the plurality of gate stacks comprises etching a plurality of replacement gate stacks.

[0105] Example 5 is the method described in Example 1, wherein the first opening has a first length and a first width, and the second opening has a second length and a second width, and wherein the first length is greater than the second length and the first width is less than the second width.

[0106] Example 6 is the method described in Example 5, further comprising: forming a patterned photoresist including a first additional opening and a second additional opening, wherein the first opening is formed by etching a first portion of the first gate stack located directly below the first additional opening, and the second opening is formed by etching a second portion of the second gate stack located directly below the second additional opening, and wherein: the first additional opening has a third length and a third width, and the second additional opening has a fourth length and a fourth width, wherein the third length is greater than the fourth length, and the third width is less than the fourth width.

[0107] Example 7 is the method of Example 5, wherein the first end of the first opening is not aligned with the midpoint of two first adjacent source / drain regions, and the second end of the second opening is aligned with additional midpoints of two second adjacent source / drain regions.

[0108] Example 8 is the method of Example 1, comprising: forming a dummy fin overlapping the dielectric isolation region, wherein the dummy fin is exposed to the plurality of openings after the plurality of gate stacks are etched.

[0109] Example 9 is the method described in Example 1, wherein the fin isolation region includes a first fin isolation region located in the first opening and a second fin isolation region located in the second opening, and wherein both the first fin isolation region and the second fin isolation region intersect with the same semiconductor region among the multiple semiconductor regions.

[0110] Example 10 is the method of Example 9, further comprising: forming an epitaxial region, wherein the epitaxial region is located between the first gate stack and the second gate stack and is located on the same semiconductor region.

[0111] Example 11 is the method of Example 10, wherein the epitaxial region is completely surrounded by a dielectric material.

[0112] Example 12 is the method described in Example 10, wherein portions of the multiple semiconductor regions and the multiple gate stacks form multiple transistors, and the epitaxial region and the multiple source / drain regions of the multiple transistors are formed in a common epitaxial process.

[0113] Example 13 is a semiconductor structure comprising: a plurality of semiconductor regions; a first gate stack and a second gate stack directly adjacent to each other; a first fin isolation region located in the first gate stack; a second fin isolation region located in the second gate stack, wherein the first fin isolation region and the second fin isolation region have a lateral overlap, the lateral overlap having an overlap distance equal to or greater than a spacing between the plurality of semiconductor regions, and wherein the overlap distance is measured in a direction parallel to a longitudinal direction of the first gate stack and the second gate stack; and a plurality of source / drain regions located on opposite sides of the first gate stack and the second gate stack to form a plurality of transistors.

[0114] Example 14 is the structure of Example 13, wherein the plurality of semiconductor regions include semiconductor nanostructures.

[0115] Example 15 is the structure described in Example 13, further comprising: a semiconductor region located between the first gate stack and the second gate stack, wherein the semiconductor region includes a small plane and is formed of the same semiconductor material as the multiple source / drain regions.

[0116] Example 16 is the structure of Example 13, wherein the overlap distance is equal to a multiple of the spacing.

[0117] Example 17 is a semiconductor structure comprising: an elongated semiconductor region comprising a plurality of portions, wherein the elongated semiconductor region comprises a first semiconductor material; a first gate stack and a second gate stack directly adjacent to each other; an epitaxial semiconductor region located between and in contact with the first and second portions of the elongated semiconductor region, wherein the epitaxial semiconductor region comprises a second semiconductor material different from the first semiconductor material; a first dielectric isolation region located in the first gate stack; and a second dielectric isolation region located in the second gate stack, wherein both the first dielectric isolation region and the second dielectric isolation region intersect with the elongated semiconductor region.

[0118] Example 18 is the structure of Example 17, wherein, in a top view of the structure, the epitaxial semiconductor region is surrounded by a dielectric material.

[0119] Example 19 is the structure of Example 17, wherein the first dielectric isolation region is longer and narrower than the second dielectric isolation region.

[0120] Example 20 is the structure of Example 17, wherein the elongated semiconductor region comprises a nanostructure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a plurality of semiconductor regions having a first longitudinal direction parallel to the first direction; forming a plurality of gate stacks having a second longitudinal direction parallel to a second direction, the second direction being perpendicular to the first direction, wherein the plurality of gate stacks are located on a first portion of the plurality of semiconductor regions; etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks, wherein the plurality of openings comprises: A first opening located in a first gate stack among the plurality of gate stacks; and a second opening located in a second gate stack of the plurality of gate stacks, wherein the first opening and the second opening are directly adjacent to each other and have a lateral overlap, the lateral overlap having an overlap distance that is equal to or greater than a pitch between the plurality of semiconductor regions, and wherein the overlap distance is parallel to the second longitudinal direction; etching the plurality of semiconductor regions exposed by the plurality of openings so that the plurality of openings extend downwardly between dielectric isolation regions; and The plurality of openings are filled to form fin isolation regions.

2. The method according to claim 1, wherein: The overlapping distance is equal to or greater than twice the spacing.

3. The method according to claim 1, wherein: Etching the plurality of gate stacks includes etching a plurality of dummy gate stacks, and the method further includes replacing remaining portions of the dummy gate stacks with replacement gate stacks after the fin isolation region is formed.

4. The method according to claim 1, wherein: Etching the plurality of gate stacks includes etching a plurality of replacement gate stacks.

5. The method according to claim 1, wherein: The first opening has a first length and a first width, and the second opening has a second length and a second width, and wherein the first length is greater than the second length and the first width is less than the second width.

6. The method according to claim 5, further comprising: forming a patterned photoresist including a first additional opening and a second additional opening, wherein the first opening is formed by etching a first portion of the first gate stack directly below the first additional opening, and the second opening is formed by etching a second portion of the second gate stack directly below the second additional opening, and wherein: The first additional opening has a third length and a third width, and the second additional opening has a fourth length and a fourth width, wherein the third length is greater than the fourth length, and the third width is less than the fourth width.

7. The method according to claim 5, wherein: The first end of the first opening is not aligned with the midpoints of the two first adjacent source / drain regions, and the second end of the second opening is aligned with the additional midpoints of the two second adjacent source / drain regions.

8. The method according to claim 1, comprising: A dummy fin is formed overlapping the dielectric isolation region, wherein the dummy fin is exposed to the plurality of openings after the plurality of gate stacks are etched.

9. A semiconductor structure comprising: multiple semiconductor regions; a first gate stack and a second gate stack directly adjacent to each other; A first fin isolation region, located in the first gate stack; a second fin isolation region located in the second gate stack, wherein the first fin isolation region and the second fin isolation region have a lateral overlap, the lateral overlap having an overlap distance that is equal to or greater than a pitch of the plurality of semiconductor regions, and wherein the overlap distance is measured in a direction parallel to a longitudinal direction of the first gate stack and the second gate stack; and A plurality of source / drain regions are located on opposite sides of the first gate stack and the second gate stack to form a plurality of transistors.

10. A semiconductor structure comprising: an elongated semiconductor region comprising a plurality of portions, wherein the elongated semiconductor region comprises a first semiconductor material; a first gate stack and a second gate stack directly adjacent to each other; an epitaxial semiconductor region located between and in contact with the first and second portions of the elongated semiconductor region, wherein the epitaxial semiconductor region comprises a second semiconductor material different from the first semiconductor material; a first dielectric isolation region located in the first gate stack; and A second dielectric isolation region is located in the second gate stack, wherein both the first dielectric isolation region and the second dielectric isolation region intersect the elongated semiconductor region.

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